brgphy.c revision 1.76.26.2
1 /* $NetBSD: brgphy.c,v 1.76.26.2 2019/01/26 22:00:06 pgoyette Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2000, 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1997 Manuel Bouyer. All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 45 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 46 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 47 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 48 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 49 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 50 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 51 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 52 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 53 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 54 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 55 */ 56 57 /* 58 * driver for the Broadcom BCM5400 and BCM5700 Gig-E PHYs. 59 * 60 * Programming information for this PHY was gleaned from FreeBSD 61 * (they were apparently able to get a datasheet from Broadcom). 62 */ 63 64 #include <sys/cdefs.h> 65 __KERNEL_RCSID(0, "$NetBSD: brgphy.c,v 1.76.26.2 2019/01/26 22:00:06 pgoyette Exp $"); 66 67 #include <sys/param.h> 68 #include <sys/systm.h> 69 #include <sys/kernel.h> 70 #include <sys/device.h> 71 #include <sys/socket.h> 72 #include <sys/errno.h> 73 #include <prop/proplib.h> 74 75 #include <net/if.h> 76 #include <net/if_media.h> 77 78 #include <dev/mii/mii.h> 79 #include <dev/mii/miivar.h> 80 #include <dev/mii/miidevs.h> 81 #include <dev/mii/brgphyreg.h> 82 83 #include <dev/pci/if_bgereg.h> 84 #include <dev/pci/if_bnxreg.h> 85 86 static int brgphymatch(device_t, cfdata_t, void *); 87 static void brgphyattach(device_t, device_t, void *); 88 89 struct brgphy_softc { 90 struct mii_softc sc_mii; 91 bool sc_isbge; 92 bool sc_isbnx; 93 uint32_t sc_chipid; /* parent's chipid */ 94 uint32_t sc_phyflags; /* parent's phyflags */ 95 uint32_t sc_shared_hwcfg; /* shared hw config */ 96 uint32_t sc_port_hwcfg; /* port specific hw config */ 97 }; 98 99 CFATTACH_DECL3_NEW(brgphy, sizeof(struct brgphy_softc), 100 brgphymatch, brgphyattach, mii_phy_detach, mii_phy_activate, NULL, NULL, 101 DVF_DETACH_SHUTDOWN); 102 103 static int brgphy_service(struct mii_softc *, struct mii_data *, int); 104 static void brgphy_copper_status(struct mii_softc *); 105 static void brgphy_fiber_status(struct mii_softc *); 106 static void brgphy_5708s_status(struct mii_softc *); 107 static void brgphy_5709s_status(struct mii_softc *); 108 static int brgphy_mii_phy_auto(struct mii_softc *); 109 static void brgphy_loop(struct mii_softc *); 110 static void brgphy_reset(struct mii_softc *); 111 static void brgphy_bcm5401_dspcode(struct mii_softc *); 112 static void brgphy_bcm5411_dspcode(struct mii_softc *); 113 static void brgphy_bcm5421_dspcode(struct mii_softc *); 114 static void brgphy_bcm54k2_dspcode(struct mii_softc *); 115 static void brgphy_adc_bug(struct mii_softc *); 116 static void brgphy_5704_a0_bug(struct mii_softc *); 117 static void brgphy_ber_bug(struct mii_softc *); 118 static void brgphy_crc_bug(struct mii_softc *); 119 static void brgphy_disable_early_dac(struct mii_softc *); 120 static void brgphy_jumbo_settings(struct mii_softc *); 121 static void brgphy_eth_wirespeed(struct mii_softc *); 122 123 124 static const struct mii_phy_funcs brgphy_copper_funcs = { 125 brgphy_service, brgphy_copper_status, brgphy_reset, 126 }; 127 128 static const struct mii_phy_funcs brgphy_fiber_funcs = { 129 brgphy_service, brgphy_fiber_status, brgphy_reset, 130 }; 131 132 static const struct mii_phy_funcs brgphy_5708s_funcs = { 133 brgphy_service, brgphy_5708s_status, brgphy_reset, 134 }; 135 136 static const struct mii_phy_funcs brgphy_5709s_funcs = { 137 brgphy_service, brgphy_5709s_status, brgphy_reset, 138 }; 139 140 static const struct mii_phydesc brgphys[] = { 141 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5400, 142 MII_STR_BROADCOM_BCM5400 }, 143 144 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5401, 145 MII_STR_BROADCOM_BCM5401 }, 146 147 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5411, 148 MII_STR_BROADCOM_BCM5411 }, 149 150 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5421, 151 MII_STR_BROADCOM_BCM5421 }, 152 153 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5462, 154 MII_STR_BROADCOM_BCM5462 }, 155 156 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5461, 157 MII_STR_BROADCOM_BCM5461 }, 158 159 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM54K2, 160 MII_STR_BROADCOM_BCM54K2 }, 161 162 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5464, 163 MII_STR_BROADCOM_BCM5464 }, 164 165 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5701, 166 MII_STR_BROADCOM_BCM5701 }, 167 168 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5703, 169 MII_STR_BROADCOM_BCM5703 }, 170 171 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5704, 172 MII_STR_BROADCOM_BCM5704 }, 173 174 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5705, 175 MII_STR_BROADCOM_BCM5705 }, 176 177 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5706, 178 MII_STR_BROADCOM_BCM5706 }, 179 180 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5714, 181 MII_STR_BROADCOM_BCM5714 }, 182 183 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5750, 184 MII_STR_BROADCOM_BCM5750 }, 185 186 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5752, 187 MII_STR_BROADCOM_BCM5752 }, 188 189 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5780, 190 MII_STR_BROADCOM_BCM5780 }, 191 192 { MII_OUI_BROADCOM, MII_MODEL_BROADCOM_BCM5708C, 193 MII_STR_BROADCOM_BCM5708C }, 194 195 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5481, 196 MII_STR_BROADCOM2_BCM5481 }, 197 198 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5482, 199 MII_STR_BROADCOM2_BCM5482 }, 200 201 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5708S, 202 MII_STR_BROADCOM2_BCM5708S }, 203 204 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5709C, 205 MII_STR_BROADCOM2_BCM5709C }, 206 207 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5709S, 208 MII_STR_BROADCOM2_BCM5709S }, 209 210 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5709CAX, 211 MII_STR_BROADCOM2_BCM5709CAX }, 212 213 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5722, 214 MII_STR_BROADCOM2_BCM5722 }, 215 216 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5754, 217 MII_STR_BROADCOM2_BCM5754 }, 218 219 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5755, 220 MII_STR_BROADCOM2_BCM5755 }, 221 222 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5756, 223 MII_STR_BROADCOM2_BCM5756 }, 224 225 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5761, 226 MII_STR_BROADCOM2_BCM5761 }, 227 228 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5784, 229 MII_STR_BROADCOM2_BCM5784 }, 230 231 { MII_OUI_BROADCOM2, MII_MODEL_BROADCOM2_BCM5785, 232 MII_STR_BROADCOM2_BCM5785 }, 233 234 { MII_OUI_BROADCOM3, MII_MODEL_BROADCOM3_BCM5717C, 235 MII_STR_BROADCOM3_BCM5717C }, 236 237 { MII_OUI_BROADCOM3, MII_MODEL_BROADCOM3_BCM5719C, 238 MII_STR_BROADCOM3_BCM5719C }, 239 240 { MII_OUI_BROADCOM3, MII_MODEL_BROADCOM3_BCM5720C, 241 MII_STR_BROADCOM3_BCM5720C }, 242 243 { MII_OUI_BROADCOM3, MII_MODEL_BROADCOM3_BCM57765, 244 MII_STR_BROADCOM3_BCM57765 }, 245 246 { MII_OUI_BROADCOM3, MII_MODEL_BROADCOM3_BCM57780, 247 MII_STR_BROADCOM3_BCM57780 }, 248 249 { MII_OUI_xxBROADCOM_ALT1, MII_MODEL_xxBROADCOM_ALT1_BCM5906, 250 MII_STR_xxBROADCOM_ALT1_BCM5906 }, 251 252 { 0, 0, 253 NULL }, 254 }; 255 256 static int 257 brgphymatch(device_t parent, cfdata_t match, void *aux) 258 { 259 struct mii_attach_args *ma = aux; 260 261 if (mii_phy_match(ma, brgphys) != NULL) 262 return (10); 263 264 return (0); 265 } 266 267 static void 268 brgphyattach(device_t parent, device_t self, void *aux) 269 { 270 struct brgphy_softc *bsc = device_private(self); 271 struct mii_softc *sc = &bsc->sc_mii; 272 struct mii_attach_args *ma = aux; 273 struct mii_data *mii = ma->mii_data; 274 const struct mii_phydesc *mpd; 275 prop_dictionary_t dict; 276 277 mpd = mii_phy_match(ma, brgphys); 278 aprint_naive(": Media interface\n"); 279 aprint_normal(": %s, rev. %d\n", mpd->mpd_name, MII_REV(ma->mii_id2)); 280 281 sc->mii_dev = self; 282 sc->mii_inst = mii->mii_instance; 283 sc->mii_phy = ma->mii_phyno; 284 sc->mii_mpd_oui = MII_OUI(ma->mii_id1, ma->mii_id2); 285 sc->mii_mpd_model = MII_MODEL(ma->mii_id2); 286 sc->mii_mpd_rev = MII_REV(ma->mii_id2); 287 sc->mii_pdata = mii; 288 sc->mii_flags = ma->mii_flags; 289 sc->mii_anegticks = MII_ANEGTICKS; 290 291 if (device_is_a(parent, "bge")) 292 bsc->sc_isbge = true; 293 else if (device_is_a(parent, "bnx")) 294 bsc->sc_isbnx = true; 295 296 dict = device_properties(parent); 297 if (bsc->sc_isbge || bsc->sc_isbnx) { 298 if (!prop_dictionary_get_uint32(dict, "phyflags", 299 &bsc->sc_phyflags)) 300 aprint_error_dev(self, "failed to get phyflags\n"); 301 if (!prop_dictionary_get_uint32(dict, "chipid", 302 &bsc->sc_chipid)) 303 aprint_error_dev(self, "failed to get chipid\n"); 304 } 305 306 if (bsc->sc_isbnx) { 307 /* Currently, only bnx use sc_shared_hwcfg and sc_port_hwcfg */ 308 if (!prop_dictionary_get_uint32(dict, "shared_hwcfg", 309 &bsc->sc_shared_hwcfg)) 310 aprint_error_dev(self, "failed to get shared_hwcfg\n"); 311 if (!prop_dictionary_get_uint32(dict, "port_hwcfg", 312 &bsc->sc_port_hwcfg)) 313 aprint_error_dev(self, "failed to get port_hwcfg\n"); 314 } 315 316 if (sc->mii_flags & MIIF_HAVEFIBER) { 317 if ((sc->mii_mpd_oui == MII_OUI_BROADCOM2) 318 && sc->mii_mpd_model == MII_MODEL_BROADCOM2_BCM5708S) 319 sc->mii_funcs = &brgphy_5708s_funcs; 320 else if ((sc->mii_mpd_oui == MII_OUI_BROADCOM2) 321 && (sc->mii_mpd_model == MII_MODEL_BROADCOM2_BCM5709S)) { 322 if (bsc->sc_isbnx) 323 sc->mii_funcs = &brgphy_5709s_funcs; 324 else { 325 /* 326 * XXX 327 * 5720S and 5709S shares the same PHY id. 328 * Assume 5720S PHY if parent device is bge(4). 329 */ 330 sc->mii_funcs = &brgphy_5708s_funcs; 331 } 332 } else 333 sc->mii_funcs = &brgphy_fiber_funcs; 334 } else 335 sc->mii_funcs = &brgphy_copper_funcs; 336 337 PHY_RESET(sc); 338 339 PHY_READ(sc, MII_BMSR, &sc->mii_capabilities); 340 sc->mii_capabilities &= ma->mii_capmask; 341 if (sc->mii_capabilities & BMSR_EXTSTAT) 342 PHY_READ(sc, MII_EXTSR, &sc->mii_extcapabilities); 343 344 aprint_normal_dev(self, ""); 345 if (sc->mii_flags & MIIF_HAVEFIBER) { 346 sc->mii_flags |= MIIF_NOISOLATE | MIIF_NOLOOP; 347 348 /* 349 * Set the proper bits for capabilities so that the 350 * correct media get selected by mii_phy_add_media() 351 */ 352 sc->mii_capabilities |= BMSR_ANEG; 353 sc->mii_capabilities &= ~BMSR_100T4; 354 sc->mii_extcapabilities |= EXTSR_1000XFDX; 355 356 if (bsc->sc_isbnx) { 357 /* 358 * 2.5Gb support is a software enabled feature 359 * on the BCM5708S and BCM5709S controllers. 360 */ 361 #define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL) 362 if (bsc->sc_phyflags 363 & BNX_PHY_2_5G_CAPABLE_FLAG) { 364 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_2500_SX, 365 IFM_FDX, sc->mii_inst), 0); 366 aprint_normal("2500baseSX-FDX, "); 367 #undef ADD 368 } 369 } 370 } 371 mii_phy_add_media(sc); 372 373 aprint_normal("\n"); 374 } 375 376 static int 377 brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 378 { 379 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 380 uint16_t reg, speed, gig; 381 382 switch (cmd) { 383 case MII_POLLSTAT: 384 /* If we're not polling our PHY instance, just return. */ 385 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 386 return (0); 387 break; 388 389 case MII_MEDIACHG: 390 /* 391 * If the media indicates a different PHY instance, 392 * isolate ourselves. 393 */ 394 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 395 PHY_READ(sc, MII_BMCR, ®); 396 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO); 397 return (0); 398 } 399 400 /* If the interface is not up, don't do anything. */ 401 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 402 break; 403 404 PHY_RESET(sc); /* XXX hardware bug work-around */ 405 406 switch (IFM_SUBTYPE(ife->ifm_media)) { 407 case IFM_AUTO: 408 (void) brgphy_mii_phy_auto(sc); 409 break; 410 case IFM_2500_SX: 411 speed = BRGPHY_5708S_BMCR_2500; 412 goto setit; 413 case IFM_1000_SX: 414 case IFM_1000_T: 415 speed = BMCR_S1000; 416 goto setit; 417 case IFM_100_TX: 418 speed = BMCR_S100; 419 goto setit; 420 case IFM_10_T: 421 speed = BMCR_S10; 422 setit: 423 brgphy_loop(sc); 424 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 425 speed |= BMCR_FDX; 426 gig = GTCR_ADV_1000TFDX; 427 } else 428 gig = GTCR_ADV_1000THDX; 429 430 PHY_WRITE(sc, MII_100T2CR, 0); 431 PHY_WRITE(sc, MII_ANAR, ANAR_CSMA); 432 PHY_WRITE(sc, MII_BMCR, speed); 433 434 if ((IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T) && 435 (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_SX) && 436 (IFM_SUBTYPE(ife->ifm_media) != IFM_2500_SX)) 437 break; 438 439 PHY_WRITE(sc, MII_100T2CR, gig); 440 PHY_WRITE(sc, MII_BMCR, 441 speed | BMCR_AUTOEN | BMCR_STARTNEG); 442 443 if ((sc->mii_mpd_oui != MII_OUI_BROADCOM) 444 || (sc->mii_mpd_model != MII_MODEL_BROADCOM_BCM5701)) 445 break; 446 447 if (mii->mii_media.ifm_media & IFM_ETH_MASTER) 448 gig |= GTCR_MAN_MS | GTCR_ADV_MS; 449 PHY_WRITE(sc, MII_100T2CR, gig); 450 break; 451 default: 452 return (EINVAL); 453 } 454 break; 455 456 case MII_TICK: 457 /* If we're not currently selected, just return. */ 458 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 459 return (0); 460 461 /* Is the interface even up? */ 462 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 463 return 0; 464 465 /* Only used for autonegotiation. */ 466 if ((IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) && 467 (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T)) { 468 sc->mii_ticks = 0; 469 break; 470 } 471 472 /* 473 * Check for link. 474 * Read the status register twice; BMSR_LINK is latch-low. 475 */ 476 PHY_READ(sc, MII_BMSR, ®); 477 PHY_READ(sc, MII_BMSR, ®); 478 if (reg & BMSR_LINK) { 479 sc->mii_ticks = 0; 480 break; 481 } 482 483 /* 484 * mii_ticks == 0 means it's the first tick after changing the 485 * media or the link became down since the last tick 486 * (see above), so break to update the status. 487 */ 488 if (sc->mii_ticks++ == 0) 489 break; 490 491 /* Only retry autonegotiation every mii_anegticks seconds. */ 492 KASSERT(sc->mii_anegticks != 0); 493 if (sc->mii_ticks <= sc->mii_anegticks) 494 break; 495 496 brgphy_mii_phy_auto(sc); 497 break; 498 499 case MII_DOWN: 500 mii_phy_down(sc); 501 return (0); 502 } 503 504 /* Update the media status. */ 505 mii_phy_status(sc); 506 507 /* 508 * Callback if something changed. Note that we need to poke the DSP on 509 * the Broadcom PHYs if the media changes. 510 */ 511 if (sc->mii_media_active != mii->mii_media_active || 512 sc->mii_media_status != mii->mii_media_status || 513 cmd == MII_MEDIACHG) { 514 switch (sc->mii_mpd_oui) { 515 case MII_OUI_BROADCOM: 516 switch (sc->mii_mpd_model) { 517 case MII_MODEL_BROADCOM_BCM5400: 518 brgphy_bcm5401_dspcode(sc); 519 break; 520 case MII_MODEL_BROADCOM_BCM5401: 521 if (sc->mii_mpd_rev == 1 || sc->mii_mpd_rev == 3) 522 brgphy_bcm5401_dspcode(sc); 523 break; 524 case MII_MODEL_BROADCOM_BCM5411: 525 brgphy_bcm5411_dspcode(sc); 526 break; 527 } 528 break; 529 } 530 } 531 532 /* Callback if something changed. */ 533 mii_phy_update(sc, cmd); 534 return (0); 535 } 536 537 static void 538 brgphy_copper_status(struct mii_softc *sc) 539 { 540 struct mii_data *mii = sc->mii_pdata; 541 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 542 uint16_t bmcr, bmsr, auxsts, gtsr; 543 544 mii->mii_media_status = IFM_AVALID; 545 mii->mii_media_active = IFM_ETHER; 546 547 PHY_READ(sc, MII_BMSR, &bmsr); 548 PHY_READ(sc, MII_BMSR, &bmsr); 549 if (bmsr & BMSR_LINK) 550 mii->mii_media_status |= IFM_ACTIVE; 551 552 PHY_READ(sc, MII_BMCR, &bmcr); 553 if (bmcr & BMCR_ISO) { 554 mii->mii_media_active |= IFM_NONE; 555 mii->mii_media_status = 0; 556 return; 557 } 558 559 if (bmcr & BMCR_LOOP) 560 mii->mii_media_active |= IFM_LOOP; 561 562 if (bmcr & BMCR_AUTOEN) { 563 /* 564 * The media status bits are only valid of autonegotiation 565 * has completed (or it's disabled). 566 */ 567 if ((bmsr & BMSR_ACOMP) == 0) { 568 /* Erg, still trying, I guess... */ 569 mii->mii_media_active |= IFM_NONE; 570 return; 571 } 572 573 PHY_READ(sc, BRGPHY_MII_AUXSTS, &auxsts); 574 575 switch (auxsts & BRGPHY_AUXSTS_AN_RES) { 576 case BRGPHY_RES_1000FD: 577 mii->mii_media_active |= IFM_1000_T | IFM_FDX; 578 PHY_READ(sc, MII_100T2SR, >sr); 579 if (gtsr & GTSR_MS_RES) 580 mii->mii_media_active |= IFM_ETH_MASTER; 581 break; 582 583 case BRGPHY_RES_1000HD: 584 mii->mii_media_active |= IFM_1000_T | IFM_HDX; 585 PHY_READ(sc, MII_100T2SR, >sr); 586 if (gtsr & GTSR_MS_RES) 587 mii->mii_media_active |= IFM_ETH_MASTER; 588 break; 589 590 case BRGPHY_RES_100FD: 591 mii->mii_media_active |= IFM_100_TX | IFM_FDX; 592 break; 593 594 case BRGPHY_RES_100T4: 595 mii->mii_media_active |= IFM_100_T4 | IFM_HDX; 596 break; 597 598 case BRGPHY_RES_100HD: 599 mii->mii_media_active |= IFM_100_TX | IFM_HDX; 600 break; 601 602 case BRGPHY_RES_10FD: 603 mii->mii_media_active |= IFM_10_T | IFM_FDX; 604 break; 605 606 case BRGPHY_RES_10HD: 607 mii->mii_media_active |= IFM_10_T | IFM_HDX; 608 break; 609 610 default: 611 mii->mii_media_active |= IFM_NONE; 612 mii->mii_media_status = 0; 613 } 614 615 if (mii->mii_media_active & IFM_FDX) 616 mii->mii_media_active |= mii_phy_flowstatus(sc); 617 618 } else 619 mii->mii_media_active = ife->ifm_media; 620 } 621 622 void 623 brgphy_fiber_status(struct mii_softc *sc) 624 { 625 struct mii_data *mii = sc->mii_pdata; 626 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 627 uint16_t bmcr, bmsr, anar, anlpar, result; 628 629 mii->mii_media_status = IFM_AVALID; 630 mii->mii_media_active = IFM_ETHER; 631 632 PHY_READ(sc, MII_BMSR, &bmsr); 633 PHY_READ(sc, MII_BMSR, &bmsr); 634 if (bmsr & BMSR_LINK) 635 mii->mii_media_status |= IFM_ACTIVE; 636 637 PHY_READ(sc, MII_BMCR, &bmcr); 638 if (bmcr & BMCR_LOOP) 639 mii->mii_media_active |= IFM_LOOP; 640 641 if (bmcr & BMCR_AUTOEN) { 642 if ((bmsr & BMSR_ACOMP) == 0) { 643 /* Erg, still trying, I guess... */ 644 mii->mii_media_active |= IFM_NONE; 645 return; 646 } 647 648 mii->mii_media_active |= IFM_1000_SX; 649 650 PHY_READ(sc, MII_ANAR, &anar); 651 PHY_READ(sc, MII_ANLPAR, &anlpar); 652 result = anar & anlpar; 653 654 if (result & ANAR_X_FD) 655 mii->mii_media_active |= IFM_FDX; 656 else 657 mii->mii_media_active |= IFM_HDX; 658 659 if (mii->mii_media_active & IFM_FDX) 660 mii->mii_media_active |= mii_phy_flowstatus(sc); 661 } else 662 mii->mii_media_active = ife->ifm_media; 663 } 664 665 void 666 brgphy_5708s_status(struct mii_softc *sc) 667 { 668 struct mii_data *mii = sc->mii_pdata; 669 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 670 uint16_t bmcr, bmsr; 671 672 mii->mii_media_status = IFM_AVALID; 673 mii->mii_media_active = IFM_ETHER; 674 675 PHY_READ(sc, MII_BMSR, &bmsr); 676 PHY_READ(sc, MII_BMSR, &bmsr); 677 if (bmsr & BMSR_LINK) 678 mii->mii_media_status |= IFM_ACTIVE; 679 680 PHY_READ(sc, MII_BMCR, &bmcr); 681 if (bmcr & BMCR_LOOP) 682 mii->mii_media_active |= IFM_LOOP; 683 684 if (bmcr & BMCR_AUTOEN) { 685 uint16_t xstat; 686 687 if ((bmsr & BMSR_ACOMP) == 0) { 688 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 689 BRGPHY_5708S_DIG_PG0); 690 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_STAT1, &xstat); 691 if ((xstat & BRGPHY_5708S_PG0_1000X_STAT1_LINK) == 0) { 692 /* Erg, still trying, I guess... */ 693 mii->mii_media_active |= IFM_NONE; 694 return; 695 } 696 } 697 698 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 699 BRGPHY_5708S_DIG_PG0); 700 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_STAT1, &xstat); 701 702 switch (xstat & BRGPHY_5708S_PG0_1000X_STAT1_SPEED_MASK) { 703 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_10: 704 mii->mii_media_active |= IFM_10_FL; 705 break; 706 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_100: 707 mii->mii_media_active |= IFM_100_FX; 708 break; 709 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_1G: 710 mii->mii_media_active |= IFM_1000_SX; 711 break; 712 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_25G: 713 mii->mii_media_active |= IFM_2500_SX; 714 break; 715 } 716 717 if (xstat & BRGPHY_5708S_PG0_1000X_STAT1_FDX) 718 mii->mii_media_active |= IFM_FDX; 719 else 720 mii->mii_media_active |= IFM_HDX; 721 722 if (mii->mii_media_active & IFM_FDX) { 723 if (xstat & BRGPHY_5708S_PG0_1000X_STAT1_TX_PAUSE) 724 mii->mii_media_active |= IFM_FLOW | IFM_ETH_TXPAUSE; 725 if (xstat & BRGPHY_5708S_PG0_1000X_STAT1_RX_PAUSE) 726 mii->mii_media_active |= IFM_FLOW | IFM_ETH_RXPAUSE; 727 } 728 } else 729 mii->mii_media_active = ife->ifm_media; 730 } 731 732 static void 733 brgphy_5709s_status(struct mii_softc *sc) 734 { 735 struct mii_data *mii = sc->mii_pdata; 736 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 737 uint16_t bmcr, bmsr, auxsts; 738 739 mii->mii_media_status = IFM_AVALID; 740 mii->mii_media_active = IFM_ETHER; 741 742 PHY_READ(sc, MII_BMSR, &bmsr); 743 PHY_READ(sc, MII_BMSR, &bmsr); 744 if (bmsr & BMSR_LINK) 745 mii->mii_media_status |= IFM_ACTIVE; 746 747 PHY_READ(sc, MII_BMCR, &bmcr); 748 if (bmcr & BMCR_ISO) { 749 mii->mii_media_active |= IFM_NONE; 750 mii->mii_media_status = 0; 751 return; 752 } 753 754 if (bmcr & BMCR_LOOP) 755 mii->mii_media_active |= IFM_LOOP; 756 757 if (bmcr & BMCR_AUTOEN) { 758 /* 759 * The media status bits are only valid of autonegotiation 760 * has completed (or it's disabled). 761 */ 762 if ((bmsr & BMSR_ACOMP) == 0) { 763 /* Erg, still trying, I guess... */ 764 mii->mii_media_active |= IFM_NONE; 765 return; 766 } 767 768 /* 5709S has its own general purpose status registers */ 769 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_GP_STATUS); 770 PHY_READ(sc, BRGPHY_GP_STATUS_TOP_ANEG_STATUS, &auxsts); 771 772 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, 773 BRGPHY_BLOCK_ADDR_COMBO_IEEE0); 774 775 switch (auxsts & BRGPHY_GP_STATUS_TOP_ANEG_SPEED_MASK) { 776 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_10: 777 mii->mii_media_active |= IFM_10_FL; 778 break; 779 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_100: 780 mii->mii_media_active |= IFM_100_FX; 781 break; 782 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_1G: 783 mii->mii_media_active |= IFM_1000_SX; 784 break; 785 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_25G: 786 mii->mii_media_active |= IFM_2500_SX; 787 break; 788 default: 789 mii->mii_media_active |= IFM_NONE; 790 mii->mii_media_status = 0; 791 break; 792 } 793 794 if (auxsts & BRGPHY_GP_STATUS_TOP_ANEG_FDX) 795 mii->mii_media_active |= IFM_FDX; 796 else 797 mii->mii_media_active |= IFM_HDX; 798 799 if (mii->mii_media_active & IFM_FDX) 800 mii->mii_media_active |= mii_phy_flowstatus(sc); 801 } else 802 mii->mii_media_active = ife->ifm_media; 803 } 804 805 int 806 brgphy_mii_phy_auto(struct mii_softc *sc) 807 { 808 uint16_t anar, ktcr = 0; 809 810 sc->mii_ticks = 0; 811 brgphy_loop(sc); 812 PHY_RESET(sc); 813 814 if (sc->mii_flags & MIIF_HAVEFIBER) { 815 anar = ANAR_X_FD | ANAR_X_HD; 816 if (sc->mii_flags & MIIF_DOPAUSE) 817 anar |= ANAR_X_PAUSE_TOWARDS; 818 } else { 819 anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA; 820 if (sc->mii_flags & MIIF_DOPAUSE) 821 anar |= ANAR_FC | ANAR_PAUSE_ASYM; 822 ktcr = GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX; 823 if ((sc->mii_mpd_oui == MII_OUI_BROADCOM) 824 && (sc->mii_mpd_model == MII_MODEL_BROADCOM_BCM5701)) 825 ktcr |= GTCR_MAN_MS | GTCR_ADV_MS; 826 PHY_WRITE(sc, MII_100T2CR, ktcr); 827 } 828 PHY_WRITE(sc, MII_ANAR, anar); 829 830 /* Start autonegotiation */ 831 PHY_WRITE(sc, MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG); 832 PHY_WRITE(sc, BRGPHY_MII_IMR, 0xFF00); 833 834 return (EJUSTRETURN); 835 } 836 837 void 838 brgphy_loop(struct mii_softc *sc) 839 { 840 uint16_t bmsr; 841 int i; 842 843 PHY_WRITE(sc, MII_BMCR, BMCR_LOOP); 844 for (i = 0; i < 15000; i++) { 845 PHY_READ(sc, MII_BMSR, &bmsr); 846 if (!(bmsr & BMSR_LINK)) 847 break; 848 DELAY(10); 849 } 850 } 851 852 static void 853 brgphy_reset(struct mii_softc *sc) 854 { 855 struct brgphy_softc *bsc = device_private(sc->mii_dev); 856 uint16_t reg; 857 858 mii_phy_reset(sc); 859 switch (sc->mii_mpd_oui) { 860 case MII_OUI_BROADCOM: 861 switch (sc->mii_mpd_model) { 862 case MII_MODEL_BROADCOM_BCM5400: 863 brgphy_bcm5401_dspcode(sc); 864 break; 865 case MII_MODEL_BROADCOM_BCM5401: 866 if (sc->mii_mpd_rev == 1 || sc->mii_mpd_rev == 3) 867 brgphy_bcm5401_dspcode(sc); 868 break; 869 case MII_MODEL_BROADCOM_BCM5411: 870 brgphy_bcm5411_dspcode(sc); 871 break; 872 case MII_MODEL_BROADCOM_BCM5421: 873 brgphy_bcm5421_dspcode(sc); 874 break; 875 case MII_MODEL_BROADCOM_BCM54K2: 876 brgphy_bcm54k2_dspcode(sc); 877 break; 878 } 879 break; 880 case MII_OUI_BROADCOM3: 881 switch (sc->mii_mpd_model) { 882 case MII_MODEL_BROADCOM3_BCM5717C: 883 case MII_MODEL_BROADCOM3_BCM5719C: 884 case MII_MODEL_BROADCOM3_BCM5720C: 885 case MII_MODEL_BROADCOM3_BCM57765: 886 return; 887 } 888 break; 889 default: 890 break; 891 } 892 893 /* Handle any bge (NetXtreme/NetLink) workarounds. */ 894 if (bsc->sc_isbge) { 895 if (!(sc->mii_flags & MIIF_HAVEFIBER)) { 896 897 if (bsc->sc_phyflags & BGEPHYF_ADC_BUG) 898 brgphy_adc_bug(sc); 899 if (bsc->sc_phyflags & BGEPHYF_5704_A0_BUG) 900 brgphy_5704_a0_bug(sc); 901 if (bsc->sc_phyflags & BGEPHYF_BER_BUG) 902 brgphy_ber_bug(sc); 903 else if (bsc->sc_phyflags & BGEPHYF_JITTER_BUG) { 904 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0c00); 905 PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x000a); 906 907 if (bsc->sc_phyflags 908 & BGEPHYF_ADJUST_TRIM) { 909 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, 910 0x110b); 911 PHY_WRITE(sc, BRGPHY_TEST1, 912 BRGPHY_TEST1_TRIM_EN | 0x4); 913 } else { 914 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, 915 0x010b); 916 } 917 918 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0400); 919 } 920 if (bsc->sc_phyflags & BGEPHYF_CRC_BUG) 921 brgphy_crc_bug(sc); 922 923 /* Set Jumbo frame settings in the PHY. */ 924 if (bsc->sc_phyflags & BGEPHYF_JUMBO_CAPABLE) 925 brgphy_jumbo_settings(sc); 926 927 /* Adjust output voltage */ 928 if ((sc->mii_mpd_oui == MII_OUI_BROADCOM2) 929 && (sc->mii_mpd_model == MII_MODEL_BROADCOM2_BCM5906)) 930 PHY_WRITE(sc, BRGPHY_MII_EPHY_PTEST, 0x12); 931 932 /* Enable Ethernet@Wirespeed */ 933 if (!(bsc->sc_phyflags & BGEPHYF_NO_WIRESPEED)) 934 brgphy_eth_wirespeed(sc); 935 936 #if 0 937 /* Enable Link LED on Dell boxes */ 938 if (bsc->sc_phyflags & BGEPHYF_NO_3LED) { 939 PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL, ®); 940 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 941 reg & ~BRGPHY_PHY_EXTCTL_3_LED); 942 } 943 #endif 944 } 945 /* Handle any bnx (NetXtreme II) workarounds. */ 946 } else if (bsc->sc_isbnx) { 947 if ((sc->mii_mpd_oui == MII_OUI_BROADCOM2) 948 && sc->mii_mpd_model == MII_MODEL_BROADCOM2_BCM5708S) { 949 /* Store autoneg capabilities/results in digital block (Page 0) */ 950 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG3_PG2); 951 PHY_WRITE(sc, BRGPHY_5708S_PG2_DIGCTL_3_0, 952 BRGPHY_5708S_PG2_DIGCTL_3_0_USE_IEEE); 953 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0); 954 955 /* Enable fiber mode and autodetection */ 956 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL1, ®); 957 PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL1, reg | 958 BRGPHY_5708S_PG0_1000X_CTL1_AUTODET_EN | 959 BRGPHY_5708S_PG0_1000X_CTL1_FIBER_MODE); 960 961 /* Enable parallel detection */ 962 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL2, ®); 963 PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL2, 964 reg | BRGPHY_5708S_PG0_1000X_CTL2_PAR_DET_EN); 965 966 /* Advertise 2.5G support through next page during autoneg */ 967 if (bsc->sc_phyflags & BNX_PHY_2_5G_CAPABLE_FLAG) { 968 PHY_READ(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1, 969 ®); 970 PHY_WRITE(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1, 971 reg | BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G); 972 } 973 974 /* Increase TX signal amplitude */ 975 if ((_BNX_CHIP_ID(bsc->sc_chipid) == BNX_CHIP_ID_5708_A0) || 976 (_BNX_CHIP_ID(bsc->sc_chipid) == BNX_CHIP_ID_5708_B0) || 977 (_BNX_CHIP_ID(bsc->sc_chipid) == BNX_CHIP_ID_5708_B1)) { 978 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 979 BRGPHY_5708S_TX_MISC_PG5); 980 PHY_READ(sc, BRGPHY_5708S_PG5_TXACTL1, ®); 981 PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL1, 982 reg & ~BRGPHY_5708S_PG5_TXACTL1_VCM); 983 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 984 BRGPHY_5708S_DIG_PG0); 985 } 986 987 /* Backplanes use special driver/pre-driver/pre-emphasis values. */ 988 if ((bsc->sc_shared_hwcfg & BNX_SHARED_HW_CFG_PHY_BACKPLANE) && 989 (bsc->sc_port_hwcfg & BNX_PORT_HW_CFG_CFG_TXCTL3_MASK)) { 990 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 991 BRGPHY_5708S_TX_MISC_PG5); 992 PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL3, 993 bsc->sc_port_hwcfg & 994 BNX_PORT_HW_CFG_CFG_TXCTL3_MASK); 995 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 996 BRGPHY_5708S_DIG_PG0); 997 } 998 } else if ((sc->mii_mpd_oui == MII_OUI_BROADCOM2) 999 && (sc->mii_mpd_model == MII_MODEL_BROADCOM2_BCM5709S)) { 1000 /* Select the SerDes Digital block of the AN MMD. */ 1001 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, 1002 BRGPHY_BLOCK_ADDR_SERDES_DIG); 1003 1004 PHY_READ(sc, BRGPHY_SERDES_DIG_1000X_CTL1, ®); 1005 PHY_WRITE(sc, BRGPHY_SERDES_DIG_1000X_CTL1, 1006 (reg & ~BRGPHY_SD_DIG_1000X_CTL1_AUTODET) | 1007 BRGPHY_SD_DIG_1000X_CTL1_FIBER); 1008 1009 if (bsc->sc_phyflags & BNX_PHY_2_5G_CAPABLE_FLAG) { 1010 /* Select the Over 1G block of the AN MMD. */ 1011 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, 1012 BRGPHY_BLOCK_ADDR_OVER_1G); 1013 1014 /* 1015 * Enable autoneg "Next Page" to advertise 1016 * 2.5G support. 1017 */ 1018 PHY_READ(sc, BRGPHY_OVER_1G_UNFORMAT_PG1, 1019 ®); 1020 PHY_WRITE(sc, BRGPHY_OVER_1G_UNFORMAT_PG1, 1021 reg | BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G); 1022 } 1023 1024 /* 1025 * Select the Multi-Rate Backplane Ethernet block of 1026 * the AN MMD. 1027 */ 1028 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, 1029 BRGPHY_BLOCK_ADDR_MRBE); 1030 1031 /* Enable MRBE speed autoneg. */ 1032 PHY_READ(sc, BRGPHY_MRBE_MSG_PG5_NP, ®); 1033 PHY_WRITE(sc, BRGPHY_MRBE_MSG_PG5_NP, 1034 reg | BRGPHY_MRBE_MSG_PG5_NP_MBRE | 1035 BRGPHY_MRBE_MSG_PG5_NP_T2); 1036 1037 /* Select the Clause 73 User B0 block of the AN MMD. */ 1038 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, 1039 BRGPHY_BLOCK_ADDR_CL73_USER_B0); 1040 1041 /* Enable MRBE speed autoneg. */ 1042 PHY_WRITE(sc, BRGPHY_CL73_USER_B0_MBRE_CTL1, 1043 BRGPHY_CL73_USER_B0_MBRE_CTL1_NP_AFT_BP | 1044 BRGPHY_CL73_USER_B0_MBRE_CTL1_STA_MGR | 1045 BRGPHY_CL73_USER_B0_MBRE_CTL1_ANEG); 1046 1047 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, 1048 BRGPHY_BLOCK_ADDR_COMBO_IEEE0); 1049 1050 } else if (_BNX_CHIP_NUM(bsc->sc_chipid) == BNX_CHIP_NUM_5709) { 1051 if (_BNX_CHIP_REV(bsc->sc_chipid) == BNX_CHIP_REV_Ax || 1052 _BNX_CHIP_REV(bsc->sc_chipid) == BNX_CHIP_REV_Bx) 1053 brgphy_disable_early_dac(sc); 1054 1055 /* Set Jumbo frame settings in the PHY. */ 1056 brgphy_jumbo_settings(sc); 1057 1058 /* Enable Ethernet@Wirespeed */ 1059 brgphy_eth_wirespeed(sc); 1060 } else { 1061 if (!(sc->mii_flags & MIIF_HAVEFIBER)) { 1062 brgphy_ber_bug(sc); 1063 1064 /* Set Jumbo frame settings in the PHY. */ 1065 brgphy_jumbo_settings(sc); 1066 1067 /* Enable Ethernet@Wirespeed */ 1068 brgphy_eth_wirespeed(sc); 1069 } 1070 } 1071 } 1072 } 1073 1074 /* Turn off tap power management on 5401. */ 1075 static void 1076 brgphy_bcm5401_dspcode(struct mii_softc *sc) 1077 { 1078 static const struct { 1079 int reg; 1080 uint16_t val; 1081 } dspcode[] = { 1082 { BRGPHY_MII_AUXCTL, 0x0c20 }, 1083 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 }, 1084 { BRGPHY_MII_DSP_RW_PORT, 0x1804 }, 1085 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 }, 1086 { BRGPHY_MII_DSP_RW_PORT, 0x1204 }, 1087 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 1088 { BRGPHY_MII_DSP_RW_PORT, 0x0132 }, 1089 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 1090 { BRGPHY_MII_DSP_RW_PORT, 0x0232 }, 1091 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 1092 { BRGPHY_MII_DSP_RW_PORT, 0x0a20 }, 1093 { 0, 0 }, 1094 }; 1095 int i; 1096 1097 for (i = 0; dspcode[i].reg != 0; i++) 1098 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 1099 delay(40); 1100 } 1101 1102 static void 1103 brgphy_bcm5411_dspcode(struct mii_softc *sc) 1104 { 1105 static const struct { 1106 int reg; 1107 uint16_t val; 1108 } dspcode[] = { 1109 { 0x1c, 0x8c23 }, 1110 { 0x1c, 0x8ca3 }, 1111 { 0x1c, 0x8c23 }, 1112 { 0, 0 }, 1113 }; 1114 int i; 1115 1116 for (i = 0; dspcode[i].reg != 0; i++) 1117 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 1118 } 1119 1120 void 1121 brgphy_bcm5421_dspcode(struct mii_softc *sc) 1122 { 1123 uint16_t data; 1124 1125 /* Set Class A mode */ 1126 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x1007); 1127 PHY_READ(sc, BRGPHY_MII_AUXCTL, &data); 1128 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, data | 0x0400); 1129 1130 /* Set FFE gamma override to -0.125 */ 1131 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0007); 1132 PHY_READ(sc, BRGPHY_MII_AUXCTL, &data); 1133 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, data | 0x0800); 1134 PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x000a); 1135 PHY_READ(sc, BRGPHY_MII_DSP_RW_PORT, &data); 1136 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, data | 0x0200); 1137 } 1138 1139 void 1140 brgphy_bcm54k2_dspcode(struct mii_softc *sc) 1141 { 1142 static const struct { 1143 int reg; 1144 uint16_t val; 1145 } dspcode[] = { 1146 { 4, 0x01e1 }, 1147 { 9, 0x0300 }, 1148 { 0, 0 }, 1149 }; 1150 int i; 1151 1152 for (i = 0; dspcode[i].reg != 0; i++) 1153 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 1154 } 1155 1156 static void 1157 brgphy_adc_bug(struct mii_softc *sc) 1158 { 1159 static const struct { 1160 int reg; 1161 uint16_t val; 1162 } dspcode[] = { 1163 { BRGPHY_MII_AUXCTL, 0x0c00 }, 1164 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 1165 { BRGPHY_MII_DSP_RW_PORT, 0x2aaa }, 1166 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 1167 { BRGPHY_MII_DSP_RW_PORT, 0x0323 }, 1168 { BRGPHY_MII_AUXCTL, 0x0400 }, 1169 { 0, 0 }, 1170 }; 1171 int i; 1172 1173 for (i = 0; dspcode[i].reg != 0; i++) 1174 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 1175 } 1176 1177 static void 1178 brgphy_5704_a0_bug(struct mii_softc *sc) 1179 { 1180 static const struct { 1181 int reg; 1182 uint16_t val; 1183 } dspcode[] = { 1184 { 0x1c, 0x8d68 }, 1185 { 0x1c, 0x8d68 }, 1186 { 0, 0 }, 1187 }; 1188 int i; 1189 1190 for (i = 0; dspcode[i].reg != 0; i++) 1191 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 1192 } 1193 1194 static void 1195 brgphy_ber_bug(struct mii_softc *sc) 1196 { 1197 static const struct { 1198 int reg; 1199 uint16_t val; 1200 } dspcode[] = { 1201 { BRGPHY_MII_AUXCTL, 0x0c00 }, 1202 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 1203 { BRGPHY_MII_DSP_RW_PORT, 0x310b }, 1204 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 1205 { BRGPHY_MII_DSP_RW_PORT, 0x9506 }, 1206 { BRGPHY_MII_DSP_ADDR_REG, 0x401f }, 1207 { BRGPHY_MII_DSP_RW_PORT, 0x14e2 }, 1208 { BRGPHY_MII_AUXCTL, 0x0400 }, 1209 { 0, 0 }, 1210 }; 1211 int i; 1212 1213 for (i = 0; dspcode[i].reg != 0; i++) 1214 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 1215 } 1216 1217 /* BCM5701 A0/B0 CRC bug workaround */ 1218 void 1219 brgphy_crc_bug(struct mii_softc *sc) 1220 { 1221 static const struct { 1222 int reg; 1223 uint16_t val; 1224 } dspcode[] = { 1225 { BRGPHY_MII_DSP_ADDR_REG, 0x0a75 }, 1226 { 0x1c, 0x8c68 }, 1227 { 0x1c, 0x8d68 }, 1228 { 0x1c, 0x8c68 }, 1229 { 0, 0 }, 1230 }; 1231 int i; 1232 1233 for (i = 0; dspcode[i].reg != 0; i++) 1234 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 1235 } 1236 1237 static void 1238 brgphy_disable_early_dac(struct mii_softc *sc) 1239 { 1240 uint16_t val; 1241 1242 PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x0f08); 1243 PHY_READ(sc, BRGPHY_MII_DSP_RW_PORT, &val); 1244 val &= ~(1 << 8); 1245 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, val); 1246 1247 } 1248 1249 static void 1250 brgphy_jumbo_settings(struct mii_softc *sc) 1251 { 1252 uint16_t val; 1253 1254 /* Set Jumbo frame settings in the PHY. */ 1255 if ((sc->mii_mpd_oui == MII_OUI_BROADCOM) 1256 && (sc->mii_mpd_model == MII_MODEL_BROADCOM_BCM5401)) { 1257 /* Cannot do read-modify-write on the BCM5401 */ 1258 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x4c20); 1259 } else { 1260 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7); 1261 PHY_READ(sc, BRGPHY_MII_AUXCTL, &val); 1262 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 1263 val & ~(BRGPHY_AUXCTL_LONG_PKT | 0x7)); 1264 } 1265 1266 PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL, &val); 1267 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, val & ~BRGPHY_PHY_EXTCTL_HIGH_LA); 1268 } 1269 1270 static void 1271 brgphy_eth_wirespeed(struct mii_softc *sc) 1272 { 1273 uint16_t val; 1274 1275 /* Enable Ethernet@Wirespeed */ 1276 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007); 1277 PHY_READ(sc, BRGPHY_MII_AUXCTL, &val); 1278 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, val | (1 << 15) | (1 << 4)); 1279 } 1280
Indexes created Tue Oct 21 08:09:48 GMT 2025