brgphy.c revision 1.81
1 /* $NetBSD: brgphy.c,v 1.81 2019/02/24 17:22:21 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2000, 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1997 Manuel Bouyer. All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 45 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 46 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 47 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 48 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 49 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 50 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 51 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 52 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 53 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 54 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 55 */ 56 57 /* 58 * driver for the Broadcom BCM5400 and BCM5700 Gig-E PHYs. 59 * 60 * Programming information for this PHY was gleaned from FreeBSD 61 * (they were apparently able to get a datasheet from Broadcom). 62 */ 63 64 #include <sys/cdefs.h> 65 __KERNEL_RCSID(0, "$NetBSD: brgphy.c,v 1.81 2019/02/24 17:22:21 christos Exp $"); 66 67 #include <sys/param.h> 68 #include <sys/systm.h> 69 #include <sys/kernel.h> 70 #include <sys/device.h> 71 #include <sys/socket.h> 72 #include <sys/errno.h> 73 #include <prop/proplib.h> 74 75 #include <net/if.h> 76 #include <net/if_media.h> 77 78 #include <dev/mii/mii.h> 79 #include <dev/mii/miivar.h> 80 #include <dev/mii/miidevs.h> 81 #include <dev/mii/brgphyreg.h> 82 83 #include <dev/pci/if_bgereg.h> 84 #include <dev/pci/if_bnxreg.h> 85 86 static int brgphymatch(device_t, cfdata_t, void *); 87 static void brgphyattach(device_t, device_t, void *); 88 89 struct brgphy_softc { 90 struct mii_softc sc_mii; 91 bool sc_isbge; 92 bool sc_isbnx; 93 uint32_t sc_chipid; /* parent's chipid */ 94 uint32_t sc_phyflags; /* parent's phyflags */ 95 uint32_t sc_shared_hwcfg; /* shared hw config */ 96 uint32_t sc_port_hwcfg; /* port specific hw config */ 97 }; 98 99 CFATTACH_DECL3_NEW(brgphy, sizeof(struct brgphy_softc), 100 brgphymatch, brgphyattach, mii_phy_detach, mii_phy_activate, NULL, NULL, 101 DVF_DETACH_SHUTDOWN); 102 103 static int brgphy_service(struct mii_softc *, struct mii_data *, int); 104 static void brgphy_copper_status(struct mii_softc *); 105 static void brgphy_fiber_status(struct mii_softc *); 106 static void brgphy_5708s_status(struct mii_softc *); 107 static void brgphy_5709s_status(struct mii_softc *); 108 static int brgphy_mii_phy_auto(struct mii_softc *); 109 static void brgphy_loop(struct mii_softc *); 110 static void brgphy_reset(struct mii_softc *); 111 static void brgphy_bcm5401_dspcode(struct mii_softc *); 112 static void brgphy_bcm5411_dspcode(struct mii_softc *); 113 static void brgphy_bcm5421_dspcode(struct mii_softc *); 114 static void brgphy_bcm54k2_dspcode(struct mii_softc *); 115 static void brgphy_adc_bug(struct mii_softc *); 116 static void brgphy_5704_a0_bug(struct mii_softc *); 117 static void brgphy_ber_bug(struct mii_softc *); 118 static void brgphy_crc_bug(struct mii_softc *); 119 static void brgphy_disable_early_dac(struct mii_softc *); 120 static void brgphy_jumbo_settings(struct mii_softc *); 121 static void brgphy_eth_wirespeed(struct mii_softc *); 122 123 124 static const struct mii_phy_funcs brgphy_copper_funcs = { 125 brgphy_service, brgphy_copper_status, brgphy_reset, 126 }; 127 128 static const struct mii_phy_funcs brgphy_fiber_funcs = { 129 brgphy_service, brgphy_fiber_status, brgphy_reset, 130 }; 131 132 static const struct mii_phy_funcs brgphy_5708s_funcs = { 133 brgphy_service, brgphy_5708s_status, brgphy_reset, 134 }; 135 136 static const struct mii_phy_funcs brgphy_5709s_funcs = { 137 brgphy_service, brgphy_5709s_status, brgphy_reset, 138 }; 139 140 static const struct mii_phydesc brgphys[] = { 141 MII_PHY_DESC(BROADCOM, BCM5400), 142 MII_PHY_DESC(BROADCOM, BCM5401), 143 MII_PHY_DESC(BROADCOM, BCM5411), 144 MII_PHY_DESC(BROADCOM, BCM5421), 145 MII_PHY_DESC(BROADCOM, BCM5462), 146 MII_PHY_DESC(BROADCOM, BCM5461), 147 MII_PHY_DESC(BROADCOM, BCM54K2), 148 MII_PHY_DESC(BROADCOM, BCM5464), 149 MII_PHY_DESC(BROADCOM, BCM5701), 150 MII_PHY_DESC(BROADCOM, BCM5703), 151 MII_PHY_DESC(BROADCOM, BCM5704), 152 MII_PHY_DESC(BROADCOM, BCM5705), 153 MII_PHY_DESC(BROADCOM, BCM5706), 154 MII_PHY_DESC(BROADCOM, BCM5714), 155 MII_PHY_DESC(BROADCOM, BCM5750), 156 MII_PHY_DESC(BROADCOM, BCM5752), 157 MII_PHY_DESC(BROADCOM, BCM5780), 158 MII_PHY_DESC(BROADCOM, BCM5708C), 159 MII_PHY_DESC(BROADCOM2, BCM5481), 160 MII_PHY_DESC(BROADCOM2, BCM5482), 161 MII_PHY_DESC(BROADCOM2, BCM5708S), 162 MII_PHY_DESC(BROADCOM2, BCM5709C), 163 MII_PHY_DESC(BROADCOM2, BCM5709S), 164 MII_PHY_DESC(BROADCOM2, BCM5709CAX), 165 MII_PHY_DESC(BROADCOM2, BCM5722), 166 MII_PHY_DESC(BROADCOM2, BCM5754), 167 MII_PHY_DESC(BROADCOM2, BCM5755), 168 MII_PHY_DESC(BROADCOM2, BCM5756), 169 MII_PHY_DESC(BROADCOM2, BCM5761), 170 MII_PHY_DESC(BROADCOM2, BCM5784), 171 MII_PHY_DESC(BROADCOM2, BCM5785), 172 MII_PHY_DESC(BROADCOM3, BCM5717C), 173 MII_PHY_DESC(BROADCOM3, BCM5719C), 174 MII_PHY_DESC(BROADCOM3, BCM5720C), 175 MII_PHY_DESC(BROADCOM3, BCM57765), 176 MII_PHY_DESC(BROADCOM3, BCM57780), 177 MII_PHY_DESC(BROADCOM4, BCM5725C), 178 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5906), 179 MII_PHY_END, 180 }; 181 182 static int 183 brgphymatch(device_t parent, cfdata_t match, void *aux) 184 { 185 struct mii_attach_args *ma = aux; 186 187 if (mii_phy_match(ma, brgphys) != NULL) 188 return (10); 189 190 return (0); 191 } 192 193 static void 194 brgphyattach(device_t parent, device_t self, void *aux) 195 { 196 struct brgphy_softc *bsc = device_private(self); 197 struct mii_softc *sc = &bsc->sc_mii; 198 struct mii_attach_args *ma = aux; 199 struct mii_data *mii = ma->mii_data; 200 const struct mii_phydesc *mpd; 201 prop_dictionary_t dict; 202 203 mpd = mii_phy_match(ma, brgphys); 204 aprint_naive(": Media interface\n"); 205 aprint_normal(": %s, rev. %d\n", mpd->mpd_name, MII_REV(ma->mii_id2)); 206 207 sc->mii_dev = self; 208 sc->mii_inst = mii->mii_instance; 209 sc->mii_phy = ma->mii_phyno; 210 sc->mii_mpd_oui = MII_OUI(ma->mii_id1, ma->mii_id2); 211 sc->mii_mpd_model = MII_MODEL(ma->mii_id2); 212 sc->mii_mpd_rev = MII_REV(ma->mii_id2); 213 sc->mii_pdata = mii; 214 sc->mii_flags = ma->mii_flags; 215 sc->mii_anegticks = MII_ANEGTICKS; 216 217 if (device_is_a(parent, "bge")) 218 bsc->sc_isbge = true; 219 else if (device_is_a(parent, "bnx")) 220 bsc->sc_isbnx = true; 221 222 dict = device_properties(parent); 223 if (bsc->sc_isbge || bsc->sc_isbnx) { 224 if (!prop_dictionary_get_uint32(dict, "phyflags", 225 &bsc->sc_phyflags)) 226 aprint_error_dev(self, "failed to get phyflags\n"); 227 if (!prop_dictionary_get_uint32(dict, "chipid", 228 &bsc->sc_chipid)) 229 aprint_error_dev(self, "failed to get chipid\n"); 230 } 231 232 if (bsc->sc_isbnx) { 233 /* Currently, only bnx use sc_shared_hwcfg and sc_port_hwcfg */ 234 if (!prop_dictionary_get_uint32(dict, "shared_hwcfg", 235 &bsc->sc_shared_hwcfg)) 236 aprint_error_dev(self, "failed to get shared_hwcfg\n"); 237 if (!prop_dictionary_get_uint32(dict, "port_hwcfg", 238 &bsc->sc_port_hwcfg)) 239 aprint_error_dev(self, "failed to get port_hwcfg\n"); 240 } 241 242 if (sc->mii_flags & MIIF_HAVEFIBER) { 243 if ((sc->mii_mpd_oui == MII_OUI_BROADCOM2) 244 && sc->mii_mpd_model == MII_MODEL_BROADCOM2_BCM5708S) 245 sc->mii_funcs = &brgphy_5708s_funcs; 246 else if ((sc->mii_mpd_oui == MII_OUI_BROADCOM2) 247 && (sc->mii_mpd_model == MII_MODEL_BROADCOM2_BCM5709S)) { 248 if (bsc->sc_isbnx) 249 sc->mii_funcs = &brgphy_5709s_funcs; 250 else { 251 /* 252 * XXX 253 * 5720S and 5709S shares the same PHY id. 254 * Assume 5720S PHY if parent device is bge(4). 255 */ 256 sc->mii_funcs = &brgphy_5708s_funcs; 257 } 258 } else 259 sc->mii_funcs = &brgphy_fiber_funcs; 260 } else 261 sc->mii_funcs = &brgphy_copper_funcs; 262 263 PHY_RESET(sc); 264 265 PHY_READ(sc, MII_BMSR, &sc->mii_capabilities); 266 sc->mii_capabilities &= ma->mii_capmask; 267 if (sc->mii_capabilities & BMSR_EXTSTAT) 268 PHY_READ(sc, MII_EXTSR, &sc->mii_extcapabilities); 269 270 aprint_normal_dev(self, ""); 271 if (sc->mii_flags & MIIF_HAVEFIBER) { 272 sc->mii_flags |= MIIF_NOISOLATE | MIIF_NOLOOP; 273 274 /* 275 * Set the proper bits for capabilities so that the 276 * correct media get selected by mii_phy_add_media() 277 */ 278 sc->mii_capabilities |= BMSR_ANEG; 279 sc->mii_capabilities &= ~BMSR_100T4; 280 sc->mii_extcapabilities |= EXTSR_1000XFDX; 281 282 if (bsc->sc_isbnx) { 283 /* 284 * 2.5Gb support is a software enabled feature 285 * on the BCM5708S and BCM5709S controllers. 286 */ 287 #define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL) 288 if (bsc->sc_phyflags 289 & BNX_PHY_2_5G_CAPABLE_FLAG) { 290 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_2500_SX, 291 IFM_FDX, sc->mii_inst), 0); 292 aprint_normal("2500baseSX-FDX, "); 293 #undef ADD 294 } 295 } 296 } 297 mii_phy_add_media(sc); 298 299 aprint_normal("\n"); 300 } 301 302 static int 303 brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 304 { 305 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 306 uint16_t reg, speed, gig; 307 308 switch (cmd) { 309 case MII_POLLSTAT: 310 /* If we're not polling our PHY instance, just return. */ 311 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 312 return (0); 313 break; 314 315 case MII_MEDIACHG: 316 /* 317 * If the media indicates a different PHY instance, 318 * isolate ourselves. 319 */ 320 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 321 PHY_READ(sc, MII_BMCR, ®); 322 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO); 323 return (0); 324 } 325 326 /* If the interface is not up, don't do anything. */ 327 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 328 break; 329 330 PHY_RESET(sc); /* XXX hardware bug work-around */ 331 332 switch (IFM_SUBTYPE(ife->ifm_media)) { 333 case IFM_AUTO: 334 (void) brgphy_mii_phy_auto(sc); 335 break; 336 case IFM_2500_SX: 337 speed = BRGPHY_5708S_BMCR_2500; 338 goto setit; 339 case IFM_1000_SX: 340 case IFM_1000_T: 341 speed = BMCR_S1000; 342 goto setit; 343 case IFM_100_TX: 344 speed = BMCR_S100; 345 goto setit; 346 case IFM_10_T: 347 speed = BMCR_S10; 348 setit: 349 brgphy_loop(sc); 350 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 351 speed |= BMCR_FDX; 352 gig = GTCR_ADV_1000TFDX; 353 } else 354 gig = GTCR_ADV_1000THDX; 355 356 PHY_WRITE(sc, MII_100T2CR, 0); 357 PHY_WRITE(sc, MII_ANAR, ANAR_CSMA); 358 PHY_WRITE(sc, MII_BMCR, speed); 359 360 if ((IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T) && 361 (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_SX) && 362 (IFM_SUBTYPE(ife->ifm_media) != IFM_2500_SX)) 363 break; 364 365 PHY_WRITE(sc, MII_100T2CR, gig); 366 PHY_WRITE(sc, MII_BMCR, 367 speed | BMCR_AUTOEN | BMCR_STARTNEG); 368 369 if ((sc->mii_mpd_oui != MII_OUI_BROADCOM) 370 || (sc->mii_mpd_model != MII_MODEL_BROADCOM_BCM5701)) 371 break; 372 373 if (mii->mii_media.ifm_media & IFM_ETH_MASTER) 374 gig |= GTCR_MAN_MS | GTCR_ADV_MS; 375 PHY_WRITE(sc, MII_100T2CR, gig); 376 break; 377 default: 378 return (EINVAL); 379 } 380 break; 381 382 case MII_TICK: 383 /* If we're not currently selected, just return. */ 384 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 385 return (0); 386 387 /* Is the interface even up? */ 388 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 389 return 0; 390 391 /* Only used for autonegotiation. */ 392 if ((IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) && 393 (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T)) { 394 sc->mii_ticks = 0; 395 break; 396 } 397 398 /* 399 * Check for link. 400 * Read the status register twice; BMSR_LINK is latch-low. 401 */ 402 PHY_READ(sc, MII_BMSR, ®); 403 PHY_READ(sc, MII_BMSR, ®); 404 if (reg & BMSR_LINK) { 405 sc->mii_ticks = 0; 406 break; 407 } 408 409 /* 410 * mii_ticks == 0 means it's the first tick after changing the 411 * media or the link became down since the last tick 412 * (see above), so break to update the status. 413 */ 414 if (sc->mii_ticks++ == 0) 415 break; 416 417 /* Only retry autonegotiation every mii_anegticks seconds. */ 418 KASSERT(sc->mii_anegticks != 0); 419 if (sc->mii_ticks <= sc->mii_anegticks) 420 break; 421 422 brgphy_mii_phy_auto(sc); 423 break; 424 425 case MII_DOWN: 426 mii_phy_down(sc); 427 return (0); 428 } 429 430 /* Update the media status. */ 431 mii_phy_status(sc); 432 433 /* 434 * Callback if something changed. Note that we need to poke the DSP on 435 * the Broadcom PHYs if the media changes. 436 */ 437 if (sc->mii_media_active != mii->mii_media_active || 438 sc->mii_media_status != mii->mii_media_status || 439 cmd == MII_MEDIACHG) { 440 switch (sc->mii_mpd_oui) { 441 case MII_OUI_BROADCOM: 442 switch (sc->mii_mpd_model) { 443 case MII_MODEL_BROADCOM_BCM5400: 444 brgphy_bcm5401_dspcode(sc); 445 break; 446 case MII_MODEL_BROADCOM_BCM5401: 447 if (sc->mii_mpd_rev == 1 || sc->mii_mpd_rev == 3) 448 brgphy_bcm5401_dspcode(sc); 449 break; 450 case MII_MODEL_BROADCOM_BCM5411: 451 brgphy_bcm5411_dspcode(sc); 452 break; 453 } 454 break; 455 } 456 } 457 458 /* Callback if something changed. */ 459 mii_phy_update(sc, cmd); 460 return (0); 461 } 462 463 static void 464 brgphy_copper_status(struct mii_softc *sc) 465 { 466 struct mii_data *mii = sc->mii_pdata; 467 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 468 uint16_t bmcr, bmsr, auxsts, gtsr; 469 470 mii->mii_media_status = IFM_AVALID; 471 mii->mii_media_active = IFM_ETHER; 472 473 PHY_READ(sc, MII_BMSR, &bmsr); 474 PHY_READ(sc, MII_BMSR, &bmsr); 475 if (bmsr & BMSR_LINK) 476 mii->mii_media_status |= IFM_ACTIVE; 477 478 PHY_READ(sc, MII_BMCR, &bmcr); 479 if (bmcr & BMCR_ISO) { 480 mii->mii_media_active |= IFM_NONE; 481 mii->mii_media_status = 0; 482 return; 483 } 484 485 if (bmcr & BMCR_LOOP) 486 mii->mii_media_active |= IFM_LOOP; 487 488 if (bmcr & BMCR_AUTOEN) { 489 /* 490 * The media status bits are only valid of autonegotiation 491 * has completed (or it's disabled). 492 */ 493 if ((bmsr & BMSR_ACOMP) == 0) { 494 /* Erg, still trying, I guess... */ 495 mii->mii_media_active |= IFM_NONE; 496 return; 497 } 498 499 PHY_READ(sc, BRGPHY_MII_AUXSTS, &auxsts); 500 501 switch (auxsts & BRGPHY_AUXSTS_AN_RES) { 502 case BRGPHY_RES_1000FD: 503 mii->mii_media_active |= IFM_1000_T | IFM_FDX; 504 PHY_READ(sc, MII_100T2SR, >sr); 505 if (gtsr & GTSR_MS_RES) 506 mii->mii_media_active |= IFM_ETH_MASTER; 507 break; 508 509 case BRGPHY_RES_1000HD: 510 mii->mii_media_active |= IFM_1000_T | IFM_HDX; 511 PHY_READ(sc, MII_100T2SR, >sr); 512 if (gtsr & GTSR_MS_RES) 513 mii->mii_media_active |= IFM_ETH_MASTER; 514 break; 515 516 case BRGPHY_RES_100FD: 517 mii->mii_media_active |= IFM_100_TX | IFM_FDX; 518 break; 519 520 case BRGPHY_RES_100T4: 521 mii->mii_media_active |= IFM_100_T4 | IFM_HDX; 522 break; 523 524 case BRGPHY_RES_100HD: 525 mii->mii_media_active |= IFM_100_TX | IFM_HDX; 526 break; 527 528 case BRGPHY_RES_10FD: 529 mii->mii_media_active |= IFM_10_T | IFM_FDX; 530 break; 531 532 case BRGPHY_RES_10HD: 533 mii->mii_media_active |= IFM_10_T | IFM_HDX; 534 break; 535 536 default: 537 mii->mii_media_active |= IFM_NONE; 538 mii->mii_media_status = 0; 539 } 540 541 if (mii->mii_media_active & IFM_FDX) 542 mii->mii_media_active |= mii_phy_flowstatus(sc); 543 544 } else 545 mii->mii_media_active = ife->ifm_media; 546 } 547 548 void 549 brgphy_fiber_status(struct mii_softc *sc) 550 { 551 struct mii_data *mii = sc->mii_pdata; 552 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 553 uint16_t bmcr, bmsr, anar, anlpar, result; 554 555 mii->mii_media_status = IFM_AVALID; 556 mii->mii_media_active = IFM_ETHER; 557 558 PHY_READ(sc, MII_BMSR, &bmsr); 559 PHY_READ(sc, MII_BMSR, &bmsr); 560 if (bmsr & BMSR_LINK) 561 mii->mii_media_status |= IFM_ACTIVE; 562 563 PHY_READ(sc, MII_BMCR, &bmcr); 564 if (bmcr & BMCR_LOOP) 565 mii->mii_media_active |= IFM_LOOP; 566 567 if (bmcr & BMCR_AUTOEN) { 568 if ((bmsr & BMSR_ACOMP) == 0) { 569 /* Erg, still trying, I guess... */ 570 mii->mii_media_active |= IFM_NONE; 571 return; 572 } 573 574 mii->mii_media_active |= IFM_1000_SX; 575 576 PHY_READ(sc, MII_ANAR, &anar); 577 PHY_READ(sc, MII_ANLPAR, &anlpar); 578 result = anar & anlpar; 579 580 if (result & ANAR_X_FD) 581 mii->mii_media_active |= IFM_FDX; 582 else 583 mii->mii_media_active |= IFM_HDX; 584 585 if (mii->mii_media_active & IFM_FDX) 586 mii->mii_media_active |= mii_phy_flowstatus(sc); 587 } else 588 mii->mii_media_active = ife->ifm_media; 589 } 590 591 void 592 brgphy_5708s_status(struct mii_softc *sc) 593 { 594 struct mii_data *mii = sc->mii_pdata; 595 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 596 uint16_t bmcr, bmsr; 597 598 mii->mii_media_status = IFM_AVALID; 599 mii->mii_media_active = IFM_ETHER; 600 601 PHY_READ(sc, MII_BMSR, &bmsr); 602 PHY_READ(sc, MII_BMSR, &bmsr); 603 if (bmsr & BMSR_LINK) 604 mii->mii_media_status |= IFM_ACTIVE; 605 606 PHY_READ(sc, MII_BMCR, &bmcr); 607 if (bmcr & BMCR_LOOP) 608 mii->mii_media_active |= IFM_LOOP; 609 610 if (bmcr & BMCR_AUTOEN) { 611 uint16_t xstat; 612 613 if ((bmsr & BMSR_ACOMP) == 0) { 614 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 615 BRGPHY_5708S_DIG_PG0); 616 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_STAT1, &xstat); 617 if ((xstat & BRGPHY_5708S_PG0_1000X_STAT1_LINK) == 0) { 618 /* Erg, still trying, I guess... */ 619 mii->mii_media_active |= IFM_NONE; 620 return; 621 } 622 } 623 624 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 625 BRGPHY_5708S_DIG_PG0); 626 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_STAT1, &xstat); 627 628 switch (xstat & BRGPHY_5708S_PG0_1000X_STAT1_SPEED_MASK) { 629 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_10: 630 mii->mii_media_active |= IFM_10_FL; 631 break; 632 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_100: 633 mii->mii_media_active |= IFM_100_FX; 634 break; 635 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_1G: 636 mii->mii_media_active |= IFM_1000_SX; 637 break; 638 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_25G: 639 mii->mii_media_active |= IFM_2500_SX; 640 break; 641 } 642 643 if (xstat & BRGPHY_5708S_PG0_1000X_STAT1_FDX) 644 mii->mii_media_active |= IFM_FDX; 645 else 646 mii->mii_media_active |= IFM_HDX; 647 648 if (mii->mii_media_active & IFM_FDX) { 649 if (xstat & BRGPHY_5708S_PG0_1000X_STAT1_TX_PAUSE) 650 mii->mii_media_active |= IFM_FLOW | IFM_ETH_TXPAUSE; 651 if (xstat & BRGPHY_5708S_PG0_1000X_STAT1_RX_PAUSE) 652 mii->mii_media_active |= IFM_FLOW | IFM_ETH_RXPAUSE; 653 } 654 } else 655 mii->mii_media_active = ife->ifm_media; 656 } 657 658 static void 659 brgphy_5709s_status(struct mii_softc *sc) 660 { 661 struct mii_data *mii = sc->mii_pdata; 662 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 663 uint16_t bmcr, bmsr, auxsts; 664 665 mii->mii_media_status = IFM_AVALID; 666 mii->mii_media_active = IFM_ETHER; 667 668 PHY_READ(sc, MII_BMSR, &bmsr); 669 PHY_READ(sc, MII_BMSR, &bmsr); 670 if (bmsr & BMSR_LINK) 671 mii->mii_media_status |= IFM_ACTIVE; 672 673 PHY_READ(sc, MII_BMCR, &bmcr); 674 if (bmcr & BMCR_ISO) { 675 mii->mii_media_active |= IFM_NONE; 676 mii->mii_media_status = 0; 677 return; 678 } 679 680 if (bmcr & BMCR_LOOP) 681 mii->mii_media_active |= IFM_LOOP; 682 683 if (bmcr & BMCR_AUTOEN) { 684 /* 685 * The media status bits are only valid of autonegotiation 686 * has completed (or it's disabled). 687 */ 688 if ((bmsr & BMSR_ACOMP) == 0) { 689 /* Erg, still trying, I guess... */ 690 mii->mii_media_active |= IFM_NONE; 691 return; 692 } 693 694 /* 5709S has its own general purpose status registers */ 695 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_GP_STATUS); 696 PHY_READ(sc, BRGPHY_GP_STATUS_TOP_ANEG_STATUS, &auxsts); 697 698 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, 699 BRGPHY_BLOCK_ADDR_COMBO_IEEE0); 700 701 switch (auxsts & BRGPHY_GP_STATUS_TOP_ANEG_SPEED_MASK) { 702 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_10: 703 mii->mii_media_active |= IFM_10_FL; 704 break; 705 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_100: 706 mii->mii_media_active |= IFM_100_FX; 707 break; 708 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_1G: 709 mii->mii_media_active |= IFM_1000_SX; 710 break; 711 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_25G: 712 mii->mii_media_active |= IFM_2500_SX; 713 break; 714 default: 715 mii->mii_media_active |= IFM_NONE; 716 mii->mii_media_status = 0; 717 break; 718 } 719 720 if (auxsts & BRGPHY_GP_STATUS_TOP_ANEG_FDX) 721 mii->mii_media_active |= IFM_FDX; 722 else 723 mii->mii_media_active |= IFM_HDX; 724 725 if (mii->mii_media_active & IFM_FDX) 726 mii->mii_media_active |= mii_phy_flowstatus(sc); 727 } else 728 mii->mii_media_active = ife->ifm_media; 729 } 730 731 int 732 brgphy_mii_phy_auto(struct mii_softc *sc) 733 { 734 uint16_t anar, ktcr = 0; 735 736 sc->mii_ticks = 0; 737 brgphy_loop(sc); 738 PHY_RESET(sc); 739 740 if (sc->mii_flags & MIIF_HAVEFIBER) { 741 anar = ANAR_X_FD | ANAR_X_HD; 742 if (sc->mii_flags & MIIF_DOPAUSE) 743 anar |= ANAR_X_PAUSE_TOWARDS; 744 } else { 745 anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA; 746 if (sc->mii_flags & MIIF_DOPAUSE) 747 anar |= ANAR_FC | ANAR_PAUSE_ASYM; 748 ktcr = GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX; 749 if ((sc->mii_mpd_oui == MII_OUI_BROADCOM) 750 && (sc->mii_mpd_model == MII_MODEL_BROADCOM_BCM5701)) 751 ktcr |= GTCR_MAN_MS | GTCR_ADV_MS; 752 PHY_WRITE(sc, MII_100T2CR, ktcr); 753 } 754 PHY_WRITE(sc, MII_ANAR, anar); 755 756 /* Start autonegotiation */ 757 PHY_WRITE(sc, MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG); 758 PHY_WRITE(sc, BRGPHY_MII_IMR, 0xFF00); 759 760 return (EJUSTRETURN); 761 } 762 763 void 764 brgphy_loop(struct mii_softc *sc) 765 { 766 uint16_t bmsr; 767 int i; 768 769 PHY_WRITE(sc, MII_BMCR, BMCR_LOOP); 770 for (i = 0; i < 15000; i++) { 771 PHY_READ(sc, MII_BMSR, &bmsr); 772 if (!(bmsr & BMSR_LINK)) 773 break; 774 DELAY(10); 775 } 776 } 777 778 static void 779 brgphy_reset(struct mii_softc *sc) 780 { 781 struct brgphy_softc *bsc = device_private(sc->mii_dev); 782 uint16_t reg; 783 784 mii_phy_reset(sc); 785 switch (sc->mii_mpd_oui) { 786 case MII_OUI_BROADCOM: 787 switch (sc->mii_mpd_model) { 788 case MII_MODEL_BROADCOM_BCM5400: 789 brgphy_bcm5401_dspcode(sc); 790 break; 791 case MII_MODEL_BROADCOM_BCM5401: 792 if (sc->mii_mpd_rev == 1 || sc->mii_mpd_rev == 3) 793 brgphy_bcm5401_dspcode(sc); 794 break; 795 case MII_MODEL_BROADCOM_BCM5411: 796 brgphy_bcm5411_dspcode(sc); 797 break; 798 case MII_MODEL_BROADCOM_BCM5421: 799 brgphy_bcm5421_dspcode(sc); 800 break; 801 case MII_MODEL_BROADCOM_BCM54K2: 802 brgphy_bcm54k2_dspcode(sc); 803 break; 804 } 805 break; 806 case MII_OUI_BROADCOM3: 807 switch (sc->mii_mpd_model) { 808 case MII_MODEL_BROADCOM3_BCM5717C: 809 case MII_MODEL_BROADCOM3_BCM5719C: 810 case MII_MODEL_BROADCOM3_BCM5720C: 811 case MII_MODEL_BROADCOM3_BCM57765: 812 return; 813 } 814 break; 815 default: 816 break; 817 } 818 819 /* Handle any bge (NetXtreme/NetLink) workarounds. */ 820 if (bsc->sc_isbge) { 821 if (!(sc->mii_flags & MIIF_HAVEFIBER)) { 822 823 if (bsc->sc_phyflags & BGEPHYF_ADC_BUG) 824 brgphy_adc_bug(sc); 825 if (bsc->sc_phyflags & BGEPHYF_5704_A0_BUG) 826 brgphy_5704_a0_bug(sc); 827 if (bsc->sc_phyflags & BGEPHYF_BER_BUG) 828 brgphy_ber_bug(sc); 829 else if (bsc->sc_phyflags & BGEPHYF_JITTER_BUG) { 830 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0c00); 831 PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x000a); 832 833 if (bsc->sc_phyflags 834 & BGEPHYF_ADJUST_TRIM) { 835 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, 836 0x110b); 837 PHY_WRITE(sc, BRGPHY_TEST1, 838 BRGPHY_TEST1_TRIM_EN | 0x4); 839 } else { 840 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, 841 0x010b); 842 } 843 844 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0400); 845 } 846 if (bsc->sc_phyflags & BGEPHYF_CRC_BUG) 847 brgphy_crc_bug(sc); 848 849 /* Set Jumbo frame settings in the PHY. */ 850 if (bsc->sc_phyflags & BGEPHYF_JUMBO_CAPABLE) 851 brgphy_jumbo_settings(sc); 852 853 /* Adjust output voltage */ 854 if ((sc->mii_mpd_oui == MII_OUI_BROADCOM2) 855 && (sc->mii_mpd_model == MII_MODEL_BROADCOM2_BCM5906)) 856 PHY_WRITE(sc, BRGPHY_MII_EPHY_PTEST, 0x12); 857 858 /* Enable Ethernet@Wirespeed */ 859 if (!(bsc->sc_phyflags & BGEPHYF_NO_WIRESPEED)) 860 brgphy_eth_wirespeed(sc); 861 862 #if 0 863 /* Enable Link LED on Dell boxes */ 864 if (bsc->sc_phyflags & BGEPHYF_NO_3LED) { 865 PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL, ®); 866 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 867 reg & ~BRGPHY_PHY_EXTCTL_3_LED); 868 } 869 #endif 870 } 871 /* Handle any bnx (NetXtreme II) workarounds. */ 872 } else if (bsc->sc_isbnx) { 873 if ((sc->mii_mpd_oui == MII_OUI_BROADCOM2) 874 && sc->mii_mpd_model == MII_MODEL_BROADCOM2_BCM5708S) { 875 /* Store autoneg capabilities/results in digital block (Page 0) */ 876 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG3_PG2); 877 PHY_WRITE(sc, BRGPHY_5708S_PG2_DIGCTL_3_0, 878 BRGPHY_5708S_PG2_DIGCTL_3_0_USE_IEEE); 879 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0); 880 881 /* Enable fiber mode and autodetection */ 882 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL1, ®); 883 PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL1, reg | 884 BRGPHY_5708S_PG0_1000X_CTL1_AUTODET_EN | 885 BRGPHY_5708S_PG0_1000X_CTL1_FIBER_MODE); 886 887 /* Enable parallel detection */ 888 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL2, ®); 889 PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL2, 890 reg | BRGPHY_5708S_PG0_1000X_CTL2_PAR_DET_EN); 891 892 /* Advertise 2.5G support through next page during autoneg */ 893 if (bsc->sc_phyflags & BNX_PHY_2_5G_CAPABLE_FLAG) { 894 PHY_READ(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1, 895 ®); 896 PHY_WRITE(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1, 897 reg | BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G); 898 } 899 900 /* Increase TX signal amplitude */ 901 if ((_BNX_CHIP_ID(bsc->sc_chipid) == BNX_CHIP_ID_5708_A0) || 902 (_BNX_CHIP_ID(bsc->sc_chipid) == BNX_CHIP_ID_5708_B0) || 903 (_BNX_CHIP_ID(bsc->sc_chipid) == BNX_CHIP_ID_5708_B1)) { 904 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 905 BRGPHY_5708S_TX_MISC_PG5); 906 PHY_READ(sc, BRGPHY_5708S_PG5_TXACTL1, ®); 907 PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL1, 908 reg & ~BRGPHY_5708S_PG5_TXACTL1_VCM); 909 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 910 BRGPHY_5708S_DIG_PG0); 911 } 912 913 /* Backplanes use special driver/pre-driver/pre-emphasis values. */ 914 if ((bsc->sc_shared_hwcfg & BNX_SHARED_HW_CFG_PHY_BACKPLANE) && 915 (bsc->sc_port_hwcfg & BNX_PORT_HW_CFG_CFG_TXCTL3_MASK)) { 916 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 917 BRGPHY_5708S_TX_MISC_PG5); 918 PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL3, 919 bsc->sc_port_hwcfg & 920 BNX_PORT_HW_CFG_CFG_TXCTL3_MASK); 921 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 922 BRGPHY_5708S_DIG_PG0); 923 } 924 } else if ((sc->mii_mpd_oui == MII_OUI_BROADCOM2) 925 && (sc->mii_mpd_model == MII_MODEL_BROADCOM2_BCM5709S)) { 926 /* Select the SerDes Digital block of the AN MMD. */ 927 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, 928 BRGPHY_BLOCK_ADDR_SERDES_DIG); 929 930 PHY_READ(sc, BRGPHY_SERDES_DIG_1000X_CTL1, ®); 931 PHY_WRITE(sc, BRGPHY_SERDES_DIG_1000X_CTL1, 932 (reg & ~BRGPHY_SD_DIG_1000X_CTL1_AUTODET) | 933 BRGPHY_SD_DIG_1000X_CTL1_FIBER); 934 935 if (bsc->sc_phyflags & BNX_PHY_2_5G_CAPABLE_FLAG) { 936 /* Select the Over 1G block of the AN MMD. */ 937 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, 938 BRGPHY_BLOCK_ADDR_OVER_1G); 939 940 /* 941 * Enable autoneg "Next Page" to advertise 942 * 2.5G support. 943 */ 944 PHY_READ(sc, BRGPHY_OVER_1G_UNFORMAT_PG1, 945 ®); 946 PHY_WRITE(sc, BRGPHY_OVER_1G_UNFORMAT_PG1, 947 reg | BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G); 948 } 949 950 /* 951 * Select the Multi-Rate Backplane Ethernet block of 952 * the AN MMD. 953 */ 954 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, 955 BRGPHY_BLOCK_ADDR_MRBE); 956 957 /* Enable MRBE speed autoneg. */ 958 PHY_READ(sc, BRGPHY_MRBE_MSG_PG5_NP, ®); 959 PHY_WRITE(sc, BRGPHY_MRBE_MSG_PG5_NP, 960 reg | BRGPHY_MRBE_MSG_PG5_NP_MBRE | 961 BRGPHY_MRBE_MSG_PG5_NP_T2); 962 963 /* Select the Clause 73 User B0 block of the AN MMD. */ 964 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, 965 BRGPHY_BLOCK_ADDR_CL73_USER_B0); 966 967 /* Enable MRBE speed autoneg. */ 968 PHY_WRITE(sc, BRGPHY_CL73_USER_B0_MBRE_CTL1, 969 BRGPHY_CL73_USER_B0_MBRE_CTL1_NP_AFT_BP | 970 BRGPHY_CL73_USER_B0_MBRE_CTL1_STA_MGR | 971 BRGPHY_CL73_USER_B0_MBRE_CTL1_ANEG); 972 973 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, 974 BRGPHY_BLOCK_ADDR_COMBO_IEEE0); 975 976 } else if (_BNX_CHIP_NUM(bsc->sc_chipid) == BNX_CHIP_NUM_5709) { 977 if (_BNX_CHIP_REV(bsc->sc_chipid) == BNX_CHIP_REV_Ax || 978 _BNX_CHIP_REV(bsc->sc_chipid) == BNX_CHIP_REV_Bx) 979 brgphy_disable_early_dac(sc); 980 981 /* Set Jumbo frame settings in the PHY. */ 982 brgphy_jumbo_settings(sc); 983 984 /* Enable Ethernet@Wirespeed */ 985 brgphy_eth_wirespeed(sc); 986 } else { 987 if (!(sc->mii_flags & MIIF_HAVEFIBER)) { 988 brgphy_ber_bug(sc); 989 990 /* Set Jumbo frame settings in the PHY. */ 991 brgphy_jumbo_settings(sc); 992 993 /* Enable Ethernet@Wirespeed */ 994 brgphy_eth_wirespeed(sc); 995 } 996 } 997 } 998 } 999 1000 /* Turn off tap power management on 5401. */ 1001 static void 1002 brgphy_bcm5401_dspcode(struct mii_softc *sc) 1003 { 1004 static const struct { 1005 int reg; 1006 uint16_t val; 1007 } dspcode[] = { 1008 { BRGPHY_MII_AUXCTL, 0x0c20 }, 1009 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 }, 1010 { BRGPHY_MII_DSP_RW_PORT, 0x1804 }, 1011 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 }, 1012 { BRGPHY_MII_DSP_RW_PORT, 0x1204 }, 1013 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 1014 { BRGPHY_MII_DSP_RW_PORT, 0x0132 }, 1015 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 1016 { BRGPHY_MII_DSP_RW_PORT, 0x0232 }, 1017 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 1018 { BRGPHY_MII_DSP_RW_PORT, 0x0a20 }, 1019 { 0, 0 }, 1020 }; 1021 int i; 1022 1023 for (i = 0; dspcode[i].reg != 0; i++) 1024 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 1025 delay(40); 1026 } 1027 1028 static void 1029 brgphy_bcm5411_dspcode(struct mii_softc *sc) 1030 { 1031 static const struct { 1032 int reg; 1033 uint16_t val; 1034 } dspcode[] = { 1035 { 0x1c, 0x8c23 }, 1036 { 0x1c, 0x8ca3 }, 1037 { 0x1c, 0x8c23 }, 1038 { 0, 0 }, 1039 }; 1040 int i; 1041 1042 for (i = 0; dspcode[i].reg != 0; i++) 1043 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 1044 } 1045 1046 void 1047 brgphy_bcm5421_dspcode(struct mii_softc *sc) 1048 { 1049 uint16_t data; 1050 1051 /* Set Class A mode */ 1052 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x1007); 1053 PHY_READ(sc, BRGPHY_MII_AUXCTL, &data); 1054 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, data | 0x0400); 1055 1056 /* Set FFE gamma override to -0.125 */ 1057 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0007); 1058 PHY_READ(sc, BRGPHY_MII_AUXCTL, &data); 1059 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, data | 0x0800); 1060 PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x000a); 1061 PHY_READ(sc, BRGPHY_MII_DSP_RW_PORT, &data); 1062 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, data | 0x0200); 1063 } 1064 1065 void 1066 brgphy_bcm54k2_dspcode(struct mii_softc *sc) 1067 { 1068 static const struct { 1069 int reg; 1070 uint16_t val; 1071 } dspcode[] = { 1072 { 4, 0x01e1 }, 1073 { 9, 0x0300 }, 1074 { 0, 0 }, 1075 }; 1076 int i; 1077 1078 for (i = 0; dspcode[i].reg != 0; i++) 1079 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 1080 } 1081 1082 static void 1083 brgphy_adc_bug(struct mii_softc *sc) 1084 { 1085 static const struct { 1086 int reg; 1087 uint16_t val; 1088 } dspcode[] = { 1089 { BRGPHY_MII_AUXCTL, 0x0c00 }, 1090 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 1091 { BRGPHY_MII_DSP_RW_PORT, 0x2aaa }, 1092 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 1093 { BRGPHY_MII_DSP_RW_PORT, 0x0323 }, 1094 { BRGPHY_MII_AUXCTL, 0x0400 }, 1095 { 0, 0 }, 1096 }; 1097 int i; 1098 1099 for (i = 0; dspcode[i].reg != 0; i++) 1100 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 1101 } 1102 1103 static void 1104 brgphy_5704_a0_bug(struct mii_softc *sc) 1105 { 1106 static const struct { 1107 int reg; 1108 uint16_t val; 1109 } dspcode[] = { 1110 { 0x1c, 0x8d68 }, 1111 { 0x1c, 0x8d68 }, 1112 { 0, 0 }, 1113 }; 1114 int i; 1115 1116 for (i = 0; dspcode[i].reg != 0; i++) 1117 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 1118 } 1119 1120 static void 1121 brgphy_ber_bug(struct mii_softc *sc) 1122 { 1123 static const struct { 1124 int reg; 1125 uint16_t val; 1126 } dspcode[] = { 1127 { BRGPHY_MII_AUXCTL, 0x0c00 }, 1128 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 1129 { BRGPHY_MII_DSP_RW_PORT, 0x310b }, 1130 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 1131 { BRGPHY_MII_DSP_RW_PORT, 0x9506 }, 1132 { BRGPHY_MII_DSP_ADDR_REG, 0x401f }, 1133 { BRGPHY_MII_DSP_RW_PORT, 0x14e2 }, 1134 { BRGPHY_MII_AUXCTL, 0x0400 }, 1135 { 0, 0 }, 1136 }; 1137 int i; 1138 1139 for (i = 0; dspcode[i].reg != 0; i++) 1140 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 1141 } 1142 1143 /* BCM5701 A0/B0 CRC bug workaround */ 1144 void 1145 brgphy_crc_bug(struct mii_softc *sc) 1146 { 1147 static const struct { 1148 int reg; 1149 uint16_t val; 1150 } dspcode[] = { 1151 { BRGPHY_MII_DSP_ADDR_REG, 0x0a75 }, 1152 { 0x1c, 0x8c68 }, 1153 { 0x1c, 0x8d68 }, 1154 { 0x1c, 0x8c68 }, 1155 { 0, 0 }, 1156 }; 1157 int i; 1158 1159 for (i = 0; dspcode[i].reg != 0; i++) 1160 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 1161 } 1162 1163 static void 1164 brgphy_disable_early_dac(struct mii_softc *sc) 1165 { 1166 uint16_t val; 1167 1168 PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x0f08); 1169 PHY_READ(sc, BRGPHY_MII_DSP_RW_PORT, &val); 1170 val &= ~(1 << 8); 1171 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, val); 1172 1173 } 1174 1175 static void 1176 brgphy_jumbo_settings(struct mii_softc *sc) 1177 { 1178 uint16_t val; 1179 1180 /* Set Jumbo frame settings in the PHY. */ 1181 if ((sc->mii_mpd_oui == MII_OUI_BROADCOM) 1182 && (sc->mii_mpd_model == MII_MODEL_BROADCOM_BCM5401)) { 1183 /* Cannot do read-modify-write on the BCM5401 */ 1184 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x4c20); 1185 } else { 1186 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7); 1187 PHY_READ(sc, BRGPHY_MII_AUXCTL, &val); 1188 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 1189 val & ~(BRGPHY_AUXCTL_LONG_PKT | 0x7)); 1190 } 1191 1192 PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL, &val); 1193 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, val & ~BRGPHY_PHY_EXTCTL_HIGH_LA); 1194 } 1195 1196 static void 1197 brgphy_eth_wirespeed(struct mii_softc *sc) 1198 { 1199 uint16_t val; 1200 1201 /* Enable Ethernet@Wirespeed */ 1202 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007); 1203 PHY_READ(sc, BRGPHY_MII_AUXCTL, &val); 1204 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, val | (1 << 15) | (1 << 4)); 1205 } 1206
Indexes created Mon Sep 29 03:10:08 GMT 2025