brgphyreg.h revision 1.11
1 /* $NetBSD: brgphyreg.h,v 1.11 2019/04/11 09:14:07 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 2000 5 * Bill Paul <wpaul (at) ee.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * FreeBSD: src/sys/dev/mii/brgphyreg.h,v 1.1 2000/04/22 01:58:17 wpaul Exp 35 */ 36 37 #ifndef _DEV_MII_BRGPHYREG_H_ 38 #define _DEV_MII_BRGPHYREG_H_ 39 40 /* 41 * Broadcom BCM5400 registers 42 */ 43 44 #define BRGPHY_MII_PHY_EXTCTL 0x10 /* PHY extended control */ 45 #define BRGPHY_PHY_EXTCTL_MAC_PHY 0x8000 /* 10BIT/GMI-interface */ 46 #define BRGPHY_PHY_EXTCTL_DIS_CROSS 0x4000 /* Disable MDI crossover */ 47 #define BRGPHY_PHY_EXTCTL_TX_DIS 0x2000 /* Tx output disabled */ 48 #define BRGPHY_PHY_EXTCTL_INT_DIS 0x1000 /* Interrupts disabled */ 49 #define BRGPHY_PHY_EXTCTL_F_INT 0x0800 /* Force interrupt */ 50 #define BRGPHY_PHY_EXTCTL_BY_45 0x0400 /* Bypass 4B5B-Decoder */ 51 #define BRGPHY_PHY_EXTCTL_BY_SCR 0x0200 /* Bypass scrambler */ 52 #define BRGPHY_PHY_EXTCTL_BY_MLT3 0x0100 /* Bypass MLT3 encoder */ 53 #define BRGPHY_PHY_EXTCTL_BY_RXA 0x0080 /* Bypass RX alignment */ 54 #define BRGPHY_PHY_EXTCTL_RES_SCR 0x0040 /* Reset scrambler */ 55 #define BRGPHY_PHY_EXTCTL_EN_LTR 0x0020 /* Enable LED traffic mode */ 56 #define BRGPHY_PHY_EXTCTL_LED_ON 0x0010 /* Force LEDs on */ 57 #define BRGPHY_PHY_EXTCTL_LED_OFF 0x0008 /* Force LEDs off */ 58 #define BRGPHY_PHY_EXTCTL_EX_IPG 0x0004 /* Extended TX IPG mode */ 59 #define BRGPHY_PHY_EXTCTL_3_LED 0x0002 /* Three link LED mode */ 60 #define BRGPHY_PHY_EXTCTL_HIGH_LA 0x0001 /* GMII Fifo Elasticy (?) */ 61 62 #define BRGPHY_MII_PHY_EXTSTS 0x11 /* PHY extended status */ 63 #define BRGPHY_PHY_EXTSTS_CROSS_STAT 0x2000 /* MDI crossover status */ 64 #define BRGPHY_PHY_EXTSTS_INT_STAT 0x1000 /* Interrupt status */ 65 #define BRGPHY_PHY_EXTSTS_RRS 0x0800 /* Remote receiver status */ 66 #define BRGPHY_PHY_EXTSTS_LRS 0x0400 /* Local receiver status */ 67 #define BRGPHY_PHY_EXTSTS_LOCKED 0x0200 /* Locked */ 68 #define BRGPHY_PHY_EXTSTS_LS 0x0100 /* Link status */ 69 #define BRGPHY_PHY_EXTSTS_RF 0x0080 /* Remove fault */ 70 #define BRGPHY_PHY_EXTSTS_CE_ER 0x0040 /* Carrier ext error */ 71 #define BRGPHY_PHY_EXTSTS_BAD_SSD 0x0020 /* Bad SSD */ 72 #define BRGPHY_PHY_EXTSTS_BAD_ESD 0x0010 /* Bad ESS */ 73 #define BRGPHY_PHY_EXTSTS_RX_ER 0x0008 /* RX error */ 74 #define BRGPHY_PHY_EXTSTS_TX_ER 0x0004 /* TX error */ 75 #define BRGPHY_PHY_EXTSTS_LOCK_ER 0x0002 /* Lock error */ 76 #define BRGPHY_PHY_EXTSTS_MLT3_ER 0x0001 /* MLT3 code error */ 77 78 #define BRGPHY_MII_RXERRCNT 0x12 /* RX error counter */ 79 80 #define BRGPHY_MII_FCERRCNT 0x13 /* False carrier sense counter */ 81 #define BGRPHY_FCERRCNT 0x00FF /* False carrier counter */ 82 83 #define BRGPHY_MII_RXNOCNT 0x14 /* RX not OK counter */ 84 #define BRGPHY_RXNOCNT_LOCAL 0xFF00 /* Local RX not OK counter */ 85 #define BRGPHY_RXNOCNT_REMOTE 0x00FF /* Local RX not OK counter */ 86 87 #define BRGPHY_MII_DSP_RW_PORT 0x15 /* DSP coefficient r/w port */ 88 89 #define BRGPHY_MII_EPHY_PTEST 0x17 /* 5906 PHY register */ 90 #define BRGPHY_MII_DSP_ADDR_REG 0x17 /* DSP coefficient addr register */ 91 92 #define BRGPHY_DSP_TAP_NUMBER_MASK 0x00 93 #define BRGPHY_DSP_AGC_A 0x00 94 #define BRGPHY_DSP_AGC_B 0x01 95 #define BRGPHY_DSP_MSE_PAIR_STATUS 0x02 96 #define BRGPHY_DSP_SOFT_DECISION 0x03 97 #define BRGPHY_DSP_PHASE_REG 0x04 98 #define BRGPHY_DSP_SKEW 0x05 99 #define BRGPHY_DSP_POWER_SAVER_UPPER_BOUND 0x06 100 #define BRGPHY_DSP_POWER_SAVER_LOWER_BOUND 0x07 101 #define BRGPHY_DSP_LAST_ECHO 0x08 102 #define BRGPHY_DSP_FREQUENCY 0x09 103 #define BRGPHY_DSP_PLL_BANDWIDTH 0x0A 104 #define BRGPHY_DSP_PLL_PHASE_OFFSET 0x0B 105 106 #define BRGPHYDSP_FILTER_DCOFFSET 0x0C00 107 #define BRGPHY_DSP_FILTER_FEXT3 0x0B00 108 #define BRGPHY_DSP_FILTER_FEXT2 0x0A00 109 #define BRGPHY_DSP_FILTER_FEXT1 0x0900 110 #define BRGPHY_DSP_FILTER_FEXT0 0x0800 111 #define BRGPHY_DSP_FILTER_NEXT3 0x0700 112 #define BRGPHY_DSP_FILTER_NEXT2 0x0600 113 #define BRGPHY_DSP_FILTER_NEXT1 0x0500 114 #define BRGPHY_DSP_FILTER_NEXT0 0x0400 115 #define BRGPHY_DSP_FILTER_ECHO 0x0300 116 #define BRGPHY_DSP_FILTER_DFE 0x0200 117 #define BRGPHY_DSP_FILTER_FFE 0x0100 118 119 #define BRGPHY_DSP_CONTROL_ALL_FILTERS 0x1000 120 121 #define BRGPHY_DSP_SEL_CH_0 0x0000 122 #define BRGPHY_DSP_SEL_CH_1 0x2000 123 #define BRGPHY_DSP_SEL_CH_2 0x4000 124 #define BRGPHY_DSP_SEL_CH_3 0x6000 125 126 #define BRGPHY_MII_AUXCTL 0x18 /* AUX control */ 127 #define BRGPHY_AUXCTL_LOW_SQ 0x8000 /* Low squelch */ 128 #define BRGPHY_AUXCTL_LONG_PKT 0x4000 /* RX long packets */ 129 #define BRGPHY_AUXCTL_ER_CTL 0x3000 /* Edgerate control */ 130 #define BRGPHY_AUXCTL_TX_TST 0x0400 /* TX test, always 1 */ 131 #define BRGPHY_AUXCTL_DIS_PRF 0x0080 /* dis part resp filter */ 132 #define BRGPHY_AUXCTL_DIAG_MODE 0x0004 /* Diagnostic mode */ 133 134 #define BRGPHY_MII_AUXSTS 0x19 /* AUX status */ 135 #define BRGPHY_AUXSTS_ACOMP 0x8000 /* Autoneg complete */ 136 #define BRGPHY_AUXSTS_AN_ACK 0x4000 /* Autoneg complete ack */ 137 #define BRGPHY_AUXSTS_AN_ACK_D 0x2000 /* Autoneg complete ack detect */ 138 #define BRGPHY_AUXSTS_AN_NPW 0x1000 /* Autoneg next page wait */ 139 #define BRGPHY_AUXSTS_AN_RES 0x0700 /* Autoneg HCD */ 140 #define BRGPHY_AUXSTS_PDF 0x0080 /* Parallel detect. fault */ 141 #define BRGPHY_AUXSTS_RF 0x0040 /* Remote fault */ 142 #define BRGPHY_AUXSTS_ANP_R 0x0020 /* Autoneg page received */ 143 #define BRGPHY_AUXSTS_LP_ANAB 0x0010 /* LP AN ability */ 144 #define BRGPHY_AUXSTS_LP_NPAB 0x0008 /* LP Next page ability */ 145 #define BRGPHY_AUXSTS_LINK 0x0004 /* Link status */ 146 #define BRGPHY_AUXSTS_PRR 0x0002 /* Pause resolution-RX */ 147 #define BRGPHY_AUXSTS_PRT 0x0001 /* Pause resolution-TX */ 148 149 #define BRGPHY_RES_1000FD 0x0700 /* 1000baseT full duplex */ 150 #define BRGPHY_RES_1000HD 0x0600 /* 1000baseT half duplex */ 151 #define BRGPHY_RES_100FD 0x0500 /* 100baseT full duplex */ 152 #define BRGPHY_RES_100T4 0x0400 /* 100baseT4 */ 153 #define BRGPHY_RES_100HD 0x0300 /* 100baseT half duplex */ 154 #define BRGPHY_RES_10FD 0x0200 /* 10baseT full duplex */ 155 #define BRGPHY_RES_10HD 0x0100 /* 10baseT half duplex */ 156 157 #define BRGPHY_MII_ISR 0x1A /* Interrupt status */ 158 #define BRGPHY_ISR_PSERR 0x4000 /* Pair swap error */ 159 #define BRGPHY_ISR_MDXI_SC 0x2000 /* MDIX Status Change */ 160 #define BRGPHY_ISR_HCT 0x1000 /* Counter above 32K */ 161 #define BRGPHY_ISR_LCT 0x0800 /* All counter below 128 */ 162 #define BRGPHY_ISR_AN_PR 0x0400 /* Autoneg page received */ 163 #define BRGPHY_ISR_NO_HDCL 0x0200 /* No HCD Link */ 164 #define BRGPHY_ISR_NO_HDC 0x0100 /* No HCD */ 165 #define BRGPHY_ISR_USHDC 0x0080 /* Negotiated Unsupported HCD */ 166 #define BRGPHY_ISR_SCR_S_ERR 0x0040 /* Scrambler sync error */ 167 #define BRGPHY_ISR_RRS_CHG 0x0020 /* Remote RX status change */ 168 #define BRGPHY_ISR_LRS_CHG 0x0010 /* Local RX status change */ 169 #define BRGPHY_ISR_DUP_CHG 0x0008 /* Duplex mode change */ 170 #define BRGPHY_ISR_LSP_CHG 0x0004 /* Link speed changed */ 171 #define BRGPHY_ISR_LNK_CHG 0x0002 /* Link status change */ 172 #define BRGPHY_ISR_CRCERR 0x0001 /* CRC error */ 173 174 #define BRGPHY_MII_IMR 0x1B /* Interrupt mask */ 175 #define BRGPHY_IMR_PSERR 0x4000 /* Pair swap error */ 176 #define BRGPHY_IMR_MDXI_SC 0x2000 /* MDIX Status Change */ 177 #define BRGPHY_IMR_HCT 0x1000 /* Counter above 32K */ 178 #define BRGPHY_IMR_LCT 0x0800 /* All counter below 128 */ 179 #define BRGPHY_IMR_AN_PR 0x0400 /* Autoneg page received */ 180 #define BRGPHY_IMR_NO_HDCL 0x0200 /* No HCD Link */ 181 #define BRGPHY_IMR_NO_HDC 0x0100 /* No HCD */ 182 #define BRGPHY_IMR_USHDC 0x0080 /* Negotiated Unsupported HCD */ 183 #define BRGPHY_IMR_SCR_S_ERR 0x0040 /* Scrambler sync error */ 184 #define BRGPHY_IMR_RRS_CHG 0x0020 /* Remote RX status change */ 185 #define BRGPHY_IMR_LRS_CHG 0x0010 /* Local RX status change */ 186 #define BRGPHY_IMR_DUP_CHG 0x0008 /* Duplex mode change */ 187 #define BRGPHY_IMR_LSP_CHG 0x0004 /* Link speed changed */ 188 #define BRGPHY_IMR_LNK_CHG 0x0002 /* Link status change */ 189 #define BRGPHY_IMR_CRCERR 0x0001 /* CRC error */ 190 191 /*******************************************************/ 192 /* Begin: PHY register values for the 5706 PHY */ 193 /*******************************************************/ 194 195 /* 196 * Shadow register 0x1C, bit 15 is write enable, 197 * bits 14-10 select function (0x00 to 0x1F). 198 */ 199 #define BRGPHY_MII_SHADOW_1C 0x1C 200 #define BRGPHY_SHADOW_1C_WRITE_EN 0x8000 201 #define BRGPHY_SHADOW_1C_SELECT_MASK 0x7C00 202 203 /* Shadow 0x1C Mode Control Register (select value 0x1F) */ 204 #define BRGPHY_SHADOW_1C_MODE_CTRL (0x1F << 10) 205 /* When set, Regs 0-0x0F are 1000X, else 1000T */ 206 #define BRGPHY_SHADOW_1C_ENA_1000X 0x0001 207 208 #define BRGPHY_TEST1 0x1E 209 #define BRGPHY_TEST1_TRIM_EN 0x0010 210 #define BRGPHY_TEST1_CRC_EN 0x8000 211 212 #define BRGPHY_MII_TEST2 0x1F 213 214 /*******************************************************/ 215 /* End: PHY register values for the 5706 PHY */ 216 /*******************************************************/ 217 218 /*******************************************************/ 219 /* Begin: PHY register values for the 5708S SerDes PHY */ 220 /*******************************************************/ 221 222 #define BRGPHY_5708S_BMCR_2500 0x20 223 224 /* Autoneg Next Page Transmit 1 Regiser */ 225 #define BRGPHY_5708S_ANEG_NXT_PG_XMIT1 0x0B 226 #define BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G 0x0001 227 228 /* Use the BLOCK_ADDR register to select the page for registers 0x10 to 0x1E */ 229 #define BRGPHY_5708S_BLOCK_ADDR 0x1f 230 #define BRGPHY_5708S_DIG_PG0 0x0000 231 #define BRGPHY_5708S_DIG3_PG2 0x0002 232 #define BRGPHY_5708S_TX_MISC_PG5 0x0005 233 234 /* 5708S SerDes "Digital" Registers (page 0) */ 235 #define BRGPHY_5708S_PG0_1000X_CTL1 0x10 236 #define BRGPHY_5708S_PG0_1000X_CTL1_FIBER_MODE 0x0001 237 #define BRGPHY_5708S_PG0_1000X_CTL1_AUTODET_EN 0x0010 238 239 #define BRGPHY_5708S_PG0_1000X_CTL2 0x11 240 #define BRGPHY_5708S_PG0_1000X_CTL2_PAR_DET_EN 0x0001 241 242 #define BRGPHY_5708S_PG0_1000X_STAT1 0x14 243 #define BRGPHY_5708S_PG0_1000X_STAT1_SGMII 0x0001 244 #define BRGPHY_5708S_PG0_1000X_STAT1_LINK 0x0002 245 #define BRGPHY_5708S_PG0_1000X_STAT1_FDX 0x0004 246 #define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_MASK 0x0018 247 #define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_10 (0x0 << 3) 248 #define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_100 (0x1 << 3) 249 #define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_1G (0x2 << 3) 250 #define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_25G (0x3 << 3) 251 #define BRGPHY_5708S_PG0_1000X_STAT1_TX_PAUSE 0x0020 252 #define BRGPHY_5708S_PG0_1000X_STAT1_RX_PAUSE 0x0040 253 254 /* 5708S SerDes "Digital 3" Registers (page 2) */ 255 #define BRGPHY_5708S_PG2_DIGCTL_3_0 0x10 256 #define BRGPHY_5708S_PG2_DIGCTL_3_0_USE_IEEE 0x0001 257 258 /* 5708S SerDes "TX Misc" Registers (page 5) */ 259 #define BRGPHY_5708S_PG5_2500STATUS1 0x10 260 261 #define BRGPHY_5708S_PG5_TXACTL1 0x15 262 #define BRGPHY_5708S_PG5_TXACTL1_VCM 0x30 263 264 #define BRGPHY_5708S_PG5_TXACTL3 0x17 265 266 /*******************************************************/ 267 /* End: PHY register values for the 5708S SerDes PHY */ 268 /*******************************************************/ 269 270 /*******************************************************/ 271 /* Begin: PHY register values for the 5709S SerDes PHY */ 272 /*******************************************************/ 273 274 /* 5709S SerDes "General Purpose Status" Registers */ 275 #define BRGPHY_BLOCK_ADDR_GP_STATUS 0x8120 276 #define BRGPHY_GP_STATUS_TOP_ANEG_STATUS 0x1B 277 #define BRGPHY_GP_STATUS_TOP_ANEG_SPEED_MASK 0x3F00 278 #define BRGPHY_GP_STATUS_TOP_ANEG_SPEED_10 0x0000 279 #define BRGPHY_GP_STATUS_TOP_ANEG_SPEED_100 0x0100 280 #define BRGPHY_GP_STATUS_TOP_ANEG_SPEED_1G 0x0200 281 #define BRGPHY_GP_STATUS_TOP_ANEG_SPEED_25G 0x0300 282 #define BRGPHY_GP_STATUS_TOP_ANEG_SPEED_1GKX 0x0D00 283 #define BRGPHY_GP_STATUS_TOP_ANEG_FDX 0x0008 284 #define BRGPHY_GP_STATUS_TOP_ANEG_LINK_UP 0x0004 285 #define BRGPHY_GP_STATUS_TOP_ANEG_CL73_COMP 0x0001 286 287 /* 5709S SerDes "SerDes Digital" Registers */ 288 #define BRGPHY_BLOCK_ADDR_SERDES_DIG 0x8300 289 #define BRGPHY_SERDES_DIG_1000X_CTL1 0x0010 290 #define BRGPHY_SD_DIG_1000X_CTL1_AUTODET 0x0010 291 #define BRGPHY_SD_DIG_1000X_CTL1_FIBER 0x0001 292 293 /* 5709S SerDes "Over 1G" Registers */ 294 #define BRGPHY_BLOCK_ADDR_OVER_1G 0x8320 295 #define BRGPHY_OVER_1G_UNFORMAT_PG1 0x19 296 297 /* 5709S SerDes "Multi-Rate Backplane Ethernet" Registers */ 298 #define BRGPHY_BLOCK_ADDR_MRBE 0x8350 299 #define BRGPHY_MRBE_MSG_PG5_NP 0x10 300 #define BRGPHY_MRBE_MSG_PG5_NP_MBRE 0x0001 301 #define BRGPHY_MRBE_MSG_PG5_NP_T2 0x0002 302 303 /* 5709S SerDes "IEEE Clause 73 User B0" Registers */ 304 #define BRGPHY_BLOCK_ADDR_CL73_USER_B0 0x8370 305 #define BRGPHY_CL73_USER_B0_MBRE_CTL1 0x12 306 #define BRGPHY_CL73_USER_B0_MBRE_CTL1_NP_AFT_BP 0x2000 307 #define BRGPHY_CL73_USER_B0_MBRE_CTL1_STA_MGR 0x4000 308 #define BRGPHY_CL73_USER_B0_MBRE_CTL1_ANEG 0x8000 309 310 /* 5709S SerDes "IEEE Clause 73 User B0" Registers */ 311 #define BRGPHY_BLOCK_ADDR_ADDR_EXT 0xFFD0 312 313 /* 5709S SerDes "Combo IEEE 0" Registers */ 314 #define BRGPHY_BLOCK_ADDR_COMBO_IEEE0 0xFFE0 315 316 #define BRGPHY_ADDR_EXT 0x1E 317 #define BRGPHY_BLOCK_ADDR 0x1F 318 319 #define BRGPHY_ADDR_EXT_AN_MMD 0x3800 320 321 /*******************************************************/ 322 /* End: PHY register values for the 5709S SerDes PHY */ 323 /*******************************************************/ 324 325 #define BRGPHY_INTRS \ 326 ~(BRGPHY_IMR_LNK_CHG | BRGPHY_IMR_LSP_CHG | BRGPHY_IMR_DUP_CHG) 327 328 #endif /* _DEV_BRGPHY_MIIREG_H_ */ 329
Indexes created Thu Oct 02 01:09:59 GMT 2025