igphyreg.h revision 1.8
1 /* $NetBSD: igphyreg.h,v 1.8 2015/10/26 02:31:31 msaitoh Exp $ */ 2 3 /******************************************************************************* 4 5 Copyright (c) 2001-2003, Intel Corporation 6 All rights reserved. 7 8 Redistribution and use in source and binary forms, with or without 9 modification, are permitted provided that the following conditions are met: 10 11 1. Redistributions of source code must retain the above copyright notice, 12 this list of conditions and the following disclaimer. 13 14 2. Redistributions in binary form must reproduce the above copyright 15 notice, this list of conditions and the following disclaimer in the 16 documentation and/or other materials provided with the distribution. 17 18 3. Neither the name of the Intel Corporation nor the names of its 19 contributors may be used to endorse or promote products derived from 20 this software without specific prior written permission. 21 22 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 23 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 26 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 POSSIBILITY OF SUCH DAMAGE. 33 34 *******************************************************************************/ 35 36 /* 37 * Copied from the Intel code, and then modified to match NetBSD 38 * style for MII registers more. 39 */ 40 41 /* 42 * IGP01E1000 Specific Registers 43 */ 44 45 /* IGP01E1000 Specific Port Config Register - R/W */ 46 #define MII_IGPHY_PORT_CONFIG 0x10 /* PHY specific config register */ 47 #define PSCFR_AUTO_MDIX_PAR_DETECT 0x0010 48 #define PSCFR_PRE_EN 0x0020 49 #define PSCFR_SMART_SPEED 0x0080 50 #define PSCFR_DISABLE_TPLOOPBACK 0x0100 51 #define PSCFR_DISABLE_JABBER 0x0400 52 #define PSCFR_DISABLE_TRANSMIT 0x2000 53 54 /* IGP01E1000 Specific Port Status Register - R/O */ 55 #define MII_IGPHY_PORT_STATUS 0x11 56 #define PSSR_AUTONEG_FAILED 0x0001 /* RO LH SC */ 57 #define PSSR_POLARITY_REVERSED 0x0002 58 #define PSSR_CABLE_LENGTH 0x007C 59 #define PSSR_FULL_DUPLEX 0x0200 60 #define PSSR_LINK_UP 0x0400 61 #define PSSR_MDIX 0x0800 62 #define PSSR_SPEED_MASK 0xC000 /* speed bits mask */ 63 #define PSSR_SPEED_10MBPS 0x4000 64 #define PSSR_SPEED_100MBPS 0x8000 65 #define PSSR_SPEED_1000MBPS 0xC000 66 #define PSSR_CABLE_LENGTH_SHIFT 0x0002 /* shift right 2 */ 67 #define PSSR_MDIX_SHIFT 0x000B /* shift right 11 */ 68 69 /* IGP01E1000 Specific Port Control Register - R/W */ 70 #define MII_IGPHY_PORT_CTRL 0x12 71 #define PSCR_TP_LOOPBACK 0x0010 72 #define PSCR_CORRECT_NC_SCMBLR 0x0200 73 #define PSCR_TEN_CRS_SELECT 0x0400 74 #define PSCR_FLIP_CHIP 0x0800 75 #define PSCR_AUTO_MDIX 0x1000 76 #define PSCR_FORCE_MDI_MDIX 0x2000 /* 0-MDI, 1-MDIX */ 77 78 /* IGP01E1000 Specific Port Link Health Register */ 79 #define MII_IGPHY_LINK_HEALTH 0x13 80 #define PLHR_VALID_CHANNEL_A 0x0001 81 #define PLHR_VALID_CHANNEL_B 0x0002 82 #define PLHR_VALID_CHANNEL_C 0x0004 83 #define PLHR_VALID_CHANNEL_D 0x0008 84 #define PLHR_AUTONEG_ACTIVE 0x0010 85 #define PLHR_AUTONEG_FAULT 0x0040 86 #define PLHR_DATA_ERR_0 0x0100 87 #define PLHR_DATA_ERR_1 0x0200 /* LH */ 88 #define PLHR_IDLE_ERROR_CNT_OFLOW 0x0400 /* LH */ 89 #define PLHR_GIG_REM_RCVR_NOK 0x0800 /* LH */ 90 #define PLHR_GIG_SCRAMBLER_ERROR 0x4000 91 #define PLHR_SS_DOWNGRADE 0x8000 92 93 /* IGP01E1000 GMII FIFO Register */ 94 #define MII_IGGMII_FIFO 0x14 95 #define GMII_FLEX_SPD 0x10 /* Enable flexible speed */ 96 #define GMII_SPD 0x20 /* Enable SPD */ 97 98 /* IGP01E1000 Channel Quality Register */ 99 #define MII_IGPHY_CHANNEL_QUALITY 0x15 100 #define MSE_CHANNEL_A 0x000F 101 #define MSE_CHANNEL_B 0x00F0 102 #define MSE_CHANNEL_C 0x0F00 103 #define MSE_CHANNEL_D 0xF000 104 105 /* IGP01E1000 Power Management */ 106 #define MII_IGPHY_POWER_MGMT 0x19 107 #define PMR_SPD_EN 0x0001 108 #define PMR_D0_LPLU 0x0002 109 #define PMR_D3_LPLU 0x0004 110 #define PMR_DIS_1000 0x0040 111 112 #define MII_IGPHY_PAGE_SELECT 0x1F 113 #define IGPHY_MAXREGADDR 0x1F 114 #define IGPHY_PAGEMASK (~IGPHY_MAXREGADDR) 115 116 /* IGP01E1000 AGC Registers - stores the cable length values*/ 117 #define MII_IGPHY_AGC_A 0x1172 118 #define MII_IGPHY_AGC_PARAM_A 0x1171 119 #define MII_IGPHY_AGC_B 0x1272 120 #define MII_IGPHY_AGC_PARAM_B 0x1271 121 #define MII_IGPHY_AGC_C 0x1472 122 #define MII_IGPHY_AGC_PARAM_C 0x1471 123 #define MII_IGPHY_AGC_D 0x1872 124 #define MII_IGPHY_AGC_PARAM_D 0x1871 125 #define AGC_LENGTH_SHIFT 7 /* Coarse - 13:11, Fine - 10:7 */ 126 #define AGC_LENGTH_TABLE_SIZE 128 127 #define AGC_RANGE 10 128 129 /* IGP01E1000 DSP Reset Register */ 130 #define MII_IGPHY_DSP_RESET 0x1F33 131 #define MII_IGPHY_DSP_SET 0x1F71 132 #define MII_IGPHY_DSP_FFE 0x1F35 133 #define MII_IGPHY_CHANNEL_NUM 4 134 #define MII_IGPHY_EDAC_MU_INDEX 0xC000 135 #define MII_IGPHY_EDAC_SIGN_EXT_9_BITS 0x8000 136 #define MII_IGPHY_ANALOG_TX_STATE 0x2890 137 #define MII_IGPHY_ANALOG_CLASS_A 0x2000 138 #define MII_IGPHY_FORCE_ANALOG_ENABLE 0x0004 139 #define MII_IGPHY_DSP_FFE_CM_CP 0x0069 140 #define MII_IGPHY_DSP_FFE_DEFAULT 0x002A 141 142 /* IGP01E1000 PCS Initialization register - stores the polarity status */ 143 #define MII_IGPHY_PCS_INIT_REG 0x00B4 144 #define MII_IGPHY_PCS_CTRL_REG 0x00B5 145 146 #define MII_IGPHY_ANALOG_REGS_PAGE 0x20C0 147 #define PHY_POLARITY_MASK 0x0078 148 149 /* IGP01E1000 Analog Register */ 150 #define MII_IGPHY_ANALOG_SPARE_FUSE_STATUS 0x20D1 151 #define MII_IGPHY_ANALOG_FUSE_STATUS 0x20D0 152 #define MII_IGPHY_ANALOG_FUSE_CONTROL 0x20DC 153 #define MII_IGPHY_ANALOG_FUSE_BYPASS 0x20DE 154 #define ANALOG_FUSE_POLY_MASK 0xF000 155 #define ANALOG_FUSE_FINE_MASK 0x0F80 156 #define ANALOG_FUSE_COARSE_MASK 0x0070 157 #define ANALOG_SPARE_FUSE_ENABLED 0x0100 158 #define ANALOG_FUSE_ENABLE_SW_CONTROL 0x0002 159 #define ANALOG_FUSE_COARSE_THRESH 0x0040 160 #define ANALOG_FUSE_COARSE_10 0x0010 161 #define ANALOG_FUSE_FINE_1 0x0080 162 #define ANALOG_FUSE_FINE_10 0x0500 163 164 /* 165 * IGP3 regs 166 */ 167 #define IGP3_PAGE_SHIFT 5 168 #define IGP3_MAX_REG_ADDRESS 0x1f /* 5 bit address bus (0-0x1f) */ 169 #define IGP3_REG(page, reg) \ 170 (((page) << IGP3_PAGE_SHIFT) | ((reg) & IGP3_MAX_REG_ADDRESS)) 171 172 #define IGP3_VR_CTRL IGP3_REG(776, 18) 173 #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300 174 #define IGP3_VR_CTRL_MODE_SHUTDOWN 0x0200 175 176 #define IGP3_PM_CTRL IGP3_REG(769, 20) 177 #define IGP3_PM_CTRL_FORCE_PWR_DOWN 0x0020 178 179 180 #define IGPHY_READ(sc, reg) \ 181 (PHY_WRITE(sc, MII_IGPHY_PAGE_SELECT, (reg) & ~0x1f), \ 182 PHY_READ(sc, (reg) & 0x1f)) 183 184 #define IGPHY_WRITE(sc, reg, val) \ 185 do { \ 186 PHY_WRITE(sc, MII_IGPHY_PAGE_SELECT, (reg) & ~0x1f); \ 187 PHY_WRITE(sc, (reg) & 0x1f, val); \ 188 } while (/*CONSTCOND*/0) 189 190 #define IGPHY_TICK_DOWNSHIFT 3 191 #define IGPHY_TICK_MAX 15 192
Indexes created Tue Sep 30 11:09:46 GMT 2025