makphyreg.h revision 1.6.20.1
1 /* $NetBSD: makphyreg.h,v 1.6.20.1 2019/01/17 17:23:02 martin Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _DEV_MII_MAKPHYREG_H_ 33 #define _DEV_MII_MAKPHYREG_H_ 34 35 /* 36 * Marvell 88E1000 ``Alaska'' 10/100/1000 PHY registers. 37 */ 38 39 #define MAKPHY_PSCR 0x10 /* PHY specific control register */ 40 #define PSCR_DIS_JABBER (1U << 0) /* disable jabber */ 41 #define PSCR_POL_REV (1U << 1) /* polarity reversal */ 42 #define PSCR_SQE_TEST (1U << 2) /* SQE test */ 43 #define PSCR_MBO (1U << 3) /* must be one */ 44 #define PSCR_DIS_125CLK (1U << 4) /* 125CLK low */ 45 #define PSCR_MDI_XOVER_MODE(x) ((x) << 5) /* crossover mode */ 46 #define PSCR_LOW_10T_THRESH (1U << 7) /* lower 10BASE-T Rx threshold */ 47 #define PSCR_EN_DETECT(x) ((x) << 8) /* Energy Detect */ 48 #define PSCR_FORCE_LINK_GOOD (1U << 10) /* force link good */ 49 #define PSCR_CRS_ON_TX (1U << 11) /* assert CRS on transmit */ 50 #define PSCR_RX_FIFO(x) ((x) << 12) /* Rx FIFO depth */ 51 #define PSCR_TX_FIFO(x) ((x) << 14) /* Tx FIFO depth */ 52 53 #define XOVER_MODE_MDI 0 54 #define XOVER_MODE_MDIX 1 55 #define XOVER_MODE_AUTO 2 56 57 /* 88E3016 */ 58 /* bit 2 and 3 are reserved */ 59 #define E3016_PSCR_MDI_XOVER_MODE(x) ((x) << 4) /* crossover mode */ 60 #define E3016_PSCR_SIGDET_POLARITY (1U << 6) /* 0: Active H, 1: Active L */ 61 #define E3016_PSCR_EXTDIST (1U << 7) /* Enable Extended Distance */ 62 #define E3016_PSCR_FEFI_DIS (1U << 8) /* Disable FEFI */ 63 #define E3016_PSCR_SCRAMBLE_DIS (1U << 9) /* Disable Scrambler */ 64 /* bit 10 is reserved */ 65 #define E3016_PSCR_NLPGEN_DIS (1U << 11) /* Disable Linkpulse Generation */ 66 #define E3016_PSCR_REG8NXTPG (1U << 12) /* En. Link Partner Next Page R */ 67 #define E3016_PSCR_NLPCHK_DIS (1U << 13) /* Disable NLP check */ 68 #define E3016_PSCR_EN_DETECT (1U << 14) /* Energy Detect */ 69 /* bit 15 is reserved */ 70 71 /* 88E1112 page 1 */ 72 #define MAKPHY_FSCR 0x10 /* Fiber specific control register */ 73 #define FSCR_XMITTER_DIS 0x0008 /* Transmitter Disable */ 74 75 /* 88E1112 page 2 */ 76 #define MAKPHY_MSCR 0x10 /* MAC specific control register */ 77 #define MSCR_TX_FIFODEPTH 0xc000 /* Transmi FIFO Depth */ 78 #define MSCR_RX_FIFODEPTH 0x3000 /* Receive FIFO Depth */ 79 #define MSCR_AUTOPREF_MASK 0x0c00 /* Autoselect preferred media mask */ 80 #define MSCR_AUTOPREF_NO 0x0000 /* No preference */ 81 #define MSCR_AUTOPREF_FIBER 0x0400 /* Preferred Fiber */ 82 #define MSCR_AUTOPREF_COPPER 0x0800 /* Preferred Copper */ 83 #define MSCR_MODE_MASK 0x0380 /* Mode select mask */ 84 #define MSCR_M_100FX 0x0000 /* 100BASE-FX */ 85 #define MSCR_M_COOPER_GBIC 0x0080 /* Copper GBIC */ 86 #define MSCR_M_AUTO_COPPER_SGMII 0x0100 /* Auto Copper/SGMII */ 87 #define MSCR_M_AUTO_COPPER_1000X 0x0180 /* Auto Copper/1000BASE-X */ 88 #define MSCR_M_COPPER 0x0280 /* Copper only */ 89 #define MSCR_M_SGMII 0x0300 /* SGMII only */ 90 #define MSCR_M_1000X 0x0380 /* 1000BASE-X only */ 91 #define MSCR_SGMII_PDOWN 0x0008 /* SGMII MAC Interface Power Down */ 92 #define MSCR_ENHANCED_SGMII 0x0004 /* Enhanced SGMII */ 93 94 #define MAKPHY_PSSR 0x11 /* PHY specific status register */ 95 #define PSSR_JABBER (1U << 0) /* jabber indication */ 96 #define PSSR_POLARITY (1U << 1) /* polarity indiciation */ 97 #define PSSR_MDIX (1U << 6) /* 1 = MIDX, 0 = MDI */ 98 #define PSSR_CABLE_LENGTH_get(x) (((x) >> 7) & 0x3) 99 #define PSSR_LINK (1U << 10) /* link indication */ 100 #define PSSR_RESOLVED (1U << 11) /* speed and duplex resolved */ 101 #define PSSR_PAGE_RECEIVED (1U << 12) /* page received */ 102 #define PSSR_DUPLEX (1U << 13) /* 1 = FDX */ 103 #define PSSR_SPEED_get(x) (((x) >> 14) & 0x3) 104 105 #define SPEED_10 0 106 #define SPEED_100 1 107 #define SPEED_1000 2 108 #define SPEED_reserved 3 109 110 #define MAKPHY_IE 0x12 /* Interrupt enable */ 111 #define IE_JABBER (1U << 0) /* jabber indication */ 112 #define IE_POL_CHANGED (1U << 1) /* polarity changed */ 113 #define IE_MDI_XOVER_CHANGED (1U << 6) /* MDI/MDIX changed */ 114 #define IE_FIFO_OVER_UNDER (1U << 7) /* FIFO over/underflow */ 115 #define IE_FALSE_CARRIER (1U << 8) /* false carrier detected */ 116 #define IE_SYMBOL_ERROR (1U << 9) /* symbol error occurred */ 117 #define IE_LINK_CHANGED (1U << 10) /* link status changed */ 118 #define IE_ANEG_COMPLETE (1U << 11) /* autonegotiation completed */ 119 #define IE_PAGE_RECEIVED (1U << 12) /* page received */ 120 #define IE_DUPLEX_CHANGED (1U << 13) /* duplex changed */ 121 #define IE_SPEED_CHANGED (1U << 14) /* speed changed */ 122 #define IE_ANEG_ERROR (1U << 15) /* autonegotiation error occurred */ 123 124 #define MAKPHY_IS 0x13 /* Interrupt status */ 125 /* See Interrupt enable bits */ 126 127 #define MAKPHY_EPSC 0x14 /* extended PHY specific control */ 128 #define EPSC_TX_CLK(x) ((x) << 4) /* transmit clock */ 129 #define EPSC_TBI_RCLK_DIS (1U << 12) /* TBI RCLK disable */ 130 #define EPSC_TBI_RX_CLK125_EN (1U << 13) /* TBI RX_CLK125 enable */ 131 #define EPSC_LINK_DOWN_NO_IDLES (1U << 15) /* 1 = lost lock detect */ 132 133 #define MAKPHY_REC 0x15 /* receive error counter */ 134 135 #define MAKPHY_EADR 0x16 /* extended address register */ 136 137 #define MAKPHY_LEDCTRL 0x18 /* LED control */ 138 #define LEDCTRL_LED_TX (1U << 0) /* 1 = activ/link, 0 = xmit */ 139 #define LEDCTRL_LED_RX (1U << 1) /* 1 = activ/link, 1 = recv */ 140 #define LEDCTRL_LED_DUPLEX (1U << 2) /* 1 = duplex, 0 = dup/coll */ 141 #define LEDCTRL_LED_LINK (1U << 3) /* 1 = spd/link, 0 = link */ 142 #define LEDCTRL_BLINK_RATE(x) ((x) << 8) 143 #define LEDCTRL_PULSE_STRCH(x) ((x) << 12) 144 #define LEDCTRL_DISABLE (1U << 15) /* disable LED */ 145 146 #define MAKPHY_ESSR 0x1b /* Extended PHY specific status */ 147 #define ESSR_AUTOSEL_DISABLE 0x8000 /* Fiber/Copper autoselect disable */ 148 #define ESSR_FIBER_LINK 0x2000 /* Fiber/Copper resolution */ 149 #define ESSR_SER_ANEG_BYPASS 0x1000 /* Serial Iface Aneg bypass enable */ 150 #define ESSR_SER_ANEG_BYPASS_ST 0x0800 /* Serial Iface Aneg bypass status */ 151 #define ESSR_INTR_POLARITY 0x0400 /* Interrupt Polarity */ 152 #define ESSR_AUTO_MEDIAREG_SEL 0x0200 /* Auto Medium Register Selection */ 153 #define ESSR_DTE_DROP_HYST 0x01e0 /* DTE detect status drop hysteresis */ 154 #define ESSR_DTE_POWER 0x0010 155 #define ESSR_HWCFG_MODE 0x000f 156 #define ESSR_GMII_COPPER 0x000f 157 #define ESSR_GMII_FIBER 0x0007 158 #define ESSR_RGMII_COPPER 0x000b 159 #define ESSR_RGMII_FIBER 0x0003 160 #define ESSR_RGMII_SGMII 0x0006 161 #define ESSR_TBI_COPPER 0x000d 162 #define ESSR_TBI_FIBER 0x0005 163 164 165 #endif /* _DEV_MII_MAKPHYREG_H_ */ 166
Indexes created Sun Oct 26 21:10:03 GMT 2025