mdio.h revision 1.3.16.1
1 /* $NetBSD: mdio.h,v 1.3.16.1 2017/08/28 17:52:04 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2013 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Masanobu SAITOH. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _DEV_MII_MDIO_H_ 33 #define _DEV_MII_MDIO_H_ 34 35 /* 36 * IEEE 802.3 Clause 45 definitions. 37 * From: 38 * IEEE 802.3 2015 39 * IEEE 802.3at 40 * IEEE 802.3av 41 */ 42 43 /* 44 * MDIO Manageable Device (MMD) addresses. 45 * Table 45-1 46 */ 47 #define MDIO_MMD_PMAPMD 1 48 #define MDIO_MMD_WIS 2 49 #define MDIO_MMD_PCS 3 50 #define MDIO_MMD_PHYXS 4 51 #define MDIO_MMD_DTEXS 5 52 #define MDIO_MMD_TC 6 53 #define MDIO_MMD_AN 7 54 #define MDIO_MMD_SEPPMA1 8 55 #define MDIO_MMD_SEPPMA2 9 56 #define MDIO_MMD_SEPPMA3 10 57 #define MDIO_MMD_SEPPMA4 11 58 #define MDIO_MMD_CL22EXT 29 59 #define MDIO_MMD_VNDSP1 30 60 #define MDIO_MMD_VNDSP2 31 61 62 /* 63 * PMA/PMD registers. 64 * Table 45-3 65 */ 66 #define MDIO_PMAPMD_CTRL1 0 /* PMA/PMD control 1 */ 67 #define MDIO_PMAPMD_STAT1 1 /* PMA/PMD status 1 */ 68 #define MDIO_PMAPMD_DEVID1 2 /* PMA/PMD device identifier 1 */ 69 #define MDIO_PMAPMD_DEVID2 3 /* PMA/PMD device identifier 2 */ 70 #define MDIO_PMAPMD_SPEED 4 /* PMA/PMD speed ability */ 71 #define MDIO_PMAPMD_DEVS1 5 /* PMA/PMD devices in package 1 */ 72 #define MDIO_PMAPMD_DEVS2 6 /* PMA/PMD devices in package 2 */ 73 #define MDIO_PMAPMD_CTRL2 7 /* PMA/PMD control 2 */ 74 #define MDIO_PMAPMD_10GSTAT2 8 /* 10G PMA/PMD status 2 */ 75 #define MDIO_PMAPMD_10GTXDIS 9 /* 10G PMA/PMD transmit disable */ 76 #define MDIO_PMAPMD_RXSIGDTCT 10 /* 10G PMD receive signal detect */ 77 #define MDIO_PMAPMD_EXTABLTY 11 /* 10G PMA/PMD ext. ability reg */ 78 #define MDIO_PMAPMD_P2MPABLTY 12 /* P2MP ability register(802.3av)*/ 79 #define MDIO_PMAPMD_40G100GEXTABLTY 13 /* 40G/100G extended ability */ 80 #define MDIO_PMAPMD_PKGID1 14 /* PMA/PMD package identifier 1 */ 81 #define MDIO_PMAPMD_PKGID2 15 /* PMA/PMD package identifier 2 */ 82 #define MDIO_PMAPMD_EEECAP 16 /* PMA/PMD EEE capability */ 83 /* Values 17 to 29 are reserved */ 84 #define MDIO_PMAPMD_10P2BCTRL 30 /* 10P/2B PMA/PMD control */ 85 #define MDIO_PMAPMD_10P2BSTAT 31 /* 10P/2B PMA/PMD status */ 86 #define MDIO_PMAPMD_10P2BLPCTRL 32 /* 10P/2B link partner PMA/D ctrl*/ 87 #define MDIO_PMAPMD_10P2BLPSTAT 33 /* 10P/2B link partner PMA/D stat*/ 88 /* Values 34 to 35 are reserved */ 89 #define MDIO_PMAPMD_10P2BLLOSCNT 36 /* 10P/2B link loss counter */ 90 #define MDIO_PMAPMD_10P2BRXSNMGN 37 /* 10P/2B RX SNR margin */ 91 #define MDIO_PMAPMD_10P2BLPRXSNMG 38 /* 10P/2B link partner RX SNR mgn*/ 92 #define MDIO_PMAPMD_10P2BLINEATTN 39 /* 10P/2B line attenuation */ 93 #define MDIO_PMAPMD_10P2BLPLINEATTN 40 /* 10P/2B link partner line atten*/ 94 #define MDIO_PMAPMD_10P2BLQTHRES 41 /* 10P/2B line quality thresholds*/ 95 #define MDIO_PMAPMD_10P2BLPLQLTHRES 42 /* 10P/2B link partner LQ thresh.*/ 96 #define MDIO_PMAPMD_10PFECCOERRS 43 /* 10P FEC correctable errors cnt*/ 97 #define MDIO_PMAPMD_10PFECUNCOERRS 44 /* 10P FEC uncorrectable err cnt*/ 98 #define MDIO_PMAPMD_10PLPFECCOERRS 45 /* 10P LP FEC correctable err cnt*/ 99 #define MDIO_PMAPMD_10PLPFECUNCOERRS 46 /* 10P LP FEC uncorrectable errcn*/ 100 #define MDIO_PMAPMD_10PELECLENGTH 47 /* 10P electrical length */ 101 #define MDIO_PMAPMD_10PLPELECLENGTH 48 /* 10P LP electrical length */ 102 #define MDIO_PMAPMD_10PGENCONFIG 49 /* 10P PMA/PMD general config. */ 103 #define MDIO_PMAPMD_10PPSDCONFIG 50 /* 10P PSD configuration */ 104 #define MDIO_PMAPMD_10PDSDRCONF1 51 /* 10P downstream data rate cnf1 */ 105 #define MDIO_PMAPMD_10PDSDRCONF2 52 /* 10P downstream data rate cnf2 */ 106 #define MDIO_PMAPMD_10PDSRSCONF 53 /* 10P downstream ReedSolomon cnf*/ 107 #define MDIO_PMAPMD_10PUSDR1 54 /* 10P upstream data rate cnf1 */ 108 #define MDIO_PMAPMD_10PUSDR2 55 /* 10P upstream data rate cnf2 */ 109 #define MDIO_PMAPMD_10PUSRSCONF 56 /* 10P upstream ReedSolomon cnf */ 110 #define MDIO_PMAPMD_10PTONEGROUP1 57 /* 10P tone group 1 */ 111 #define MDIO_PMAPMD_10PTONEGROUP2 58 /* 10P tone group 2 */ 112 #define MDIO_PMAPMD_10PTONEPARAM1 59 /* 10P tone parameter 1 */ 113 #define MDIO_PMAPMD_10PTONEPARAM2 60 /* 10P tone parameter 2 */ 114 #define MDIO_PMAPMD_10PTONEPARAM3 61 /* 10P tone parameter 3 */ 115 #define MDIO_PMAPMD_10PTONEPARAM4 62 /* 10P tone parameter 4 */ 116 #define MDIO_PMAPMD_10PTONEPARAM5 63 /* 10P tone parameter 5 */ 117 #define MDIO_PMAPMD_10PTONECTLACTN 64 /* 10P tone control action */ 118 #define MDIO_PMAPMD_10PTONESTAT1 65 /* 10P tone status 1 */ 119 #define MDIO_PMAPMD_10PTONESTAT2 66 /* 10P tone status 2 */ 120 #define MDIO_PMAPMD_10PTONESTAT3 67 /* 10P tone status 3 */ 121 #define MDIO_PMAPMD_10POUTINDICAT 68 /* 10P outgoing indicator bits */ 122 #define MDIO_PMAPMD_10PININDICAT 69 /* 10P incoming indicator bits */ 123 #define MDIO_PMAPMD_10PCYCLICEXTCNF 70 /* 10P cyclic extension config. */ 124 #define MDIO_PMAPMD_10PATTAINDSDR 71 /* 10P attainable downstream DR */ 125 /* Values 72 to 79 are reserved */ 126 #define MDIO_PMAPMD_2BGENPARAM 80 /* 2B general parameter */ 127 #define MDIO_PMAPMD_2BPMDPARAM1 81 /* 2B PMD parameter 1 */ 128 #define MDIO_PMAPMD_2BPMDPARAM2 82 /* 2B PMD parameter 2 */ 129 #define MDIO_PMAPMD_2BPMDPARAM3 83 /* 2B PMD parameter 3 */ 130 #define MDIO_PMAPMD_2BPMDPARAM4 84 /* 2B PMD parameter 4 */ 131 #define MDIO_PMAPMD_2BPMDPARAM5 85 /* 2B PMD parameter 5 */ 132 #define MDIO_PMAPMD_2BPMDPARAM6 86 /* 2B PMD parameter 6 */ 133 #define MDIO_PMAPMD_2BPMDPARAM7 87 /* 2B PMD parameter 7 */ 134 #define MDIO_PMAPMD_2BPMDPARAM8 88 /* 2B PMD parameter 8 */ 135 #define MDIO_PMAPMD_2BCODEVIOERRCNT 89 /* 2B code violation errors cnt. */ 136 #define MDIO_PMAPMD_2BLPCODEVIOERR 90 /* 2B LP code violation errors */ 137 #define MDIO_PMAPMD_2BERRSECCNT 91 /* 2B errored seconds counter */ 138 #define MDIO_PMAPMD_2BLPERRSEC 92 /* 2B LP errored seconds */ 139 #define MDIO_PMAPMD_2BSEVERRSECCNT 93 /* 2B severely errored seconds cn*/ 140 #define MDIO_PMAPMD_2BLPSEVERRSECCNT 94 /* 2B LP severely errored secs cn*/ 141 #define MDIO_PMAPMD_2BLOSWCNT 95 /* 2B LOSW counter */ 142 #define MDIO_PMAPMD_2BLPLOSW 96 /* 2B LP LOSW */ 143 #define MDIO_PMAPMD_2BUNAVSECCNT 97 /* 2B unavailable seconds counter*/ 144 #define MDIO_PMAPMD_2BLPUNAVSECCNT 98 /* 2B LP unavailable seconds cnt */ 145 #define MDIO_PMAPMD_2BSTATDEFECT 99 /* 2B state defects */ 146 #define MDIO_PMAPMD_2BLPSTATDEFECT 100 /* 2B LP state defects */ 147 #define MDIO_PMAPMD_2BNEGOCONSTEL 101 /* 2B negotiated constellation */ 148 #define MDIO_PMAPMD_2BEXTPMDPARAM1 102 /* 2B extended PMD parameters 1 */ 149 #define MDIO_PMAPMD_2BEXTPMDPARAM2 103 /* 2B extended PMD parameters 2 */ 150 #define MDIO_PMAPMD_2BEXTPMDPARAM3 104 /* 2B extended PMD parameters 3 */ 151 #define MDIO_PMAPMD_2BEXTPMDPARAM4 105 /* 2B extended PMD parameters 4 */ 152 #define MDIO_PMAPMD_2BEXTPMDPARAM5 106 /* 2B extended PMD parameters 5 */ 153 #define MDIO_PMAPMD_2BEXTPMDPARAM6 107 /* 2B extended PMD parameters 6 */ 154 #define MDIO_PMAPMD_2BEXTPMDPARAM7 108 /* 2B extended PMD parameters 7 */ 155 #define MDIO_PMAPMD_2BEXTPMDPARAM8 109 /* 2B extended PMD parameters 8 */ 156 /* Values 110 to 128 are reserved */ 157 #define MDIO_PMAPMD_10GTSTAT 129 /* 10GBASE-T status */ 158 #define MDIO_PMAPMD_10GTPASWPOLAR 130 /* 10G-T pair swap & polarity */ 159 #define MDIO_PMAPMD_10GTTXPWBOSHRCH 131 /* 10G-T PWR backoff&PHY shrt rch*/ 160 #define MDIO_PMAPMD_10GTTSTMODE 132 /* 10G-T test mode */ 161 #define MDIO_PMAPMD_10GTSNROMARGA 133 /* 10G-T SNR operating margin chA*/ 162 #define MDIO_PMAPMD_10GTSNROMARGB 134 /* 10G-T SNR operating margin chB*/ 163 #define MDIO_PMAPMD_10GTSNROMARGC 135 /* 10G-T SNR operating margin chC*/ 164 #define MDIO_PMAPMD_10GTSNROMARGD 136 /* 10G-T SNR operating margin chD*/ 165 #define MDIO_PMAPMD_10GTMINMARGA 137 /* 10G-T minimum margin ch. A */ 166 #define MDIO_PMAPMD_10GTMINMARGB 138 /* 10G-T minimum margin ch. B */ 167 #define MDIO_PMAPMD_10GTMINMARGC 139 /* 10G-T minimum margin ch. C */ 168 #define MDIO_PMAPMD_10GTMINMARGD 140 /* 10G-T minimum margin ch. D */ 169 #define MDIO_PMAPMD_10GTSIGPWRA 141 /* 10G-T RX signal power ch. A */ 170 #define MDIO_PMAPMD_10GTSIGPWRB 142 /* 10G-T RX signal power ch. B */ 171 #define MDIO_PMAPMD_10GTSIGPWRC 143 /* 10G-T RX signal power ch. C */ 172 #define MDIO_PMAPMD_10GTSIGPWRD 144 /* 10G-T RX signal power ch. D */ 173 #define MDIO_PMAPMD_10GTSKEWDLY1 145 /* 10G-T skew delay 1 */ 174 #define MDIO_PMAPMD_10GTSKEWDLY2 146 /* 10G-T skew delay 2 */ 175 #define MDIO_PMAPMD_10GTFSTRETSTATCTRL 147 /* 10G-T fast retrain stat&ctrl */ 176 /* Values 148 to 149 are reserved */ 177 #define MDIO_PMAPMD_BASERPMDCTRL 150 /* BASE-R PMD control */ 178 #define MDIO_PMAPMD_BASERPMDSTAT 151 /* BASE-R PMD status */ 179 #define MDIO_PMAPMD_BASERLPCOEFUPDL0 152 /* BASE-R LP coeffici. update ln0*/ 180 #define MDIO_PMAPMD_BASERLPSTATRPTL0 153 /* BASE-R LP status report lane0 */ 181 #define MDIO_PMAPMD_BASERLDCOEFFUPDL0 154 /* BASE-R LD coeffici. update ln0*/ 182 #define MDIO_PMAPMD_BASERLDSTATRPTL0 155 /* BASE-R LD status report lane0 */ 183 #define MDIO_PMAPMD_BASERSTAT2 156 /* BASE-R PMD status 2 */ 184 #define MDIO_PMAPMD_BASERSTAT3 157 /* BASE-R PMD status 3 */ 185 /* Values 158 to 159 are reserved */ 186 #define MDIO_PMAPMD_1000KXCTRL 160 /* 1000BASE-KX control */ 187 #define MDIO_PMAPMD_1000KXSTAT 161 /* 1000BASE-KX status */ 188 #define MDIO_PMAPMD_PMAOVHDCTRL1 162 /* PMA Overhead Control 1 */ 189 #define MDIO_PMAPMD_PMAOVHDCTRL2 163 /* PMA Overhead Control 2 */ 190 #define MDIO_PMAPMD_PMAOVHDCTRL3 164 /* PMA Overhead Control 3 */ 191 #define MDIO_PMAPMD_PMAOVHDSTAT1 165 /* PMA Overhead Status 1 */ 192 #define MDIO_PMAPMD_PMAOVHDSTAT2 166 /* PMA Overhead Status 2 */ 193 /* Values 167 to 169 are reserved */ 194 #define MDIO_PMAPMD_BASERFECABLTY 170 /* BASE-R FEC ability */ 195 #define MDIO_PMAPMD_BASERFECCTRL 171 /* BASE-R FEC control */ 196 #define MDIO_PMAPMD_10GRFECCOBLCNTL 172 /* 10G-R FEC corrected blks cntL */ 197 #define MDIO_PMAPMD_10GRFECCOBLCNTH 173 /* 10G-R FEC corrected blks cntH */ 198 #define MDIO_PMAPMD_10GRFECUNCOBLCNTL 174 /* 10G-R FEC uncorrect blks cntL */ 199 #define MDIO_PMAPMD_10GRFECUNCOBLCNTH 175 /* 10G-R FEC uncorrect blks cntH */ 200 /* Values 176 to 178 are reserved */ 201 #define MDIO_PMAPMD_CAUI4C2MRECCTLE 179 /* CAUI-4 Chip2Mod recomme. CTLE */ 202 #define MDIO_PMAPMD_CAUI4C2CTERDIL0 180 /* CAUI-4 Ch2Ch TxEq RxDir lane0 */ 203 #define MDIO_PMAPMD_CAUI4C2CTERDIL1 181 /* lane1 */ 204 #define MDIO_PMAPMD_CAUI4C2CTERDIL2 182 /* lane2 */ 205 #define MDIO_PMAPMD_CAUI4C2CTERDIL3 183 /* lane3 */ 206 #define MDIO_PMAPMD_CAUI4C2CTETDEL0 184 /* CAUI-4 Ch2Ch TxEq TxDet lane0 */ 207 #define MDIO_PMAPMD_CAUI4C2CTETDEL1 185 /* lane1 */ 208 #define MDIO_PMAPMD_CAUI4C2CTETDEL2 186 /* lane2 */ 209 #define MDIO_PMAPMD_CAUI4C2CTETDEL3 187 /* lane3 */ 210 /* Values 188 to 199 are reserved */ 211 #define MDIO_PMAPMD_RSFECCTRL 200 /* RS-FEC Control */ 212 #define MDIO_PMAPMD_RSFECSTAT 201 /* RS-FEC Status */ 213 #define MDIO_PMAPMD_RSFECCORRCWCNTL 202 /* RS-FEC correct. codeword cntL */ 214 #define MDIO_PMAPMD_RSFECCORRCWCNTH 203 /* RS-FEC correct. codeword cntH */ 215 #define MDIO_PMAPMD_RSFECUNCORRCWCNTL 204 /* RS-FEC uncorre. codeword cntL */ 216 #define MDIO_PMAPMD_RSFECUNCORRCWCNTH 205 /* RS-FEC uncorre. codeword cntH */ 217 #define MDIO_PMAPMD_RSFECLANEMAP 206 /* RS-FEC Lane Mapping */ 218 /* Values 207 to 209 are reserved */ 219 #define MDIO_PMAPMD_RSFECSMBLERRCNTL(x) /* RS-FEC Symbol Error CntLow */ \ 220 (210 + ((x) * 2)) /* lane 0 to 3 */ 221 #define MDIO_PMAPMD_RSFECSMBLERRCNTH(x) /* RS-FEC Symbol Error CntHigh */ \ 222 (211 + ((x) * 2)) /* lane 0 to 3 */ 223 /* Values 218 to 229 are reserved */ 224 #define MDIO_PMAPMD_RSFECBIPERRCNT(x) /* RS-FEC BIP Error Counter */ \ 225 (230 + (x)) /* lane 0 to 19 */ 226 #define MDIO_PMAPMD_RSFECPCSLMAP(x) /* RS-FEC PCS Lane Mapping */ \ 227 (250 + (x)) /* lane 0 to 19 */ 228 /* Values 270 to 279 are reserved */ 229 #define MDIO_PMAPMD_RSFECPCSALGNSTAT1 280 /* RS-FEC PCS Alignment Status 1 */ 230 #define MDIO_PMAPMD_RSFECPCSALGNSTAT2 281 /* RS-FEC PCS Alignment Status 2 */ 231 #define MDIO_PMAPMD_RSFECPCSALGNSTAT3 282 /* RS-FEC PCS Alignment Status 3 */ 232 #define MDIO_PMAPMD_RSFECPCSALGNSTAT4 283 /* RS-FEC PCS Alignment Status 4 */ 233 /* Values 284 to 299 are reserved */ 234 #define MDIO_PMAPMD_BASERFECCORBLKCNTL(x) /* BASE-R FEC Corr. Blk. CntL */ \ 235 (300 + ((x) * 2)) /* lane0 to 19 */ 236 #define MDIO_PMAPMD_BASERFECCORBLKCNTH(x) /* BASE-R FEC Corr. Blk. CntH */ \ 237 (301 + ((x) * 2)) /* lane0 to 19 */ 238 /* Values 340 to 699 are reserved */ 239 #define MDIO_PMAPMD_BASERFECUNCORBLKCNTL(x) /* BASE-R FEC UnCorr. Blk. CntL*/ \ 240 (700 + ((x) * 2)) /* lane0 to 19 */ 241 #define MDIO_PMAPMD_BASERFECUNCORBLKCNTH(x) /* BASE-R FEC UnCorr. Blk. CntH*/ \ 242 (701 + ((x) * 2)) /* lane0 to 19 */ 243 /* Values 740 to 1099 are reserved */ 244 #define MDIO_PMAPMD_BASERLPCOEFUPD(x) /* BASE-R LP coefficient update */\ 245 (1100 + (x)) /* lane0 to 9 */ 246 /* Values 1110 to 1199 are reserved */ 247 #define MDIO_PMAPMD_BASERLPSTATRPT(x) /* BASE-R LP status report */ \ 248 (1200 + (x)) /* lane0 to 9 */ 249 /* Values 1210 to 1299 are reserved */ 250 #define MDIO_PMAPMD_BASERLDCOEFUPD(x) /* BASE-R LD coefficient update */\ 251 (1300 + (x)) /* lane0 to 9 */ 252 /* Values 1310 to 1399 are reserved */ 253 #define MDIO_PMAPMD_BASERLDSTATRPT(x) /* BASE-R LD status report */ \ 254 (1400 + (x)) /* lane0 to 9 */ 255 /* Values 1410 to 1449 are reserved */ 256 #define MDIO_PMAPMD_PMDTRAINPATTERN(x) /* PMD training pattern */ \ 257 (1450 + (x)) /* lane0 to 3 */ 258 /* Values 1454 to 1499 are reserved */ 259 #define MDIO_PMAPMD_TSTPAT 1500 /* Test-pattern ability */ 260 #define MDIO_PMAPMD_PRBSPATTSTCTRL 1501 /* PRBS pattern testing control */ 261 /* Values 1502 to 1509 are reserved */ 262 #define MDIO_PMAPMD_SQWVTSTCTRL 1510 /* Square wave testing control */ 263 /* Values 1511 to 1599 are reserved */ 264 #define MDIO_PMAPMD_PRBSTXERRCNT(x) /* PRBS Tx Error Counter */ \ 265 (1600 + (x)) /* lane0 to 9 */ 266 /* Values 1610 to 1699 are reserved */ 267 #define MDIO_PMAPMD_PRBSRXERRCNT(x) /* PRBS Rx Error Counter */ \ 268 (1700 + (x)) /* lane0 to 9 */ 269 /* Values 1710 to 1799 are reserved */ 270 #define MDIO_PMAPMD_TSYNCCAP 1800 /* TimeSync PMA/PMD capability */ 271 #define MDIO_PMAPMD_TSYNCTXMAXDLYL 1801 /* TimeSync PMAPMD TX MAXdelay L*/ 272 #define MDIO_PMAPMD_TSYNCTXMAXDLYH 1802 /* TimeSync PMAPMD TX MAXdelay H*/ 273 #define MDIO_PMAPMD_TSYNCTXMINDLYL 1803 /* TimeSync PMAPMD TX MINdelay L*/ 274 #define MDIO_PMAPMD_TSYNCTXMINDLYH 1804 /* TimeSync PMAPMD TX MINdelay H*/ 275 #define MDIO_PMAPMD_TSYNCRXMAXDLYL 1805 /* TimeSync PMAPMD RX MAXdelay L*/ 276 #define MDIO_PMAPMD_TSYNCRXMAXDLYH 1806 /* TimeSync PMAPMD RX MAXdelay H*/ 277 #define MDIO_PMAPMD_TSYNCRXMINDLYL 1807 /* TimeSync PMAPMD RX MINdelay L*/ 278 #define MDIO_PMAPMD_TSYNCRXMINDLYH 1808 /* TimeSync PMAPMD RX MINdelay H*/ 279 /* Values 1809 to 32767 are reserved */ 280 /* Values 32768 to 65535 are vendor specific */ 281 282 /* 283 * WIS registers. 284 * Table 45-99 285 */ 286 #define MDIO_WIS_CTRL1 0 /* WIS control 1 */ 287 #define MDIO_WIS_STAT1 1 /* WIS status 1 */ 288 #define MDIO_WIS_DEVID1 2 /* WIS device identifier 1 */ 289 #define MDIO_WIS_DEVID2 3 /* WIS device identifier 2 */ 290 #define MDIO_WIS_SPEED 4 /* WIS speed ability */ 291 #define MDIO_WIS_DEVS1 5 /* WIS devices in package 1 */ 292 #define MDIO_WIS_DEVS2 6 /* WIS devices in package 2 */ 293 #define MDIO_WIS_10GCTRL2 7 /* 10G WIS control 2 */ 294 #define MDIO_WIS_10GSTAT2 8 /* 10G WIS status 2 */ 295 #define MDIO_WIS_10GTSTERRCNT 9 /* 10G WIS test-pattern error counter*/ 296 /* Values 10 to 13 are reserved */ 297 #define MDIO_WIS_PKGID1 14 /* WIS package identifier 1 */ 298 #define MDIO_WIS_PKGID2 15 /* WIS package identifier 2 */ 299 /* Values 16 to 32 are reserved */ 300 #define MDIO_WIS_10GSTAT3 33 /* 10G WIS status 3 */ 301 /* Values 34 to 36 are reserved */ 302 #define MDIO_WIS_10GFARENDPBERRCNT 37 /* 10G WIS far end path block errcnt */ 303 /* Value 38 is reserved */ 304 #define MDIO_WIS_J1XMIT(x) /* 10G WIS J1 transmit */ \ 305 (39 + ((x) / 2))/* 0to15. L8=even, H8=odd */ 306 307 #define MDIO_WIS_J1RCV(x) /* 10G WIS J1 receive */ \ 308 (47 + ((x) / 2))/* 0to15. L8=even, H8=odd */ 309 #define MDIO_WIS_FARENDLBIPERR1 55 /* 10G WIS far end line BIP errors 1 */ 310 #define MDIO_WIS_FARENDLBIPERR2 56 /* 10G WIS far end line BIP errors 2 */ 311 #define MDIO_WIS_LBIPERR1 57 /* 10G WIS line BIP errors 1 */ 312 #define MDIO_WIS_LBIPERR2 58 /* 10G WIS line BIP errors 2 */ 313 #define MDIO_WIS_PBERRCNT 59 /* 10G WIS path block error count */ 314 #define MDIO_WIS_SECBIPERRCNT 60 /* 10G WIS section BIP error count */ 315 /* Values 61 to 63 are reserved */ 316 #define MDIO_WIS_J0XMIT(x) /* 10G WIS J0 transmit */ \ 317 (64 + ((x) / 2))/* 0to15. L8=even, H8=odd */ 318 319 #define MDIO_WIS_J0RCV(x) /* 10G WIS J0 receive */ \ 320 (72 + ((x) / 2))/* 0to15. L8=even, H8=odd */ 321 /* Values 80 to 1799 are reserved */ 322 #define MDIO_WIS_TSYNCCAP 1800 /* TimeSync WIS capability */ 323 #define MDIO_WIS_TSYNCTXMAXDLYL 1801 /* TimeSync WIS TX MAXdelay L*/ 324 #define MDIO_WIS_TSYNCTXMAXDLYH 1802 /* TimeSync WIS TX MAXdelay H*/ 325 #define MDIO_WIS_TSYNCTXMINDLYL 1803 /* TimeSync WIS TX MINdelay L*/ 326 #define MDIO_WIS_TSYNCTXMINDLYH 1804 /* TimeSync WIS TX MINdelay H*/ 327 #define MDIO_WIS_TSYNCRXMAXDLYL 1805 /* TimeSync WIS RX MAXdelay L*/ 328 #define MDIO_WIS_TSYNCRXMAXDLYH 1806 /* TimeSync WIS RX MAXdelay H*/ 329 #define MDIO_WIS_TSYNCRXMINDLYL 1807 /* TimeSync WIS RX MINdelay L*/ 330 #define MDIO_WIS_TSYNCRXMINDLYH 1808 /* TimeSync WIS RX MINdelay H*/ 331 /* Values 1809 to 32767 are reserved */ 332 /* Values 32768 to 65535 are vendor specific */ 333 334 /* 335 * PCS registers. 336 * Table 45-119 337 */ 338 #define MDIO_PCS_CTRL1 0 /* PCS control 1 */ 339 #define MDIO_PCS_STAT1 1 /* PCS status 1 */ 340 #define MDIO_PCS_DEVID1 2 /* PCS device identifier 1 */ 341 #define MDIO_PCS_DEVID2 3 /* PCS device identifier 2 */ 342 #define MDIO_PCS_SPEED 4 /* PCS speed ability */ 343 #define MDIO_PCS_DEVS1 5 /* PCS devices in package 1 */ 344 #define MDIO_PCS_DEVS2 6 /* PCS devices in package 2 */ 345 #define MDIO_PCS_10GCTRL2 7 /* 10G PCS control 2 */ 346 #define MDIO_PCS_10GSTAT2 8 /* 10G PCS status 2 */ 347 /* Values 9 to 13 are reserved */ 348 #define MDIO_PCS_PKGID1 14 /* PCS package identifier 1 */ 349 #define MDIO_PCS_PKGID2 15 /* PCS package identifier 2 */ 350 /* Values 16 to 19 are reserved */ 351 #define MDIO_PCS_EEECTRLCAP 20 /* EEE control and capability */ 352 /* Value 21 is reserved */ 353 #define MDIO_PCS_EEEWKERRCNT 22 /* EEE wake error counter */ 354 /* Value 23 is reserved */ 355 #define MDIO_PCS_10GXSTAT 24 /* 10G-X PCS status */ 356 #define MDIO_PCS_10GXSTSCTRL 25 /* 10G-X PCS test control */ 357 /* Values 26 to 31 are reserved */ 358 #define MDIO_PCS_BASERTSTAT1 32 /* BASE-R & 10G-T PCS status 1 */ 359 #define MDIO_PCS_BASERTSTAT2 33 /* BASE-R & 10G-T PCS status 2 */ 360 #define MDIO_PCS_10GRTPSEEDA(x) /* 10G-R PCS test pattern seed A */ \ 361 (34 + (x)) /* 0 to 3 */ 362 #define MDIO_PCS_10GRTPSEEDB /* 10G-R PCS test pattern seed B */ \ 363 (38 + (x)) /* 0 to 3 */ 364 #define MDIO_PCS_10GRTPCTRL 42 /* 10G-R PCS test pattern control */ 365 #define MDIO_PCS_10GRTPERRCNT 43 /* 10G-R PCS test pattern err counter*/ 366 #define MDIO_PCS_BERHIORDERCNT 44 /* BER high order counter */ 367 #define MDIO_PCS_ERRBHIORDERCNT 45 /* Errored blocks high order counter */ 368 /* Values 46 to 49 are reserved */ 369 #define MDIO_PCS_MLBRPCSALGNSTAT1 50 /* Mlt-lane BASE-R PCS Align. Stat1 */ 370 #define MDIO_PCS_MLBRPCSALGNSTAT2 51 /* Mlt-lane BASE-R PCS Align. Stat2 */ 371 #define MDIO_PCS_MLBRPCSALGNSTAT3 52 /* Mlt-lane BASE-R PCS Align. Stat3 */ 372 #define MDIO_PCS_MLBRPCSALGNSTAT4 53 /* Mlt-lane BASE-R PCS Align. Stat4 */ 373 /* Values 54 to 59 are reserved */ 374 #define MDIO_PCS_10P2BCAP 60 /* 10P/2B capability */ 375 #define MDIO_PCS_10P2BCTRL 61 /* 10P/2B PCS control */ 376 #define MDIO_PCS_10P2BPMEAVAIL1 62 /* 10P/2B PME available 1 */ 377 #define MDIO_PCS_10P2BPMEAVAIL2 63 /* 10P/2B PME available 2 */ 378 #define MDIO_PCS_10P2BPMEAGGRG1 64 /* 10P/2B PME aggregate 1 */ 379 #define MDIO_PCS_10P2BPMEAGGRG2 65 /* 10P/2B PME aggregate 2 */ 380 #define MDIO_PCS_10P2BPAFRXERRCNT 66 /* 10P/2B PAF RX error counter */ 381 #define MDIO_PCS_10P2BPAFSMLFRCNT 67 /* 10P/2B PAF small fragment counter */ 382 #define MDIO_PCS_10P2BPAFLARFLCNT 68 /* 10P/2B PAF large fragment counter */ 383 #define MDIO_PCS_10P2BPAFOVFLCNT 69 /* 10P/2B PAF overflow counter */ 384 #define MDIO_PCS_10P2BPAFBADFLCNT 70 /* 10P/2B PAF bad fragments counter */ 385 #define MDIO_PCS_10P2BPAFLSTFLCNT 71 /* 10P/2B PAF lost fragments counter */ 386 #define MDIO_PCS_10P2BPAFLSTSTFLCNT 72 /* 10P/2B PAF lost starts of fr. cnt */ 387 #define MDIO_PCS_10P2BPAFLSTENFLCNT 73 /* 10P/2B PAF lost ends of fr. count */ 388 #define MDIO_PCS_10GPRFECABLTY 74 /* 10G-PR & 10/1G-PRX FEC ability */ 389 #define MDIO_PCS_10GPRFECCTRL 75 /* 10G-PR & 10/1G-PRX FEC control */ 390 #define MDIO_PCS_10GPRCOFECCOCNT1 76 /*10(/1)G-PR(X) corrected FECcodecnt1*/ 391 #define MDIO_PCS_10GPRCOFECCOCNT2 77 /*10(/1)G-PR(X) corrected FECcodecnt2*/ 392 #define MDIO_PCS_10GPRUNCOFECCOCNT1 78 /*10(/1)G-PR(X)uncorrected FECcdecnt1*/ 393 #define MDIO_PCS_10GPRUNCOFECCOCNT2 79 /*10(/1)G-PR(X)uncorrected FECcdecnt2*/ 394 #define MDIO_PCS_10GPRBERMONTMRCTRL 80 /*10(/1)G-PR(X) BER monitor tmr ctrl */ 395 #define MDIO_PCS_10GPRBERMONSTAT 81 /*10(/1)G-PR(X) BER monitor status */ 396 #define MDIO_PCS_10GPRBERMONTHRCTRL 82 /*10(/1)G-PR(X) BER mntr thresh ctrl */ 397 /* Values 83 to 199 are reserved */ 398 #define MDIO_PCS_BIPERRCNT(x) /* BIP Error Counter */ \ 399 (200 + (x)) /* lane 0 to 19 */ 400 /* Values 220 to 399 are reserved */ 401 #define MDIO_PCS_PCSLMAP(x) /* PCS Lane Mapping */ \ 402 (400 + (x)) /* lane 0 to 19 */ 403 /* Values 420 to 1799 are reserved */ 404 #define MDIO_PCS_TSYNCCAP 1800 /* TimeSync PCS capability */ 405 #define MDIO_PCS_TSYNCTXMAXDLYL 1801 /* TimeSync PCS TX MAXdelay L*/ 406 #define MDIO_PCS_TSYNCTXMAXDLYH 1802 /* TimeSync PCS TX MAXdelay H*/ 407 #define MDIO_PCS_TSYNCTXMINDLYL 1803 /* TimeSync PCS TX MINdelay L*/ 408 #define MDIO_PCS_TSYNCTXMINDLYH 1804 /* TimeSync PCS TX MINdelay H*/ 409 #define MDIO_PCS_TSYNCRXMAXDLYL 1805 /* TimeSync PCS RX MAXdelay L*/ 410 #define MDIO_PCS_TSYNCRXMAXDLYH 1806 /* TimeSync PCS RX MAXdelay H*/ 411 #define MDIO_PCS_TSYNCRXMINDLYL 1807 /* TimeSync PCS RX MINdelay L*/ 412 #define MDIO_PCS_TSYNCRXMINDLYH 1808 /* TimeSync PCS RX MINdelay H*/ 413 /* Values 1809 to 32767 are reserved */ 414 /* Values 32768 to 65535 are vendor specific */ 415 416 /* 417 * PHY XS registers. 418 * Table 45-164 419 */ 420 #define MDIO_PHYXS_CTRL1 0 /* PHY XS control 1 */ 421 #define MDIO_PHYXS_STAT1 1 /* PHY XS status 1 */ 422 #define MDIO_PHYXS_DEVID1 2 /* PHY XS device identifier 1 */ 423 #define MDIO_PHYXS_DEVID2 3 /* PHY XS device identifier 2 */ 424 #define MDIO_PHYXS_SPEED 4 /* PHY XS speed ability */ 425 #define MDIO_PHYXS_DEVS1 5 /* PHY XS devices in package 1 */ 426 #define MDIO_PHYXS_DEVS2 6 /* PHY XS devices in package 2 */ 427 /* Value 7 is reserved */ 428 #define MDIO_PHYXS_STAT2 8 /* PHY XS status 2 */ 429 /* Values 9 to 13 are reserved */ 430 #define MDIO_PHYXS_PKGID1 14 /* PHY XS package identifier 1 */ 431 #define MDIO_PHYXS_PKGID2 15 /* PHY XS package identifier 2 */ 432 /* Values 16 to 19 are reserved */ 433 #define MDIO_PHYXS_EEECAP 20 /* EEE capability register */ 434 /* Value 21 is reserved */ 435 #define MDIO_PHYXS_EEEWKERRCNT 22 /* EEE wake error counter */ 436 /* Value 23 is reserved */ 437 #define MDIO_PHYXS_10GXGXLNSTAT 24 /* 10G-X PHY XGXS lane status */ 438 #define MDIO_PHYXS_10GXGXSTSCTRL 25 /* 10G-X PHY XGXS test control */ 439 /* Values 26 to 1799 are reserved */ 440 #define MDIO_PHYXS_TSYNCCSP 1800 /* TimeSync PHY XS capability */ 441 #define MDIO_PHYXS_TSYNCTXMAXDLYL 1801 /* TimeSync PHY XS TX MAX delay L */ 442 #define MDIO_PHYXS_TSYNCTXMAXDLYH 1802 /* TimeSync PHY XS TX MAX delay H */ 443 #define MDIO_PHYXS_TSYNCTXMINDLYL 1803 /* TimeSync PHY XS TX MIN delay L */ 444 #define MDIO_PHYXS_TSYNCTXMINDLYH 1804 /* TimeSync PHY XS TX MIN delay H */ 445 #define MDIO_PHYXS_TSYNCRXMAXDLYL 1805 /* TimeSync PHY XS RX MAX delay L */ 446 #define MDIO_PHYXS_TSYNCRXMAXDLYH 1806 /* TimeSync PHY XS RX MAX delay H */ 447 #define MDIO_PHYXS_TSYNCRXMINDLYL 1807 /* TimeSync PHY XS RX MIN delay L */ 448 #define MDIO_PHYXS_TSYNCRXMINDLYH 1808 /* TimeSync PHY XS RX MIN delay H */ 449 /* Values 1809 to 32767 are reserved */ 450 /* Values 32768 to 65535 are vendor specific */ 451 452 /* 453 * DTE XS registers. 454 * Table 45-175 455 */ 456 #define MDIO_DTEXS_CTRL1 0 /* DTE XS control 1 */ 457 #define MDIO_DTEXS_STAT1 1 /* DTE XS status 1 */ 458 #define MDIO_DTEXS_DEVID1 2 /* DTE XS device identifier 1 */ 459 #define MDIO_DTEXS_DEVID2 3 /* DTE XS device identifier 2 */ 460 #define MDIO_DTEXS_SPEED 4 /* DTE XS speed ability */ 461 #define MDIO_DTEXS_DEVS1 5 /* DTE XS devices in package 1 */ 462 #define MDIO_DTEXS_DEVS2 6 /* DTE XS devices in package 2 */ 463 /* Value 7 is reserved */ 464 #define MDIO_DTEXS_STAT2 8 /* DTE XS status 2 */ 465 /* Values 9 to 13 are reserved */ 466 #define MDIO_DTEXS_PKGID1 14 /* DTE XS package identifier 1 */ 467 #define MDIO_DTEXS_PKGID2 15 /* DTE XS package identifier 2 */ 468 /* Values 16 to 19 are reserved */ 469 #define MDIO_DTEXS_EEECAP 20 /* EEE capability register */ 470 /* Value 21 is reserved */ 471 #define MDIO_DTEXS_EEEWKERRCNT 22 /* EEE wake error counter */ 472 /* Value 23 is reserved */ 473 #define MDIO_DTEXS_10GXGXLNSTAT 24 /* 10G DTE XGXS lane status */ 474 #define MDIO_DTEXS_10GXGXSTSCTRL 25 /* 10G DTE XGXS test control */ 475 /* Values 26 to 1799 are reserved */ 476 #define MDIO_DTEXS_TSYNCCAP 1800 /* TimeSync DTE XS capability */ 477 #define MDIO_DTEXS_TSYNCTXMAXDLYL 1801 /* TimeSync DTE XS TX MAX delay L */ 478 #define MDIO_DTEXS_TSYNCTXMAXDLYH 1802 /* TimeSync DTE XS TX MAX delay H */ 479 #define MDIO_DTEXS_TSYNCTXMINDLYL 1803 /* TimeSync DTE XS TX MIN delay L */ 480 #define MDIO_DTEXS_TSYNCTXMINDLYH 1804 /* TimeSync DTE XS TX MIN delay H */ 481 #define MDIO_DTEXS_TSYNCRXMAXDLYL 1805 /* TimeSync DTE XS RX MAX delay L */ 482 #define MDIO_DTEXS_TSYNCRXMAXDLYH 1806 /* TimeSync DTE XS RX MAX delay H */ 483 #define MDIO_DTEXS_TSYNCRXMINDLYL 1807 /* TimeSync DTE XS RX MIN delay L */ 484 #define MDIO_DTEXS_TSYNCRXMINDLYH 1808 /* TimeSync DTE XS RX MIN delay H */ 485 /* Values 1809 to 32767 are reserved */ 486 /* Values 32768 to 65535 are vendor specific */ 487 488 /* 489 * TC registers. 490 * Table 45-186 491 */ 492 #define MDIO_TC_CTRL1 0 /* TC control 1 */ 493 /* Value 1 is reserved */ 494 #define MDIO_TC_DEVID1 2 /* TC device identifier 1 */ 495 #define MDIO_TC_DEVID2 3 /* TC device identifier 2 */ 496 #define MDIO_TC_SPEED 4 /* TC speed ability */ 497 #define MDIO_TC_DEVS1 5 /* TC devices in package 1 */ 498 #define MDIO_TC_DEVS2 6 /* TC devices in package 2 */ 499 /* Values 7 to 13 are reserved */ 500 #define MDIO_TC_PKGID1 14 /* TC package identifier 1 */ 501 #define MDIO_TC_PKGID2 15 /* TC package identifier 2 */ 502 #define MDIO_TC_10P2BAGGDCCTRL 16 /* 10P/2B aggregation discovery ctrl */ 503 #define MDIO_TC_10P2BAGGDCSTAT 17 /* 10P/2B aggregation&discovery stat */ 504 #define MDIO_TC_10P2BAGGDCCODE1 18 /* 10P/2B aggregation discovery code1*/ 505 #define MDIO_TC_10P2BAGGDCCODE2 19 /* 10P/2B aggregation discovery code2*/ 506 #define MDIO_TC_10P2BAGGDCCODE3 20 /* 10P/2B aggregation discovery code3*/ 507 #define MDIO_TC_10P2BLPPMEAGGCTRL 21 /* 10P/2B LP PME aggregate control */ 508 #define MDIO_TC_10P2BLPPMEAGGDAT1 22 /* 10P/2B LP PME aggregate data 1 */ 509 #define MDIO_TC_10P2BLPPMEAGGDAT2 23 /* 10P/2B LP PME aggregate data 2 */ 510 #define MDIO_TC_10P2BCRCERRCNT 24 /* 10P/2B TC CRC error counter */ 511 #define MDIO_TC_10P2BTPSCOVIOCNT1 25 /* 10P/2B TPS-TC coding viol. cnt. 1 */ 512 #define MDIO_TC_10P2BTPSCOVIOCNT2 26 /* 10P/2B TPS-TC coding viol. cnt. 2 */ 513 #define MDIO_TC_10P2BINDIC 27 /* 10P/2B TC indications */ 514 /* Values 28 to 1799 are reserved */ 515 #define MDIO_TC_TSYNCCAP 1800 /* TimeSync TC capability */ 516 #define MDIO_TC_TSYNCTXMAXDLYL 1801 /* TimeSync TC TX MAX delay L */ 517 #define MDIO_TC_TSYNCTXMAXDLYH 1802 /* TimeSync TC TX MAX delay H */ 518 #define MDIO_TC_TSYNCTXMINDLYL 1803 /* TimeSync TC TX MIN delay L */ 519 #define MDIO_TC_TSYNCTXMINDLYH 1804 /* TimeSync TC TX MIN delay H */ 520 #define MDIO_TC_TSYNCRXMAXDLYL 1805 /* TimeSync TC RX MAX delay L */ 521 #define MDIO_TC_TSYNCRXMAXDLYH 1806 /* TimeSync TC RX MAX delay H */ 522 #define MDIO_TC_TSYNCRXMINDLYL 1807 /* TimeSync TC RX MIN delay L */ 523 #define MDIO_TC_TSYNCRXMINDLYH 1808 /* TimeSync TC RX MIN delay H */ 524 /* Values 1809 to 32767 are reserved */ 525 /* Values 32768 to 65535 are vendor specific */ 526 527 /* 528 * Auto-Negotiation registers. 529 * Table 45-200 530 */ 531 #define MDIO_AN_CTRL1 0 /* AN control 1 */ 532 #define MDIO_AN_STAT1 1 /* AN status 1 */ 533 #define MDIO_AN_DEVID1 2 /* AN device identifier 1 */ 534 #define MDIO_AN_DEVID2 3 /* AN device identifier 2 */ 535 /* Value 4 is reserved */ 536 #define MDIO_AN_DEVS1 5 /* AN devices in package 1 */ 537 #define MDIO_AN_DEVS2 6 /* AN devices in package 2 */ 538 /* Values 7 to 13 are reserved */ 539 #define MDIO_AN_PKGID1 14 /* AN package identifier 1 */ 540 #define MDIO_AN_PKGID2 15 /* AN package identifier 2 */ 541 #define MDIO_AN_ADVERT1 16 /* AN advertisement 1 */ 542 #define MDIO_AN_ADVERT2 17 /* AN advertisement 2 */ 543 #define MDIO_AN_ADVERT3 18 /* AN advertisement 3 */ 544 #define MDIO_AN_LPBPABLTY1 19 /* AN LP base page ability 1 */ 545 #define MDIO_AN_LPBPABLTY2 20 /* AN LP base page ability 2 */ 546 #define MDIO_AN_LPBPABLTY3 21 /* AN LP base page ability 3 */ 547 #define MDIO_AN_XNPXMIT1 22 /* AN XNP transmit 1 */ 548 #define MDIO_AN_XNPXMIT2 23 /* AN XNP transmit 2 */ 549 #define MDIO_AN_XNPXMIT3 24 /* AN XNP transmit 3 */ 550 #define MDIO_AN_LPXNPABLTY1 25 /* AN LP XNP ability 1 */ 551 #define MDIO_AN_LPXNPABLTY2 26 /* AN LP XNP ability 2 */ 552 #define MDIO_AN_LPXNPABLTY3 27 /* AN LP XNP ability 3 */ 553 /* Values 28 to 31 are reserved */ 554 #define MDIO_AN_10GTANCTRL 32 /* 10G-T AN control */ 555 #define MDIO_AN_10GTANSTAT 33 /* 10G-T AN status */ 556 /* Values 34 to 47 are reserved */ 557 #define MDIO_AN_BPETHSTAT 48 /* BP Ethernet status */ 558 /* Values 49 to 59 are reserved */ 559 #define MDIO_AN_EEEADVERT 60 /* EEE advertisement */ 560 #define MDIO_AN_EEELPABLTY 61 /* EEE LP ability */ 561 /* Values 62 to 32767 are reserved */ 562 /* Values 32768 to 65535 are vendor specific */ 563 564 /* 565 * Clause 22 extension registers. 566 * Table 45-212 567 */ 568 /* Values 0 to 4 are reserved */ 569 #define MDIO_CL22E_DEVS1 5 /* Clause 22 ext. devices in package 1 */ 570 #define MDIO_CL22E_DEVS2 6 /* Clause 22 ext. devices in package 2 */ 571 #define MDIO_CL22E_FECCAP 7 /* FEC capability */ 572 #define MDIO_CL22E_FECCTRL 8 /* FEC control */ 573 #define MDIO_CL22E_FECBHCVIOCNT 9 /* FEC buffer head coding violation cnt. */ 574 #define MDIO_CL22E_FECCOBLCNT 10 /* FEC corrected blocks counter */ 575 #define MDIO_CL22E_FECUNCOBLCNT 11 /* FEC uncorrected blocks counter */ 576 /* Values 12 to 32767 are reserved */ 577 578 /* 579 * Vendor specific MMD 1 registers. 580 * Table 45-218 581 */ 582 /* Values 0 to 1 are vendor specific */ 583 #define MDIO_VSMMD1_DEVID1 2 /* Vendor specific MMD 1 device ident. 1 */ 584 #define MDIO_VSMMD1_DEVID2 3 /* Vendor specific MMD 1 device ident. 2 */ 585 /* Values 4 to 7 are vendor specific */ 586 #define MDIO_VSMMD1_STAT 8 /* Vendor specific MMD 1 status register */ 587 /* Values 9 to 13 are vendor specific */ 588 #define MDIO_VSMMD1_PKGID1 14 /* Vendor specific MMD 1 package ident 1 */ 589 #define MDIO_VSMMD1_PKGID2 15 /* Vendor specific MMD 1 package ident 2 */ 590 /* Values 16 to 65535 are vendor specific */ 591 592 /* 593 * Vendor specific MMD 2 registers. 594 * Table 45-220 595 */ 596 /* Values 0 to 1 are vendor specific */ 597 #define MDIO_VSMMD2_DEVID1 2 /* Vendor specific MMD 2 device ident. 1 */ 598 #define MDIO_VSMMD2_DEVID2 3 /* Vendor specific MMD 2 device ident. 2 */ 599 /* Values 4 to 7 are vendor specific */ 600 #define MDIO_VSMMD2_STAT 8 /* Vendor specific MMD 2 status register */ 601 /* Values 9 to 13 are vendor specific */ 602 #define MDIO_VSMMD2_PKGID1 14 /* Vendor specific MMD 2 package ident 1 */ 603 #define MDIO_VSMMD2_PKGID2 15 /* Vendor specific MMD 2 package ident 2 */ 604 /* Values 16 to 65535 are vendor specific */ 605 606 #endif /* _DEV_MII_MDIO_H_ */ 607
Indexes created Mon Oct 20 05:10:11 GMT 2025