mdio.h revision 1.5
1 /* $NetBSD: mdio.h,v 1.5 2017/06/07 03:32:39 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 2013 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Masanobu SAITOH. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _DEV_MII_MDIO_H_ 33 #define _DEV_MII_MDIO_H_ 34 35 /* 36 * IEEE 802.3 Clause 45 definitions. 37 * From: 38 * IEEE 802.3 2009 39 * IEEE 802.3at 40 * IEEE 802.3av 41 * IEEE 802.3az 42 */ 43 44 /* 45 * MDIO Manageable Device addresses. 46 * Table 45-1 47 */ 48 #define MDIO_MMD_PMAPMD 1 49 #define MDIO_MMD_WIS 2 50 #define MDIO_MMD_PCS 3 51 #define MDIO_MMD_PHYXS 4 52 #define MDIO_MMD_DTEXS 5 53 #define MDIO_MMD_TC 6 54 #define MDIO_MMD_AN 7 55 #define MDIO_MMD_CL22EXT 29 56 #define MDIO_MMD_VNDSP1 30 57 #define MDIO_MMD_VNDSP2 31 58 59 /* 60 * MDIO PMA/PMD registers. 61 * Table 45-3 62 */ 63 #define MDIO_PMAPMD_CTRL1 0 /* PMA/PMD control 1 */ 64 #define MDIO_PMAPMD_STAT1 1 /* PMA/PMD status 1 */ 65 #define MDIO_PMAPMD_DEVID1 2 /* PMA/PMD device identifier 1 */ 66 #define MDIO_PMAPMD_DEVID2 3 /* PMA/PMD device identifier 2 */ 67 #define MDIO_PMAPMD_SPEED 4 /* PMA/PMD speed ability */ 68 #define MDIO_PMAPMD_DEVS1 5 /* PMA/PMD devices in package 1 */ 69 #define MDIO_PMAPMD_DEVS2 6 /* PMA/PMD devices in package 2 */ 70 #define MDIO_PMAPMD_CTRL2 7 /* PMA/PMD control 2 */ 71 #define MDIO_PMAPMD_10GSTAT2 8 /* 10G PMA/PMD status 2 */ 72 #define MDIO_PMAPMD_10GTXDIS 9 /* 10G PMA/PMD transmit disable */ 73 #define MDIO_PMAPMD_RXSIGDTCT 10 /* 10G PMD receive signal detect */ 74 #define MDIO_PMAPMD_EXTABLTY 11 /* 10G PMA/PMD ext. ability reg */ 75 #define MDIO_PMAPMD_P2MPABLTY 12 /* P2MP ability register(802.3av)*/ 76 /* Value 13 is reserved */ 77 #define MDIO_PMAPMD_PKGID1 14 /* PMA/PMD package identifier 1 */ 78 #define MDIO_PMAPMD_PKGID2 15 /* PMA/PMD package identifier 2 */ 79 /* Values 16 to 29 are reserved */ 80 #define MDIO_PMAPMD_10P2BCTRL 30 /* 10P/2B PMA/PMD control */ 81 #define MDIO_PMAPMD_10P2BSTAT 31 /* 10P/2B PMA/PMD status */ 82 #define MDIO_PMAPMD_10P2BLPCTRL 32 /* 10P/2B link partner PMA/D ctrl*/ 83 #define MDIO_PMAPMD_10P2BLPSTAT 33 /* 10P/2B link partner PMA/D stat*/ 84 /* Values 34 to 35 are reserved */ 85 #define MDIO_PMAPMD_10P2BLLOSCNT 36 /* 10P/2B link loss counter */ 86 #define MDIO_PMAPMD_10P2BRXSNMGN 37 /* 10P/2B RX SNR margin */ 87 #define MDIO_PMAPMD_10P2BLPRXSNMG 38 /* 10P/2B link partner RX SNR mgn*/ 88 #define MDIO_PMAPMD_10P2BLINEATTN 39 /* 10P/2B line attenuation */ 89 #define MDIO_PMAPMD_10P2BLPLINEATTN 40 /* 10P/2B link partner line atten*/ 90 #define MDIO_PMAPMD_10P2BLQTHRES 41 /* 10P/2B line quality thresholds*/ 91 #define MDIO_PMAPMD_10P2BLPLQLTHRES 42 /* 10P/2B link partner LQ thresh.*/ 92 #define MDIO_PMAPMD_10PFECCOERRS 43 /* 10P FEC correctable errors cnt*/ 93 #define MDIO_PMAPMD_10PFECUNCOERRS 44 /* 10P FEC uncorrectable err cnt*/ 94 #define MDIO_PMAPMD_10PLPFECCOERRS 45 /* 10P LP FEC correctable err cnt*/ 95 #define MDIO_PMAPMD_10PLPFECUNCOERRS 46 /* 10P LP FEC uncorrectable errcn*/ 96 #define MDIO_PMAPMD_10PELECLENGTH 47 /* 10P electrical length */ 97 #define MDIO_PMAPMD_10PLPELECLENGTH 48 /* 10P LP electrical length */ 98 #define MDIO_PMAPMD_10PGENCONFIG 49 /* 10P PMA/PMD general config. */ 99 #define MDIO_PMAPMD_10PPSDCONFIG 50 /* 10P PSD configuration */ 100 #define MDIO_PMAPMD_10PDSDRCONF1 51 /* 10P downstream data rate cnf1 */ 101 #define MDIO_PMAPMD_10PDSDRCONF2 52 /* 10P downstream data rate cnf2 */ 102 #define MDIO_PMAPMD_10PDSRSCONF 53 /* 10P downstream ReedSolomon cnf*/ 103 #define MDIO_PMAPMD_10PUSDR1 54 /* 10P upstream data rate cnf1 */ 104 #define MDIO_PMAPMD_10PUSDR2 55 /* 10P upstream data rate cnf2 */ 105 #define MDIO_PMAPMD_10PUSRSCONF 56 /* 10P upstream ReedSolomon cnf */ 106 #define MDIO_PMAPMD_10PTONEGROUP1 57 /* 10P tone group 1 */ 107 #define MDIO_PMAPMD_10PTONEGROUP2 58 /* 10P tone group 2 */ 108 #define MDIO_PMAPMD_10PTONEPARAM1 59 /* 10P tone parameter 1 */ 109 #define MDIO_PMAPMD_10PTONEPARAM2 60 /* 10P tone parameter 2 */ 110 #define MDIO_PMAPMD_10PTONEPARAM3 61 /* 10P tone parameter 3 */ 111 #define MDIO_PMAPMD_10PTONEPARAM4 62 /* 10P tone parameter 4 */ 112 #define MDIO_PMAPMD_10PTONEPARAM5 63 /* 10P tone parameter 5 */ 113 #define MDIO_PMAPMD_10PTONECTLACTN 64 /* 10P tone control action */ 114 #define MDIO_PMAPMD_10PTONESTAT1 65 /* 10P tone status 1 */ 115 #define MDIO_PMAPMD_10PTONESTAT2 66 /* 10P tone status 2 */ 116 #define MDIO_PMAPMD_10PTONESTAT3 67 /* 10P tone status 3 */ 117 #define MDIO_PMAPMD_10POUTINDICAT 68 /* 10P outgoing indicator bits */ 118 #define MDIO_PMAPMD_10PININDICAT 69 /* 10P incoming indicator bits */ 119 #define MDIO_PMAPMD_10PCYCLICEXTCNF 70 /* 10P cyclic extension config. */ 120 #define MDIO_PMAPMD_10PATTAINDSDR 71 /* 10P attainable downstream DR */ 121 /* Values 72 to 79 are reserved */ 122 #define MDIO_PMAPMD_2BGENPARAM 80 /* 2B general parameter */ 123 #define MDIO_PMAPMD_2BPMDPARAM1 81 /* 2B PMD parameter 1 */ 124 #define MDIO_PMAPMD_2BPMDPARAM2 82 /* 2B PMD parameter 2 */ 125 #define MDIO_PMAPMD_2BPMDPARAM3 83 /* 2B PMD parameter 3 */ 126 #define MDIO_PMAPMD_2BPMDPARAM4 84 /* 2B PMD parameter 4 */ 127 #define MDIO_PMAPMD_2BPMDPARAM5 85 /* 2B PMD parameter 5 */ 128 #define MDIO_PMAPMD_2BPMDPARAM6 86 /* 2B PMD parameter 6 */ 129 #define MDIO_PMAPMD_2BPMDPARAM7 87 /* 2B PMD parameter 7 */ 130 #define MDIO_PMAPMD_2BPMDPARAM8 88 /* 2B PMD parameter 8 */ 131 #define MDIO_PMAPMD_2BCODEVIOERRCNT 89 /* 2B code violation errors cnt. */ 132 #define MDIO_PMAPMD_2BLPCODEVIOERR 90 /* 2B LP code violation errors */ 133 #define MDIO_PMAPMD_2BERRSECCNT 91 /* 2B errored seconds counter */ 134 #define MDIO_PMAPMD_2BLPERRSEC 92 /* 2B LP errored seconds */ 135 #define MDIO_PMAPMD_2BSEVERRSECCNT 93 /* 2B severely errored seconds cn*/ 136 #define MDIO_PMAPMD_2BLPSEVERRSECCNT 94 /* 2B LP severely errored secs cn*/ 137 #define MDIO_PMAPMD_2BLOSWCNT 95 /* 2B LOSW counter */ 138 #define MDIO_PMAPMD_2BLPLOSW 96 /* 2B LP LOSW */ 139 #define MDIO_PMAPMD_2BUNAVSECCNT 97 /* 2B unavailable seconds counter*/ 140 #define MDIO_PMAPMD_2BLPUNAVSECCNT 98 /* 2B LP unavailable seconds cnt */ 141 #define MDIO_PMAPMD_2BSTATDEFECT 99 /* 2B state defects */ 142 #define MDIO_PMAPMD_2BLPSTATDEFECT 100 /* 2B LP state defects */ 143 #define MDIO_PMAPMD_2BNEGOCONSTEL 101 /* 2B negotiated constellation */ 144 #define MDIO_PMAPMD_2BEXTPMDPARAM1 102 /* 2B extended PMD parameters 1 */ 145 #define MDIO_PMAPMD_2BEXTPMDPARAM2 103 /* 2B extended PMD parameters 2 */ 146 #define MDIO_PMAPMD_2BEXTPMDPARAM3 104 /* 2B extended PMD parameters 3 */ 147 #define MDIO_PMAPMD_2BEXTPMDPARAM4 105 /* 2B extended PMD parameters 4 */ 148 #define MDIO_PMAPMD_2BEXTPMDPARAM5 106 /* 2B extended PMD parameters 5 */ 149 #define MDIO_PMAPMD_2BEXTPMDPARAM6 107 /* 2B extended PMD parameters 6 */ 150 #define MDIO_PMAPMD_2BEXTPMDPARAM7 108 /* 2B extended PMD parameters 7 */ 151 #define MDIO_PMAPMD_2BEXTPMDPARAM8 109 /* 2B extended PMD parameters 8 */ 152 /* Values 110 to 128 are reserved */ 153 #define MDIO_PMAPMD_10GTSTAT 129 /* 10GBASE-T status */ 154 #define MDIO_PMAPMD_10GTPASWPOLAR 130 /* 10G-T pair swap & polarity */ 155 #define MDIO_PMAPMD_10GTTXPWBOSHRCH 131 /* 10G-T PWR backoff&PHY shrt rch*/ 156 #define MDIO_PMAPMD_10GTTSTMODE 132 /* 10G-T test mode */ 157 #define MDIO_PMAPMD_10GTSNROMARGA 133 /* 10G-T SNR operating margin chA*/ 158 #define MDIO_PMAPMD_10GTSNROMARGB 134 /* 10G-T SNR operating margin chB*/ 159 #define MDIO_PMAPMD_10GTSNROMARGC 135 /* 10G-T SNR operating margin chC*/ 160 #define MDIO_PMAPMD_10GTSNROMARGD 136 /* 10G-T SNR operating margin chD*/ 161 #define MDIO_PMAPMD_10GTMINMARGA 137 /* 10G-T minimum margin ch. A */ 162 #define MDIO_PMAPMD_10GTMINMARGB 138 /* 10G-T minimum margin ch. B */ 163 #define MDIO_PMAPMD_10GTMINMARGC 139 /* 10G-T minimum margin ch. C */ 164 #define MDIO_PMAPMD_10GTMINMARGD 140 /* 10G-T minimum margin ch. D */ 165 #define MDIO_PMAPMD_10GTSIGPWRA 141 /* 10G-T RX signal power ch. A */ 166 #define MDIO_PMAPMD_10GTSIGPWRB 142 /* 10G-T RX signal power ch. B */ 167 #define MDIO_PMAPMD_10GTSIGPWRC 143 /* 10G-T RX signal power ch. C */ 168 #define MDIO_PMAPMD_10GTSIGPWRD 144 /* 10G-T RX signal power ch. D */ 169 #define MDIO_PMAPMD_10GTSKEWDLY1 145 /* 10G-T skew delay 1 */ 170 #define MDIO_PMAPMD_10GTSKEWDLY2 146 /* 10G-T skew delay 2 */ 171 #define MDIO_PMAPMD_10GTFSTRETSTATCTRL 147 /* 10G-T fast retrain stat&ctrl */ 172 /* Values 148 to 149 are reserved */ 173 #define MDIO_PMAPMD_10GKRPMDCTRL 150 /* 10G-KR PMD control */ 174 #define MDIO_PMAPMD_10GKRPMDSTAT 151 /* 10G-KR PMD status */ 175 #define MDIO_PMAPMD_10GKRLPCOEFUPD 152 /* 10G-KR LP coefficient update */ 176 #define MDIO_PMAPMD_10GKRLPSTATRPT 153 /* 10G-KR LP status report */ 177 #define MDIO_PMAPMD_10GKRLDCOEFFUPD 154 /* 10G-KR LD coefficient update */ 178 #define MDIO_PMAPMD_10GKRLDSTATRPT 155 /* 10G-KR LD status report */ 179 /* Values 156 to 159 are reserved */ 180 #define MDIO_PMAPMD_10GKXCTRL 160 /* 10G-KX control */ 181 #define MDIO_PMAPMD_10GKXSTAT 161 /* 10G-KX status */ 182 /* Values 162 to 169 are reserved */ 183 #define MDIO_PMAPMD_10GRFECABLTY 170 /* 10G-R FEC ability */ 184 #define MDIO_PMAPMD_10GRFECCTRL 171 /* 10G-R FEC control */ 185 #define MDIO_PMAPMD_10GRFECCOBLCNT1 172 /* 10G-R FEC corrected blks cnt1 */ 186 #define MDIO_PMAPMD_10GRFECCOBLCNT2 173 /* 10G-R FEC corrected blks cnt2 */ 187 #define MDIO_PMAPMD_10GRFECUNCOBLCNT1 174 /* 10G-R FEC uncorrect blks cnt1 */ 188 #define MDIO_PMAPMD_10GRFECUNCOBLCNT2 175 /* 10G-R FEC uncorrect blks cnt2 */ 189 /* Values 176 to 32767 are reserved */ 190 /* Values 32768 to 65535 are vendor specific */ 191 192 /* 193 * MDIO WIS registers. 194 * Table 45-65 195 */ 196 #define MDIO_WIS_CTRL1 0 /* WIS control 1 */ 197 #define MDIO_WIS_STAT1 1 /* WIS status 1 */ 198 #define MDIO_WIS_DEVID1 2 /* WIS device identifier 1 */ 199 #define MDIO_WIS_DEVID2 3 /* WIS device identifier 2 */ 200 #define MDIO_WIS_SPEED 4 /* WIS speed ability */ 201 #define MDIO_WIS_DEVS1 5 /* WIS devices in package 1 */ 202 #define MDIO_WIS_DEVS2 6 /* WIS devices in package 2 */ 203 #define MDIO_WIS_10GCTRL2 7 /* 10G WIS control 2 */ 204 #define MDIO_WIS_10GSTAT2 8 /* 10G WIS status 2 */ 205 #define MDIO_WIS_10GTSTERRCNT 9 /* 10G WIS test-pattern error counter*/ 206 /* Values 10 to 13 are reserved */ 207 #define MDIO_WIS_PKGID1 14 /* WIS package identifier 1 */ 208 #define MDIO_WIS_PKGID2 15 /* WIS package identifier 2 */ 209 /* Values 16 to 32 are reserved */ 210 #define MDIO_WIS_10GSTAT3 33 /* 10G WIS status 3 */ 211 /* Values 34 to 36 are reserved */ 212 #define MDIO_WIS_FARENDPBERRCNT 37 /* WIS far end path block error count*/ 213 /* Value 38 is reserved */ 214 #define MDIO_WIS_J1XMIT1 39 /* 10G WIS J1 transmit 1 */ 215 #define MDIO_WIS_J1XMIT2 40 /* 10G WIS J1 transmit 2 */ 216 #define MDIO_WIS_J1XMIT3 41 /* 10G WIS J1 transmit 3 */ 217 #define MDIO_WIS_J1XMIT4 42 /* 10G WIS J1 transmit 4 */ 218 #define MDIO_WIS_J1XMIT5 43 /* 10G WIS J1 transmit 5 */ 219 #define MDIO_WIS_J1XMIT6 44 /* 10G WIS J1 transmit 6 */ 220 #define MDIO_WIS_J1XMIT7 45 /* 10G WIS J1 transmit 7 */ 221 #define MDIO_WIS_J1XMIT8 46 /* 10G WIS J1 transmit 8 */ 222 #define MDIO_WIS_J1RECV1 47 /* 10G WIS J1 receive 1 */ 223 #define MDIO_WIS_J1RECV2 48 /* 10G WIS J1 receive 2 */ 224 #define MDIO_WIS_J1RECV3 49 /* 10G WIS J1 receive 3 */ 225 #define MDIO_WIS_J1RECV4 50 /* 10G WIS J1 receive 4 */ 226 #define MDIO_WIS_J1RECV5 51 /* 10G WIS J1 receive 5 */ 227 #define MDIO_WIS_J1RECV6 52 /* 10G WIS J1 receive 6 */ 228 #define MDIO_WIS_J1RECV7 53 /* 10G WIS J1 receive 7 */ 229 #define MDIO_WIS_J1RECV8 54 /* 10G WIS J1 receive 8 */ 230 #define MDIO_WIS_FARENDLBIPERR1 55 /* 10G WIS far end line BIP errors 1 */ 231 #define MDIO_WIS_FARENDLBIPERR2 56 /* 10G WIS far end line BIP errors 2 */ 232 #define MDIO_WIS_LBIPERR1 57 /* 10G WIS line BIP errors 1 */ 233 #define MDIO_WIS_LBIPERR2 58 /* 10G WIS line BIP errors 2 */ 234 #define MDIO_WIS_PBERRCNT 59 /* 10G WIS path block error count */ 235 #define MDIO_WIS_SECBIPERRCNT 60 /* 10G WIS section BIP error count */ 236 /* Values 61 to 63 are reserved */ 237 #define MDIO_WIS_J0XMIT1 64 /* 10G WIS J0 transmit 1 */ 238 #define MDIO_WIS_J0XMIT2 65 /* 10G WIS J0 transmit 2 */ 239 #define MDIO_WIS_J0XMIT3 66 /* 10G WIS J0 transmit 3 */ 240 #define MDIO_WIS_J0XMIT4 67 /* 10G WIS J0 transmit 4 */ 241 #define MDIO_WIS_J0XMIT5 68 /* 10G WIS J0 transmit 5 */ 242 #define MDIO_WIS_J0XMIT6 69 /* 10G WIS J0 transmit 6 */ 243 #define MDIO_WIS_J0XMIT7 70 /* 10G WIS J0 transmit 7 */ 244 #define MDIO_WIS_J0XMIT8 71 /* 10G WIS J0 transmit 8 */ 245 #define MDIO_WIS_J0RECV1 72 /* 10G WIS J0 receive 1 */ 246 #define MDIO_WIS_J0RECV2 73 /* 10G WIS J0 receive 2 */ 247 #define MDIO_WIS_J0RECV3 74 /* 10G WIS J0 receive 3 */ 248 #define MDIO_WIS_J0RECV4 75 /* 10G WIS J0 receive 4 */ 249 #define MDIO_WIS_J0RECV5 76 /* 10G WIS J0 receive 5 */ 250 #define MDIO_WIS_J0RECV6 77 /* 10G WIS J0 receive 6 */ 251 #define MDIO_WIS_J0RECV7 78 /* 10G WIS J0 receive 7 */ 252 #define MDIO_WIS_J0RECV8 79 /* 10G WIS J0 receive 8 */ 253 /* Values 80 to 32767 are reserved */ 254 /* Values 32768 to 65535 are vendor specific */ 255 256 /* 257 * MDIO PCS registers. 258 * Table 45-82 259 */ 260 #define MDIO_PCS_CTRL1 0 /* PCS control 1 */ 261 #define MDIO_PCS_STAT1 1 /* PCS status 1 */ 262 #define MDIO_PCS_DEVID1 2 /* PCS device identifier 1 */ 263 #define MDIO_PCS_DEVID2 3 /* PCS device identifier 2 */ 264 #define MDIO_PCS_SPEED 4 /* PCS speed ability */ 265 #define MDIO_PCS_DEVS1 5 /* PCS devices in package 1 */ 266 #define MDIO_PCS_DEVS2 6 /* PCS devices in package 2 */ 267 #define MDIO_PCS_10GCTRL2 7 /* 10G PCS control 2 */ 268 #define MDIO_PCS_10GSTAT2 8 /* 10G PCS status 2 */ 269 /* Values 9 to 13 are reserved */ 270 #define MDIO_PCS_PKGID1 14 /* PCS package identifier 1 */ 271 #define MDIO_PCS_PKGID2 15 /* PCS package identifier 2 */ 272 /* Values 16 to 19 are reserved */ 273 #define MDIO_PCS_EEECAP 20 /* EEE capability register (802.3az) */ 274 /* Value 21 is reserved */ 275 #define MDIO_PCS_EEEWKERRCNT 22 /* EEE wake error counter (802.3az) */ 276 /* Value 23 is reserved */ 277 #define MDIO_PCS_10GXSTAT 24 /* 10G-X PCS status */ 278 #define MDIO_PCS_10GXSTSCTRL 25 /* 10G-X PCS test control */ 279 /* Values 26 to 31 are reserved */ 280 #define MDIO_PCS_10GRTSTAT1 32 /* 10G-R & 10G-T PCS status 1 */ 281 #define MDIO_PCS_10GRTSTAT2 33 /* 10G-R & 10G-T PCS status 2 */ 282 #define MDIO_PCS_10GRTPSEEDA1 34 /* 10G-R PCS test pattern seed A1 */ 283 #define MDIO_PCS_10GRTPSEEDA2 35 /* 10G-R PCS test pattern seed A2 */ 284 #define MDIO_PCS_10GRTPSEEDA3 36 /* 10G-R PCS test pattern seed A3 */ 285 #define MDIO_PCS_10GRTPSEEDA4 37 /* 10G-R PCS test pattern seed A4 */ 286 #define MDIO_PCS_10GRTPSEEDB1 38 /* 10G-R PCS test pattern seed B1 */ 287 #define MDIO_PCS_10GRTPSEEDB2 39 /* 10G-R PCS test pattern seed B2 */ 288 #define MDIO_PCS_10GRTPSEEDB3 40 /* 10G-R PCS test pattern seed B3 */ 289 #define MDIO_PCS_10GRTPSEEDB4 41 /* 10G-R PCS test pattern seed B4 */ 290 #define MDIO_PCS_10GRTPCTRL 42 /* 10G-R PCS test pattern control */ 291 #define MDIO_PCS_10GRTPERRCNT 43 /* 10G-R PCS test pattern err counter*/ 292 /* Values 44 to 59 are reserved */ 293 #define MDIO_PCS_10P2BCAP 60 /* 10P/2B capability */ 294 #define MDIO_PCS_10P2BCTRL 61 /* 10P/2B PCS control register */ 295 #define MDIO_PCS_10P2BPMEAVAIL1 62 /* 10P/2B PME available 1 */ 296 #define MDIO_PCS_10P2BPMEAVAIL2 63 /* 10P/2B PME available 2 */ 297 #define MDIO_PCS_10P2BPMEAGGRG1 64 /* 10P/2B PME aggregate 1 */ 298 #define MDIO_PCS_10P2BPMEAGGRG2 65 /* 10P/2B PME aggregate 2 */ 299 #define MDIO_PCS_10P2BPAFRXERRCNT 66 /* 10P/2B PAF RX error counter */ 300 #define MDIO_PCS_10P2BPAFSMLFRCNT 67 /* 10P/2B PAF small fragment counter */ 301 #define MDIO_PCS_10P2BPAFLARFLCNT 68 /* 10P/2B PAF large fragment counter */ 302 #define MDIO_PCS_10P2BPAFOVFLCNT 69 /* 10P/2B PAF overflow counter */ 303 #define MDIO_PCS_10P2BPAFBADFLCNT 70 /* 10P/2B PAF bad fragments counter */ 304 #define MDIO_PCS_10P2BPAFLSTFLCNT 71 /* 10P/2B PAF lost fragments counter */ 305 #define MDIO_PCS_10P2BPAFLSTSTFLCNT 72 /* 10P/2B PAF lost starts of fr. cnt */ 306 #define MDIO_PCS_10P2BPAFLSTENFLCNT 73 /* 10P/2B PAF lost ends of fr. count */ 307 #define MDIO_PCS_10GPRFECABLTY 74 /* 10G-PR & 10/1G-PRX FEC ability */ 308 #define MDIO_PCS_10GPRFECCTRL 75 /* 10G-PR & 10/1G-PRX FEC control */ 309 #define MDIO_PCS_10GPRCOFECCOCNT1 76 /*10(/1)G-PR(X) corrected FECcodecnt1*/ 310 #define MDIO_PCS_10GPRCOFECCOCNT2 77 /*10(/1)G-PR(X) corrected FECcodecnt2*/ 311 #define MDIO_PCS_10GPRUNCOFECCOCNT1 78 /*10(/1)G-PR(X)uncorrected FECcdecnt1*/ 312 #define MDIO_PCS_10GPRUNCOFECCOCNT2 79 /*10(/1)G-PR(X)uncorrected FECcdecnt2*/ 313 #define MDIO_PCS_10GPRBERMONTMRCTRL 80 /*10(/1)G-PR(X) BER monitor tmr ctrl */ 314 #define MDIO_PCS_10GPRBERMONSTAT 81 /*10(/1)G-PR(X) BER monitor status */ 315 #define MDIO_PCS_10GPRBERMONTHRCTRL 82 /*10(/1)G-PR(X) BER mntr thresh ctrl */ 316 /* Values 83 to 32767 are reserved */ 317 /* Values 32768 to 65535 are vendor specific */ 318 319 /* 320 * MDIO PHY XS registers. 321 * Table 45-108 322 */ 323 #define MDIO_PHYXS_CTRL1 0 /* PHY XS control 1 */ 324 #define MDIO_PHYXS_STAT1 1 /* PHY XS status 1 */ 325 #define MDIO_PHYXS_DEVID1 2 /* PHY XS device identifier 1 */ 326 #define MDIO_PHYXS_DEVID2 3 /* PHY XS device identifier 2 */ 327 #define MDIO_PHYXS_SPEED 4 /* PHY XS speed ability */ 328 #define MDIO_PHYXS_DEVS1 5 /* PHY XS devices in package 1 */ 329 #define MDIO_PHYXS_DEVS2 6 /* PHY XS devices in package 2 */ 330 /* Value 7 is reserved */ 331 #define MDIO_PHYXS_STAT2 8 /* PHY XS status 2 */ 332 /* Values 9 to 13 are reserved */ 333 #define MDIO_PHYXS_PKGID1 14 /* PHY XS package identifier 1 */ 334 #define MDIO_PHYXS_PKGID2 15 /* PHY XS package identifier 2 */ 335 /* Values 16 to 19 are reserved */ 336 #define MDIO_PHYXS_EEECAP 20 /* EEE capability register (802.3az) */ 337 /* Value 21 is reserved */ 338 #define MDIO_PHYXS_EEEWKERRCNT 22 /* EEE wake error counter (802.3az) */ 339 /* Value 23 is reserved */ 340 #define MDIO_PHYXS_10GXGXLNSTAT 24 /* 10G-X PHY XGXS lane status */ 341 #define MDIO_PHYXS_10GXGXSTSCTRL 25 /* 10G-X PHY XGXS test control */ 342 /* Values 26 to 32767 are reserved */ 343 /* Values 32768 to 65535 are vendor specific */ 344 345 /* 346 * MDIO DTE XS registers. 347 * Table 45-115 348 */ 349 #define MDIO_DTEXS_CTRL1 0 /* DTE XS control 1 */ 350 #define MDIO_DTEXS_STAT1 1 /* DTE XS status 1 */ 351 #define MDIO_DTEXS_DEVID1 2 /* DTE XS device identifier 1 */ 352 #define MDIO_DTEXS_DEVID2 3 /* DTE XS device identifier 2 */ 353 #define MDIO_DTEXS_SPEED 4 /* DTE XS speed ability */ 354 #define MDIO_DTEXS_DEVS1 5 /* DTE XS devices in package 1 */ 355 #define MDIO_DTEXS_DEVS2 6 /* DTE XS devices in package 2 */ 356 /* Value 7 is reserved */ 357 #define MDIO_DTEXS_STAT2 8 /* DTE XS status 2 */ 358 /* Values 9 to 13 are reserved */ 359 #define MDIO_DTEXS_PKGID1 14 /* DTE XS package identifier 1 */ 360 #define MDIO_DTEXS_PKGID2 15 /* DTE XS package identifier 2 */ 361 /* Values 16 to 19 are reserved */ 362 #define MDIO_DTEXS_EEECAP 20 /* EEE capability register (802.3az) */ 363 /* Value 21 is reserved */ 364 #define MDIO_DTEXS_EEEWKERRCNT 22 /* EEE wake error counter (802.3az) */ 365 /* Value 23 is reserved */ 366 #define MDIO_DTEXS_10GXGXLNSTAT 24 /* 10G DTE XGXS lane status */ 367 #define MDIO_DTEXS_10GXGXSTSCTRL 25 /* 10G DTE XGXS test control */ 368 /* Values 26 to 32767 are reserved */ 369 /* Values 32768 to 65535 are vendor specific */ 370 371 /* 372 * MDIO TC registers. 373 * Table 45-122 374 */ 375 #define MDIO_TC_CTRL1 0 /* TC control 1 */ 376 /* Value 1 is reserved */ 377 #define MDIO_TC_DEVID1 2 /* TC device identifier 1 */ 378 #define MDIO_TC_DEVID2 3 /* TC device identifier 2 */ 379 #define MDIO_TC_SPEED 4 /* TC speed ability */ 380 #define MDIO_TC_DEVS1 5 /* TC devices in package 1 */ 381 #define MDIO_TC_DEVS2 6 /* TC devices in package 2 */ 382 /* Values 7 to 13 are reserved */ 383 #define MDIO_TC_PKGID1 14 /* TC package identifier 1 */ 384 #define MDIO_TC_PKGID2 15 /* TC package identifier 2 */ 385 #define MDIO_TC_10P2BAGGDCCTRL 16 /* 10P/2B aggregation discovery ctrl */ 386 #define MDIO_TC_10P2BAGGDCSTAT 17 /* 10P/2B aggregation&discovery stat */ 387 #define MDIO_TC_10P2BAGGDCCODE1 18 /* 10P/2B aggregation discovery code1*/ 388 #define MDIO_TC_10P2BAGGDCCODE2 19 /* 10P/2B aggregation discovery code2*/ 389 #define MDIO_TC_10P2BAGGDCCODE3 20 /* 10P/2B aggregation discovery code3*/ 390 #define MDIO_TC_10P2BLPPMEAGGCTRL 21 /* 10P/2B LP PME aggregate control */ 391 #define MDIO_TC_10P2BLPPMEAGGDAT1 22 /* 10P/2B LP PME aggregate data 1 */ 392 #define MDIO_TC_10P2BLPPMEAGGDAT2 23 /* 10P/2B LP PME aggregate data 2 */ 393 #define MDIO_TC_10P2BCRCERRCNT 24 /* 10P/2B TC CRC error counter */ 394 #define MDIO_TC_10P2BTPSCOVIOCNT1 25 /* 10P/2B TPS-TC coding viol. cnt. 1 */ 395 #define MDIO_TC_10P2BTPSCOVIOCNT2 26 /* 10P/2B TPS-TC coding viol. cnt. 2 */ 396 #define MDIO_TC_10P2BINDIC 27 /* 10P/2B TC indications */ 397 /* Values 28 to 32767 are reserved */ 398 /* Values 32768 to 65535 are vendor specific */ 399 400 /* 401 * MDIO Auto-Negotiation registers. 402 * Table 45-133 403 */ 404 #define MDIO_AN_CTRL1 0 /* AN control 1 */ 405 #define MDIO_AN_STAT1 1 /* AN status 1 */ 406 #define MDIO_AN_DEVID1 2 /* AN device identifier 1 */ 407 #define MDIO_AN_DEVID2 3 /* AN device identifier 2 */ 408 /* Value 4 is reserved */ 409 #define MDIO_AN_DEVS1 5 /* AN devices in package 1 */ 410 #define MDIO_AN_DEVS2 6 /* AN devices in package 2 */ 411 /* Values 7 to 13 are reserved */ 412 #define MDIO_AN_PKGID1 14 /* AN package identifier 1 */ 413 #define MDIO_AN_PKGID2 15 /* AN package identifier 2 */ 414 #define MDIO_AN_ADVERT1 16 /* AN advertisement 1 */ 415 #define MDIO_AN_ADVERT2 17 /* AN advertisement 2 */ 416 #define MDIO_AN_ADVERT3 18 /* AN advertisement 3 */ 417 #define MDIO_AN_LPBPABLTY1 19 /* AN LP base page ability 1 */ 418 #define MDIO_AN_LPBPABLTY2 20 /* AN LP base page ability 2 */ 419 #define MDIO_AN_LPBPABLTY3 21 /* AN LP base page ability 3 */ 420 #define MDIO_AN_XNPXMIT1 22 /* AN XNP transmit 1 */ 421 #define MDIO_AN_XNPXMIT2 23 /* AN XNP transmit 2 */ 422 #define MDIO_AN_XNPXMIT3 24 /* AN XNP transmit 3 */ 423 #define MDIO_AN_LPXNPABLTY1 25 /* AN LP XNP ability 1 */ 424 #define MDIO_AN_LPXNPABLTY2 26 /* AN LP XNP ability 2 */ 425 #define MDIO_AN_LPXNPABLTY3 27 /* AN LP XNP ability 3 */ 426 /* Values 28 to 31 are reserved */ 427 #define MDIO_AN_10GTANCTRL 32 /* 10G-T AN control */ 428 #define MDIO_AN_10GTANSTAT 33 /* 10G-T AN status */ 429 /* Values 34 to 47 are reserved */ 430 #define MDIO_AN_BPETHSTAT 48 /* BP Ethernet status */ 431 /* Values 49 to 59 are reserved */ 432 #define MDIO_PCS_EEEADVERT 60 /* EEE advertisement (802.3az) */ 433 #define MDIO_PCS_EEELPABLTY 61 /* EEE LP ability (802.3az) */ 434 /* Values 62 to 32767 are reserved */ 435 /* Values 32768 to 65535 are vendor specific */ 436 437 /* 438 * MDIO Clause 22 extension registers. 439 * Table 45-143 440 */ 441 /* Values 0 to 4 are reserved */ 442 #define MDIO_CL22E_DEVS1 5 /* Clause 22 ext. devices in package 1 */ 443 #define MDIO_CL22E_DEVS2 6 /* Clause 22 ext. devices in package 2 */ 444 #define MDIO_CL22E_FECCAP 7 /* FEC capability */ 445 #define MDIO_CL22E_FECCTRL 8 /* FEC control */ 446 #define MDIO_CL22E_FECBHCVIOCNT 9 /* FEC buffer head coding violation cnt. */ 447 #define MDIO_CL22E_FECCOBLCNT 10 /* FEC corrected blocks counter */ 448 #define MDIO_CL22E_FECUNCOBLCNT 11 /* FEC uncorrected blocks counter */ 449 /* Values 12 to 32767 are reserved */ 450 451 /* 452 * MDIO Vendor specific MMD 1 registers. 453 * Table 45-149 454 */ 455 /* Values 0 to 1 are vendor specific */ 456 #define MDIO_VSMMD1_DEVID1 2 /* Vendor specific MMD 1 device ident. 1 */ 457 #define MDIO_VSMMD1_DEVID2 3 /* Vendor specific MMD 1 device ident. 2 */ 458 /* Values 4 to 7 are vendor specific */ 459 #define MDIO_VSMMD1_STAT 8 /* Vendor specific MMD 1 status register */ 460 /* Values 9 to 13 are vendor specific */ 461 #define MDIO_VSMMD1_PKGID1 14 /* Vendor specific MMD 1 package ident 1 */ 462 #define MDIO_VSMMD1_PKGID2 15 /* Vendor specific MMD 1 package ident 2 */ 463 /* Values 16 to 65535 are vendor specific */ 464 465 /* 466 * MDIO Vendor specific MMD 2 registers. 467 * Table 45-152 468 */ 469 /* Values 0 to 1 are vendor specific */ 470 #define MDIO_VSMMD2_DEVID1 2 /* Vendor specific MMD 2 device ident. 1 */ 471 #define MDIO_VSMMD2_DEVID2 3 /* Vendor specific MMD 2 device ident. 2 */ 472 /* Values 4 to 7 are vendor specific */ 473 #define MDIO_VSMMD2_STAT 8 /* Vendor specific MMD 2 status register */ 474 /* Values 9 to 13 are vendor specific */ 475 #define MDIO_VSMMD2_PKGID1 14 /* Vendor specific MMD 2 package ident 1 */ 476 #define MDIO_VSMMD2_PKGID2 15 /* Vendor specific MMD 2 package ident 2 */ 477 /* Values 16 to 65535 are vendor specific */ 478 479 #endif /* _DEV_MII_MDIO_H_ */ 480
Indexes created Sat Sep 27 14:09:57 GMT 2025