micphy.c revision 1.12
1 /* $NetBSD: micphy.c,v 1.12 2020/02/14 12:14:33 nisimura Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center, and by Frank van der Linden. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1997 Manuel Bouyer. All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 45 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 46 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 47 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 48 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 49 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 50 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 51 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 52 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 53 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 54 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 55 */ 56 57 /* 58 * Driver for Micrel KSZ8xxx 10/100 and KSZ9xxx 10/100/1000 PHY. 59 */ 60 61 #include <sys/cdefs.h> 62 __KERNEL_RCSID(0, "$NetBSD: micphy.c,v 1.12 2020/02/14 12:14:33 nisimura Exp $"); 63 64 #include "opt_mii.h" 65 66 #include <sys/param.h> 67 #include <sys/systm.h> 68 #include <sys/kernel.h> 69 #include <sys/device.h> 70 #include <sys/socket.h> 71 #include <sys/errno.h> 72 73 #include <net/if.h> 74 #include <net/if_media.h> 75 76 #include <dev/mii/mii.h> 77 #include <dev/mii/miivar.h> 78 #include <dev/mii/miidevs.h> 79 80 static int micphymatch(device_t, cfdata_t, void *); 81 static void micphyattach(device_t, device_t, void *); 82 static void micphy_reset(struct mii_softc *); 83 static int micphy_service(struct mii_softc *, struct mii_data *, int); 84 85 CFATTACH_DECL3_NEW(micphy, sizeof(struct mii_softc), 86 micphymatch, micphyattach, mii_phy_detach, mii_phy_activate, NULL, NULL, 87 DVF_DETACH_SHUTDOWN); 88 89 static int micphy_service(struct mii_softc *, struct mii_data *, int); 90 static void micphy_status(struct mii_softc *); 91 static void micphy_fixup(struct mii_softc *, int, int, device_t); 92 93 static const struct mii_phy_funcs micphy_funcs = { 94 micphy_service, micphy_status, micphy_reset, 95 }; 96 97 struct micphy_softc { 98 struct mii_softc sc_mii; 99 uint32_t sc_lstype; /* Type of link status register */ 100 }; 101 102 static const struct mii_phydesc micphys[] = { 103 MII_PHY_DESC(MICREL, KSZ8041), 104 MII_PHY_DESC(MICREL, KSZ8051), /* +8021,8031 */ 105 MII_PHY_DESC(MICREL, KSZ8061), 106 MII_PHY_DESC(MICREL, KSZ8081), /* +8051,8091 */ 107 MII_PHY_DESC(MICREL, KS8737), 108 MII_PHY_DESC(MICREL, KSZ9021_8001_8721), 109 MII_PHY_DESC(MICREL, KSZ9031), 110 MII_PHY_DESC(MICREL, KSZ9131), 111 MII_PHY_DESC(MICREL, KSZ9477), /* +LAN7430internal */ 112 MII_PHY_END, 113 }; 114 115 /* 116 * Model Rev. Media LSTYPE Devices 117 * 118 * 0x11 100 1F_42 KSZ8041 119 * 0x13 100 1F_42? KSZ8041RNLI 120 * 0x15 ? 100 1E_20 KSZ8051 121 * 0x5 100 1E_20 KSZ8021 122 * 0x6 100 1E_20 KSZ8031 123 * 0x16 ? 100 1E_20 KSZ8081 124 * ? 100 1E_20 KSZ8091 125 * 0x17 100 1E_20 KSZ8061 126 * 0x21 0x0 giga GIGA KSZ9021 127 * 0x1 giga GIGA KSZ9021RLRN 128 * 0x9 100 1F_42 KSZ8721BL/SL 129 * 0x9 100 none? KSZ8721CL 130 * 0xa 100 1F_42 KSZ8001 131 * 0x22 giga GIGA KSZ9031 132 * 0x23 1? gigasw GIGA KSZ9477 (No master/slave bit) 133 * 5? giga GIGA LAN7430internal 134 * 0x24 giga GIGA KSZ9131 135 * 0x32 100 1F_42 KS8737 136 */ 137 138 /* Type of link status register */ 139 #define MICPHYF_LSTYPE_DEFAULT 0 140 #define MICPHYF_LSTYPE_1F_42 1 141 #define MICPHYF_LSTYPE_1E_20 2 142 #define MICPHYF_LSTYPE_GIGA 3 143 144 /* Return if the device is Gigabit (KSZ9021) */ 145 #define KSZ_MODEL21H_GIGA(rev) \ 146 ((((rev) & 0x0e) == 0) ? true : false) 147 148 #define KSZ_XREG_CONTROL 0x0b 149 #define KSZ_XREG_WRITE 0x0c 150 #define KSZ_XREG_READ 0x0d 151 #define KSZ_XREG_CTL_SEL_READ 0x0000 152 #define KSZ_XREG_CTL_SEL_WRITE 0x8000 153 154 #define REG_RGMII_CLOCK_AND_CONTROL 0x104 155 #define REG_RGMII_RX_DATA 0x105 156 157 /* PHY control 1 register for 10/100 PHYs (KSZ80[235689]1) */ 158 #define KSZ8051_PHYCTL1 0x1e 159 #define KSZ8051_PHY_LINK 0x0100 160 #define KSZ8051_PHY_MDIX 0x0020 161 #define KSZ8051_PHY_FDX 0x0004 162 #define KSZ8051_PHY_SPD_MASK 0x0003 163 #define KSZ8051_PHY_SPD_10T 0x0001 164 #define KSZ8051_PHY_SPD_100TX 0x0002 165 166 /* PHY control 2 register for 10/100 PHYs (KSZ8041, KSZ8721 and KSZ8001) */ 167 #define KSZ8041_PHYCTL2 0x1f 168 #define KSZ8041_PHY_ACOMP 0x0080 169 #define KSZ8041_PHY_SPD_MASK 0x001c 170 #define KSZ8041_PHY_SPD_10T 0x0004 171 #define KSZ8041_PHY_SPD_100TX 0x0008 172 #define KSZ8041_PHY_FDX 0x0010 173 #define KSZ8051_PHYCTL2 0x1f 174 175 /* PHY control register for Gigabit PHYs */ 176 #define KSZ_GPHYCTL 0x1f 177 #define KSZ_GPHY_SPD_1000T 0x0040 178 #define KSZ_GPHY_SPD_100TX 0x0020 179 #define KSZ_GPHY_SPD_10T 0x0010 180 #define KSZ_GPHY_FDX 0x0008 181 #define KSZ_GPHY_1000T_MS 0x0004 182 183 static int 184 micphymatch(device_t parent, cfdata_t match, void *aux) 185 { 186 struct mii_attach_args *ma = aux; 187 188 if (mii_phy_match(ma, micphys) != NULL) 189 return 10; 190 191 return 1; 192 } 193 194 static void 195 micphyattach(device_t parent, device_t self, void *aux) 196 { 197 struct micphy_softc *msc = device_private(self); 198 struct mii_softc *sc = &msc->sc_mii; 199 struct mii_attach_args *ma = aux; 200 struct mii_data *mii = ma->mii_data; 201 int model = MII_MODEL(ma->mii_id2); 202 int rev = MII_REV(ma->mii_id2); 203 const struct mii_phydesc *mpd; 204 205 mpd = mii_phy_match(ma, micphys); 206 aprint_naive(": Media interface\n"); 207 aprint_normal(": %s, rev. %d\n", mpd->mpd_name, rev); 208 209 sc->mii_dev = self; 210 sc->mii_inst = mii->mii_instance; 211 sc->mii_phy = ma->mii_phyno; 212 sc->mii_funcs = &micphy_funcs; 213 sc->mii_pdata = mii; 214 sc->mii_flags = ma->mii_flags; 215 216 if ((sc->mii_mpd_model == MII_MODEL_MICREL_KSZ8041) 217 || (sc->mii_mpd_model == MII_MODEL_MICREL_KSZ8041RNLI) 218 || (sc->mii_mpd_model == MII_MODEL_MICREL_KS8737) 219 || ((sc->mii_mpd_model == MII_MODEL_MICREL_KSZ9021_8001_8721) 220 && !KSZ_MODEL21H_GIGA(sc->mii_mpd_rev))) { 221 msc->sc_lstype = MICPHYF_LSTYPE_1F_42; 222 } else if ((sc->mii_mpd_model == MII_MODEL_MICREL_KSZ8051) 223 || (sc->mii_mpd_model == MII_MODEL_MICREL_KSZ8081) 224 || (sc->mii_mpd_model == MII_MODEL_MICREL_KSZ8061)) { 225 msc->sc_lstype = MICPHYF_LSTYPE_1E_20; 226 } else if (((sc->mii_mpd_model == MII_MODEL_MICREL_KSZ9021_8001_8721) 227 && KSZ_MODEL21H_GIGA(sc->mii_mpd_rev)) 228 || (sc->mii_mpd_model == MII_MODEL_MICREL_KSZ9031) 229 || (sc->mii_mpd_model == MII_MODEL_MICREL_KSZ9477) 230 || (sc->mii_mpd_model == MII_MODEL_MICREL_KSZ9131)) { 231 msc->sc_lstype = MICPHYF_LSTYPE_GIGA; 232 } else 233 msc->sc_lstype = MICPHYF_LSTYPE_DEFAULT; 234 235 PHY_RESET(sc); 236 237 micphy_fixup(sc, model, rev, parent); 238 239 PHY_READ(sc, MII_BMSR, &sc->mii_capabilities); 240 sc->mii_capabilities &= ma->mii_capmask; 241 if (sc->mii_capabilities & BMSR_EXTSTAT) 242 PHY_READ(sc, MII_EXTSR, &sc->mii_extcapabilities); 243 244 aprint_normal_dev(self, ""); 245 mii_phy_add_media(sc); 246 aprint_normal("\n"); 247 } 248 249 static void 250 micphy_reset(struct mii_softc *sc) 251 { 252 uint16_t reg; 253 254 /* 255 * The 8081 has no "sticky bits" that survive a soft reset; several 256 * bits in the Phy Control Register 2 must be preserved across the 257 * reset. These bits are set up by the bootloader; they control how the 258 * phy interfaces to the board (such as clock frequency and LED 259 * behavior). 260 */ 261 if (sc->mii_mpd_model == MII_MODEL_MICREL_KSZ8081) 262 PHY_READ(sc, KSZ8051_PHYCTL2, ®); 263 mii_phy_reset(sc); 264 if (sc->mii_mpd_model == MII_MODEL_MICREL_KSZ8081) 265 PHY_WRITE(sc, KSZ8051_PHYCTL2, reg); 266 } 267 268 static int 269 micphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 270 { 271 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 272 uint16_t reg; 273 274 switch (cmd) { 275 case MII_POLLSTAT: 276 /* If we're not polling our PHY instance, just return. */ 277 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 278 return 0; 279 break; 280 281 case MII_MEDIACHG: 282 /* 283 * If the media indicates a different PHY instance, 284 * isolate ourselves. 285 */ 286 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 287 PHY_READ(sc, MII_BMCR, ®); 288 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO); 289 return 0; 290 } 291 292 /* If the interface is not up, don't do anything. */ 293 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 294 break; 295 296 mii_phy_setmedia(sc); 297 break; 298 299 case MII_TICK: 300 /* If we're not currently selected, just return. */ 301 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 302 return 0; 303 304 if (mii_phy_tick(sc) == EJUSTRETURN) 305 return 0; 306 break; 307 308 case MII_DOWN: 309 mii_phy_down(sc); 310 return 0; 311 } 312 313 /* Update the media status. */ 314 mii_phy_status(sc); 315 316 /* Callback if something changed. */ 317 mii_phy_update(sc, cmd); 318 return 0; 319 } 320 321 static void 322 micphy_writexreg(struct mii_softc *sc, uint32_t reg, uint32_t wval) 323 { 324 uint16_t rval __debugused; 325 326 PHY_WRITE(sc, KSZ_XREG_CONTROL, KSZ_XREG_CTL_SEL_WRITE | reg); 327 PHY_WRITE(sc, KSZ_XREG_WRITE, wval); 328 PHY_WRITE(sc, KSZ_XREG_CONTROL, KSZ_XREG_CTL_SEL_READ | reg); 329 PHY_READ(sc, KSZ_XREG_READ, &rval); 330 KDASSERT(wval == rval); 331 } 332 333 static void 334 micphy_fixup(struct mii_softc *sc, int model, int rev, device_t parent) 335 { 336 switch (model) { 337 case MII_MODEL_MICREL_KSZ9021_8001_8721: 338 if (!device_is_a(parent, "cpsw")) 339 break; 340 341 aprint_normal_dev(sc->mii_dev, 342 "adjusting RGMII signal timing for cpsw\n"); 343 344 // RGMII RX Data Pad Skew 345 micphy_writexreg(sc, REG_RGMII_RX_DATA, 0x0000); 346 347 // RGMII Clock and Control Pad Skew 348 micphy_writexreg(sc, REG_RGMII_CLOCK_AND_CONTROL, 0x9090); 349 350 break; 351 default: 352 break; 353 } 354 355 return; 356 } 357 358 static void 359 micphy_status(struct mii_softc *sc) 360 { 361 struct micphy_softc *msc = device_private(sc->mii_dev); 362 struct mii_data *mii = sc->mii_pdata; 363 uint16_t bmsr, bmcr, sr; 364 365 /* For unknown devices */ 366 if (msc->sc_lstype == MICPHYF_LSTYPE_DEFAULT) { 367 ukphy_status(sc); 368 return; 369 } 370 371 mii->mii_media_status = IFM_AVALID; 372 mii->mii_media_active = IFM_ETHER; 373 374 PHY_READ(sc, MII_BMCR, &bmcr); 375 376 PHY_READ(sc, MII_BMSR, &bmsr); 377 PHY_READ(sc, MII_BMSR, &bmsr); 378 if (bmsr & BMSR_LINK) 379 mii->mii_media_status |= IFM_ACTIVE; 380 381 if (bmcr & BMCR_AUTOEN) { 382 if ((bmsr & BMSR_ACOMP) == 0) { 383 mii->mii_media_active |= IFM_NONE; 384 return; 385 } 386 } 387 388 if (msc->sc_lstype == MICPHYF_LSTYPE_1F_42) { 389 PHY_READ(sc, KSZ8041_PHYCTL2, &sr); 390 if ((sr & KSZ8041_PHY_SPD_MASK) == 0) 391 mii->mii_media_active |= IFM_NONE; 392 else if (sr & KSZ8041_PHY_SPD_100TX) 393 mii->mii_media_active |= IFM_100_TX; 394 else if (sr & KSZ8041_PHY_SPD_10T) 395 mii->mii_media_active |= IFM_10_T; 396 if (sr & KSZ8041_PHY_FDX) 397 mii->mii_media_active |= IFM_FDX 398 | mii_phy_flowstatus(sc); 399 } else if (msc->sc_lstype == MICPHYF_LSTYPE_1E_20) { 400 PHY_READ(sc, KSZ8051_PHYCTL1, &sr); 401 if ((sr & KSZ8051_PHY_SPD_MASK) == 0) 402 mii->mii_media_active |= IFM_NONE; 403 else if (sr & KSZ8051_PHY_SPD_100TX) 404 mii->mii_media_active |= IFM_100_TX; 405 else if (sr & KSZ8051_PHY_SPD_10T) 406 mii->mii_media_active |= IFM_10_T; 407 if (sr & KSZ8051_PHY_FDX) 408 mii->mii_media_active |= IFM_FDX 409 | mii_phy_flowstatus(sc); 410 } else if (msc->sc_lstype == MICPHYF_LSTYPE_GIGA) { 411 /* 9021/9031/7430/9131 gphy */ 412 PHY_READ(sc, KSZ_GPHYCTL, &sr); 413 if (sr & KSZ_GPHY_SPD_1000T) 414 mii->mii_media_active |= IFM_1000_T; 415 else if (sr & KSZ_GPHY_SPD_100TX) 416 mii->mii_media_active |= IFM_100_TX; 417 else if (sr & KSZ_GPHY_SPD_10T) 418 mii->mii_media_active |= IFM_10_T; 419 else 420 mii->mii_media_active |= IFM_NONE; 421 if ((mii->mii_media_active & IFM_1000_T) 422 && (sr & KSZ_GPHY_1000T_MS)) 423 mii->mii_media_active |= IFM_ETH_MASTER; 424 if (sr & KSZ_GPHY_FDX) 425 mii->mii_media_active |= IFM_FDX 426 | mii_phy_flowstatus(sc); 427 else 428 mii->mii_media_active |= IFM_HDX; 429 } 430 } 431
Indexes created Wed Oct 15 16:09:53 GMT 2025