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miidevs.h revision 1.26 
      1 /*	$NetBSD: miidevs.h,v 1.26 2001/07/20 07:07:28 thorpej Exp $	*/
      2 
      3 /*
      4  * THIS FILE AUTOMATICALLY GENERATED.  DO NOT EDIT.
      5  *
      6  * generated from:
      7  *	NetBSD: miidevs,v 1.26 2001/07/20 07:06:42 thorpej Exp
      8  */
      9 
     10 /*-
     11  * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc.
     12  * All rights reserved.
     13  *
     14  * This code is derived from software contributed to The NetBSD Foundation
     15  * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
     16  * NASA Ames Research Center.
     17  *
     18  * Redistribution and use in source and binary forms, with or without
     19  * modification, are permitted provided that the following conditions
     20  * are met:
     21  * 1. Redistributions of source code must retain the above copyright
     22  *    notice, this list of conditions and the following disclaimer.
     23  * 2. Redistributions in binary form must reproduce the above copyright
     24  *    notice, this list of conditions and the following disclaimer in the
     25  *    documentation and/or other materials provided with the distribution.
     26  * 3. All advertising materials mentioning features or use of this software
     27  *    must display the following acknowledgement:
     28  *	This product includes software developed by the NetBSD
     29  *	Foundation, Inc. and its contributors.
     30  * 4. Neither the name of The NetBSD Foundation nor the names of its
     31  *    contributors may be used to endorse or promote products derived
     32  *    from this software without specific prior written permission.
     33  *
     34  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     35  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     36  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     37  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     38  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     39  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     40  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     41  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     42  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     43  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     44  * POSSIBILITY OF SUCH DAMAGE.
     45  */
     46 
     47 /*
     48  * List of known MII OUIs.
     49  * For a complete list see http://standards.ieee.org/regauth/oui/
     50  *
     51  * XXX Vendors do obviously not agree how OUIs (24 bit) are mapped
     52  * to the 22 bits available in the id registers.
     53  * IEEE 802.3u-1995, subclause 22.2.4.3.1, figure 22-12, depicts the right
     54  * mapping; the bit positions are defined in IEEE 802-1990, figure 5.2.
     55  * (There is a formal 802.3 interpretation, number 1-07/98 of July 09 1998,
     56  * about this.)
     57  * The MII_OUI() macro in "mii.h" reflects this.
     58  * If a vendor uses a different mapping, an "xx" prefixed OUI is defined here
     59  * which is mangled accordingly to compensate.
     60  */
     61 
     62 #define	MII_OUI_ALTIMA	0x0010a9	/* Altima Communications */
     63 #define	MII_OUI_AMD	0x00001a	/* Advanced Micro Devices */
     64 #define	MII_OUI_BROADCOM	0x001018	/* Broadcom Corporation */
     65 #define	MII_OUI_DAVICOM	0x00606e	/* Davicom Semiconductor */
     66 #define	MII_OUI_ENABLESEMI	0x0010dd	/* Enable Semiconductor */
     67 #define	MII_OUI_ICS	0x00a0be	/* Integrated Circuit Systems */
     68 #define	MII_OUI_INTEL	0x00aa00	/* Intel */
     69 #define	MII_OUI_LEVEL1	0x00207b	/* Level 1 */
     70 #define	MII_OUI_MARVELL	0x005043	/* Marvell Semiconductor */
     71 #define	MII_OUI_MYSON	0x00c0b4	/* Myson Technology */
     72 #define	MII_OUI_NATSEMI	0x080017	/* National Semiconductor */
     73 #define	MII_OUI_PMCSIERRA	0x00e004	/* PMC-Sierra */
     74 #define	MII_OUI_QUALSEMI	0x006051	/* Quality Semiconductor */
     75 #define	MII_OUI_SEEQ	0x00a07d	/* Seeq */
     76 #define	MII_OUI_SIS	0x00e006	/* Silicon Integrated Systems */
     77 #define	MII_OUI_TI	0x080028	/* Texas Instruments */
     78 #define	MII_OUI_TSC	0x00c039	/* TDK Semiconductor */
     79 #define	MII_OUI_XAQTI	0x00e0ae	/* XaQti Corp. */
     80 
     81 /* in the 79c873, AMD uses another OUI (which matches reversed Davicom!) */
     82 #define	MII_OUI_xxAMD	0x000676	/* Advanced Micro Devices */
     83 
     84 /* Some Intel 82553's use an alternative OUI. */
     85 #define	MII_OUI_xxINTEL	0x001f00	/* Intel */
     86 
     87 /* bad bitorder (bits "g" and "h" (= MSBs byte 1) lost) */
     88 #define	MII_OUI_yyAMD	0x000058	/* Advanced Micro Devices */
     89 #define	MII_OUI_xxBROADCOM	0x000818	/* Broadcom Corporation */
     90 #define	MII_OUI_yyINTEL	0x005500	/* Intel */
     91 #define	MII_OUI_xxMYSON	0x00032d	/* Myson Technology */
     92 #define	MII_OUI_xxNATSEMI	0x1000e8	/* National Semiconductor */
     93 #define	MII_OUI_xxQUALSEMI	0x00068a	/* Quality Semiconductor */
     94 #define	MII_OUI_xxTSC	0x00039c	/* TDK Semiconductor */
     95 
     96 /* bad byteorder (bits "q" and "r" (= LSBs byte 3) lost) */
     97 #define	MII_OUI_xxLEVEL1	0x782000	/* Level 1 */
     98 #define	MII_OUI_xxXAQTI	0xace000	/* XaQti Corp. */
     99 
    100 /* Don't know what's going on here. */
    101 #define	MII_OUI_xxDAVICOM	0x000602	/* Davicom Semiconductor */
    102 #define	MII_OUI_xxPMCSIERRA	0x0009c0	/* PMC-Sierra */
    103 
    104 #define	MII_OUI_xxMARVELL	0x000ac2	/* Marvell Semiconductor */
    105 
    106 /*
    107  * List of known models.  Grouped by oui.
    108  */
    109 
    110 /* Altima Communications PHYs */
    111 #define	MII_MODEL_ALTIMA_AC101	0x0021
    112 #define	MII_STR_ALTIMA_AC101	"AC101 10/100 media interface"
    113 
    114 /* Advanced Micro Devices PHYs */
    115 #define	MII_MODEL_xxAMD_79C873	0x0000
    116 #define	MII_STR_xxAMD_79C873	"Am79C873 10/100 media interface"
    117 #define	MII_MODEL_yyAMD_79c973phy	0x0036
    118 #define	MII_STR_yyAMD_79c973phy	"Am79C973 internal PHY"
    119 #define	MII_MODEL_yyAMD_79c901	0x0037
    120 #define	MII_STR_yyAMD_79c901	"Am79C901 10 PHY"
    121 #define	MII_MODEL_yyAMD_79c901home	0x0039
    122 #define	MII_STR_yyAMD_79c901home	"Am79C901 HomePHY"
    123 
    124 /* Broadcom Corp. PHYs */
    125 #define	MII_MODEL_xxBROADCOM_3C905C	0x0017
    126 #define	MII_STR_xxBROADCOM_3C905C	"Broadcom 3C905C internal PHY"
    127 #define	MII_MODEL_xxBROADCOM_BCM5201	0x0021
    128 #define	MII_STR_xxBROADCOM_BCM5201	"BCM5201 10/100 media interface"
    129 #define	MII_MODEL_BROADCOM_BCM5221	0x001e
    130 #define	MII_STR_BROADCOM_BCM5221	"BCM5221 10/100 media interface"
    131 #define	MII_MODEL_BROADCOM_BCM5400	0x0004
    132 #define	MII_STR_BROADCOM_BCM5400	"BCM5400 1000BASE-T media interface"
    133 #define	MII_MODEL_BROADCOM_BCM5401	0x0005
    134 #define	MII_STR_BROADCOM_BCM5401	"BCM5401 1000BASE-T media interface"
    135 #define	MII_MODEL_BROADCOM_BCM5411	0x0007
    136 #define	MII_STR_BROADCOM_BCM5411	"BCM5411 1000BASE-T media interface"
    137 
    138 /* Davicom Semiconductor PHYs */
    139 #define	MII_MODEL_xxDAVICOM_DM9101	0x0000
    140 #define	MII_STR_xxDAVICOM_DM9101	"DM9101 10/100 media interface"
    141 
    142 /* Integrated Circuit Systems PHYs */
    143 #define	MII_MODEL_ICS_1890	0x0002
    144 #define	MII_STR_ICS_1890	"ICS1890 10/100 media interface"
    145 
    146 /* Intel PHYs */
    147 #define	MII_MODEL_xxINTEL_I82553	0x0000
    148 #define	MII_STR_xxINTEL_I82553	"i82553 10/100 media interface"
    149 #define	MII_MODEL_yyINTEL_I82555	0x0015
    150 #define	MII_STR_yyINTEL_I82555	"i82555 10/100 media interface"
    151 #define	MII_MODEL_yyINTEL_I82562EH	0x0017
    152 #define	MII_STR_yyINTEL_I82562EH	"i82562EH HomePNA interface"
    153 #define	MII_MODEL_yyINTEL_I82562EM	0x0032
    154 #define	MII_STR_yyINTEL_I82562EM	"i82562EM 10/100 media interface"
    155 #define	MII_MODEL_yyINTEL_I82562ET	0x0033
    156 #define	MII_STR_yyINTEL_I82562ET	"i82562ET 10/100 media interface"
    157 #define	MII_MODEL_yyINTEL_I82553	0x0035
    158 #define	MII_STR_yyINTEL_I82553	"i82553 10/100 media interface"
    159 
    160 /* Level 1 PHYs */
    161 #define	MII_MODEL_xxLEVEL1_LXT970	0x0000
    162 #define	MII_STR_xxLEVEL1_LXT970	"LXT970 10/100 media interface"
    163 #define	MII_MODEL_LEVEL1_LXT1000_OLD	0x0003
    164 #define	MII_STR_LEVEL1_LXT1000_OLD	"LXT1000 1000BASE-T media interface"
    165 #define	MII_MODEL_LEVEL1_LXT1000	0x000c
    166 #define	MII_STR_LEVEL1_LXT1000	"LXT1000 1000BASE-T media interface"
    167 
    168 /* Marvell Semiconductor PHYs */
    169 #define	MII_MODEL_xxMARVELL_E1000	0x0005
    170 #define	MII_STR_xxMARVELL_E1000	"Marvell 88E1000 Gigabit PHY"
    171 
    172 /* Myson Technology PHYs */
    173 #define	MII_MODEL_xxMYSON_MTD972	0x0000
    174 #define	MII_STR_xxMYSON_MTD972	"MTD972 10/100 media interface"
    175 
    176 /* National Semiconductor PHYs */
    177 #define	MII_MODEL_xxNATSEMI_DP83840	0x0000
    178 #define	MII_STR_xxNATSEMI_DP83840	"DP83840 10/100 media interface"
    179 #define	MII_MODEL_xxNATSEMI_DP83843	0x0001
    180 #define	MII_STR_xxNATSEMI_DP83843	"DP83843 10/100 media interface"
    181 #define	MII_MODEL_xxNATSEMI_DP83815	0x0002
    182 #define	MII_STR_xxNATSEMI_DP83815	"DP83815 10/100 media interface"
    183 #define	MII_MODEL_xxNATSEMI_DP83891	0x0005
    184 #define	MII_STR_xxNATSEMI_DP83891	"DP83891 1000BASE-T media interface"
    185 #define	MII_MODEL_xxNATSEMI_DP83861	0x0006
    186 #define	MII_STR_xxNATSEMI_DP83861	"DP83861 1000BASE-T media interface"
    187 
    188 /* PMC Sierra PHYs */
    189 #define	MII_MODEL_xxPMCSIERRA_PM8351	0x0000
    190 #define	MII_STR_xxPMCSIERRA_PM8351	"PM8351 OctalPHY Gigabit interface"
    191 
    192 /* Quality Semiconductor PHYs */
    193 #define	MII_MODEL_xxQUALSEMI_QS6612	0x0000
    194 #define	MII_STR_xxQUALSEMI_QS6612	"QS6612 10/100 media interface"
    195 
    196 /* Seeq PHYs */
    197 #define	MII_MODEL_SEEQ_80220	0x0003
    198 #define	MII_STR_SEEQ_80220	"Seeq 80220 10/100 media interface"
    199 #define	MII_MODEL_SEEQ_84220	0x0004
    200 #define	MII_STR_SEEQ_84220	"Seeq 84220 10/100 media interface"
    201 #define	MII_MODEL_SEEQ_80225	0x0008
    202 #define	MII_STR_SEEQ_80225	"Seeq 80225 10/100 media interface"
    203 
    204 /* Silicon Integrated Systems PHYs */
    205 #define	MII_MODEL_SIS_900	0x0000
    206 #define	MII_STR_SIS_900	"SiS 900 10/100 media interface"
    207 
    208 /* Texas Instruments PHYs */
    209 #define	MII_MODEL_TI_TLAN10T	0x0001
    210 #define	MII_STR_TI_TLAN10T	"ThunderLAN 10BASE-T media interface"
    211 #define	MII_MODEL_TI_100VGPMI	0x0002
    212 #define	MII_STR_TI_100VGPMI	"ThunderLAN 100VG-AnyLan media interface"
    213 #define	MII_MODEL_TI_TNETE2101	0x0003
    214 #define	MII_STR_TI_TNETE2101	"TNETE2101 media interface"
    215 
    216 /* TDK Semiconductor PHYs */
    217 #define	MII_MODEL_xxTSC_78Q2120	0x0014
    218 #define	MII_STR_xxTSC_78Q2120	"78Q2120 10/100 media interface"
    219 #define	MII_MODEL_xxTSC_78Q2121	0x0015
    220 #define	MII_STR_xxTSC_78Q2121	"78Q2121 100BASE-TX media interface"
    221 
    222 /* XaQti Corp. PHYs */
    223 #define	MII_MODEL_xxXAQTI_XMACII	0x0000
    224 #define	MII_STR_xxXAQTI_XMACII	"XaQti Corp. XMAC II gigabit interface"
    225