miidevs.h revision 1.6
1 /* $NetBSD: miidevs.h,v 1.6 1999/05/14 11:38:05 drochner Exp $ */ 2 3 /* 4 * THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT. 5 * 6 * generated from: 7 * NetBSD: miidevs,v 1.6 1999/05/14 11:37:30 drochner Exp 8 */ 9 10 /*- 11 * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc. 12 * All rights reserved. 13 * 14 * This code is derived from software contributed to The NetBSD Foundation 15 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 16 * NASA Ames Research Center. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions 20 * are met: 21 * 1. Redistributions of source code must retain the above copyright 22 * notice, this list of conditions and the following disclaimer. 23 * 2. Redistributions in binary form must reproduce the above copyright 24 * notice, this list of conditions and the following disclaimer in the 25 * documentation and/or other materials provided with the distribution. 26 * 3. All advertising materials mentioning features or use of this software 27 * must display the following acknowledgement: 28 * This product includes software developed by the NetBSD 29 * Foundation, Inc. and its contributors. 30 * 4. Neither the name of The NetBSD Foundation nor the names of its 31 * contributors may be used to endorse or promote products derived 32 * from this software without specific prior written permission. 33 * 34 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 35 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 36 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 37 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 38 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 39 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 40 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 41 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 42 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 43 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 44 * POSSIBILITY OF SUCH DAMAGE. 45 */ 46 47 /* 48 * List of known MII OUIs. 49 * For a complete list see http://standards.ieee.org/regauth/oui/ 50 * 51 * XXX Vendors do obviously not agree how OUIs (18 bit) are mapped 52 * to the 16 bits available in the id registers. The MII_OUI() macro 53 * in "mii.h" reflects the most obvious way. If a vendor uses a 54 * different mapping, an "xx" prefixed OUI is defined here which is 55 * mangled accordingly to compensate. 56 */ 57 58 #define MII_OUI_AMD 0x00001a /* Advanced Micro Devices */ 59 #define MII_OUI_DAVICOM 0x00606e /* Davicom Semiconductor */ 60 #define MII_OUI_ICS 0x00a0be /* Integrated Circuit Systems */ 61 #define MII_OUI_INTEL 0x00aa00 /* Intel */ 62 #define MII_OUI_LEVEL1 0x00207b /* Level 1 */ 63 #define MII_OUI_NATSEMI 0x080017 /* National Semiconductor */ 64 #define MII_OUI_QUALSEMI 0x006051 /* Quality Semiconductor */ 65 #define MII_OUI_SEEQ 0x00a07d /* Seeq */ 66 #define MII_OUI_SIS 0x00e006 /* Silicon Integrated Systems */ 67 #define MII_OUI_TI 0x080028 /* Texas Instruments */ 68 69 70 /* in the 79c873, AMD uses another OUI (which matches Davicom!) */ 71 #define MII_OUI_xxAMD 0x00606e /* Advanced Micro Devices */ 72 73 /* some vendors have the bits swapped within bytes 74 (ie, ordered as on the wire) */ 75 #define MII_OUI_xxICS 0x00057d /* Integrated Circuit Systems */ 76 #define MII_OUI_xxSEEQ 0x0005be /* Seeq */ 77 #define MII_OUI_xxSIS 0x000760 /* Silicon Integrated Systems */ 78 #define MII_OUI_xxTI 0x100014 /* Texas Instruments */ 79 80 /* Level 1 is completely different - from right to left. 81 (Two bits get lost in the third OUI byte.) */ 82 #define MII_OUI_xxLEVEL1 0x1e0400 /* Level 1 */ 83 84 /* Don't know what's going on here. */ 85 #define MII_OUI_xxDAVICOM 0x006040 /* Davicom Semiconductor */ 86 87 88 /* 89 * List of known models. Grouped by oui. 90 */ 91 92 /* Advanced Micro Devices PHYs */ 93 #define MII_MODEL_xxAMD_79C873 0x0000 94 #define MII_STR_xxAMD_79C873 "Am79C873 10/100 media interface" 95 #define MII_MODEL_AMD_79c973phy 0x0036 96 #define MII_STR_AMD_79c973phy "Am79c973 internal PHY" 97 98 /* Davicom Semiconductor PHYs */ 99 #define MII_MODEL_xxDAVICOM_DM9101 0x0000 100 #define MII_STR_xxDAVICOM_DM9101 "DM9101 10/100 media interface" 101 102 /* Integrated Circuit Systems PHYs */ 103 #define MII_MODEL_xxICS_1890 0x0002 104 #define MII_STR_xxICS_1890 "ICS1890 10/100 media interface" 105 106 /* Intel PHYs */ 107 #define MII_MODEL_INTEL_I82555 0x0015 108 #define MII_STR_INTEL_I82555 "i82555 10/100 media interface" 109 110 /* Level 1 PHYs */ 111 #define MII_MODEL_xxLEVEL1_LXT970 0x0000 112 #define MII_STR_xxLEVEL1_LXT970 "LXT970 10/100 media interface" 113 114 /* National Semiconductor PHYs */ 115 #define MII_MODEL_NATSEMI_DP83840 0x0000 116 #define MII_STR_NATSEMI_DP83840 "DP83840 10/100 media interface" 117 #define MII_MODEL_NATSEMI_DP83843 0x0001 118 #define MII_STR_NATSEMI_DP83843 "DP83843 10/100 media interface" 119 120 /* Quality Semiconductor PHYs */ 121 #define MII_MODEL_QUALSEMI_QS6612 0x0000 122 #define MII_STR_QUALSEMI_QS6612 "QS6612 10/100 media interface" 123 124 /* Seeq PHYs */ 125 #define MII_MODEL_xxSEEQ_80220 0x0003 126 #define MII_STR_xxSEEQ_80220 "Seeq 80220 10/100 media interface" 127 #define MII_MODEL_xxSEEQ_84220 0x0004 128 #define MII_STR_xxSEEQ_84220 "Seeq 84220 10/100 media interface" 129 130 /* Silicon Integrated Systems PHYs */ 131 #define MII_MODEL_xxSIS_900 0x0000 132 #define MII_STR_xxSIS_900 "SiS 900 10/100 media interface" 133 134 /* Texas Instruments PHYs */ 135 #define MII_MODEL_xxTI_TLAN10T 0x0001 136 #define MII_STR_xxTI_TLAN10T "ThunderLAN 10baseT media interface" 137 #define MII_MODEL_xxTI_100VGPMI 0x0002 138 #define MII_STR_xxTI_100VGPMI "ThunderLAN 100VG-AnyLan media interface" 139
Indexes created Mon Sep 29 21:09:56 GMT 2025