rgephy.c revision 1.1
1 /* $NetBSD: rgephy.c,v 1.1 2004/12/23 06:26:30 jonathan Exp $ */ 2 3 /* 4 * Copyright (c) 2003 5 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: rgephy.c,v 1.1 2004/12/23 06:26:30 jonathan Exp $"); 37 38 39 /* 40 * Driver for the RealTek 8169S/8110S internal 10/100/1000 PHY. 41 */ 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/kernel.h> 46 #include <sys/socket.h> 47 48 49 #include <net/if.h> 50 #include <net/if_media.h> 51 52 #include <dev/mii/mii.h> 53 #include <dev/mii/miivar.h> 54 #include <dev/mii/miidevs.h> 55 56 #include <dev/mii/rgephyreg.h> 57 58 #include <dev/ic/rtl81x9reg.h> 59 60 static int rgephy_match(struct device *, struct cfdata *, void *); 61 static void rgephy_attach(struct device *, struct device *, void *); 62 63 CFATTACH_DECL(rgephy, sizeof(struct mii_softc), 64 rgephy_match, rgephy_attach, mii_phy_detach, mii_phy_activate); 65 66 67 static int rgephy_service(struct mii_softc *, struct mii_data *, int); 68 static void rgephy_status(struct mii_softc *); 69 static int rgephy_mii_phy_auto(struct mii_softc *); 70 static void rgephy_reset(struct mii_softc *); 71 static void rgephy_reset(struct mii_softc *); 72 static void rgephy_loop(struct mii_softc *); 73 static void rgephy_load_dspcode(struct mii_softc *); 74 static int rgephy_mii_model; 75 76 static const struct mii_phy_funcs rgephy_funcs = { 77 rgephy_service, rgephy_status, rgephy_reset, 78 }; 79 80 static const struct mii_phydesc rgephys[] = { 81 { MII_OUI_xxREALTEK, MII_MODEL_xxREALTEK_RTL8169S, 82 MII_STR_xxREALTEK_RTL8169S }, 83 84 { MII_OUI_REALTEK, MII_MODEL_REALTEK_RTL8169S, 85 MII_STR_REALTEK_RTL8169S }, 86 87 }; 88 89 static int 90 rgephy_match(struct device *parent, struct cfdata *match, void *aux) 91 { 92 struct mii_attach_args *ma = aux; 93 94 if (mii_phy_match(ma, rgephys) != NULL) 95 return (10); 96 97 return (0); 98 } 99 100 static void 101 rgephy_attach(struct device *parent, struct device *self, void *aux) 102 { 103 struct mii_softc *sc = (struct mii_softc *)self; 104 struct mii_attach_args *ma = aux; 105 struct mii_data *mii = ma->mii_data; 106 const struct mii_phydesc *mpd; 107 int rev; 108 const char *sep = ""; 109 110 rev = MII_REV(ma->mii_id2); 111 mpd = mii_phy_match(ma, rgephys); 112 aprint_naive(": Media interface\n"); 113 aprint_normal(": %s, rev. %d\n", mpd->mpd_name, rev); 114 115 sc->mii_mpd_model = rev; /* XXX miivar.h comment vs usage? */ 116 sc->mii_inst = mii->mii_instance; 117 sc->mii_phy = ma->mii_phyno; 118 sc->mii_pdata = mii; 119 sc->mii_flags = mii->mii_flags; 120 sc->mii_anegticks = 5; 121 122 sc->mii_funcs = &rgephy_funcs; 123 124 /* Don't do isolate on this PHY. */ 125 sc->mii_flags |= MIIF_NOISOLATE; 126 127 #define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL) 128 #define PRINT(n) aprint_normal("%s%s", sep, (n)); sep = ", " 129 130 #if 0 131 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, sc->mii_inst), 132 BMCR_ISO); 133 #endif 134 #ifdef __FreeBSD__ 135 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst), 136 BMCR_LOOP|BMCR_S100); 137 #endif 138 139 rgephy_mii_model = MII_MODEL(ma->mii_id2); 140 PHY_RESET(sc); 141 142 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask; 143 sc->mii_capabilities &= ~BMSR_ANEG; 144 145 /* 146 * FreeBSD does not check EXSTAT, but instead adds gigabit 147 * media explicitly. Why? 148 */ 149 aprint_normal("%s: ", sc->mii_dev.dv_xname); 150 #ifdef __FreeBSD__ 151 mii_phy_add_media(sc); 152 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, 0, sc->mii_inst), 153 RGEPHY_BMCR_FDX); 154 PRINT(", 1000baseTX"); 155 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, IFM_FDX, sc->mii_inst), 0); 156 PRINT("1000baseTX-FDX"); 157 #else 158 if (sc->mii_capabilities & BMSR_EXTSTAT) { 159 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); 160 } 161 mii_phy_add_media(sc); 162 #endif 163 /* rtl8169S does not report auto-sense; add manually. */ 164 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), MII_NMEDIA); 165 sep =", "; 166 PRINT("auto"); 167 168 #undef ADD 169 #undef PRINT 170 171 aprint_normal("\n"); 172 } 173 174 static int 175 rgephy_service(sc, mii, cmd) 176 struct mii_softc *sc; 177 struct mii_data *mii; 178 int cmd; 179 { 180 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 181 int reg, speed, gig; 182 183 switch (cmd) { 184 case MII_POLLSTAT: 185 /* 186 * If we're not polling our PHY instance, just return. 187 */ 188 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 189 return (0); 190 break; 191 192 case MII_MEDIACHG: 193 /* 194 * If the media indicates a different PHY instance, 195 * isolate ourselves. 196 */ 197 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 198 reg = PHY_READ(sc, MII_BMCR); 199 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO); 200 return (0); 201 } 202 203 /* 204 * If the interface is not up, don't do anything. 205 */ 206 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 207 break; 208 209 PHY_RESET(sc); /* XXX hardware bug work-around */ 210 211 switch (IFM_SUBTYPE(ife->ifm_media)) { 212 case IFM_AUTO: 213 #ifdef foo 214 /* 215 * If we're already in auto mode, just return. 216 */ 217 if (PHY_READ(sc, RGEPHY_MII_BMCR) & RGEPHY_BMCR_AUTOEN) 218 return (0); 219 #endif 220 (void) rgephy_mii_phy_auto(sc); 221 break; 222 case IFM_1000_T: 223 speed = RGEPHY_S1000; 224 goto setit; 225 case IFM_100_TX: 226 speed = RGEPHY_S100; 227 goto setit; 228 case IFM_10_T: 229 speed = RGEPHY_S10; 230 setit: 231 rgephy_loop(sc); 232 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 233 speed |= RGEPHY_BMCR_FDX; 234 gig = RGEPHY_1000CTL_AFD; 235 } else { 236 gig = RGEPHY_1000CTL_AHD; 237 } 238 239 PHY_WRITE(sc, RGEPHY_MII_1000CTL, 0); 240 PHY_WRITE(sc, RGEPHY_MII_BMCR, speed); 241 PHY_WRITE(sc, RGEPHY_MII_ANAR, RGEPHY_SEL_TYPE); 242 243 if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T) 244 break; 245 246 PHY_WRITE(sc, RGEPHY_MII_1000CTL, gig); 247 PHY_WRITE(sc, RGEPHY_MII_BMCR, 248 speed|RGEPHY_BMCR_AUTOEN|RGEPHY_BMCR_STARTNEG); 249 250 /* 251 * When settning the link manually, one side must 252 * be the master and the other the slave. However 253 * ifmedia doesn't give us a good way to specify 254 * this, so we fake it by using one of the LINK 255 * flags. If LINK0 is set, we program the PHY to 256 * be a master, otherwise it's a slave. 257 */ 258 if ((mii->mii_ifp->if_flags & IFF_LINK0)) { 259 PHY_WRITE(sc, RGEPHY_MII_1000CTL, 260 gig|RGEPHY_1000CTL_MSE|RGEPHY_1000CTL_MSC); 261 } else { 262 PHY_WRITE(sc, RGEPHY_MII_1000CTL, 263 gig|RGEPHY_1000CTL_MSE); 264 } 265 break; 266 #ifdef foo 267 case IFM_NONE: 268 PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN); 269 break; 270 #endif 271 case IFM_100_T4: 272 default: 273 return (EINVAL); 274 } 275 break; 276 277 case MII_TICK: 278 /* 279 * If we're not currently selected, just return. 280 */ 281 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 282 return (0); 283 284 /* 285 * Is the interface even up? 286 */ 287 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 288 return (0); 289 290 /* 291 * Only used for autonegotiation. 292 */ 293 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) 294 break; 295 296 /* 297 * Check to see if we have link. If we do, we don't 298 * need to restart the autonegotiation process. Read 299 * the BMSR twice in case it's latched. 300 */ 301 reg = PHY_READ(sc, RTK_GMEDIASTAT); 302 if (reg & RTK_GMEDIASTAT_LINK) 303 break; 304 305 /* 306 * Only retry autonegotiation every 5 seconds. 307 */ 308 if (++sc->mii_ticks <= 5/*10*/) 309 break; 310 311 sc->mii_ticks = 0; 312 rgephy_mii_phy_auto(sc); 313 return (0); 314 } 315 316 /* Update the media status. */ 317 rgephy_status(sc); 318 319 /* 320 * Callback if something changed. Note that we need to poke 321 * the DSP on the RealTek PHYs if the media changes. 322 * 323 */ 324 if (sc->mii_media_active != mii->mii_media_active || 325 sc->mii_media_status != mii->mii_media_status || 326 cmd == MII_MEDIACHG) { 327 /* XXX only for v0/v1 phys. */ 328 if (sc->mii_mpd_model < 2) 329 rgephy_load_dspcode(sc); 330 } 331 mii_phy_update(sc, cmd); 332 return (0); 333 } 334 335 static void 336 rgephy_status(sc) 337 struct mii_softc *sc; 338 { 339 struct mii_data *mii = sc->mii_pdata; 340 int bmsr, bmcr; 341 342 mii->mii_media_status = IFM_AVALID; 343 mii->mii_media_active = IFM_ETHER; 344 345 bmsr = PHY_READ(sc, RTK_GMEDIASTAT); 346 347 if (bmsr & RTK_GMEDIASTAT_LINK) 348 mii->mii_media_status |= IFM_ACTIVE; 349 bmsr = PHY_READ(sc, RGEPHY_MII_BMSR); 350 351 bmcr = PHY_READ(sc, RGEPHY_MII_BMCR); 352 353 if (bmcr & RGEPHY_BMCR_LOOP) 354 mii->mii_media_active |= IFM_LOOP; 355 356 if (bmcr & RGEPHY_BMCR_AUTOEN) { 357 if ((bmsr & RGEPHY_BMSR_ACOMP) == 0) { 358 /* Erg, still trying, I guess... */ 359 mii->mii_media_active |= IFM_NONE; 360 return; 361 } 362 } 363 364 bmsr = PHY_READ(sc, RTK_GMEDIASTAT); 365 if (bmsr & RTK_GMEDIASTAT_10MBPS) 366 mii->mii_media_active |= IFM_10_T; 367 if (bmsr & RTK_GMEDIASTAT_100MBPS) 368 mii->mii_media_active |= IFM_100_TX; 369 if (bmsr & RTK_GMEDIASTAT_1000MBPS) 370 mii->mii_media_active |= IFM_1000_T; 371 if (bmsr & RTK_GMEDIASTAT_FDX) 372 mii->mii_media_active |= IFM_FDX; 373 374 return; 375 } 376 377 378 static int 379 rgephy_mii_phy_auto(mii) 380 struct mii_softc *mii; 381 { 382 rgephy_loop(mii); 383 PHY_RESET(mii); 384 385 PHY_WRITE(mii, RGEPHY_MII_ANAR, 386 BMSR_MEDIA_TO_ANAR(mii->mii_capabilities) | ANAR_CSMA); 387 DELAY(1000); 388 PHY_WRITE(mii, RGEPHY_MII_1000CTL, RGEPHY_1000CTL_AFD); 389 DELAY(1000); 390 PHY_WRITE(mii, RGEPHY_MII_BMCR, 391 RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG); 392 DELAY(100); 393 394 return (EJUSTRETURN); 395 } 396 397 static void 398 rgephy_loop(struct mii_softc *sc) 399 { 400 u_int32_t bmsr; 401 int i; 402 403 PHY_WRITE(sc, RGEPHY_MII_BMCR, RGEPHY_BMCR_PDOWN); 404 DELAY(1000); 405 406 for (i = 0; i < 15000; i++) { 407 bmsr = PHY_READ(sc, RGEPHY_MII_BMSR); 408 if (!(bmsr & RGEPHY_BMSR_LINK)) { 409 #if 0 410 device_printf(sc->mii_dev, "looped %d\n", i); 411 #endif 412 break; 413 } 414 DELAY(10); 415 } 416 } 417 418 #define PHY_SETBIT(x, y, z) \ 419 PHY_WRITE(x, y, (PHY_READ(x, y) | (z))) 420 #define PHY_CLRBIT(x, y, z) \ 421 PHY_WRITE(x, y, (PHY_READ(x, y) & ~(z))) 422 423 /* 424 * Initialize RealTek PHY per the datasheet. The DSP in the PHYs of 425 * existing revisions of the 8169S/8110S chips need to be tuned in 426 * order to reliably negotiate a 1000Mbps link. Later revs of the 427 * chips may not require this software tuning. 428 */ 429 static void 430 rgephy_load_dspcode(struct mii_softc *sc) 431 { 432 int val; 433 434 435 436 #if 1 437 PHY_WRITE(sc, 31, 0x0001); 438 PHY_WRITE(sc, 21, 0x1000); 439 PHY_WRITE(sc, 24, 0x65C7); 440 PHY_CLRBIT(sc, 4, 0x0800); 441 val = PHY_READ(sc, 4) & 0xFFF; 442 PHY_WRITE(sc, 4, val); 443 PHY_WRITE(sc, 3, 0x00A1); 444 PHY_WRITE(sc, 2, 0x0008); 445 PHY_WRITE(sc, 1, 0x1020); 446 PHY_WRITE(sc, 0, 0x1000); 447 PHY_SETBIT(sc, 4, 0x0800); 448 PHY_CLRBIT(sc, 4, 0x0800); 449 val = (PHY_READ(sc, 4) & 0xFFF) | 0x7000; 450 PHY_WRITE(sc, 4, val); 451 PHY_WRITE(sc, 3, 0xFF41); 452 PHY_WRITE(sc, 2, 0xDE60); 453 PHY_WRITE(sc, 1, 0x0140); 454 PHY_WRITE(sc, 0, 0x0077); 455 val = (PHY_READ(sc, 4) & 0xFFF) | 0xA000; 456 PHY_WRITE(sc, 4, val); 457 PHY_WRITE(sc, 3, 0xDF01); 458 PHY_WRITE(sc, 2, 0xDF20); 459 PHY_WRITE(sc, 1, 0xFF95); 460 PHY_WRITE(sc, 0, 0xFA00); 461 val = (PHY_READ(sc, 4) & 0xFFF) | 0xB000; 462 PHY_WRITE(sc, 4, val); 463 PHY_WRITE(sc, 3, 0xFF41); 464 PHY_WRITE(sc, 2, 0xDE20); 465 PHY_WRITE(sc, 1, 0x0140); 466 PHY_WRITE(sc, 0, 0x00BB); 467 val = (PHY_READ(sc, 4) & 0xFFF) | 0xF000; 468 PHY_WRITE(sc, 4, val); 469 PHY_WRITE(sc, 3, 0xDF01); 470 PHY_WRITE(sc, 2, 0xDF20); 471 PHY_WRITE(sc, 1, 0xFF95); 472 PHY_WRITE(sc, 0, 0xBF00); 473 PHY_SETBIT(sc, 4, 0x0800); 474 PHY_CLRBIT(sc, 4, 0x0800); 475 PHY_WRITE(sc, 31, 0x0000); 476 #else 477 (void)val; 478 PHY_WRITE(sc, 0x1f, 0x0001); 479 PHY_WRITE(sc, 0x15, 0x1000); 480 PHY_WRITE(sc, 0x18, 0x65c7); 481 PHY_WRITE(sc, 0x04, 0x0000); 482 PHY_WRITE(sc, 0x03, 0x00a1); 483 PHY_WRITE(sc, 0x02, 0x0008); 484 PHY_WRITE(sc, 0x01, 0x1020); 485 PHY_WRITE(sc, 0x00, 0x1000); 486 PHY_WRITE(sc, 0x04, 0x0800); 487 PHY_WRITE(sc, 0x04, 0x0000); 488 PHY_WRITE(sc, 0x04, 0x7000); 489 PHY_WRITE(sc, 0x03, 0xff41); 490 PHY_WRITE(sc, 0x02, 0xde60); 491 PHY_WRITE(sc, 0x01, 0x0140); 492 PHY_WRITE(sc, 0x00, 0x0077); 493 PHY_WRITE(sc, 0x04, 0x7800); 494 PHY_WRITE(sc, 0x04, 0x7000); 495 PHY_WRITE(sc, 0x04, 0xa000); 496 PHY_WRITE(sc, 0x03, 0xdf01); 497 PHY_WRITE(sc, 0x02, 0xdf20); 498 PHY_WRITE(sc, 0x01, 0xff95); 499 PHY_WRITE(sc, 0x00, 0xfa00); 500 PHY_WRITE(sc, 0x04, 0xa800); 501 PHY_WRITE(sc, 0x04, 0xa000); 502 PHY_WRITE(sc, 0x04, 0xb000); 503 PHY_WRITE(sc, 0x0e, 0xff41); 504 PHY_WRITE(sc, 0x02, 0xde20); 505 PHY_WRITE(sc, 0x01, 0x0140); 506 PHY_WRITE(sc, 0x00, 0x00bb); 507 PHY_WRITE(sc, 0x04, 0xb800); 508 PHY_WRITE(sc, 0x04, 0xb000); 509 PHY_WRITE(sc, 0x04, 0xf000); 510 PHY_WRITE(sc, 0x03, 0xdf01); 511 PHY_WRITE(sc, 0x02, 0xdf20); 512 PHY_WRITE(sc, 0x01, 0xff95); 513 PHY_WRITE(sc, 0x00, 0xbf00); 514 PHY_WRITE(sc, 0x04, 0xf800); 515 PHY_WRITE(sc, 0x04, 0xf000); 516 PHY_WRITE(sc, 0x04, 0x0000); 517 PHY_WRITE(sc, 0x1f, 0x0000); 518 PHY_WRITE(sc, 0x0b, 0x0000); 519 520 #endif 521 522 DELAY(40); 523 524 printf(" complete\n"); 525 526 527 } 528 529 static void 530 rgephy_reset(struct mii_softc *sc) 531 { 532 mii_phy_reset(sc); 533 DELAY(1000); 534 535 if (sc->mii_mpd_model < 2) 536 rgephy_load_dspcode(sc); 537 else { 538 PHY_WRITE(sc, 0x1F, 0x0001); 539 PHY_WRITE(sc, 0x09, 0x273a); 540 PHY_WRITE(sc, 0x0e, 0x7bfb); 541 PHY_WRITE(sc, 0x1b, 0x841e); 542 543 PHY_WRITE(sc, 0x1F, 0x0002); 544 PHY_WRITE(sc, 0x01, 0x90D0); 545 PHY_WRITE(sc, 0x1F, 0x0000); 546 } 547 548 /* Reset capabilities */ 549 /* Step1: write our capability */ 550 PHY_WRITE(sc, 0x04,0x01e1); /* 10/100 capability */ 551 PHY_WRITE(sc, 0x09,0x0200); /* 1000 capability */ 552 553 #ifdef jrs_notyet 554 /* Step2: Restart NWay */ 555 PHY_WRITE(sc, 0x00, 0x1200); // NWay enable and Restart NWay 556 #endif 557 } 558
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