rgephy.c revision 1.10
1 /* $NetBSD: rgephy.c,v 1.10 2006/11/09 14:43:10 tsutsui Exp $ */ 2 3 /* 4 * Copyright (c) 2003 5 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: rgephy.c,v 1.10 2006/11/09 14:43:10 tsutsui Exp $"); 37 38 39 /* 40 * Driver for the RealTek 8169S/8110S internal 10/100/1000 PHY. 41 */ 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/kernel.h> 46 #include <sys/device.h> 47 #include <sys/socket.h> 48 49 50 #include <net/if.h> 51 #include <net/if_media.h> 52 53 #include <dev/mii/mii.h> 54 #include <dev/mii/miivar.h> 55 #include <dev/mii/miidevs.h> 56 57 #include <dev/mii/rgephyreg.h> 58 59 #include <dev/ic/rtl81x9reg.h> 60 61 static int rgephy_match(struct device *, struct cfdata *, void *); 62 static void rgephy_attach(struct device *, struct device *, void *); 63 64 CFATTACH_DECL(rgephy, sizeof(struct mii_softc), 65 rgephy_match, rgephy_attach, mii_phy_detach, mii_phy_activate); 66 67 68 static int rgephy_service(struct mii_softc *, struct mii_data *, int); 69 static void rgephy_status(struct mii_softc *); 70 static int rgephy_mii_phy_auto(struct mii_softc *); 71 static void rgephy_reset(struct mii_softc *); 72 static void rgephy_loop(struct mii_softc *); 73 static void rgephy_load_dspcode(struct mii_softc *); 74 static int rgephy_mii_model; 75 76 static const struct mii_phy_funcs rgephy_funcs = { 77 rgephy_service, rgephy_status, rgephy_reset, 78 }; 79 80 static const struct mii_phydesc rgephys[] = { 81 { MII_OUI_xxREALTEK, MII_MODEL_xxREALTEK_RTL8169S, 82 MII_STR_xxREALTEK_RTL8169S }, 83 84 { MII_OUI_REALTEK, MII_MODEL_REALTEK_RTL8169S, 85 MII_STR_REALTEK_RTL8169S }, 86 87 { 0, 0, 88 NULL } 89 }; 90 91 static int 92 rgephy_match(struct device *parent __unused, struct cfdata *match __unused, 93 void *aux) 94 { 95 struct mii_attach_args *ma = aux; 96 97 if (mii_phy_match(ma, rgephys) != NULL) 98 return (10); 99 100 return (0); 101 } 102 103 static void 104 rgephy_attach(struct device *parent __unused, struct device *self, void *aux) 105 { 106 struct mii_softc *sc = device_private(self); 107 struct mii_attach_args *ma = aux; 108 struct mii_data *mii = ma->mii_data; 109 const struct mii_phydesc *mpd; 110 int rev; 111 const char *sep = ""; 112 113 rev = MII_REV(ma->mii_id2); 114 mpd = mii_phy_match(ma, rgephys); 115 aprint_naive(": Media interface\n"); 116 aprint_normal(": %s, rev. %d\n", mpd->mpd_name, rev); 117 118 sc->mii_mpd_model = rev; /* XXX miivar.h comment vs usage? */ 119 sc->mii_inst = mii->mii_instance; 120 sc->mii_phy = ma->mii_phyno; 121 sc->mii_pdata = mii; 122 sc->mii_flags = mii->mii_flags; 123 sc->mii_anegticks = 5; 124 125 sc->mii_funcs = &rgephy_funcs; 126 127 /* Don't do isolate on this PHY. */ 128 sc->mii_flags |= MIIF_NOISOLATE; 129 130 #define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL) 131 #define PRINT(n) aprint_normal("%s%s", sep, (n)); sep = ", " 132 133 #if 0 134 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, sc->mii_inst), 135 BMCR_ISO); 136 #endif 137 #ifdef __FreeBSD__ 138 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst), 139 BMCR_LOOP|BMCR_S100); 140 #endif 141 142 rgephy_mii_model = MII_MODEL(ma->mii_id2); 143 PHY_RESET(sc); 144 145 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask; 146 sc->mii_capabilities &= ~BMSR_ANEG; 147 148 /* 149 * FreeBSD does not check EXSTAT, but instead adds gigabit 150 * media explicitly. Why? 151 */ 152 aprint_normal("%s: ", sc->mii_dev.dv_xname); 153 #ifdef __FreeBSD__ 154 mii_phy_add_media(sc); 155 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, 0, sc->mii_inst), 156 RGEPHY_BMCR_FDX); 157 PRINT(", 1000baseTX"); 158 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, IFM_FDX, sc->mii_inst), 0); 159 PRINT("1000baseTX-FDX"); 160 #else 161 if (sc->mii_capabilities & BMSR_EXTSTAT) { 162 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); 163 } 164 mii_phy_add_media(sc); 165 #endif 166 /* rtl8169S does not report auto-sense; add manually. */ 167 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), MII_NMEDIA); 168 sep =", "; 169 PRINT("auto"); 170 171 #undef ADD 172 #undef PRINT 173 174 aprint_normal("\n"); 175 } 176 177 static int 178 rgephy_service(sc, mii, cmd) 179 struct mii_softc *sc; 180 struct mii_data *mii; 181 int cmd; 182 { 183 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 184 int reg, speed, gig; 185 186 switch (cmd) { 187 case MII_POLLSTAT: 188 /* 189 * If we're not polling our PHY instance, just return. 190 */ 191 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 192 return (0); 193 break; 194 195 case MII_MEDIACHG: 196 /* 197 * If the media indicates a different PHY instance, 198 * isolate ourselves. 199 */ 200 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 201 reg = PHY_READ(sc, MII_BMCR); 202 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO); 203 return (0); 204 } 205 206 /* 207 * If the interface is not up, don't do anything. 208 */ 209 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 210 break; 211 212 PHY_RESET(sc); /* XXX hardware bug work-around */ 213 214 switch (IFM_SUBTYPE(ife->ifm_media)) { 215 case IFM_AUTO: 216 #ifdef foo 217 /* 218 * If we're already in auto mode, just return. 219 */ 220 if (PHY_READ(sc, RGEPHY_MII_BMCR) & RGEPHY_BMCR_AUTOEN) 221 return (0); 222 #endif 223 (void) rgephy_mii_phy_auto(sc); 224 break; 225 case IFM_1000_T: 226 speed = RGEPHY_S1000; 227 goto setit; 228 case IFM_100_TX: 229 speed = RGEPHY_S100; 230 goto setit; 231 case IFM_10_T: 232 speed = RGEPHY_S10; 233 setit: 234 rgephy_loop(sc); 235 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 236 speed |= RGEPHY_BMCR_FDX; 237 gig = RGEPHY_1000CTL_AFD; 238 } else { 239 gig = RGEPHY_1000CTL_AHD; 240 } 241 242 PHY_WRITE(sc, RGEPHY_MII_1000CTL, 0); 243 PHY_WRITE(sc, RGEPHY_MII_BMCR, speed); 244 PHY_WRITE(sc, RGEPHY_MII_ANAR, RGEPHY_SEL_TYPE); 245 246 if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T) 247 break; 248 249 PHY_WRITE(sc, RGEPHY_MII_1000CTL, gig); 250 PHY_WRITE(sc, RGEPHY_MII_BMCR, 251 speed|RGEPHY_BMCR_AUTOEN|RGEPHY_BMCR_STARTNEG); 252 253 /* 254 * When settning the link manually, one side must 255 * be the master and the other the slave. However 256 * ifmedia doesn't give us a good way to specify 257 * this, so we fake it by using one of the LINK 258 * flags. If LINK0 is set, we program the PHY to 259 * be a master, otherwise it's a slave. 260 */ 261 if ((mii->mii_ifp->if_flags & IFF_LINK0)) { 262 PHY_WRITE(sc, RGEPHY_MII_1000CTL, 263 gig|RGEPHY_1000CTL_MSE|RGEPHY_1000CTL_MSC); 264 } else { 265 PHY_WRITE(sc, RGEPHY_MII_1000CTL, 266 gig|RGEPHY_1000CTL_MSE); 267 } 268 break; 269 #ifdef foo 270 case IFM_NONE: 271 PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN); 272 break; 273 #endif 274 case IFM_100_T4: 275 default: 276 return (EINVAL); 277 } 278 break; 279 280 case MII_TICK: 281 /* 282 * If we're not currently selected, just return. 283 */ 284 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 285 return (0); 286 287 /* 288 * Is the interface even up? 289 */ 290 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 291 return (0); 292 293 /* 294 * Only used for autonegotiation. 295 */ 296 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) 297 break; 298 299 /* 300 * Check to see if we have link. If we do, we don't 301 * need to restart the autonegotiation process. Read 302 * the BMSR twice in case it's latched. 303 */ 304 reg = PHY_READ(sc, RTK_GMEDIASTAT); 305 if (reg & RTK_GMEDIASTAT_LINK) 306 break; 307 308 /* 309 * Only retry autonegotiation every 5 seconds. 310 */ 311 if (++sc->mii_ticks <= 5/*10*/) 312 break; 313 314 sc->mii_ticks = 0; 315 rgephy_mii_phy_auto(sc); 316 return (0); 317 } 318 319 /* Update the media status. */ 320 rgephy_status(sc); 321 322 /* 323 * Callback if something changed. Note that we need to poke 324 * the DSP on the RealTek PHYs if the media changes. 325 * 326 */ 327 if (sc->mii_media_active != mii->mii_media_active || 328 sc->mii_media_status != mii->mii_media_status || 329 cmd == MII_MEDIACHG) { 330 /* XXX only for v0/v1 phys. */ 331 if (sc->mii_mpd_model < 2) 332 rgephy_load_dspcode(sc); 333 } 334 mii_phy_update(sc, cmd); 335 return (0); 336 } 337 338 static void 339 rgephy_status(sc) 340 struct mii_softc *sc; 341 { 342 struct mii_data *mii = sc->mii_pdata; 343 int bmsr, bmcr; 344 345 mii->mii_media_status = IFM_AVALID; 346 mii->mii_media_active = IFM_ETHER; 347 348 bmsr = PHY_READ(sc, RTK_GMEDIASTAT); 349 350 if (bmsr & RTK_GMEDIASTAT_LINK) 351 mii->mii_media_status |= IFM_ACTIVE; 352 bmsr = PHY_READ(sc, RGEPHY_MII_BMSR); 353 354 bmcr = PHY_READ(sc, RGEPHY_MII_BMCR); 355 356 if (bmcr & RGEPHY_BMCR_ISO) { 357 mii->mii_media_active |= IFM_NONE; 358 mii->mii_media_status = 0; 359 return; 360 } 361 362 if (bmcr & RGEPHY_BMCR_LOOP) 363 mii->mii_media_active |= IFM_LOOP; 364 365 if (bmcr & RGEPHY_BMCR_AUTOEN) { 366 if ((bmsr & RGEPHY_BMSR_ACOMP) == 0) { 367 /* Erg, still trying, I guess... */ 368 mii->mii_media_active |= IFM_NONE; 369 return; 370 } 371 } 372 373 bmsr = PHY_READ(sc, RTK_GMEDIASTAT); 374 if (bmsr & RTK_GMEDIASTAT_10MBPS) 375 mii->mii_media_active |= IFM_10_T; 376 if (bmsr & RTK_GMEDIASTAT_100MBPS) 377 mii->mii_media_active |= IFM_100_TX; 378 if (bmsr & RTK_GMEDIASTAT_1000MBPS) 379 mii->mii_media_active |= IFM_1000_T; 380 if (bmsr & RTK_GMEDIASTAT_FDX) 381 mii->mii_media_active |= IFM_FDX; 382 383 return; 384 } 385 386 387 static int 388 rgephy_mii_phy_auto(mii) 389 struct mii_softc *mii; 390 { 391 rgephy_loop(mii); 392 PHY_RESET(mii); 393 394 PHY_WRITE(mii, RGEPHY_MII_ANAR, 395 BMSR_MEDIA_TO_ANAR(mii->mii_capabilities) | ANAR_CSMA); 396 DELAY(1000); 397 PHY_WRITE(mii, RGEPHY_MII_1000CTL, RGEPHY_1000CTL_AFD); 398 DELAY(1000); 399 PHY_WRITE(mii, RGEPHY_MII_BMCR, 400 RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG); 401 DELAY(100); 402 403 return (EJUSTRETURN); 404 } 405 406 static void 407 rgephy_loop(struct mii_softc *sc) 408 { 409 u_int32_t bmsr; 410 int i; 411 412 PHY_WRITE(sc, RGEPHY_MII_BMCR, RGEPHY_BMCR_PDOWN); 413 DELAY(1000); 414 415 for (i = 0; i < 15000; i++) { 416 bmsr = PHY_READ(sc, RGEPHY_MII_BMSR); 417 if (!(bmsr & RGEPHY_BMSR_LINK)) { 418 #if 0 419 device_printf(sc->mii_dev, "looped %d\n", i); 420 #endif 421 break; 422 } 423 DELAY(10); 424 } 425 } 426 427 #define PHY_SETBIT(x, y, z) \ 428 PHY_WRITE(x, y, (PHY_READ(x, y) | (z))) 429 #define PHY_CLRBIT(x, y, z) \ 430 PHY_WRITE(x, y, (PHY_READ(x, y) & ~(z))) 431 432 /* 433 * Initialize RealTek PHY per the datasheet. The DSP in the PHYs of 434 * existing revisions of the 8169S/8110S chips need to be tuned in 435 * order to reliably negotiate a 1000Mbps link. Later revs of the 436 * chips may not require this software tuning. 437 */ 438 static void 439 rgephy_load_dspcode(struct mii_softc *sc) 440 { 441 int val; 442 443 #if 1 444 PHY_WRITE(sc, 31, 0x0001); 445 PHY_WRITE(sc, 21, 0x1000); 446 PHY_WRITE(sc, 24, 0x65C7); 447 PHY_CLRBIT(sc, 4, 0x0800); 448 val = PHY_READ(sc, 4) & 0xFFF; 449 PHY_WRITE(sc, 4, val); 450 PHY_WRITE(sc, 3, 0x00A1); 451 PHY_WRITE(sc, 2, 0x0008); 452 PHY_WRITE(sc, 1, 0x1020); 453 PHY_WRITE(sc, 0, 0x1000); 454 PHY_SETBIT(sc, 4, 0x0800); 455 PHY_CLRBIT(sc, 4, 0x0800); 456 val = (PHY_READ(sc, 4) & 0xFFF) | 0x7000; 457 PHY_WRITE(sc, 4, val); 458 PHY_WRITE(sc, 3, 0xFF41); 459 PHY_WRITE(sc, 2, 0xDE60); 460 PHY_WRITE(sc, 1, 0x0140); 461 PHY_WRITE(sc, 0, 0x0077); 462 val = (PHY_READ(sc, 4) & 0xFFF) | 0xA000; 463 PHY_WRITE(sc, 4, val); 464 PHY_WRITE(sc, 3, 0xDF01); 465 PHY_WRITE(sc, 2, 0xDF20); 466 PHY_WRITE(sc, 1, 0xFF95); 467 PHY_WRITE(sc, 0, 0xFA00); 468 val = (PHY_READ(sc, 4) & 0xFFF) | 0xB000; 469 PHY_WRITE(sc, 4, val); 470 PHY_WRITE(sc, 3, 0xFF41); 471 PHY_WRITE(sc, 2, 0xDE20); 472 PHY_WRITE(sc, 1, 0x0140); 473 PHY_WRITE(sc, 0, 0x00BB); 474 val = (PHY_READ(sc, 4) & 0xFFF) | 0xF000; 475 PHY_WRITE(sc, 4, val); 476 PHY_WRITE(sc, 3, 0xDF01); 477 PHY_WRITE(sc, 2, 0xDF20); 478 PHY_WRITE(sc, 1, 0xFF95); 479 PHY_WRITE(sc, 0, 0xBF00); 480 PHY_SETBIT(sc, 4, 0x0800); 481 PHY_CLRBIT(sc, 4, 0x0800); 482 PHY_WRITE(sc, 31, 0x0000); 483 #else 484 (void)val; 485 PHY_WRITE(sc, 0x1f, 0x0001); 486 PHY_WRITE(sc, 0x15, 0x1000); 487 PHY_WRITE(sc, 0x18, 0x65c7); 488 PHY_WRITE(sc, 0x04, 0x0000); 489 PHY_WRITE(sc, 0x03, 0x00a1); 490 PHY_WRITE(sc, 0x02, 0x0008); 491 PHY_WRITE(sc, 0x01, 0x1020); 492 PHY_WRITE(sc, 0x00, 0x1000); 493 PHY_WRITE(sc, 0x04, 0x0800); 494 PHY_WRITE(sc, 0x04, 0x0000); 495 PHY_WRITE(sc, 0x04, 0x7000); 496 PHY_WRITE(sc, 0x03, 0xff41); 497 PHY_WRITE(sc, 0x02, 0xde60); 498 PHY_WRITE(sc, 0x01, 0x0140); 499 PHY_WRITE(sc, 0x00, 0x0077); 500 PHY_WRITE(sc, 0x04, 0x7800); 501 PHY_WRITE(sc, 0x04, 0x7000); 502 PHY_WRITE(sc, 0x04, 0xa000); 503 PHY_WRITE(sc, 0x03, 0xdf01); 504 PHY_WRITE(sc, 0x02, 0xdf20); 505 PHY_WRITE(sc, 0x01, 0xff95); 506 PHY_WRITE(sc, 0x00, 0xfa00); 507 PHY_WRITE(sc, 0x04, 0xa800); 508 PHY_WRITE(sc, 0x04, 0xa000); 509 PHY_WRITE(sc, 0x04, 0xb000); 510 PHY_WRITE(sc, 0x0e, 0xff41); 511 PHY_WRITE(sc, 0x02, 0xde20); 512 PHY_WRITE(sc, 0x01, 0x0140); 513 PHY_WRITE(sc, 0x00, 0x00bb); 514 PHY_WRITE(sc, 0x04, 0xb800); 515 PHY_WRITE(sc, 0x04, 0xb000); 516 PHY_WRITE(sc, 0x04, 0xf000); 517 PHY_WRITE(sc, 0x03, 0xdf01); 518 PHY_WRITE(sc, 0x02, 0xdf20); 519 PHY_WRITE(sc, 0x01, 0xff95); 520 PHY_WRITE(sc, 0x00, 0xbf00); 521 PHY_WRITE(sc, 0x04, 0xf800); 522 PHY_WRITE(sc, 0x04, 0xf000); 523 PHY_WRITE(sc, 0x04, 0x0000); 524 PHY_WRITE(sc, 0x1f, 0x0000); 525 PHY_WRITE(sc, 0x0b, 0x0000); 526 527 #endif 528 529 DELAY(40); 530 } 531 532 static void 533 rgephy_reset(struct mii_softc *sc) 534 { 535 mii_phy_reset(sc); 536 DELAY(1000); 537 538 if (sc->mii_mpd_model < 2) 539 rgephy_load_dspcode(sc); 540 else { 541 PHY_WRITE(sc, 0x1F, 0x0001); 542 PHY_WRITE(sc, 0x09, 0x273a); 543 PHY_WRITE(sc, 0x0e, 0x7bfb); 544 PHY_WRITE(sc, 0x1b, 0x841e); 545 546 PHY_WRITE(sc, 0x1F, 0x0002); 547 PHY_WRITE(sc, 0x01, 0x90D0); 548 PHY_WRITE(sc, 0x1F, 0x0000); 549 } 550 551 /* Reset capabilities */ 552 /* Step1: write our capability */ 553 PHY_WRITE(sc, 0x04,0x01e1); /* 10/100 capability */ 554 PHY_WRITE(sc, 0x09,0x0200); /* 1000 capability */ 555 556 #ifdef jrs_notyet 557 /* Step2: Restart NWay */ 558 PHY_WRITE(sc, 0x00, 0x1200); // NWay enable and Restart NWay 559 #endif 560 } 561
Indexes created Thu Oct 02 14:10:14 GMT 2025