rgephy.c revision 1.14
1 /* $NetBSD: rgephy.c,v 1.14 2006/11/29 13:49:24 tsutsui Exp $ */ 2 3 /* 4 * Copyright (c) 2003 5 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: rgephy.c,v 1.14 2006/11/29 13:49:24 tsutsui Exp $"); 37 38 39 /* 40 * Driver for the RealTek 8169S/8110S internal 10/100/1000 PHY. 41 */ 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/kernel.h> 46 #include <sys/device.h> 47 #include <sys/socket.h> 48 49 50 #include <net/if.h> 51 #include <net/if_media.h> 52 53 #include <dev/mii/mii.h> 54 #include <dev/mii/miivar.h> 55 #include <dev/mii/miidevs.h> 56 57 #include <dev/mii/rgephyreg.h> 58 59 #include <dev/ic/rtl81x9reg.h> 60 61 static int rgephy_match(struct device *, struct cfdata *, void *); 62 static void rgephy_attach(struct device *, struct device *, void *); 63 64 CFATTACH_DECL(rgephy, sizeof(struct mii_softc), 65 rgephy_match, rgephy_attach, mii_phy_detach, mii_phy_activate); 66 67 68 static int rgephy_service(struct mii_softc *, struct mii_data *, int); 69 static void rgephy_status(struct mii_softc *); 70 static int rgephy_mii_phy_auto(struct mii_softc *); 71 static void rgephy_reset(struct mii_softc *); 72 static void rgephy_loop(struct mii_softc *); 73 static void rgephy_load_dspcode(struct mii_softc *); 74 static int rgephy_mii_model; 75 76 static const struct mii_phy_funcs rgephy_funcs = { 77 rgephy_service, rgephy_status, rgephy_reset, 78 }; 79 80 static const struct mii_phydesc rgephys[] = { 81 { MII_OUI_xxREALTEK, MII_MODEL_xxREALTEK_RTL8169S, 82 MII_STR_xxREALTEK_RTL8169S }, 83 84 { MII_OUI_REALTEK, MII_MODEL_REALTEK_RTL8169S, 85 MII_STR_REALTEK_RTL8169S }, 86 87 { 0, 0, 88 NULL } 89 }; 90 91 static int 92 rgephy_match(struct device *parent, struct cfdata *match, 93 void *aux) 94 { 95 struct mii_attach_args *ma = aux; 96 97 if (mii_phy_match(ma, rgephys) != NULL) 98 return (10); 99 100 return (0); 101 } 102 103 static void 104 rgephy_attach(struct device *parent, struct device *self, void *aux) 105 { 106 struct mii_softc *sc = device_private(self); 107 struct mii_attach_args *ma = aux; 108 struct mii_data *mii = ma->mii_data; 109 const struct mii_phydesc *mpd; 110 int rev; 111 const char *sep = ""; 112 113 rev = MII_REV(ma->mii_id2); 114 mpd = mii_phy_match(ma, rgephys); 115 aprint_naive(": Media interface\n"); 116 aprint_normal(": %s, rev. %d\n", mpd->mpd_name, rev); 117 118 sc->mii_mpd_model = rev; /* XXX miivar.h comment vs usage? */ 119 sc->mii_inst = mii->mii_instance; 120 sc->mii_phy = ma->mii_phyno; 121 sc->mii_pdata = mii; 122 sc->mii_flags = mii->mii_flags; 123 sc->mii_anegticks = MII_ANEGTICKS; 124 125 sc->mii_funcs = &rgephy_funcs; 126 127 /* Don't do isolate on this PHY. */ 128 sc->mii_flags |= MIIF_NOISOLATE; 129 130 #define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL) 131 #define PRINT(n) aprint_normal("%s%s", sep, (n)); sep = ", " 132 133 #if 0 134 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, sc->mii_inst), 135 BMCR_ISO); 136 #endif 137 #ifdef __FreeBSD__ 138 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst), 139 BMCR_LOOP|BMCR_S100); 140 #endif 141 142 rgephy_mii_model = MII_MODEL(ma->mii_id2); 143 144 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask; 145 sc->mii_capabilities &= ~BMSR_ANEG; 146 147 /* 148 * FreeBSD does not check EXSTAT, but instead adds gigabit 149 * media explicitly. Why? 150 */ 151 aprint_normal("%s: ", sc->mii_dev.dv_xname); 152 #ifdef __FreeBSD__ 153 mii_phy_add_media(sc); 154 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, 0, sc->mii_inst), 155 RGEPHY_BMCR_FDX); 156 PRINT(", 1000baseTX"); 157 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, IFM_FDX, sc->mii_inst), 0); 158 PRINT("1000baseTX-FDX"); 159 #else 160 if (sc->mii_capabilities & BMSR_EXTSTAT) { 161 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); 162 } 163 mii_phy_add_media(sc); 164 #endif 165 /* rtl8169S does not report auto-sense; add manually. */ 166 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), MII_NMEDIA); 167 sep =", "; 168 PRINT("auto"); 169 170 #undef ADD 171 #undef PRINT 172 173 PHY_RESET(sc); 174 aprint_normal("\n"); 175 } 176 177 static int 178 rgephy_service(sc, mii, cmd) 179 struct mii_softc *sc; 180 struct mii_data *mii; 181 int cmd; 182 { 183 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 184 int reg, speed, gig, anar; 185 186 switch (cmd) { 187 case MII_POLLSTAT: 188 /* 189 * If we're not polling our PHY instance, just return. 190 */ 191 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 192 return (0); 193 break; 194 195 case MII_MEDIACHG: 196 /* 197 * If the media indicates a different PHY instance, 198 * isolate ourselves. 199 */ 200 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 201 reg = PHY_READ(sc, MII_BMCR); 202 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO); 203 return (0); 204 } 205 206 /* 207 * If the interface is not up, don't do anything. 208 */ 209 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 210 break; 211 212 PHY_RESET(sc); /* XXX hardware bug work-around */ 213 214 anar = PHY_READ(sc, RGEPHY_MII_ANAR); 215 anar &= ~(RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_TX | 216 RGEPHY_ANAR_10_FD | RGEPHY_ANAR_10); 217 218 switch (IFM_SUBTYPE(ife->ifm_media)) { 219 case IFM_AUTO: 220 #ifdef foo 221 /* 222 * If we're already in auto mode, just return. 223 */ 224 if (PHY_READ(sc, RGEPHY_MII_BMCR) & RGEPHY_BMCR_AUTOEN) 225 return (0); 226 #endif 227 (void) rgephy_mii_phy_auto(sc); 228 break; 229 case IFM_1000_T: 230 speed = RGEPHY_S1000; 231 goto setit; 232 case IFM_100_TX: 233 speed = RGEPHY_S100; 234 anar |= RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_TX; 235 goto setit; 236 case IFM_10_T: 237 speed = RGEPHY_S10; 238 anar |= RGEPHY_ANAR_10_FD | RGEPHY_ANAR_10; 239 setit: 240 rgephy_loop(sc); 241 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 242 speed |= RGEPHY_BMCR_FDX; 243 gig = RGEPHY_1000CTL_AFD; 244 anar &= ~(RGEPHY_ANAR_TX | RGEPHY_ANAR_10); 245 } else { 246 gig = RGEPHY_1000CTL_AHD; 247 anar &= 248 ~(RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_10_FD); 249 } 250 251 if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T) { 252 PHY_WRITE(sc, RGEPHY_MII_1000CTL, 0); 253 PHY_WRITE(sc, RGEPHY_MII_ANAR, anar); 254 PHY_WRITE(sc, RGEPHY_MII_BMCR, speed | 255 RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG); 256 break; 257 } 258 259 /* 260 * When settning the link manually, one side must 261 * be the master and the other the slave. However 262 * ifmedia doesn't give us a good way to specify 263 * this, so we fake it by using one of the LINK 264 * flags. If LINK0 is set, we program the PHY to 265 * be a master, otherwise it's a slave. 266 */ 267 if ((mii->mii_ifp->if_flags & IFF_LINK0)) { 268 PHY_WRITE(sc, RGEPHY_MII_1000CTL, 269 gig|RGEPHY_1000CTL_MSE|RGEPHY_1000CTL_MSC); 270 } else { 271 PHY_WRITE(sc, RGEPHY_MII_1000CTL, 272 gig|RGEPHY_1000CTL_MSE); 273 } 274 PHY_WRITE(sc, RGEPHY_MII_BMCR, speed | 275 RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG); 276 break; 277 #ifdef foo 278 case IFM_NONE: 279 PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN); 280 break; 281 #endif 282 case IFM_100_T4: 283 default: 284 return (EINVAL); 285 } 286 break; 287 288 case MII_TICK: 289 /* 290 * If we're not currently selected, just return. 291 */ 292 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 293 return (0); 294 295 /* 296 * Is the interface even up? 297 */ 298 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 299 return (0); 300 301 /* 302 * Only used for autonegotiation. 303 */ 304 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) 305 break; 306 307 /* 308 * Check to see if we have link. If we do, we don't 309 * need to restart the autonegotiation process. Read 310 * the BMSR twice in case it's latched. 311 */ 312 reg = PHY_READ(sc, RTK_GMEDIASTAT); 313 if (reg & RTK_GMEDIASTAT_LINK) 314 break; 315 316 /* 317 * Only retry autonegotiation every 5 seconds. 318 */ 319 if (++sc->mii_ticks <= MII_ANEGTICKS) 320 break; 321 322 sc->mii_ticks = 0; 323 rgephy_mii_phy_auto(sc); 324 return (0); 325 } 326 327 /* Update the media status. */ 328 rgephy_status(sc); 329 330 /* 331 * Callback if something changed. Note that we need to poke 332 * the DSP on the RealTek PHYs if the media changes. 333 * 334 */ 335 if (sc->mii_media_active != mii->mii_media_active || 336 sc->mii_media_status != mii->mii_media_status || 337 cmd == MII_MEDIACHG) { 338 /* XXX only for v0/v1 phys. */ 339 if (sc->mii_mpd_model < 2) 340 rgephy_load_dspcode(sc); 341 } 342 mii_phy_update(sc, cmd); 343 return (0); 344 } 345 346 static void 347 rgephy_status(sc) 348 struct mii_softc *sc; 349 { 350 struct mii_data *mii = sc->mii_pdata; 351 int bmsr, bmcr; 352 353 mii->mii_media_status = IFM_AVALID; 354 mii->mii_media_active = IFM_ETHER; 355 356 bmsr = PHY_READ(sc, RTK_GMEDIASTAT); 357 358 if (bmsr & RTK_GMEDIASTAT_LINK) 359 mii->mii_media_status |= IFM_ACTIVE; 360 bmsr = PHY_READ(sc, RGEPHY_MII_BMSR); 361 362 bmcr = PHY_READ(sc, RGEPHY_MII_BMCR); 363 364 if (bmcr & RGEPHY_BMCR_ISO) { 365 mii->mii_media_active |= IFM_NONE; 366 mii->mii_media_status = 0; 367 return; 368 } 369 370 if (bmcr & RGEPHY_BMCR_LOOP) 371 mii->mii_media_active |= IFM_LOOP; 372 373 if (bmcr & RGEPHY_BMCR_AUTOEN) { 374 if ((bmsr & RGEPHY_BMSR_ACOMP) == 0) { 375 /* Erg, still trying, I guess... */ 376 mii->mii_media_active |= IFM_NONE; 377 return; 378 } 379 } 380 381 bmsr = PHY_READ(sc, RTK_GMEDIASTAT); 382 if (bmsr & RTK_GMEDIASTAT_1000MBPS) 383 mii->mii_media_active |= IFM_1000_T; 384 else if (bmsr & RTK_GMEDIASTAT_100MBPS) 385 mii->mii_media_active |= IFM_100_TX; 386 else if (bmsr & RTK_GMEDIASTAT_10MBPS) 387 mii->mii_media_active |= IFM_10_T; 388 else 389 mii->mii_media_active |= IFM_NONE; 390 if (bmsr & RTK_GMEDIASTAT_FDX) 391 mii->mii_media_active |= IFM_FDX; 392 393 return; 394 } 395 396 397 static int 398 rgephy_mii_phy_auto(mii) 399 struct mii_softc *mii; 400 { 401 rgephy_loop(mii); 402 PHY_RESET(mii); 403 404 PHY_WRITE(mii, RGEPHY_MII_ANAR, 405 BMSR_MEDIA_TO_ANAR(mii->mii_capabilities) | ANAR_CSMA); 406 DELAY(1000); 407 PHY_WRITE(mii, RGEPHY_MII_1000CTL, 408 RGEPHY_1000CTL_AHD | RGEPHY_1000CTL_AFD); 409 DELAY(1000); 410 PHY_WRITE(mii, RGEPHY_MII_BMCR, 411 RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG); 412 DELAY(100); 413 414 return (EJUSTRETURN); 415 } 416 417 static void 418 rgephy_loop(struct mii_softc *sc) 419 { 420 u_int32_t bmsr; 421 int i; 422 423 PHY_WRITE(sc, RGEPHY_MII_BMCR, RGEPHY_BMCR_PDOWN); 424 DELAY(1000); 425 426 for (i = 0; i < 15000; i++) { 427 bmsr = PHY_READ(sc, RGEPHY_MII_BMSR); 428 if (!(bmsr & RGEPHY_BMSR_LINK)) { 429 #if 0 430 device_printf(sc->mii_dev, "looped %d\n", i); 431 #endif 432 break; 433 } 434 DELAY(10); 435 } 436 } 437 438 #define PHY_SETBIT(x, y, z) \ 439 PHY_WRITE(x, y, (PHY_READ(x, y) | (z))) 440 #define PHY_CLRBIT(x, y, z) \ 441 PHY_WRITE(x, y, (PHY_READ(x, y) & ~(z))) 442 443 /* 444 * Initialize RealTek PHY per the datasheet. The DSP in the PHYs of 445 * existing revisions of the 8169S/8110S chips need to be tuned in 446 * order to reliably negotiate a 1000Mbps link. This is only needed 447 * for rev 0 and rev 1 of the PHY. Later versions work without 448 * any fixups. 449 */ 450 static void 451 rgephy_load_dspcode(struct mii_softc *sc) 452 { 453 int val; 454 455 #if 1 456 PHY_WRITE(sc, 31, 0x0001); 457 PHY_WRITE(sc, 21, 0x1000); 458 PHY_WRITE(sc, 24, 0x65C7); 459 PHY_CLRBIT(sc, 4, 0x0800); 460 val = PHY_READ(sc, 4) & 0xFFF; 461 PHY_WRITE(sc, 4, val); 462 PHY_WRITE(sc, 3, 0x00A1); 463 PHY_WRITE(sc, 2, 0x0008); 464 PHY_WRITE(sc, 1, 0x1020); 465 PHY_WRITE(sc, 0, 0x1000); 466 PHY_SETBIT(sc, 4, 0x0800); 467 PHY_CLRBIT(sc, 4, 0x0800); 468 val = (PHY_READ(sc, 4) & 0xFFF) | 0x7000; 469 PHY_WRITE(sc, 4, val); 470 PHY_WRITE(sc, 3, 0xFF41); 471 PHY_WRITE(sc, 2, 0xDE60); 472 PHY_WRITE(sc, 1, 0x0140); 473 PHY_WRITE(sc, 0, 0x0077); 474 val = (PHY_READ(sc, 4) & 0xFFF) | 0xA000; 475 PHY_WRITE(sc, 4, val); 476 PHY_WRITE(sc, 3, 0xDF01); 477 PHY_WRITE(sc, 2, 0xDF20); 478 PHY_WRITE(sc, 1, 0xFF95); 479 PHY_WRITE(sc, 0, 0xFA00); 480 val = (PHY_READ(sc, 4) & 0xFFF) | 0xB000; 481 PHY_WRITE(sc, 4, val); 482 PHY_WRITE(sc, 3, 0xFF41); 483 PHY_WRITE(sc, 2, 0xDE20); 484 PHY_WRITE(sc, 1, 0x0140); 485 PHY_WRITE(sc, 0, 0x00BB); 486 val = (PHY_READ(sc, 4) & 0xFFF) | 0xF000; 487 PHY_WRITE(sc, 4, val); 488 PHY_WRITE(sc, 3, 0xDF01); 489 PHY_WRITE(sc, 2, 0xDF20); 490 PHY_WRITE(sc, 1, 0xFF95); 491 PHY_WRITE(sc, 0, 0xBF00); 492 PHY_SETBIT(sc, 4, 0x0800); 493 PHY_CLRBIT(sc, 4, 0x0800); 494 PHY_WRITE(sc, 31, 0x0000); 495 #else 496 (void)val; 497 PHY_WRITE(sc, 0x1f, 0x0001); 498 PHY_WRITE(sc, 0x15, 0x1000); 499 PHY_WRITE(sc, 0x18, 0x65c7); 500 PHY_WRITE(sc, 0x04, 0x0000); 501 PHY_WRITE(sc, 0x03, 0x00a1); 502 PHY_WRITE(sc, 0x02, 0x0008); 503 PHY_WRITE(sc, 0x01, 0x1020); 504 PHY_WRITE(sc, 0x00, 0x1000); 505 PHY_WRITE(sc, 0x04, 0x0800); 506 PHY_WRITE(sc, 0x04, 0x0000); 507 PHY_WRITE(sc, 0x04, 0x7000); 508 PHY_WRITE(sc, 0x03, 0xff41); 509 PHY_WRITE(sc, 0x02, 0xde60); 510 PHY_WRITE(sc, 0x01, 0x0140); 511 PHY_WRITE(sc, 0x00, 0x0077); 512 PHY_WRITE(sc, 0x04, 0x7800); 513 PHY_WRITE(sc, 0x04, 0x7000); 514 PHY_WRITE(sc, 0x04, 0xa000); 515 PHY_WRITE(sc, 0x03, 0xdf01); 516 PHY_WRITE(sc, 0x02, 0xdf20); 517 PHY_WRITE(sc, 0x01, 0xff95); 518 PHY_WRITE(sc, 0x00, 0xfa00); 519 PHY_WRITE(sc, 0x04, 0xa800); 520 PHY_WRITE(sc, 0x04, 0xa000); 521 PHY_WRITE(sc, 0x04, 0xb000); 522 PHY_WRITE(sc, 0x0e, 0xff41); 523 PHY_WRITE(sc, 0x02, 0xde20); 524 PHY_WRITE(sc, 0x01, 0x0140); 525 PHY_WRITE(sc, 0x00, 0x00bb); 526 PHY_WRITE(sc, 0x04, 0xb800); 527 PHY_WRITE(sc, 0x04, 0xb000); 528 PHY_WRITE(sc, 0x04, 0xf000); 529 PHY_WRITE(sc, 0x03, 0xdf01); 530 PHY_WRITE(sc, 0x02, 0xdf20); 531 PHY_WRITE(sc, 0x01, 0xff95); 532 PHY_WRITE(sc, 0x00, 0xbf00); 533 PHY_WRITE(sc, 0x04, 0xf800); 534 PHY_WRITE(sc, 0x04, 0xf000); 535 PHY_WRITE(sc, 0x04, 0x0000); 536 PHY_WRITE(sc, 0x1f, 0x0000); 537 PHY_WRITE(sc, 0x0b, 0x0000); 538 539 #endif 540 541 DELAY(40); 542 } 543 544 static void 545 rgephy_reset(struct mii_softc *sc) 546 { 547 mii_phy_reset(sc); 548 DELAY(1000); 549 550 if (sc->mii_mpd_model < 2) 551 rgephy_load_dspcode(sc); 552 else { 553 PHY_WRITE(sc, 0x1F, 0x0001); 554 PHY_WRITE(sc, 0x09, 0x273a); 555 PHY_WRITE(sc, 0x0e, 0x7bfb); 556 PHY_WRITE(sc, 0x1b, 0x841e); 557 558 PHY_WRITE(sc, 0x1F, 0x0002); 559 PHY_WRITE(sc, 0x01, 0x90D0); 560 PHY_WRITE(sc, 0x1F, 0x0000); 561 } 562 563 /* Reset capabilities */ 564 /* Step1: write our capability */ 565 /* 10/100 capability */ 566 PHY_WRITE(sc, RGEPHY_MII_ANAR, 567 RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_TX | 568 RGEPHY_ANAR_10_FD | RGEPHY_ANAR_10 | ANAR_CSMA); 569 /* 1000 capability */ 570 PHY_WRITE(sc, RGEPHY_MII_1000CTL, 571 RGEPHY_1000CTL_AFD | RGEPHY_1000CTL_AHD); 572 573 /* Step2: Restart NWay */ 574 /* NWay enable and Restart NWay */ 575 PHY_WRITE(sc, RGEPHY_MII_BMCR, 576 RGEPHY_BMCR_RESET | RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG); 577 } 578
Indexes created Thu Oct 02 07:10:07 GMT 2025