rgephy.c revision 1.15
1 /* $NetBSD: rgephy.c,v 1.15 2006/11/29 13:57:59 tsutsui Exp $ */ 2 3 /* 4 * Copyright (c) 2003 5 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: rgephy.c,v 1.15 2006/11/29 13:57:59 tsutsui Exp $"); 37 38 39 /* 40 * Driver for the RealTek 8169S/8110S internal 10/100/1000 PHY. 41 */ 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/kernel.h> 46 #include <sys/device.h> 47 #include <sys/socket.h> 48 49 50 #include <net/if.h> 51 #include <net/if_media.h> 52 53 #include <dev/mii/mii.h> 54 #include <dev/mii/miivar.h> 55 #include <dev/mii/miidevs.h> 56 57 #include <dev/mii/rgephyreg.h> 58 59 #include <dev/ic/rtl81x9reg.h> 60 61 static int rgephy_match(struct device *, struct cfdata *, void *); 62 static void rgephy_attach(struct device *, struct device *, void *); 63 64 CFATTACH_DECL(rgephy, sizeof(struct mii_softc), 65 rgephy_match, rgephy_attach, mii_phy_detach, mii_phy_activate); 66 67 68 static int rgephy_service(struct mii_softc *, struct mii_data *, int); 69 static void rgephy_status(struct mii_softc *); 70 static int rgephy_mii_phy_auto(struct mii_softc *); 71 static void rgephy_reset(struct mii_softc *); 72 static void rgephy_loop(struct mii_softc *); 73 static void rgephy_load_dspcode(struct mii_softc *); 74 75 static int rgephy_mii_model; 76 77 static const struct mii_phy_funcs rgephy_funcs = { 78 rgephy_service, rgephy_status, rgephy_reset, 79 }; 80 81 static const struct mii_phydesc rgephys[] = { 82 { MII_OUI_xxREALTEK, MII_MODEL_xxREALTEK_RTL8169S, 83 MII_STR_xxREALTEK_RTL8169S }, 84 85 { MII_OUI_REALTEK, MII_MODEL_REALTEK_RTL8169S, 86 MII_STR_REALTEK_RTL8169S }, 87 88 { 0, 0, 89 NULL } 90 }; 91 92 static int 93 rgephy_match(struct device *parent, struct cfdata *match, void *aux) 94 { 95 struct mii_attach_args *ma = aux; 96 97 if (mii_phy_match(ma, rgephys) != NULL) 98 return 10; 99 100 return 0; 101 } 102 103 static void 104 rgephy_attach(struct device *parent, struct device *self, void *aux) 105 { 106 struct mii_softc *sc = device_private(self); 107 struct mii_attach_args *ma = aux; 108 struct mii_data *mii = ma->mii_data; 109 const struct mii_phydesc *mpd; 110 int rev; 111 const char *sep = ""; 112 113 rev = MII_REV(ma->mii_id2); 114 mpd = mii_phy_match(ma, rgephys); 115 aprint_naive(": Media interface\n"); 116 aprint_normal(": %s, rev. %d\n", mpd->mpd_name, rev); 117 118 sc->mii_mpd_model = rev; /* XXX miivar.h comment vs usage? */ 119 sc->mii_inst = mii->mii_instance; 120 sc->mii_phy = ma->mii_phyno; 121 sc->mii_pdata = mii; 122 sc->mii_flags = mii->mii_flags; 123 sc->mii_anegticks = MII_ANEGTICKS; 124 125 sc->mii_funcs = &rgephy_funcs; 126 127 /* Don't do isolate on this PHY. */ 128 sc->mii_flags |= MIIF_NOISOLATE; 129 130 #define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL) 131 #define PRINT(n) aprint_normal("%s%s", sep, (n)); sep = ", " 132 133 #if 0 134 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, sc->mii_inst), 135 BMCR_ISO); 136 #endif 137 #ifdef __FreeBSD__ 138 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst), 139 BMCR_LOOP|BMCR_S100); 140 #endif 141 142 rgephy_mii_model = MII_MODEL(ma->mii_id2); 143 144 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask; 145 sc->mii_capabilities &= ~BMSR_ANEG; 146 147 /* 148 * FreeBSD does not check EXSTAT, but instead adds gigabit 149 * media explicitly. Why? 150 */ 151 aprint_normal("%s: ", sc->mii_dev.dv_xname); 152 #ifdef __FreeBSD__ 153 mii_phy_add_media(sc); 154 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, 0, sc->mii_inst), 155 RGEPHY_BMCR_FDX); 156 PRINT(", 1000baseTX"); 157 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, IFM_FDX, sc->mii_inst), 0); 158 PRINT("1000baseTX-FDX"); 159 #else 160 if (sc->mii_capabilities & BMSR_EXTSTAT) { 161 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); 162 } 163 mii_phy_add_media(sc); 164 #endif 165 /* rtl8169S does not report auto-sense; add manually. */ 166 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), MII_NMEDIA); 167 sep =", "; 168 PRINT("auto"); 169 170 #undef ADD 171 #undef PRINT 172 173 PHY_RESET(sc); 174 aprint_normal("\n"); 175 } 176 177 static int 178 rgephy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 179 { 180 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 181 int reg, speed, gig, anar; 182 183 switch (cmd) { 184 case MII_POLLSTAT: 185 /* 186 * If we're not polling our PHY instance, just return. 187 */ 188 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 189 return 0; 190 break; 191 192 case MII_MEDIACHG: 193 /* 194 * If the media indicates a different PHY instance, 195 * isolate ourselves. 196 */ 197 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 198 reg = PHY_READ(sc, MII_BMCR); 199 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO); 200 return 0; 201 } 202 203 /* 204 * If the interface is not up, don't do anything. 205 */ 206 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 207 break; 208 209 PHY_RESET(sc); /* XXX hardware bug work-around */ 210 211 anar = PHY_READ(sc, RGEPHY_MII_ANAR); 212 anar &= ~(RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_TX | 213 RGEPHY_ANAR_10_FD | RGEPHY_ANAR_10); 214 215 switch (IFM_SUBTYPE(ife->ifm_media)) { 216 case IFM_AUTO: 217 #ifdef foo 218 /* 219 * If we're already in auto mode, just return. 220 */ 221 if (PHY_READ(sc, RGEPHY_MII_BMCR) & RGEPHY_BMCR_AUTOEN) 222 return 0; 223 #endif 224 (void)rgephy_mii_phy_auto(sc); 225 break; 226 case IFM_1000_T: 227 speed = RGEPHY_S1000; 228 goto setit; 229 case IFM_100_TX: 230 speed = RGEPHY_S100; 231 anar |= RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_TX; 232 goto setit; 233 case IFM_10_T: 234 speed = RGEPHY_S10; 235 anar |= RGEPHY_ANAR_10_FD | RGEPHY_ANAR_10; 236 setit: 237 rgephy_loop(sc); 238 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 239 speed |= RGEPHY_BMCR_FDX; 240 gig = RGEPHY_1000CTL_AFD; 241 anar &= ~(RGEPHY_ANAR_TX | RGEPHY_ANAR_10); 242 } else { 243 gig = RGEPHY_1000CTL_AHD; 244 anar &= 245 ~(RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_10_FD); 246 } 247 248 if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T) { 249 PHY_WRITE(sc, RGEPHY_MII_1000CTL, 0); 250 PHY_WRITE(sc, RGEPHY_MII_ANAR, anar); 251 PHY_WRITE(sc, RGEPHY_MII_BMCR, speed | 252 RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG); 253 break; 254 } 255 256 /* 257 * When settning the link manually, one side must 258 * be the master and the other the slave. However 259 * ifmedia doesn't give us a good way to specify 260 * this, so we fake it by using one of the LINK 261 * flags. If LINK0 is set, we program the PHY to 262 * be a master, otherwise it's a slave. 263 */ 264 if ((mii->mii_ifp->if_flags & IFF_LINK0)) { 265 PHY_WRITE(sc, RGEPHY_MII_1000CTL, 266 gig|RGEPHY_1000CTL_MSE|RGEPHY_1000CTL_MSC); 267 } else { 268 PHY_WRITE(sc, RGEPHY_MII_1000CTL, 269 gig|RGEPHY_1000CTL_MSE); 270 } 271 PHY_WRITE(sc, RGEPHY_MII_BMCR, speed | 272 RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG); 273 break; 274 #ifdef foo 275 case IFM_NONE: 276 PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN); 277 break; 278 #endif 279 case IFM_100_T4: 280 default: 281 return EINVAL; 282 } 283 break; 284 285 case MII_TICK: 286 /* 287 * If we're not currently selected, just return. 288 */ 289 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 290 return 0; 291 292 /* 293 * Is the interface even up? 294 */ 295 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 296 return 0; 297 298 /* 299 * Only used for autonegotiation. 300 */ 301 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) 302 break; 303 304 /* 305 * Check to see if we have link. If we do, we don't 306 * need to restart the autonegotiation process. Read 307 * the BMSR twice in case it's latched. 308 */ 309 reg = PHY_READ(sc, RTK_GMEDIASTAT); 310 if ((reg & RTK_GMEDIASTAT_LINK) != 0) 311 break; 312 313 /* 314 * Only retry autonegotiation every 5 seconds. 315 */ 316 if (++sc->mii_ticks <= MII_ANEGTICKS) 317 break; 318 319 sc->mii_ticks = 0; 320 rgephy_mii_phy_auto(sc); 321 return 0; 322 } 323 324 /* Update the media status. */ 325 rgephy_status(sc); 326 327 /* 328 * Callback if something changed. Note that we need to poke 329 * the DSP on the RealTek PHYs if the media changes. 330 * 331 */ 332 if (sc->mii_media_active != mii->mii_media_active || 333 sc->mii_media_status != mii->mii_media_status || 334 cmd == MII_MEDIACHG) { 335 /* XXX only for v0/v1 phys. */ 336 if (sc->mii_mpd_model < 2) 337 rgephy_load_dspcode(sc); 338 } 339 mii_phy_update(sc, cmd); 340 return 0; 341 } 342 343 static void 344 rgephy_status(struct mii_softc *sc) 345 { 346 struct mii_data *mii = sc->mii_pdata; 347 int bmsr, bmcr; 348 349 mii->mii_media_status = IFM_AVALID; 350 mii->mii_media_active = IFM_ETHER; 351 352 bmsr = PHY_READ(sc, RTK_GMEDIASTAT); 353 354 if ((bmsr & RTK_GMEDIASTAT_LINK) != 0) 355 mii->mii_media_status |= IFM_ACTIVE; 356 bmsr = PHY_READ(sc, RGEPHY_MII_BMSR); 357 358 bmcr = PHY_READ(sc, RGEPHY_MII_BMCR); 359 360 if ((bmcr & RGEPHY_BMCR_ISO) != 0) { 361 mii->mii_media_active |= IFM_NONE; 362 mii->mii_media_status = 0; 363 return; 364 } 365 366 if ((bmcr & RGEPHY_BMCR_LOOP) != 0) 367 mii->mii_media_active |= IFM_LOOP; 368 369 if ((bmcr & RGEPHY_BMCR_AUTOEN) != 0) { 370 if ((bmsr & RGEPHY_BMSR_ACOMP) == 0) { 371 /* Erg, still trying, I guess... */ 372 mii->mii_media_active |= IFM_NONE; 373 return; 374 } 375 } 376 377 bmsr = PHY_READ(sc, RTK_GMEDIASTAT); 378 if ((bmsr & RTK_GMEDIASTAT_1000MBPS) != 0) 379 mii->mii_media_active |= IFM_1000_T; 380 else if ((bmsr & RTK_GMEDIASTAT_100MBPS) != 0) 381 mii->mii_media_active |= IFM_100_TX; 382 else if ((bmsr & RTK_GMEDIASTAT_10MBPS) != 0) 383 mii->mii_media_active |= IFM_10_T; 384 else 385 mii->mii_media_active |= IFM_NONE; 386 if ((bmsr & RTK_GMEDIASTAT_FDX) != 0) 387 mii->mii_media_active |= IFM_FDX; 388 389 return; 390 } 391 392 393 static int 394 rgephy_mii_phy_auto(struct mii_softc *mii) 395 { 396 397 rgephy_loop(mii); 398 PHY_RESET(mii); 399 400 PHY_WRITE(mii, RGEPHY_MII_ANAR, 401 BMSR_MEDIA_TO_ANAR(mii->mii_capabilities) | ANAR_CSMA); 402 DELAY(1000); 403 PHY_WRITE(mii, RGEPHY_MII_1000CTL, 404 RGEPHY_1000CTL_AHD | RGEPHY_1000CTL_AFD); 405 DELAY(1000); 406 PHY_WRITE(mii, RGEPHY_MII_BMCR, 407 RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG); 408 DELAY(100); 409 410 return EJUSTRETURN; 411 } 412 413 static void 414 rgephy_loop(struct mii_softc *sc) 415 { 416 uint32_t bmsr; 417 int i; 418 419 PHY_WRITE(sc, RGEPHY_MII_BMCR, RGEPHY_BMCR_PDOWN); 420 DELAY(1000); 421 422 for (i = 0; i < 15000; i++) { 423 bmsr = PHY_READ(sc, RGEPHY_MII_BMSR); 424 if ((bmsr & RGEPHY_BMSR_LINK) == 0) { 425 #if 0 426 device_printf(sc->mii_dev, "looped %d\n", i); 427 #endif 428 break; 429 } 430 DELAY(10); 431 } 432 } 433 434 #define PHY_SETBIT(x, y, z) \ 435 PHY_WRITE(x, y, (PHY_READ(x, y) | (z))) 436 #define PHY_CLRBIT(x, y, z) \ 437 PHY_WRITE(x, y, (PHY_READ(x, y) & ~(z))) 438 439 /* 440 * Initialize RealTek PHY per the datasheet. The DSP in the PHYs of 441 * existing revisions of the 8169S/8110S chips need to be tuned in 442 * order to reliably negotiate a 1000Mbps link. This is only needed 443 * for rev 0 and rev 1 of the PHY. Later versions work without 444 * any fixups. 445 */ 446 static void 447 rgephy_load_dspcode(struct mii_softc *sc) 448 { 449 int val; 450 451 #if 1 452 PHY_WRITE(sc, 31, 0x0001); 453 PHY_WRITE(sc, 21, 0x1000); 454 PHY_WRITE(sc, 24, 0x65C7); 455 PHY_CLRBIT(sc, 4, 0x0800); 456 val = PHY_READ(sc, 4) & 0xFFF; 457 PHY_WRITE(sc, 4, val); 458 PHY_WRITE(sc, 3, 0x00A1); 459 PHY_WRITE(sc, 2, 0x0008); 460 PHY_WRITE(sc, 1, 0x1020); 461 PHY_WRITE(sc, 0, 0x1000); 462 PHY_SETBIT(sc, 4, 0x0800); 463 PHY_CLRBIT(sc, 4, 0x0800); 464 val = (PHY_READ(sc, 4) & 0xFFF) | 0x7000; 465 PHY_WRITE(sc, 4, val); 466 PHY_WRITE(sc, 3, 0xFF41); 467 PHY_WRITE(sc, 2, 0xDE60); 468 PHY_WRITE(sc, 1, 0x0140); 469 PHY_WRITE(sc, 0, 0x0077); 470 val = (PHY_READ(sc, 4) & 0xFFF) | 0xA000; 471 PHY_WRITE(sc, 4, val); 472 PHY_WRITE(sc, 3, 0xDF01); 473 PHY_WRITE(sc, 2, 0xDF20); 474 PHY_WRITE(sc, 1, 0xFF95); 475 PHY_WRITE(sc, 0, 0xFA00); 476 val = (PHY_READ(sc, 4) & 0xFFF) | 0xB000; 477 PHY_WRITE(sc, 4, val); 478 PHY_WRITE(sc, 3, 0xFF41); 479 PHY_WRITE(sc, 2, 0xDE20); 480 PHY_WRITE(sc, 1, 0x0140); 481 PHY_WRITE(sc, 0, 0x00BB); 482 val = (PHY_READ(sc, 4) & 0xFFF) | 0xF000; 483 PHY_WRITE(sc, 4, val); 484 PHY_WRITE(sc, 3, 0xDF01); 485 PHY_WRITE(sc, 2, 0xDF20); 486 PHY_WRITE(sc, 1, 0xFF95); 487 PHY_WRITE(sc, 0, 0xBF00); 488 PHY_SETBIT(sc, 4, 0x0800); 489 PHY_CLRBIT(sc, 4, 0x0800); 490 PHY_WRITE(sc, 31, 0x0000); 491 #else 492 (void)val; 493 PHY_WRITE(sc, 0x1f, 0x0001); 494 PHY_WRITE(sc, 0x15, 0x1000); 495 PHY_WRITE(sc, 0x18, 0x65c7); 496 PHY_WRITE(sc, 0x04, 0x0000); 497 PHY_WRITE(sc, 0x03, 0x00a1); 498 PHY_WRITE(sc, 0x02, 0x0008); 499 PHY_WRITE(sc, 0x01, 0x1020); 500 PHY_WRITE(sc, 0x00, 0x1000); 501 PHY_WRITE(sc, 0x04, 0x0800); 502 PHY_WRITE(sc, 0x04, 0x0000); 503 PHY_WRITE(sc, 0x04, 0x7000); 504 PHY_WRITE(sc, 0x03, 0xff41); 505 PHY_WRITE(sc, 0x02, 0xde60); 506 PHY_WRITE(sc, 0x01, 0x0140); 507 PHY_WRITE(sc, 0x00, 0x0077); 508 PHY_WRITE(sc, 0x04, 0x7800); 509 PHY_WRITE(sc, 0x04, 0x7000); 510 PHY_WRITE(sc, 0x04, 0xa000); 511 PHY_WRITE(sc, 0x03, 0xdf01); 512 PHY_WRITE(sc, 0x02, 0xdf20); 513 PHY_WRITE(sc, 0x01, 0xff95); 514 PHY_WRITE(sc, 0x00, 0xfa00); 515 PHY_WRITE(sc, 0x04, 0xa800); 516 PHY_WRITE(sc, 0x04, 0xa000); 517 PHY_WRITE(sc, 0x04, 0xb000); 518 PHY_WRITE(sc, 0x0e, 0xff41); 519 PHY_WRITE(sc, 0x02, 0xde20); 520 PHY_WRITE(sc, 0x01, 0x0140); 521 PHY_WRITE(sc, 0x00, 0x00bb); 522 PHY_WRITE(sc, 0x04, 0xb800); 523 PHY_WRITE(sc, 0x04, 0xb000); 524 PHY_WRITE(sc, 0x04, 0xf000); 525 PHY_WRITE(sc, 0x03, 0xdf01); 526 PHY_WRITE(sc, 0x02, 0xdf20); 527 PHY_WRITE(sc, 0x01, 0xff95); 528 PHY_WRITE(sc, 0x00, 0xbf00); 529 PHY_WRITE(sc, 0x04, 0xf800); 530 PHY_WRITE(sc, 0x04, 0xf000); 531 PHY_WRITE(sc, 0x04, 0x0000); 532 PHY_WRITE(sc, 0x1f, 0x0000); 533 PHY_WRITE(sc, 0x0b, 0x0000); 534 535 #endif 536 537 DELAY(40); 538 } 539 540 static void 541 rgephy_reset(struct mii_softc *sc) 542 { 543 544 mii_phy_reset(sc); 545 DELAY(1000); 546 547 if (sc->mii_mpd_model < 2) 548 rgephy_load_dspcode(sc); 549 else { 550 PHY_WRITE(sc, 0x1F, 0x0001); 551 PHY_WRITE(sc, 0x09, 0x273a); 552 PHY_WRITE(sc, 0x0e, 0x7bfb); 553 PHY_WRITE(sc, 0x1b, 0x841e); 554 555 PHY_WRITE(sc, 0x1F, 0x0002); 556 PHY_WRITE(sc, 0x01, 0x90D0); 557 PHY_WRITE(sc, 0x1F, 0x0000); 558 } 559 560 /* Reset capabilities */ 561 /* Step1: write our capability */ 562 /* 10/100 capability */ 563 PHY_WRITE(sc, RGEPHY_MII_ANAR, 564 RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_TX | 565 RGEPHY_ANAR_10_FD | RGEPHY_ANAR_10 | ANAR_CSMA); 566 /* 1000 capability */ 567 PHY_WRITE(sc, RGEPHY_MII_1000CTL, 568 RGEPHY_1000CTL_AFD | RGEPHY_1000CTL_AHD); 569 570 /* Step2: Restart NWay */ 571 /* NWay enable and Restart NWay */ 572 PHY_WRITE(sc, RGEPHY_MII_BMCR, 573 RGEPHY_BMCR_RESET | RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG); 574 } 575
Indexes created Thu Oct 02 14:10:14 GMT 2025