rgephy.c revision 1.16
1 /* $NetBSD: rgephy.c,v 1.16 2006/12/03 03:16:48 tsutsui Exp $ */ 2 3 /* 4 * Copyright (c) 2003 5 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: rgephy.c,v 1.16 2006/12/03 03:16:48 tsutsui Exp $"); 37 38 39 /* 40 * Driver for the RealTek 8169S/8110S internal 10/100/1000 PHY. 41 */ 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/kernel.h> 46 #include <sys/device.h> 47 #include <sys/socket.h> 48 49 50 #include <net/if.h> 51 #include <net/if_media.h> 52 53 #include <dev/mii/mii.h> 54 #include <dev/mii/miivar.h> 55 #include <dev/mii/miidevs.h> 56 57 #include <dev/mii/rgephyreg.h> 58 59 #include <dev/ic/rtl81x9reg.h> 60 61 static int rgephy_match(struct device *, struct cfdata *, void *); 62 static void rgephy_attach(struct device *, struct device *, void *); 63 64 CFATTACH_DECL(rgephy, sizeof(struct mii_softc), 65 rgephy_match, rgephy_attach, mii_phy_detach, mii_phy_activate); 66 67 68 static int rgephy_service(struct mii_softc *, struct mii_data *, int); 69 static void rgephy_status(struct mii_softc *); 70 static int rgephy_mii_phy_auto(struct mii_softc *); 71 static void rgephy_reset(struct mii_softc *); 72 static void rgephy_loop(struct mii_softc *); 73 static void rgephy_load_dspcode(struct mii_softc *); 74 75 static const struct mii_phy_funcs rgephy_funcs = { 76 rgephy_service, rgephy_status, rgephy_reset, 77 }; 78 79 static const struct mii_phydesc rgephys[] = { 80 { MII_OUI_xxREALTEK, MII_MODEL_xxREALTEK_RTL8169S, 81 MII_STR_xxREALTEK_RTL8169S }, 82 83 { MII_OUI_REALTEK, MII_MODEL_REALTEK_RTL8169S, 84 MII_STR_REALTEK_RTL8169S }, 85 86 { 0, 0, 87 NULL } 88 }; 89 90 static int 91 rgephy_match(struct device *parent, struct cfdata *match, void *aux) 92 { 93 struct mii_attach_args *ma = aux; 94 95 if (mii_phy_match(ma, rgephys) != NULL) 96 return 10; 97 98 return 0; 99 } 100 101 static void 102 rgephy_attach(struct device *parent, struct device *self, void *aux) 103 { 104 struct mii_softc *sc = device_private(self); 105 struct mii_attach_args *ma = aux; 106 struct mii_data *mii = ma->mii_data; 107 const struct mii_phydesc *mpd; 108 int rev; 109 const char *sep = ""; 110 111 rev = MII_REV(ma->mii_id2); 112 mpd = mii_phy_match(ma, rgephys); 113 aprint_naive(": Media interface\n"); 114 aprint_normal(": %s, rev. %d\n", mpd->mpd_name, rev); 115 116 sc->mii_mpd_model = rev; /* XXX miivar.h comment vs usage? */ 117 sc->mii_inst = mii->mii_instance; 118 sc->mii_phy = ma->mii_phyno; 119 sc->mii_pdata = mii; 120 sc->mii_flags = mii->mii_flags; 121 sc->mii_anegticks = MII_ANEGTICKS; 122 123 sc->mii_funcs = &rgephy_funcs; 124 125 #define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL) 126 #define PRINT(n) aprint_normal("%s%s", sep, (n)); sep = ", " 127 128 #ifdef __FreeBSD__ 129 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst), 130 BMCR_LOOP|BMCR_S100); 131 #endif 132 133 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask; 134 sc->mii_capabilities &= ~BMSR_ANEG; 135 136 /* 137 * FreeBSD does not check EXSTAT, but instead adds gigabit 138 * media explicitly. Why? 139 */ 140 aprint_normal("%s: ", sc->mii_dev.dv_xname); 141 if (sc->mii_capabilities & BMSR_EXTSTAT) { 142 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); 143 } 144 mii_phy_add_media(sc); 145 146 /* rtl8169S does not report auto-sense; add manually. */ 147 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), MII_NMEDIA); 148 sep =", "; 149 PRINT("auto"); 150 151 #undef ADD 152 #undef PRINT 153 154 PHY_RESET(sc); 155 aprint_normal("\n"); 156 } 157 158 static int 159 rgephy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 160 { 161 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 162 int reg, speed, gig, anar; 163 164 switch (cmd) { 165 case MII_POLLSTAT: 166 /* 167 * If we're not polling our PHY instance, just return. 168 */ 169 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 170 return 0; 171 break; 172 173 case MII_MEDIACHG: 174 /* 175 * If the media indicates a different PHY instance, 176 * isolate ourselves. 177 */ 178 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 179 reg = PHY_READ(sc, MII_BMCR); 180 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO); 181 return 0; 182 } 183 184 /* 185 * If the interface is not up, don't do anything. 186 */ 187 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 188 break; 189 190 PHY_RESET(sc); /* XXX hardware bug work-around */ 191 192 anar = PHY_READ(sc, RGEPHY_MII_ANAR); 193 anar &= ~(RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_TX | 194 RGEPHY_ANAR_10_FD | RGEPHY_ANAR_10); 195 196 switch (IFM_SUBTYPE(ife->ifm_media)) { 197 case IFM_AUTO: 198 #ifdef foo 199 /* 200 * If we're already in auto mode, just return. 201 */ 202 if (PHY_READ(sc, RGEPHY_MII_BMCR) & RGEPHY_BMCR_AUTOEN) 203 return 0; 204 #endif 205 (void)rgephy_mii_phy_auto(sc); 206 break; 207 case IFM_1000_T: 208 speed = RGEPHY_S1000; 209 goto setit; 210 case IFM_100_TX: 211 speed = RGEPHY_S100; 212 anar |= RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_TX; 213 goto setit; 214 case IFM_10_T: 215 speed = RGEPHY_S10; 216 anar |= RGEPHY_ANAR_10_FD | RGEPHY_ANAR_10; 217 setit: 218 rgephy_loop(sc); 219 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 220 speed |= RGEPHY_BMCR_FDX; 221 gig = RGEPHY_1000CTL_AFD; 222 anar &= ~(RGEPHY_ANAR_TX | RGEPHY_ANAR_10); 223 } else { 224 gig = RGEPHY_1000CTL_AHD; 225 anar &= 226 ~(RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_10_FD); 227 } 228 229 if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T) { 230 PHY_WRITE(sc, RGEPHY_MII_1000CTL, 0); 231 PHY_WRITE(sc, RGEPHY_MII_ANAR, anar); 232 PHY_WRITE(sc, RGEPHY_MII_BMCR, speed | 233 RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG); 234 break; 235 } 236 237 /* 238 * When setting the link manually, one side must 239 * be the master and the other the slave. However 240 * ifmedia doesn't give us a good way to specify 241 * this, so we fake it by using one of the LINK 242 * flags. If LINK0 is set, we program the PHY to 243 * be a master, otherwise it's a slave. 244 */ 245 if ((mii->mii_ifp->if_flags & IFF_LINK0)) { 246 PHY_WRITE(sc, RGEPHY_MII_1000CTL, 247 gig|RGEPHY_1000CTL_MSE|RGEPHY_1000CTL_MSC); 248 } else { 249 PHY_WRITE(sc, RGEPHY_MII_1000CTL, 250 gig|RGEPHY_1000CTL_MSE); 251 } 252 PHY_WRITE(sc, RGEPHY_MII_BMCR, speed | 253 RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG); 254 break; 255 case IFM_NONE: 256 PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN); 257 break; 258 case IFM_100_T4: 259 default: 260 return EINVAL; 261 } 262 break; 263 264 case MII_TICK: 265 /* 266 * If we're not currently selected, just return. 267 */ 268 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 269 return 0; 270 271 /* 272 * Is the interface even up? 273 */ 274 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 275 return 0; 276 277 /* 278 * Only used for autonegotiation. 279 */ 280 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) 281 break; 282 283 /* 284 * Check to see if we have link. If we do, we don't 285 * need to restart the autonegotiation process. Read 286 * the BMSR twice in case it's latched. 287 */ 288 reg = PHY_READ(sc, RTK_GMEDIASTAT); 289 if ((reg & RTK_GMEDIASTAT_LINK) != 0) 290 break; 291 292 /* 293 * Only retry autonegotiation every 5 seconds. 294 */ 295 if (++sc->mii_ticks <= MII_ANEGTICKS) 296 break; 297 298 sc->mii_ticks = 0; 299 rgephy_mii_phy_auto(sc); 300 return 0; 301 } 302 303 /* Update the media status. */ 304 rgephy_status(sc); 305 306 /* 307 * Callback if something changed. Note that we need to poke 308 * the DSP on the RealTek PHYs if the media changes. 309 * 310 */ 311 if (sc->mii_media_active != mii->mii_media_active || 312 sc->mii_media_status != mii->mii_media_status || 313 cmd == MII_MEDIACHG) { 314 /* XXX only for v0/v1 phys. */ 315 if (sc->mii_mpd_model < 2) 316 rgephy_load_dspcode(sc); 317 } 318 mii_phy_update(sc, cmd); 319 return 0; 320 } 321 322 static void 323 rgephy_status(struct mii_softc *sc) 324 { 325 struct mii_data *mii = sc->mii_pdata; 326 int bmsr, bmcr; 327 328 mii->mii_media_status = IFM_AVALID; 329 mii->mii_media_active = IFM_ETHER; 330 331 if ((PHY_READ(sc, RTK_GMEDIASTAT) & RTK_GMEDIASTAT_LINK) != 0) 332 mii->mii_media_status |= IFM_ACTIVE; 333 334 bmsr = PHY_READ(sc, RGEPHY_MII_BMSR); 335 bmcr = PHY_READ(sc, RGEPHY_MII_BMCR); 336 337 if ((bmcr & RGEPHY_BMCR_ISO) != 0) { 338 mii->mii_media_active |= IFM_NONE; 339 mii->mii_media_status = 0; 340 return; 341 } 342 343 if ((bmcr & RGEPHY_BMCR_LOOP) != 0) 344 mii->mii_media_active |= IFM_LOOP; 345 346 if ((bmcr & RGEPHY_BMCR_AUTOEN) != 0) { 347 if ((bmsr & RGEPHY_BMSR_ACOMP) == 0) { 348 /* Erg, still trying, I guess... */ 349 mii->mii_media_active |= IFM_NONE; 350 return; 351 } 352 } 353 354 bmsr = PHY_READ(sc, RTK_GMEDIASTAT); 355 if ((bmsr & RTK_GMEDIASTAT_1000MBPS) != 0) 356 mii->mii_media_active |= IFM_1000_T; 357 else if ((bmsr & RTK_GMEDIASTAT_100MBPS) != 0) 358 mii->mii_media_active |= IFM_100_TX; 359 else if ((bmsr & RTK_GMEDIASTAT_10MBPS) != 0) 360 mii->mii_media_active |= IFM_10_T; 361 else 362 mii->mii_media_active |= IFM_NONE; 363 if ((bmsr & RTK_GMEDIASTAT_FDX) != 0) 364 mii->mii_media_active |= IFM_FDX; 365 } 366 367 368 static int 369 rgephy_mii_phy_auto(struct mii_softc *mii) 370 { 371 372 rgephy_loop(mii); 373 PHY_RESET(mii); 374 375 PHY_WRITE(mii, RGEPHY_MII_ANAR, 376 BMSR_MEDIA_TO_ANAR(mii->mii_capabilities) | ANAR_CSMA); 377 DELAY(1000); 378 PHY_WRITE(mii, RGEPHY_MII_1000CTL, 379 RGEPHY_1000CTL_AHD | RGEPHY_1000CTL_AFD); 380 DELAY(1000); 381 PHY_WRITE(mii, RGEPHY_MII_BMCR, 382 RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG); 383 DELAY(100); 384 385 return EJUSTRETURN; 386 } 387 388 static void 389 rgephy_loop(struct mii_softc *sc) 390 { 391 uint32_t bmsr; 392 int i; 393 394 PHY_WRITE(sc, RGEPHY_MII_BMCR, RGEPHY_BMCR_PDOWN); 395 DELAY(1000); 396 397 for (i = 0; i < 15000; i++) { 398 bmsr = PHY_READ(sc, RGEPHY_MII_BMSR); 399 if ((bmsr & RGEPHY_BMSR_LINK) == 0) { 400 #if 0 401 device_printf(sc->mii_dev, "looped %d\n", i); 402 #endif 403 break; 404 } 405 DELAY(10); 406 } 407 } 408 409 #define PHY_SETBIT(x, y, z) \ 410 PHY_WRITE(x, y, (PHY_READ(x, y) | (z))) 411 #define PHY_CLRBIT(x, y, z) \ 412 PHY_WRITE(x, y, (PHY_READ(x, y) & ~(z))) 413 414 /* 415 * Initialize RealTek PHY per the datasheet. The DSP in the PHYs of 416 * existing revisions of the 8169S/8110S chips need to be tuned in 417 * order to reliably negotiate a 1000Mbps link. This is only needed 418 * for rev 0 and rev 1 of the PHY. Later versions work without 419 * any fixups. 420 */ 421 static void 422 rgephy_load_dspcode(struct mii_softc *sc) 423 { 424 int val; 425 426 #if 1 427 PHY_WRITE(sc, 31, 0x0001); 428 PHY_WRITE(sc, 21, 0x1000); 429 PHY_WRITE(sc, 24, 0x65C7); 430 PHY_CLRBIT(sc, 4, 0x0800); 431 val = PHY_READ(sc, 4) & 0xFFF; 432 PHY_WRITE(sc, 4, val); 433 PHY_WRITE(sc, 3, 0x00A1); 434 PHY_WRITE(sc, 2, 0x0008); 435 PHY_WRITE(sc, 1, 0x1020); 436 PHY_WRITE(sc, 0, 0x1000); 437 PHY_SETBIT(sc, 4, 0x0800); 438 PHY_CLRBIT(sc, 4, 0x0800); 439 val = (PHY_READ(sc, 4) & 0xFFF) | 0x7000; 440 PHY_WRITE(sc, 4, val); 441 PHY_WRITE(sc, 3, 0xFF41); 442 PHY_WRITE(sc, 2, 0xDE60); 443 PHY_WRITE(sc, 1, 0x0140); 444 PHY_WRITE(sc, 0, 0x0077); 445 val = (PHY_READ(sc, 4) & 0xFFF) | 0xA000; 446 PHY_WRITE(sc, 4, val); 447 PHY_WRITE(sc, 3, 0xDF01); 448 PHY_WRITE(sc, 2, 0xDF20); 449 PHY_WRITE(sc, 1, 0xFF95); 450 PHY_WRITE(sc, 0, 0xFA00); 451 val = (PHY_READ(sc, 4) & 0xFFF) | 0xB000; 452 PHY_WRITE(sc, 4, val); 453 PHY_WRITE(sc, 3, 0xFF41); 454 PHY_WRITE(sc, 2, 0xDE20); 455 PHY_WRITE(sc, 1, 0x0140); 456 PHY_WRITE(sc, 0, 0x00BB); 457 val = (PHY_READ(sc, 4) & 0xFFF) | 0xF000; 458 PHY_WRITE(sc, 4, val); 459 PHY_WRITE(sc, 3, 0xDF01); 460 PHY_WRITE(sc, 2, 0xDF20); 461 PHY_WRITE(sc, 1, 0xFF95); 462 PHY_WRITE(sc, 0, 0xBF00); 463 PHY_SETBIT(sc, 4, 0x0800); 464 PHY_CLRBIT(sc, 4, 0x0800); 465 PHY_WRITE(sc, 31, 0x0000); 466 #else 467 (void)val; 468 PHY_WRITE(sc, 0x1f, 0x0001); 469 PHY_WRITE(sc, 0x15, 0x1000); 470 PHY_WRITE(sc, 0x18, 0x65c7); 471 PHY_WRITE(sc, 0x04, 0x0000); 472 PHY_WRITE(sc, 0x03, 0x00a1); 473 PHY_WRITE(sc, 0x02, 0x0008); 474 PHY_WRITE(sc, 0x01, 0x1020); 475 PHY_WRITE(sc, 0x00, 0x1000); 476 PHY_WRITE(sc, 0x04, 0x0800); 477 PHY_WRITE(sc, 0x04, 0x0000); 478 PHY_WRITE(sc, 0x04, 0x7000); 479 PHY_WRITE(sc, 0x03, 0xff41); 480 PHY_WRITE(sc, 0x02, 0xde60); 481 PHY_WRITE(sc, 0x01, 0x0140); 482 PHY_WRITE(sc, 0x00, 0x0077); 483 PHY_WRITE(sc, 0x04, 0x7800); 484 PHY_WRITE(sc, 0x04, 0x7000); 485 PHY_WRITE(sc, 0x04, 0xa000); 486 PHY_WRITE(sc, 0x03, 0xdf01); 487 PHY_WRITE(sc, 0x02, 0xdf20); 488 PHY_WRITE(sc, 0x01, 0xff95); 489 PHY_WRITE(sc, 0x00, 0xfa00); 490 PHY_WRITE(sc, 0x04, 0xa800); 491 PHY_WRITE(sc, 0x04, 0xa000); 492 PHY_WRITE(sc, 0x04, 0xb000); 493 PHY_WRITE(sc, 0x0e, 0xff41); 494 PHY_WRITE(sc, 0x02, 0xde20); 495 PHY_WRITE(sc, 0x01, 0x0140); 496 PHY_WRITE(sc, 0x00, 0x00bb); 497 PHY_WRITE(sc, 0x04, 0xb800); 498 PHY_WRITE(sc, 0x04, 0xb000); 499 PHY_WRITE(sc, 0x04, 0xf000); 500 PHY_WRITE(sc, 0x03, 0xdf01); 501 PHY_WRITE(sc, 0x02, 0xdf20); 502 PHY_WRITE(sc, 0x01, 0xff95); 503 PHY_WRITE(sc, 0x00, 0xbf00); 504 PHY_WRITE(sc, 0x04, 0xf800); 505 PHY_WRITE(sc, 0x04, 0xf000); 506 PHY_WRITE(sc, 0x04, 0x0000); 507 PHY_WRITE(sc, 0x1f, 0x0000); 508 PHY_WRITE(sc, 0x0b, 0x0000); 509 510 #endif 511 512 DELAY(40); 513 } 514 515 static void 516 rgephy_reset(struct mii_softc *sc) 517 { 518 519 mii_phy_reset(sc); 520 DELAY(1000); 521 522 if (sc->mii_mpd_model < 2) 523 rgephy_load_dspcode(sc); 524 else { 525 PHY_WRITE(sc, 0x1F, 0x0001); 526 PHY_WRITE(sc, 0x09, 0x273a); 527 PHY_WRITE(sc, 0x0e, 0x7bfb); 528 PHY_WRITE(sc, 0x1b, 0x841e); 529 530 PHY_WRITE(sc, 0x1F, 0x0002); 531 PHY_WRITE(sc, 0x01, 0x90D0); 532 PHY_WRITE(sc, 0x1F, 0x0000); 533 } 534 535 /* Reset capabilities */ 536 /* Step1: write our capability */ 537 /* 10/100 capability */ 538 PHY_WRITE(sc, RGEPHY_MII_ANAR, 539 RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_TX | 540 RGEPHY_ANAR_10_FD | RGEPHY_ANAR_10 | ANAR_CSMA); 541 /* 1000 capability */ 542 PHY_WRITE(sc, RGEPHY_MII_1000CTL, 543 RGEPHY_1000CTL_AFD | RGEPHY_1000CTL_AHD); 544 545 /* Step2: Restart NWay */ 546 /* NWay enable and Restart NWay */ 547 PHY_WRITE(sc, RGEPHY_MII_BMCR, 548 RGEPHY_BMCR_RESET | RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG); 549 } 550
Indexes created Thu Oct 02 14:10:14 GMT 2025