rgephy.c revision 1.17
1 /* $NetBSD: rgephy.c,v 1.17 2007/12/09 20:28:04 jmcneill Exp $ */ 2 3 /* 4 * Copyright (c) 2003 5 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: rgephy.c,v 1.17 2007/12/09 20:28:04 jmcneill Exp $"); 37 38 39 /* 40 * Driver for the RealTek 8169S/8110S internal 10/100/1000 PHY. 41 */ 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/kernel.h> 46 #include <sys/device.h> 47 #include <sys/socket.h> 48 49 50 #include <net/if.h> 51 #include <net/if_media.h> 52 53 #include <dev/mii/mii.h> 54 #include <dev/mii/miivar.h> 55 #include <dev/mii/miidevs.h> 56 57 #include <dev/mii/rgephyreg.h> 58 59 #include <dev/ic/rtl81x9reg.h> 60 61 static int rgephy_match(struct device *, struct cfdata *, void *); 62 static void rgephy_attach(struct device *, struct device *, void *); 63 64 CFATTACH_DECL(rgephy, sizeof(struct mii_softc), 65 rgephy_match, rgephy_attach, mii_phy_detach, mii_phy_activate); 66 67 68 static int rgephy_service(struct mii_softc *, struct mii_data *, int); 69 static void rgephy_status(struct mii_softc *); 70 static int rgephy_mii_phy_auto(struct mii_softc *); 71 static void rgephy_reset(struct mii_softc *); 72 static void rgephy_loop(struct mii_softc *); 73 static void rgephy_load_dspcode(struct mii_softc *); 74 75 static const struct mii_phy_funcs rgephy_funcs = { 76 rgephy_service, rgephy_status, rgephy_reset, 77 }; 78 79 static const struct mii_phydesc rgephys[] = { 80 { MII_OUI_xxREALTEK, MII_MODEL_xxREALTEK_RTL8169S, 81 MII_STR_xxREALTEK_RTL8169S }, 82 83 { MII_OUI_REALTEK, MII_MODEL_REALTEK_RTL8169S, 84 MII_STR_REALTEK_RTL8169S }, 85 86 { 0, 0, 87 NULL } 88 }; 89 90 static int 91 rgephy_match(struct device *parent, struct cfdata *match, void *aux) 92 { 93 struct mii_attach_args *ma = aux; 94 95 if (mii_phy_match(ma, rgephys) != NULL) 96 return 10; 97 98 return 0; 99 } 100 101 static void 102 rgephy_attach(struct device *parent, struct device *self, void *aux) 103 { 104 struct mii_softc *sc = device_private(self); 105 struct mii_attach_args *ma = aux; 106 struct mii_data *mii = ma->mii_data; 107 const struct mii_phydesc *mpd; 108 int rev; 109 const char *sep = ""; 110 111 rev = MII_REV(ma->mii_id2); 112 mpd = mii_phy_match(ma, rgephys); 113 aprint_naive(": Media interface\n"); 114 aprint_normal(": %s, rev. %d\n", mpd->mpd_name, rev); 115 116 sc->mii_mpd_model = rev; /* XXX miivar.h comment vs usage? */ 117 sc->mii_inst = mii->mii_instance; 118 sc->mii_phy = ma->mii_phyno; 119 sc->mii_pdata = mii; 120 sc->mii_flags = mii->mii_flags; 121 sc->mii_anegticks = MII_ANEGTICKS; 122 123 sc->mii_funcs = &rgephy_funcs; 124 125 #define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL) 126 #define PRINT(n) aprint_normal("%s%s", sep, (n)); sep = ", " 127 128 #ifdef __FreeBSD__ 129 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst), 130 BMCR_LOOP|BMCR_S100); 131 #endif 132 133 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask; 134 sc->mii_capabilities &= ~BMSR_ANEG; 135 136 /* 137 * FreeBSD does not check EXSTAT, but instead adds gigabit 138 * media explicitly. Why? 139 */ 140 aprint_normal("%s: ", sc->mii_dev.dv_xname); 141 if (sc->mii_capabilities & BMSR_EXTSTAT) { 142 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); 143 } 144 mii_phy_add_media(sc); 145 146 /* rtl8169S does not report auto-sense; add manually. */ 147 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), MII_NMEDIA); 148 sep =", "; 149 PRINT("auto"); 150 151 #undef ADD 152 #undef PRINT 153 154 PHY_RESET(sc); 155 aprint_normal("\n"); 156 157 if (!pmf_device_register(self, NULL, mii_phy_resume)) 158 aprint_error_dev(self, "couldn't establish power handler\n"); 159 } 160 161 static int 162 rgephy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 163 { 164 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 165 int reg, speed, gig, anar; 166 167 switch (cmd) { 168 case MII_POLLSTAT: 169 /* 170 * If we're not polling our PHY instance, just return. 171 */ 172 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 173 return 0; 174 break; 175 176 case MII_MEDIACHG: 177 /* 178 * If the media indicates a different PHY instance, 179 * isolate ourselves. 180 */ 181 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 182 reg = PHY_READ(sc, MII_BMCR); 183 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO); 184 return 0; 185 } 186 187 /* 188 * If the interface is not up, don't do anything. 189 */ 190 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 191 break; 192 193 PHY_RESET(sc); /* XXX hardware bug work-around */ 194 195 anar = PHY_READ(sc, RGEPHY_MII_ANAR); 196 anar &= ~(RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_TX | 197 RGEPHY_ANAR_10_FD | RGEPHY_ANAR_10); 198 199 switch (IFM_SUBTYPE(ife->ifm_media)) { 200 case IFM_AUTO: 201 #ifdef foo 202 /* 203 * If we're already in auto mode, just return. 204 */ 205 if (PHY_READ(sc, RGEPHY_MII_BMCR) & RGEPHY_BMCR_AUTOEN) 206 return 0; 207 #endif 208 (void)rgephy_mii_phy_auto(sc); 209 break; 210 case IFM_1000_T: 211 speed = RGEPHY_S1000; 212 goto setit; 213 case IFM_100_TX: 214 speed = RGEPHY_S100; 215 anar |= RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_TX; 216 goto setit; 217 case IFM_10_T: 218 speed = RGEPHY_S10; 219 anar |= RGEPHY_ANAR_10_FD | RGEPHY_ANAR_10; 220 setit: 221 rgephy_loop(sc); 222 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 223 speed |= RGEPHY_BMCR_FDX; 224 gig = RGEPHY_1000CTL_AFD; 225 anar &= ~(RGEPHY_ANAR_TX | RGEPHY_ANAR_10); 226 } else { 227 gig = RGEPHY_1000CTL_AHD; 228 anar &= 229 ~(RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_10_FD); 230 } 231 232 if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T) { 233 PHY_WRITE(sc, RGEPHY_MII_1000CTL, 0); 234 PHY_WRITE(sc, RGEPHY_MII_ANAR, anar); 235 PHY_WRITE(sc, RGEPHY_MII_BMCR, speed | 236 RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG); 237 break; 238 } 239 240 /* 241 * When setting the link manually, one side must 242 * be the master and the other the slave. However 243 * ifmedia doesn't give us a good way to specify 244 * this, so we fake it by using one of the LINK 245 * flags. If LINK0 is set, we program the PHY to 246 * be a master, otherwise it's a slave. 247 */ 248 if ((mii->mii_ifp->if_flags & IFF_LINK0)) { 249 PHY_WRITE(sc, RGEPHY_MII_1000CTL, 250 gig|RGEPHY_1000CTL_MSE|RGEPHY_1000CTL_MSC); 251 } else { 252 PHY_WRITE(sc, RGEPHY_MII_1000CTL, 253 gig|RGEPHY_1000CTL_MSE); 254 } 255 PHY_WRITE(sc, RGEPHY_MII_BMCR, speed | 256 RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG); 257 break; 258 case IFM_NONE: 259 PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN); 260 break; 261 case IFM_100_T4: 262 default: 263 return EINVAL; 264 } 265 break; 266 267 case MII_TICK: 268 /* 269 * If we're not currently selected, just return. 270 */ 271 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 272 return 0; 273 274 /* 275 * Is the interface even up? 276 */ 277 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 278 return 0; 279 280 /* 281 * Only used for autonegotiation. 282 */ 283 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) 284 break; 285 286 /* 287 * Check to see if we have link. If we do, we don't 288 * need to restart the autonegotiation process. Read 289 * the BMSR twice in case it's latched. 290 */ 291 reg = PHY_READ(sc, RTK_GMEDIASTAT); 292 if ((reg & RTK_GMEDIASTAT_LINK) != 0) 293 break; 294 295 /* 296 * Only retry autonegotiation every 5 seconds. 297 */ 298 if (++sc->mii_ticks <= MII_ANEGTICKS) 299 break; 300 301 sc->mii_ticks = 0; 302 rgephy_mii_phy_auto(sc); 303 return 0; 304 } 305 306 /* Update the media status. */ 307 rgephy_status(sc); 308 309 /* 310 * Callback if something changed. Note that we need to poke 311 * the DSP on the RealTek PHYs if the media changes. 312 * 313 */ 314 if (sc->mii_media_active != mii->mii_media_active || 315 sc->mii_media_status != mii->mii_media_status || 316 cmd == MII_MEDIACHG) { 317 /* XXX only for v0/v1 phys. */ 318 if (sc->mii_mpd_model < 2) 319 rgephy_load_dspcode(sc); 320 } 321 mii_phy_update(sc, cmd); 322 return 0; 323 } 324 325 static void 326 rgephy_status(struct mii_softc *sc) 327 { 328 struct mii_data *mii = sc->mii_pdata; 329 int bmsr, bmcr; 330 331 mii->mii_media_status = IFM_AVALID; 332 mii->mii_media_active = IFM_ETHER; 333 334 if ((PHY_READ(sc, RTK_GMEDIASTAT) & RTK_GMEDIASTAT_LINK) != 0) 335 mii->mii_media_status |= IFM_ACTIVE; 336 337 bmsr = PHY_READ(sc, RGEPHY_MII_BMSR); 338 bmcr = PHY_READ(sc, RGEPHY_MII_BMCR); 339 340 if ((bmcr & RGEPHY_BMCR_ISO) != 0) { 341 mii->mii_media_active |= IFM_NONE; 342 mii->mii_media_status = 0; 343 return; 344 } 345 346 if ((bmcr & RGEPHY_BMCR_LOOP) != 0) 347 mii->mii_media_active |= IFM_LOOP; 348 349 if ((bmcr & RGEPHY_BMCR_AUTOEN) != 0) { 350 if ((bmsr & RGEPHY_BMSR_ACOMP) == 0) { 351 /* Erg, still trying, I guess... */ 352 mii->mii_media_active |= IFM_NONE; 353 return; 354 } 355 } 356 357 bmsr = PHY_READ(sc, RTK_GMEDIASTAT); 358 if ((bmsr & RTK_GMEDIASTAT_1000MBPS) != 0) 359 mii->mii_media_active |= IFM_1000_T; 360 else if ((bmsr & RTK_GMEDIASTAT_100MBPS) != 0) 361 mii->mii_media_active |= IFM_100_TX; 362 else if ((bmsr & RTK_GMEDIASTAT_10MBPS) != 0) 363 mii->mii_media_active |= IFM_10_T; 364 else 365 mii->mii_media_active |= IFM_NONE; 366 if ((bmsr & RTK_GMEDIASTAT_FDX) != 0) 367 mii->mii_media_active |= IFM_FDX; 368 } 369 370 371 static int 372 rgephy_mii_phy_auto(struct mii_softc *mii) 373 { 374 375 rgephy_loop(mii); 376 PHY_RESET(mii); 377 378 PHY_WRITE(mii, RGEPHY_MII_ANAR, 379 BMSR_MEDIA_TO_ANAR(mii->mii_capabilities) | ANAR_CSMA); 380 DELAY(1000); 381 PHY_WRITE(mii, RGEPHY_MII_1000CTL, 382 RGEPHY_1000CTL_AHD | RGEPHY_1000CTL_AFD); 383 DELAY(1000); 384 PHY_WRITE(mii, RGEPHY_MII_BMCR, 385 RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG); 386 DELAY(100); 387 388 return EJUSTRETURN; 389 } 390 391 static void 392 rgephy_loop(struct mii_softc *sc) 393 { 394 uint32_t bmsr; 395 int i; 396 397 PHY_WRITE(sc, RGEPHY_MII_BMCR, RGEPHY_BMCR_PDOWN); 398 DELAY(1000); 399 400 for (i = 0; i < 15000; i++) { 401 bmsr = PHY_READ(sc, RGEPHY_MII_BMSR); 402 if ((bmsr & RGEPHY_BMSR_LINK) == 0) { 403 #if 0 404 device_printf(sc->mii_dev, "looped %d\n", i); 405 #endif 406 break; 407 } 408 DELAY(10); 409 } 410 } 411 412 #define PHY_SETBIT(x, y, z) \ 413 PHY_WRITE(x, y, (PHY_READ(x, y) | (z))) 414 #define PHY_CLRBIT(x, y, z) \ 415 PHY_WRITE(x, y, (PHY_READ(x, y) & ~(z))) 416 417 /* 418 * Initialize RealTek PHY per the datasheet. The DSP in the PHYs of 419 * existing revisions of the 8169S/8110S chips need to be tuned in 420 * order to reliably negotiate a 1000Mbps link. This is only needed 421 * for rev 0 and rev 1 of the PHY. Later versions work without 422 * any fixups. 423 */ 424 static void 425 rgephy_load_dspcode(struct mii_softc *sc) 426 { 427 int val; 428 429 #if 1 430 PHY_WRITE(sc, 31, 0x0001); 431 PHY_WRITE(sc, 21, 0x1000); 432 PHY_WRITE(sc, 24, 0x65C7); 433 PHY_CLRBIT(sc, 4, 0x0800); 434 val = PHY_READ(sc, 4) & 0xFFF; 435 PHY_WRITE(sc, 4, val); 436 PHY_WRITE(sc, 3, 0x00A1); 437 PHY_WRITE(sc, 2, 0x0008); 438 PHY_WRITE(sc, 1, 0x1020); 439 PHY_WRITE(sc, 0, 0x1000); 440 PHY_SETBIT(sc, 4, 0x0800); 441 PHY_CLRBIT(sc, 4, 0x0800); 442 val = (PHY_READ(sc, 4) & 0xFFF) | 0x7000; 443 PHY_WRITE(sc, 4, val); 444 PHY_WRITE(sc, 3, 0xFF41); 445 PHY_WRITE(sc, 2, 0xDE60); 446 PHY_WRITE(sc, 1, 0x0140); 447 PHY_WRITE(sc, 0, 0x0077); 448 val = (PHY_READ(sc, 4) & 0xFFF) | 0xA000; 449 PHY_WRITE(sc, 4, val); 450 PHY_WRITE(sc, 3, 0xDF01); 451 PHY_WRITE(sc, 2, 0xDF20); 452 PHY_WRITE(sc, 1, 0xFF95); 453 PHY_WRITE(sc, 0, 0xFA00); 454 val = (PHY_READ(sc, 4) & 0xFFF) | 0xB000; 455 PHY_WRITE(sc, 4, val); 456 PHY_WRITE(sc, 3, 0xFF41); 457 PHY_WRITE(sc, 2, 0xDE20); 458 PHY_WRITE(sc, 1, 0x0140); 459 PHY_WRITE(sc, 0, 0x00BB); 460 val = (PHY_READ(sc, 4) & 0xFFF) | 0xF000; 461 PHY_WRITE(sc, 4, val); 462 PHY_WRITE(sc, 3, 0xDF01); 463 PHY_WRITE(sc, 2, 0xDF20); 464 PHY_WRITE(sc, 1, 0xFF95); 465 PHY_WRITE(sc, 0, 0xBF00); 466 PHY_SETBIT(sc, 4, 0x0800); 467 PHY_CLRBIT(sc, 4, 0x0800); 468 PHY_WRITE(sc, 31, 0x0000); 469 #else 470 (void)val; 471 PHY_WRITE(sc, 0x1f, 0x0001); 472 PHY_WRITE(sc, 0x15, 0x1000); 473 PHY_WRITE(sc, 0x18, 0x65c7); 474 PHY_WRITE(sc, 0x04, 0x0000); 475 PHY_WRITE(sc, 0x03, 0x00a1); 476 PHY_WRITE(sc, 0x02, 0x0008); 477 PHY_WRITE(sc, 0x01, 0x1020); 478 PHY_WRITE(sc, 0x00, 0x1000); 479 PHY_WRITE(sc, 0x04, 0x0800); 480 PHY_WRITE(sc, 0x04, 0x0000); 481 PHY_WRITE(sc, 0x04, 0x7000); 482 PHY_WRITE(sc, 0x03, 0xff41); 483 PHY_WRITE(sc, 0x02, 0xde60); 484 PHY_WRITE(sc, 0x01, 0x0140); 485 PHY_WRITE(sc, 0x00, 0x0077); 486 PHY_WRITE(sc, 0x04, 0x7800); 487 PHY_WRITE(sc, 0x04, 0x7000); 488 PHY_WRITE(sc, 0x04, 0xa000); 489 PHY_WRITE(sc, 0x03, 0xdf01); 490 PHY_WRITE(sc, 0x02, 0xdf20); 491 PHY_WRITE(sc, 0x01, 0xff95); 492 PHY_WRITE(sc, 0x00, 0xfa00); 493 PHY_WRITE(sc, 0x04, 0xa800); 494 PHY_WRITE(sc, 0x04, 0xa000); 495 PHY_WRITE(sc, 0x04, 0xb000); 496 PHY_WRITE(sc, 0x0e, 0xff41); 497 PHY_WRITE(sc, 0x02, 0xde20); 498 PHY_WRITE(sc, 0x01, 0x0140); 499 PHY_WRITE(sc, 0x00, 0x00bb); 500 PHY_WRITE(sc, 0x04, 0xb800); 501 PHY_WRITE(sc, 0x04, 0xb000); 502 PHY_WRITE(sc, 0x04, 0xf000); 503 PHY_WRITE(sc, 0x03, 0xdf01); 504 PHY_WRITE(sc, 0x02, 0xdf20); 505 PHY_WRITE(sc, 0x01, 0xff95); 506 PHY_WRITE(sc, 0x00, 0xbf00); 507 PHY_WRITE(sc, 0x04, 0xf800); 508 PHY_WRITE(sc, 0x04, 0xf000); 509 PHY_WRITE(sc, 0x04, 0x0000); 510 PHY_WRITE(sc, 0x1f, 0x0000); 511 PHY_WRITE(sc, 0x0b, 0x0000); 512 513 #endif 514 515 DELAY(40); 516 } 517 518 static void 519 rgephy_reset(struct mii_softc *sc) 520 { 521 522 mii_phy_reset(sc); 523 DELAY(1000); 524 525 if (sc->mii_mpd_model < 2) 526 rgephy_load_dspcode(sc); 527 else { 528 PHY_WRITE(sc, 0x1F, 0x0001); 529 PHY_WRITE(sc, 0x09, 0x273a); 530 PHY_WRITE(sc, 0x0e, 0x7bfb); 531 PHY_WRITE(sc, 0x1b, 0x841e); 532 533 PHY_WRITE(sc, 0x1F, 0x0002); 534 PHY_WRITE(sc, 0x01, 0x90D0); 535 PHY_WRITE(sc, 0x1F, 0x0000); 536 } 537 538 /* Reset capabilities */ 539 /* Step1: write our capability */ 540 /* 10/100 capability */ 541 PHY_WRITE(sc, RGEPHY_MII_ANAR, 542 RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_TX | 543 RGEPHY_ANAR_10_FD | RGEPHY_ANAR_10 | ANAR_CSMA); 544 /* 1000 capability */ 545 PHY_WRITE(sc, RGEPHY_MII_1000CTL, 546 RGEPHY_1000CTL_AFD | RGEPHY_1000CTL_AHD); 547 548 /* Step2: Restart NWay */ 549 /* NWay enable and Restart NWay */ 550 PHY_WRITE(sc, RGEPHY_MII_BMCR, 551 RGEPHY_BMCR_RESET | RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG); 552 } 553
Indexes created Thu Oct 02 14:10:14 GMT 2025