rgephy.c revision 1.19
1 /* $NetBSD: rgephy.c,v 1.19 2008/04/05 07:52:08 tsutsui Exp $ */ 2 3 /* 4 * Copyright (c) 2003 5 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: rgephy.c,v 1.19 2008/04/05 07:52:08 tsutsui Exp $"); 37 38 39 /* 40 * Driver for the RealTek 8169S/8110S internal 10/100/1000 PHY. 41 */ 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/kernel.h> 46 #include <sys/device.h> 47 #include <sys/socket.h> 48 49 50 #include <net/if.h> 51 #include <net/if_media.h> 52 53 #include <dev/mii/mii.h> 54 #include <dev/mii/miivar.h> 55 #include <dev/mii/miidevs.h> 56 57 #include <dev/mii/rgephyreg.h> 58 59 #include <dev/ic/rtl81x9reg.h> 60 61 static int rgephy_match(struct device *, struct cfdata *, void *); 62 static void rgephy_attach(struct device *, struct device *, void *); 63 64 struct rgephy_softc { 65 struct mii_softc mii_sc; 66 int mii_revision; 67 }; 68 69 CFATTACH_DECL(rgephy, sizeof(struct rgephy_softc), 70 rgephy_match, rgephy_attach, mii_phy_detach, mii_phy_activate); 71 72 73 static int rgephy_service(struct mii_softc *, struct mii_data *, int); 74 static void rgephy_status(struct mii_softc *); 75 static int rgephy_mii_phy_auto(struct mii_softc *); 76 static void rgephy_reset(struct mii_softc *); 77 static void rgephy_loop(struct mii_softc *); 78 static void rgephy_load_dspcode(struct mii_softc *); 79 80 static const struct mii_phy_funcs rgephy_funcs = { 81 rgephy_service, rgephy_status, rgephy_reset, 82 }; 83 84 static const struct mii_phydesc rgephys[] = { 85 { MII_OUI_xxREALTEK, MII_MODEL_xxREALTEK_RTL8169S, 86 MII_STR_xxREALTEK_RTL8169S }, 87 88 { MII_OUI_REALTEK, MII_MODEL_REALTEK_RTL8169S, 89 MII_STR_REALTEK_RTL8169S }, 90 91 { 0, 0, 92 NULL } 93 }; 94 95 static int 96 rgephy_match(struct device *parent, struct cfdata *match, void *aux) 97 { 98 struct mii_attach_args *ma = aux; 99 100 if (mii_phy_match(ma, rgephys) != NULL) 101 return 10; 102 103 return 0; 104 } 105 106 static void 107 rgephy_attach(struct device *parent, struct device *self, void *aux) 108 { 109 struct rgephy_softc *rsc = device_private(self); 110 struct mii_softc *sc = &rsc->mii_sc; 111 struct mii_attach_args *ma = aux; 112 struct mii_data *mii = ma->mii_data; 113 const struct mii_phydesc *mpd; 114 int rev; 115 const char *sep = ""; 116 117 rsc = device_private(self); 118 sc = &rsc->mii_sc; 119 ma = aux; 120 mii = ma->mii_data; 121 122 rev = MII_REV(ma->mii_id2); 123 mpd = mii_phy_match(ma, rgephys); 124 aprint_naive(": Media interface\n"); 125 aprint_normal(": %s, rev. %d\n", mpd->mpd_name, rev); 126 127 rsc->mii_revision = rev; 128 129 sc->mii_inst = mii->mii_instance; 130 sc->mii_phy = ma->mii_phyno; 131 sc->mii_pdata = mii; 132 sc->mii_flags = mii->mii_flags; 133 sc->mii_anegticks = MII_ANEGTICKS; 134 135 sc->mii_funcs = &rgephy_funcs; 136 137 #define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL) 138 #define PRINT(n) aprint_normal("%s%s", sep, (n)); sep = ", " 139 140 #ifdef __FreeBSD__ 141 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst), 142 BMCR_LOOP|BMCR_S100); 143 #endif 144 145 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask; 146 sc->mii_capabilities &= ~BMSR_ANEG; 147 148 /* 149 * FreeBSD does not check EXSTAT, but instead adds gigabit 150 * media explicitly. Why? 151 */ 152 aprint_normal("%s: ", sc->mii_dev.dv_xname); 153 if (sc->mii_capabilities & BMSR_EXTSTAT) { 154 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); 155 } 156 mii_phy_add_media(sc); 157 158 /* rtl8169S does not report auto-sense; add manually. */ 159 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), MII_NMEDIA); 160 sep =", "; 161 PRINT("auto"); 162 163 #undef ADD 164 #undef PRINT 165 166 PHY_RESET(sc); 167 aprint_normal("\n"); 168 169 if (!pmf_device_register(self, NULL, mii_phy_resume)) 170 aprint_error_dev(self, "couldn't establish power handler\n"); 171 } 172 173 static int 174 rgephy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 175 { 176 struct rgephy_softc *rsc; 177 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 178 int reg, speed, gig, anar; 179 180 rsc = (struct rgephy_softc *)sc; 181 182 switch (cmd) { 183 case MII_POLLSTAT: 184 /* 185 * If we're not polling our PHY instance, just return. 186 */ 187 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 188 return 0; 189 break; 190 191 case MII_MEDIACHG: 192 /* 193 * If the media indicates a different PHY instance, 194 * isolate ourselves. 195 */ 196 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 197 reg = PHY_READ(sc, MII_BMCR); 198 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO); 199 return 0; 200 } 201 202 /* 203 * If the interface is not up, don't do anything. 204 */ 205 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 206 break; 207 208 PHY_RESET(sc); /* XXX hardware bug work-around */ 209 210 anar = PHY_READ(sc, RGEPHY_MII_ANAR); 211 anar &= ~(RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_TX | 212 RGEPHY_ANAR_10_FD | RGEPHY_ANAR_10); 213 214 switch (IFM_SUBTYPE(ife->ifm_media)) { 215 case IFM_AUTO: 216 #ifdef foo 217 /* 218 * If we're already in auto mode, just return. 219 */ 220 if (PHY_READ(sc, RGEPHY_MII_BMCR) & RGEPHY_BMCR_AUTOEN) 221 return 0; 222 #endif 223 (void)rgephy_mii_phy_auto(sc); 224 break; 225 case IFM_1000_T: 226 speed = RGEPHY_S1000; 227 goto setit; 228 case IFM_100_TX: 229 speed = RGEPHY_S100; 230 anar |= RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_TX; 231 goto setit; 232 case IFM_10_T: 233 speed = RGEPHY_S10; 234 anar |= RGEPHY_ANAR_10_FD | RGEPHY_ANAR_10; 235 setit: 236 rgephy_loop(sc); 237 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 238 speed |= RGEPHY_BMCR_FDX; 239 gig = RGEPHY_1000CTL_AFD; 240 anar &= ~(RGEPHY_ANAR_TX | RGEPHY_ANAR_10); 241 } else { 242 gig = RGEPHY_1000CTL_AHD; 243 anar &= 244 ~(RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_10_FD); 245 } 246 247 if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T) { 248 PHY_WRITE(sc, RGEPHY_MII_1000CTL, 0); 249 PHY_WRITE(sc, RGEPHY_MII_ANAR, anar); 250 PHY_WRITE(sc, RGEPHY_MII_BMCR, speed | 251 RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG); 252 break; 253 } 254 255 /* 256 * When setting the link manually, one side must 257 * be the master and the other the slave. However 258 * ifmedia doesn't give us a good way to specify 259 * this, so we fake it by using one of the LINK 260 * flags. If LINK0 is set, we program the PHY to 261 * be a master, otherwise it's a slave. 262 */ 263 if ((mii->mii_ifp->if_flags & IFF_LINK0)) { 264 PHY_WRITE(sc, RGEPHY_MII_1000CTL, 265 gig|RGEPHY_1000CTL_MSE|RGEPHY_1000CTL_MSC); 266 } else { 267 PHY_WRITE(sc, RGEPHY_MII_1000CTL, 268 gig|RGEPHY_1000CTL_MSE); 269 } 270 PHY_WRITE(sc, RGEPHY_MII_BMCR, speed | 271 RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG); 272 break; 273 case IFM_NONE: 274 PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN); 275 break; 276 case IFM_100_T4: 277 default: 278 return EINVAL; 279 } 280 break; 281 282 case MII_TICK: 283 /* 284 * If we're not currently selected, just return. 285 */ 286 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 287 return 0; 288 289 /* 290 * Is the interface even up? 291 */ 292 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 293 return 0; 294 295 /* 296 * Only used for autonegotiation. 297 */ 298 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) 299 break; 300 301 /* 302 * Check to see if we have link. If we do, we don't 303 * need to restart the autonegotiation process. Read 304 * the BMSR twice in case it's latched. 305 */ 306 if (rsc->mii_revision >= 2) { 307 /* RTL8211B(L) */ 308 reg = PHY_READ(sc, RGEPHY_MII_SSR); 309 if (reg & RGEPHY_SSR_LINK) { 310 sc->mii_ticks = 0; 311 break; 312 } 313 } else { 314 reg = PHY_READ(sc, RTK_GMEDIASTAT); 315 if ((reg & RTK_GMEDIASTAT_LINK) != 0) { 316 sc->mii_ticks = 0; 317 break; 318 } 319 } 320 321 /* 322 * Only retry autonegotiation every 5 seconds. 323 */ 324 if (++sc->mii_ticks <= MII_ANEGTICKS) 325 break; 326 327 sc->mii_ticks = 0; 328 rgephy_mii_phy_auto(sc); 329 return 0; 330 } 331 332 /* Update the media status. */ 333 rgephy_status(sc); 334 335 /* 336 * Callback if something changed. Note that we need to poke 337 * the DSP on the RealTek PHYs if the media changes. 338 * 339 */ 340 if (sc->mii_media_active != mii->mii_media_active || 341 sc->mii_media_status != mii->mii_media_status || 342 cmd == MII_MEDIACHG) { 343 /* XXX only for v0/v1 phys. */ 344 if (rsc->mii_revision < 2) 345 rgephy_load_dspcode(sc); 346 } 347 mii_phy_update(sc, cmd); 348 return 0; 349 } 350 351 static void 352 rgephy_status(struct mii_softc *sc) 353 { 354 struct rgephy_softc *rsc; 355 struct mii_data *mii = sc->mii_pdata; 356 int gstat, bmsr, bmcr; 357 uint16_t ssr; 358 359 mii->mii_media_status = IFM_AVALID; 360 mii->mii_media_active = IFM_ETHER; 361 362 rsc = (struct rgephy_softc *)sc; 363 if (rsc->mii_revision >= 2) { 364 ssr = PHY_READ(sc, RGEPHY_MII_SSR); 365 if (ssr & RGEPHY_SSR_LINK) 366 mii->mii_media_status |= IFM_ACTIVE; 367 } else { 368 gstat = PHY_READ(sc, RTK_GMEDIASTAT); 369 if ((gstat & RTK_GMEDIASTAT_LINK) != 0) 370 mii->mii_media_status |= IFM_ACTIVE; 371 } 372 373 bmsr = PHY_READ(sc, RGEPHY_MII_BMSR); 374 bmsr = PHY_READ(sc, RGEPHY_MII_BMSR); 375 bmcr = PHY_READ(sc, RGEPHY_MII_BMCR); 376 377 if ((bmcr & RGEPHY_BMCR_ISO) != 0) { 378 mii->mii_media_active |= IFM_NONE; 379 mii->mii_media_status = 0; 380 return; 381 } 382 383 if ((bmcr & RGEPHY_BMCR_LOOP) != 0) 384 mii->mii_media_active |= IFM_LOOP; 385 386 if ((bmcr & RGEPHY_BMCR_AUTOEN) != 0) { 387 if ((bmsr & RGEPHY_BMSR_ACOMP) == 0) { 388 /* Erg, still trying, I guess... */ 389 mii->mii_media_active |= IFM_NONE; 390 return; 391 } 392 } 393 394 if (rsc->mii_revision >= 2) { 395 ssr = PHY_READ(sc, RGEPHY_MII_SSR); 396 switch (ssr & RGEPHY_SSR_SPD_MASK) { 397 case RGEPHY_SSR_S1000: 398 mii->mii_media_active |= IFM_1000_T; 399 break; 400 case RGEPHY_SSR_S100: 401 mii->mii_media_active |= IFM_100_TX; 402 break; 403 case RGEPHY_SSR_S10: 404 mii->mii_media_active |= IFM_10_T; 405 break; 406 default: 407 mii->mii_media_active |= IFM_NONE; 408 break; 409 } 410 if (ssr & RGEPHY_SSR_FDX) 411 mii->mii_media_active |= IFM_FDX; 412 else 413 mii->mii_media_active |= IFM_HDX; 414 } else { 415 gstat = PHY_READ(sc, RTK_GMEDIASTAT); 416 if ((gstat & RTK_GMEDIASTAT_1000MBPS) != 0) 417 mii->mii_media_active |= IFM_1000_T; 418 else if ((gstat & RTK_GMEDIASTAT_100MBPS) != 0) 419 mii->mii_media_active |= IFM_100_TX; 420 else if ((gstat & RTK_GMEDIASTAT_10MBPS) != 0) 421 mii->mii_media_active |= IFM_10_T; 422 else 423 mii->mii_media_active |= IFM_NONE; 424 if ((gstat & RTK_GMEDIASTAT_FDX) != 0) 425 mii->mii_media_active |= IFM_FDX; 426 } 427 } 428 429 430 static int 431 rgephy_mii_phy_auto(struct mii_softc *mii) 432 { 433 434 rgephy_loop(mii); 435 PHY_RESET(mii); 436 437 PHY_WRITE(mii, RGEPHY_MII_ANAR, 438 BMSR_MEDIA_TO_ANAR(mii->mii_capabilities) | ANAR_CSMA); 439 DELAY(1000); 440 PHY_WRITE(mii, RGEPHY_MII_1000CTL, 441 RGEPHY_1000CTL_AHD | RGEPHY_1000CTL_AFD); 442 DELAY(1000); 443 PHY_WRITE(mii, RGEPHY_MII_BMCR, 444 RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG); 445 DELAY(100); 446 447 return EJUSTRETURN; 448 } 449 450 static void 451 rgephy_loop(struct mii_softc *sc) 452 { 453 struct rgephy_softc *rsc; 454 uint32_t bmsr; 455 int i; 456 457 rsc = (struct rgephy_softc *)sc; 458 if (rsc->mii_revision < 2) { 459 PHY_WRITE(sc, RGEPHY_MII_BMCR, RGEPHY_BMCR_PDOWN); 460 DELAY(1000); 461 } 462 463 for (i = 0; i < 15000; i++) { 464 bmsr = PHY_READ(sc, RGEPHY_MII_BMSR); 465 if ((bmsr & RGEPHY_BMSR_LINK) == 0) { 466 #if 0 467 device_printf(sc->mii_dev, "looped %d\n", i); 468 #endif 469 break; 470 } 471 DELAY(10); 472 } 473 } 474 475 #define PHY_SETBIT(x, y, z) \ 476 PHY_WRITE(x, y, (PHY_READ(x, y) | (z))) 477 #define PHY_CLRBIT(x, y, z) \ 478 PHY_WRITE(x, y, (PHY_READ(x, y) & ~(z))) 479 480 /* 481 * Initialize RealTek PHY per the datasheet. The DSP in the PHYs of 482 * existing revisions of the 8169S/8110S chips need to be tuned in 483 * order to reliably negotiate a 1000Mbps link. This is only needed 484 * for rev 0 and rev 1 of the PHY. Later versions work without 485 * any fixups. 486 */ 487 static void 488 rgephy_load_dspcode(struct mii_softc *sc) 489 { 490 int val; 491 492 #if 1 493 PHY_WRITE(sc, 31, 0x0001); 494 PHY_WRITE(sc, 21, 0x1000); 495 PHY_WRITE(sc, 24, 0x65C7); 496 PHY_CLRBIT(sc, 4, 0x0800); 497 val = PHY_READ(sc, 4) & 0xFFF; 498 PHY_WRITE(sc, 4, val); 499 PHY_WRITE(sc, 3, 0x00A1); 500 PHY_WRITE(sc, 2, 0x0008); 501 PHY_WRITE(sc, 1, 0x1020); 502 PHY_WRITE(sc, 0, 0x1000); 503 PHY_SETBIT(sc, 4, 0x0800); 504 PHY_CLRBIT(sc, 4, 0x0800); 505 val = (PHY_READ(sc, 4) & 0xFFF) | 0x7000; 506 PHY_WRITE(sc, 4, val); 507 PHY_WRITE(sc, 3, 0xFF41); 508 PHY_WRITE(sc, 2, 0xDE60); 509 PHY_WRITE(sc, 1, 0x0140); 510 PHY_WRITE(sc, 0, 0x0077); 511 val = (PHY_READ(sc, 4) & 0xFFF) | 0xA000; 512 PHY_WRITE(sc, 4, val); 513 PHY_WRITE(sc, 3, 0xDF01); 514 PHY_WRITE(sc, 2, 0xDF20); 515 PHY_WRITE(sc, 1, 0xFF95); 516 PHY_WRITE(sc, 0, 0xFA00); 517 val = (PHY_READ(sc, 4) & 0xFFF) | 0xB000; 518 PHY_WRITE(sc, 4, val); 519 PHY_WRITE(sc, 3, 0xFF41); 520 PHY_WRITE(sc, 2, 0xDE20); 521 PHY_WRITE(sc, 1, 0x0140); 522 PHY_WRITE(sc, 0, 0x00BB); 523 val = (PHY_READ(sc, 4) & 0xFFF) | 0xF000; 524 PHY_WRITE(sc, 4, val); 525 PHY_WRITE(sc, 3, 0xDF01); 526 PHY_WRITE(sc, 2, 0xDF20); 527 PHY_WRITE(sc, 1, 0xFF95); 528 PHY_WRITE(sc, 0, 0xBF00); 529 PHY_SETBIT(sc, 4, 0x0800); 530 PHY_CLRBIT(sc, 4, 0x0800); 531 PHY_WRITE(sc, 31, 0x0000); 532 #else 533 (void)val; 534 PHY_WRITE(sc, 0x1f, 0x0001); 535 PHY_WRITE(sc, 0x15, 0x1000); 536 PHY_WRITE(sc, 0x18, 0x65c7); 537 PHY_WRITE(sc, 0x04, 0x0000); 538 PHY_WRITE(sc, 0x03, 0x00a1); 539 PHY_WRITE(sc, 0x02, 0x0008); 540 PHY_WRITE(sc, 0x01, 0x1020); 541 PHY_WRITE(sc, 0x00, 0x1000); 542 PHY_WRITE(sc, 0x04, 0x0800); 543 PHY_WRITE(sc, 0x04, 0x0000); 544 PHY_WRITE(sc, 0x04, 0x7000); 545 PHY_WRITE(sc, 0x03, 0xff41); 546 PHY_WRITE(sc, 0x02, 0xde60); 547 PHY_WRITE(sc, 0x01, 0x0140); 548 PHY_WRITE(sc, 0x00, 0x0077); 549 PHY_WRITE(sc, 0x04, 0x7800); 550 PHY_WRITE(sc, 0x04, 0x7000); 551 PHY_WRITE(sc, 0x04, 0xa000); 552 PHY_WRITE(sc, 0x03, 0xdf01); 553 PHY_WRITE(sc, 0x02, 0xdf20); 554 PHY_WRITE(sc, 0x01, 0xff95); 555 PHY_WRITE(sc, 0x00, 0xfa00); 556 PHY_WRITE(sc, 0x04, 0xa800); 557 PHY_WRITE(sc, 0x04, 0xa000); 558 PHY_WRITE(sc, 0x04, 0xb000); 559 PHY_WRITE(sc, 0x0e, 0xff41); 560 PHY_WRITE(sc, 0x02, 0xde20); 561 PHY_WRITE(sc, 0x01, 0x0140); 562 PHY_WRITE(sc, 0x00, 0x00bb); 563 PHY_WRITE(sc, 0x04, 0xb800); 564 PHY_WRITE(sc, 0x04, 0xb000); 565 PHY_WRITE(sc, 0x04, 0xf000); 566 PHY_WRITE(sc, 0x03, 0xdf01); 567 PHY_WRITE(sc, 0x02, 0xdf20); 568 PHY_WRITE(sc, 0x01, 0xff95); 569 PHY_WRITE(sc, 0x00, 0xbf00); 570 PHY_WRITE(sc, 0x04, 0xf800); 571 PHY_WRITE(sc, 0x04, 0xf000); 572 PHY_WRITE(sc, 0x04, 0x0000); 573 PHY_WRITE(sc, 0x1f, 0x0000); 574 PHY_WRITE(sc, 0x0b, 0x0000); 575 576 #endif 577 578 DELAY(40); 579 } 580 581 static void 582 rgephy_reset(struct mii_softc *sc) 583 { 584 struct rgephy_softc *rsc; 585 586 mii_phy_reset(sc); 587 DELAY(1000); 588 589 rsc = (struct rgephy_softc *)sc; 590 if (rsc->mii_revision < 2) 591 rgephy_load_dspcode(sc); 592 else { 593 PHY_WRITE(sc, 0x1F, 0x0001); 594 PHY_WRITE(sc, 0x09, 0x273a); 595 PHY_WRITE(sc, 0x0e, 0x7bfb); 596 PHY_WRITE(sc, 0x1b, 0x841e); 597 598 PHY_WRITE(sc, 0x1F, 0x0002); 599 PHY_WRITE(sc, 0x01, 0x90D0); 600 PHY_WRITE(sc, 0x1F, 0x0000); 601 PHY_WRITE(sc, 0x0e, 0x0000); 602 } 603 604 /* Reset capabilities */ 605 /* Step1: write our capability */ 606 /* 10/100 capability */ 607 PHY_WRITE(sc, RGEPHY_MII_ANAR, 608 RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_TX | 609 RGEPHY_ANAR_10_FD | RGEPHY_ANAR_10 | ANAR_CSMA); 610 /* 1000 capability */ 611 PHY_WRITE(sc, RGEPHY_MII_1000CTL, 612 RGEPHY_1000CTL_AFD | RGEPHY_1000CTL_AHD); 613 614 /* Step2: Restart NWay */ 615 /* NWay enable and Restart NWay */ 616 PHY_WRITE(sc, RGEPHY_MII_BMCR, 617 RGEPHY_BMCR_RESET | RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG); 618 } 619
Indexes created Thu Oct 02 14:10:14 GMT 2025