rgephy.c revision 1.3
1 /* $NetBSD: rgephy.c,v 1.3 2005/02/04 15:17:31 kanaoka Exp $ */ 2 3 /* 4 * Copyright (c) 2003 5 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: rgephy.c,v 1.3 2005/02/04 15:17:31 kanaoka Exp $"); 37 38 39 /* 40 * Driver for the RealTek 8169S/8110S internal 10/100/1000 PHY. 41 */ 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/kernel.h> 46 #include <sys/socket.h> 47 48 49 #include <net/if.h> 50 #include <net/if_media.h> 51 52 #include <dev/mii/mii.h> 53 #include <dev/mii/miivar.h> 54 #include <dev/mii/miidevs.h> 55 56 #include <dev/mii/rgephyreg.h> 57 58 #include <dev/ic/rtl81x9reg.h> 59 60 static int rgephy_match(struct device *, struct cfdata *, void *); 61 static void rgephy_attach(struct device *, struct device *, void *); 62 63 CFATTACH_DECL(rgephy, sizeof(struct mii_softc), 64 rgephy_match, rgephy_attach, mii_phy_detach, mii_phy_activate); 65 66 67 static int rgephy_service(struct mii_softc *, struct mii_data *, int); 68 static void rgephy_status(struct mii_softc *); 69 static int rgephy_mii_phy_auto(struct mii_softc *); 70 static void rgephy_reset(struct mii_softc *); 71 static void rgephy_loop(struct mii_softc *); 72 static void rgephy_load_dspcode(struct mii_softc *); 73 static int rgephy_mii_model; 74 75 static const struct mii_phy_funcs rgephy_funcs = { 76 rgephy_service, rgephy_status, rgephy_reset, 77 }; 78 79 static const struct mii_phydesc rgephys[] = { 80 { MII_OUI_xxREALTEK, MII_MODEL_xxREALTEK_RTL8169S, 81 MII_STR_xxREALTEK_RTL8169S }, 82 83 { MII_OUI_REALTEK, MII_MODEL_REALTEK_RTL8169S, 84 MII_STR_REALTEK_RTL8169S }, 85 86 }; 87 88 static int 89 rgephy_match(struct device *parent, struct cfdata *match, void *aux) 90 { 91 struct mii_attach_args *ma = aux; 92 93 if (mii_phy_match(ma, rgephys) != NULL) 94 return (10); 95 96 return (0); 97 } 98 99 static void 100 rgephy_attach(struct device *parent, struct device *self, void *aux) 101 { 102 struct mii_softc *sc = (struct mii_softc *)self; 103 struct mii_attach_args *ma = aux; 104 struct mii_data *mii = ma->mii_data; 105 const struct mii_phydesc *mpd; 106 int rev; 107 const char *sep = ""; 108 109 rev = MII_REV(ma->mii_id2); 110 mpd = mii_phy_match(ma, rgephys); 111 aprint_naive(": Media interface\n"); 112 aprint_normal(": %s, rev. %d\n", mpd->mpd_name, rev); 113 114 sc->mii_mpd_model = rev; /* XXX miivar.h comment vs usage? */ 115 sc->mii_inst = mii->mii_instance; 116 sc->mii_phy = ma->mii_phyno; 117 sc->mii_pdata = mii; 118 sc->mii_flags = mii->mii_flags; 119 sc->mii_anegticks = 5; 120 121 sc->mii_funcs = &rgephy_funcs; 122 123 /* Don't do isolate on this PHY. */ 124 sc->mii_flags |= MIIF_NOISOLATE; 125 126 #define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL) 127 #define PRINT(n) aprint_normal("%s%s", sep, (n)); sep = ", " 128 129 #if 0 130 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, sc->mii_inst), 131 BMCR_ISO); 132 #endif 133 #ifdef __FreeBSD__ 134 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst), 135 BMCR_LOOP|BMCR_S100); 136 #endif 137 138 rgephy_mii_model = MII_MODEL(ma->mii_id2); 139 PHY_RESET(sc); 140 141 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask; 142 sc->mii_capabilities &= ~BMSR_ANEG; 143 144 /* 145 * FreeBSD does not check EXSTAT, but instead adds gigabit 146 * media explicitly. Why? 147 */ 148 aprint_normal("%s: ", sc->mii_dev.dv_xname); 149 #ifdef __FreeBSD__ 150 mii_phy_add_media(sc); 151 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, 0, sc->mii_inst), 152 RGEPHY_BMCR_FDX); 153 PRINT(", 1000baseTX"); 154 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, IFM_FDX, sc->mii_inst), 0); 155 PRINT("1000baseTX-FDX"); 156 #else 157 if (sc->mii_capabilities & BMSR_EXTSTAT) { 158 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); 159 } 160 mii_phy_add_media(sc); 161 #endif 162 /* rtl8169S does not report auto-sense; add manually. */ 163 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), MII_NMEDIA); 164 sep =", "; 165 PRINT("auto"); 166 167 #undef ADD 168 #undef PRINT 169 170 aprint_normal("\n"); 171 } 172 173 static int 174 rgephy_service(sc, mii, cmd) 175 struct mii_softc *sc; 176 struct mii_data *mii; 177 int cmd; 178 { 179 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 180 int reg, speed, gig; 181 182 switch (cmd) { 183 case MII_POLLSTAT: 184 /* 185 * If we're not polling our PHY instance, just return. 186 */ 187 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 188 return (0); 189 break; 190 191 case MII_MEDIACHG: 192 /* 193 * If the media indicates a different PHY instance, 194 * isolate ourselves. 195 */ 196 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 197 reg = PHY_READ(sc, MII_BMCR); 198 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO); 199 return (0); 200 } 201 202 /* 203 * If the interface is not up, don't do anything. 204 */ 205 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 206 break; 207 208 PHY_RESET(sc); /* XXX hardware bug work-around */ 209 210 switch (IFM_SUBTYPE(ife->ifm_media)) { 211 case IFM_AUTO: 212 #ifdef foo 213 /* 214 * If we're already in auto mode, just return. 215 */ 216 if (PHY_READ(sc, RGEPHY_MII_BMCR) & RGEPHY_BMCR_AUTOEN) 217 return (0); 218 #endif 219 (void) rgephy_mii_phy_auto(sc); 220 break; 221 case IFM_1000_T: 222 speed = RGEPHY_S1000; 223 goto setit; 224 case IFM_100_TX: 225 speed = RGEPHY_S100; 226 goto setit; 227 case IFM_10_T: 228 speed = RGEPHY_S10; 229 setit: 230 rgephy_loop(sc); 231 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 232 speed |= RGEPHY_BMCR_FDX; 233 gig = RGEPHY_1000CTL_AFD; 234 } else { 235 gig = RGEPHY_1000CTL_AHD; 236 } 237 238 PHY_WRITE(sc, RGEPHY_MII_1000CTL, 0); 239 PHY_WRITE(sc, RGEPHY_MII_BMCR, speed); 240 PHY_WRITE(sc, RGEPHY_MII_ANAR, RGEPHY_SEL_TYPE); 241 242 if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T) 243 break; 244 245 PHY_WRITE(sc, RGEPHY_MII_1000CTL, gig); 246 PHY_WRITE(sc, RGEPHY_MII_BMCR, 247 speed|RGEPHY_BMCR_AUTOEN|RGEPHY_BMCR_STARTNEG); 248 249 /* 250 * When settning the link manually, one side must 251 * be the master and the other the slave. However 252 * ifmedia doesn't give us a good way to specify 253 * this, so we fake it by using one of the LINK 254 * flags. If LINK0 is set, we program the PHY to 255 * be a master, otherwise it's a slave. 256 */ 257 if ((mii->mii_ifp->if_flags & IFF_LINK0)) { 258 PHY_WRITE(sc, RGEPHY_MII_1000CTL, 259 gig|RGEPHY_1000CTL_MSE|RGEPHY_1000CTL_MSC); 260 } else { 261 PHY_WRITE(sc, RGEPHY_MII_1000CTL, 262 gig|RGEPHY_1000CTL_MSE); 263 } 264 break; 265 #ifdef foo 266 case IFM_NONE: 267 PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN); 268 break; 269 #endif 270 case IFM_100_T4: 271 default: 272 return (EINVAL); 273 } 274 break; 275 276 case MII_TICK: 277 /* 278 * If we're not currently selected, just return. 279 */ 280 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 281 return (0); 282 283 /* 284 * Is the interface even up? 285 */ 286 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 287 return (0); 288 289 /* 290 * Only used for autonegotiation. 291 */ 292 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) 293 break; 294 295 /* 296 * Check to see if we have link. If we do, we don't 297 * need to restart the autonegotiation process. Read 298 * the BMSR twice in case it's latched. 299 */ 300 reg = PHY_READ(sc, RTK_GMEDIASTAT); 301 if (reg & RTK_GMEDIASTAT_LINK) 302 break; 303 304 /* 305 * Only retry autonegotiation every 5 seconds. 306 */ 307 if (++sc->mii_ticks <= 5/*10*/) 308 break; 309 310 sc->mii_ticks = 0; 311 rgephy_mii_phy_auto(sc); 312 return (0); 313 } 314 315 /* Update the media status. */ 316 rgephy_status(sc); 317 318 /* 319 * Callback if something changed. Note that we need to poke 320 * the DSP on the RealTek PHYs if the media changes. 321 * 322 */ 323 if (sc->mii_media_active != mii->mii_media_active || 324 sc->mii_media_status != mii->mii_media_status || 325 cmd == MII_MEDIACHG) { 326 /* XXX only for v0/v1 phys. */ 327 if (sc->mii_mpd_model < 2) 328 rgephy_load_dspcode(sc); 329 } 330 mii_phy_update(sc, cmd); 331 return (0); 332 } 333 334 static void 335 rgephy_status(sc) 336 struct mii_softc *sc; 337 { 338 struct mii_data *mii = sc->mii_pdata; 339 int bmsr, bmcr; 340 341 mii->mii_media_status = IFM_AVALID; 342 mii->mii_media_active = IFM_ETHER; 343 344 bmsr = PHY_READ(sc, RTK_GMEDIASTAT); 345 346 if (bmsr & RTK_GMEDIASTAT_LINK) 347 mii->mii_media_status |= IFM_ACTIVE; 348 bmsr = PHY_READ(sc, RGEPHY_MII_BMSR); 349 350 bmcr = PHY_READ(sc, RGEPHY_MII_BMCR); 351 352 if (bmcr & RGEPHY_BMCR_ISO) { 353 mii->mii_media_active |= IFM_NONE; 354 mii->mii_media_status = 0; 355 return; 356 } 357 358 if (bmcr & RGEPHY_BMCR_LOOP) 359 mii->mii_media_active |= IFM_LOOP; 360 361 if (bmcr & RGEPHY_BMCR_AUTOEN) { 362 if ((bmsr & RGEPHY_BMSR_ACOMP) == 0) { 363 /* Erg, still trying, I guess... */ 364 mii->mii_media_active |= IFM_NONE; 365 return; 366 } 367 } 368 369 bmsr = PHY_READ(sc, RTK_GMEDIASTAT); 370 if (bmsr & RTK_GMEDIASTAT_10MBPS) 371 mii->mii_media_active |= IFM_10_T; 372 if (bmsr & RTK_GMEDIASTAT_100MBPS) 373 mii->mii_media_active |= IFM_100_TX; 374 if (bmsr & RTK_GMEDIASTAT_1000MBPS) 375 mii->mii_media_active |= IFM_1000_T; 376 if (bmsr & RTK_GMEDIASTAT_FDX) 377 mii->mii_media_active |= IFM_FDX; 378 379 return; 380 } 381 382 383 static int 384 rgephy_mii_phy_auto(mii) 385 struct mii_softc *mii; 386 { 387 rgephy_loop(mii); 388 PHY_RESET(mii); 389 390 PHY_WRITE(mii, RGEPHY_MII_ANAR, 391 BMSR_MEDIA_TO_ANAR(mii->mii_capabilities) | ANAR_CSMA); 392 DELAY(1000); 393 PHY_WRITE(mii, RGEPHY_MII_1000CTL, RGEPHY_1000CTL_AFD); 394 DELAY(1000); 395 PHY_WRITE(mii, RGEPHY_MII_BMCR, 396 RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG); 397 DELAY(100); 398 399 return (EJUSTRETURN); 400 } 401 402 static void 403 rgephy_loop(struct mii_softc *sc) 404 { 405 u_int32_t bmsr; 406 int i; 407 408 PHY_WRITE(sc, RGEPHY_MII_BMCR, RGEPHY_BMCR_PDOWN); 409 DELAY(1000); 410 411 for (i = 0; i < 15000; i++) { 412 bmsr = PHY_READ(sc, RGEPHY_MII_BMSR); 413 if (!(bmsr & RGEPHY_BMSR_LINK)) { 414 #if 0 415 device_printf(sc->mii_dev, "looped %d\n", i); 416 #endif 417 break; 418 } 419 DELAY(10); 420 } 421 } 422 423 #define PHY_SETBIT(x, y, z) \ 424 PHY_WRITE(x, y, (PHY_READ(x, y) | (z))) 425 #define PHY_CLRBIT(x, y, z) \ 426 PHY_WRITE(x, y, (PHY_READ(x, y) & ~(z))) 427 428 /* 429 * Initialize RealTek PHY per the datasheet. The DSP in the PHYs of 430 * existing revisions of the 8169S/8110S chips need to be tuned in 431 * order to reliably negotiate a 1000Mbps link. Later revs of the 432 * chips may not require this software tuning. 433 */ 434 static void 435 rgephy_load_dspcode(struct mii_softc *sc) 436 { 437 int val; 438 439 440 441 #if 1 442 PHY_WRITE(sc, 31, 0x0001); 443 PHY_WRITE(sc, 21, 0x1000); 444 PHY_WRITE(sc, 24, 0x65C7); 445 PHY_CLRBIT(sc, 4, 0x0800); 446 val = PHY_READ(sc, 4) & 0xFFF; 447 PHY_WRITE(sc, 4, val); 448 PHY_WRITE(sc, 3, 0x00A1); 449 PHY_WRITE(sc, 2, 0x0008); 450 PHY_WRITE(sc, 1, 0x1020); 451 PHY_WRITE(sc, 0, 0x1000); 452 PHY_SETBIT(sc, 4, 0x0800); 453 PHY_CLRBIT(sc, 4, 0x0800); 454 val = (PHY_READ(sc, 4) & 0xFFF) | 0x7000; 455 PHY_WRITE(sc, 4, val); 456 PHY_WRITE(sc, 3, 0xFF41); 457 PHY_WRITE(sc, 2, 0xDE60); 458 PHY_WRITE(sc, 1, 0x0140); 459 PHY_WRITE(sc, 0, 0x0077); 460 val = (PHY_READ(sc, 4) & 0xFFF) | 0xA000; 461 PHY_WRITE(sc, 4, val); 462 PHY_WRITE(sc, 3, 0xDF01); 463 PHY_WRITE(sc, 2, 0xDF20); 464 PHY_WRITE(sc, 1, 0xFF95); 465 PHY_WRITE(sc, 0, 0xFA00); 466 val = (PHY_READ(sc, 4) & 0xFFF) | 0xB000; 467 PHY_WRITE(sc, 4, val); 468 PHY_WRITE(sc, 3, 0xFF41); 469 PHY_WRITE(sc, 2, 0xDE20); 470 PHY_WRITE(sc, 1, 0x0140); 471 PHY_WRITE(sc, 0, 0x00BB); 472 val = (PHY_READ(sc, 4) & 0xFFF) | 0xF000; 473 PHY_WRITE(sc, 4, val); 474 PHY_WRITE(sc, 3, 0xDF01); 475 PHY_WRITE(sc, 2, 0xDF20); 476 PHY_WRITE(sc, 1, 0xFF95); 477 PHY_WRITE(sc, 0, 0xBF00); 478 PHY_SETBIT(sc, 4, 0x0800); 479 PHY_CLRBIT(sc, 4, 0x0800); 480 PHY_WRITE(sc, 31, 0x0000); 481 #else 482 (void)val; 483 PHY_WRITE(sc, 0x1f, 0x0001); 484 PHY_WRITE(sc, 0x15, 0x1000); 485 PHY_WRITE(sc, 0x18, 0x65c7); 486 PHY_WRITE(sc, 0x04, 0x0000); 487 PHY_WRITE(sc, 0x03, 0x00a1); 488 PHY_WRITE(sc, 0x02, 0x0008); 489 PHY_WRITE(sc, 0x01, 0x1020); 490 PHY_WRITE(sc, 0x00, 0x1000); 491 PHY_WRITE(sc, 0x04, 0x0800); 492 PHY_WRITE(sc, 0x04, 0x0000); 493 PHY_WRITE(sc, 0x04, 0x7000); 494 PHY_WRITE(sc, 0x03, 0xff41); 495 PHY_WRITE(sc, 0x02, 0xde60); 496 PHY_WRITE(sc, 0x01, 0x0140); 497 PHY_WRITE(sc, 0x00, 0x0077); 498 PHY_WRITE(sc, 0x04, 0x7800); 499 PHY_WRITE(sc, 0x04, 0x7000); 500 PHY_WRITE(sc, 0x04, 0xa000); 501 PHY_WRITE(sc, 0x03, 0xdf01); 502 PHY_WRITE(sc, 0x02, 0xdf20); 503 PHY_WRITE(sc, 0x01, 0xff95); 504 PHY_WRITE(sc, 0x00, 0xfa00); 505 PHY_WRITE(sc, 0x04, 0xa800); 506 PHY_WRITE(sc, 0x04, 0xa000); 507 PHY_WRITE(sc, 0x04, 0xb000); 508 PHY_WRITE(sc, 0x0e, 0xff41); 509 PHY_WRITE(sc, 0x02, 0xde20); 510 PHY_WRITE(sc, 0x01, 0x0140); 511 PHY_WRITE(sc, 0x00, 0x00bb); 512 PHY_WRITE(sc, 0x04, 0xb800); 513 PHY_WRITE(sc, 0x04, 0xb000); 514 PHY_WRITE(sc, 0x04, 0xf000); 515 PHY_WRITE(sc, 0x03, 0xdf01); 516 PHY_WRITE(sc, 0x02, 0xdf20); 517 PHY_WRITE(sc, 0x01, 0xff95); 518 PHY_WRITE(sc, 0x00, 0xbf00); 519 PHY_WRITE(sc, 0x04, 0xf800); 520 PHY_WRITE(sc, 0x04, 0xf000); 521 PHY_WRITE(sc, 0x04, 0x0000); 522 PHY_WRITE(sc, 0x1f, 0x0000); 523 PHY_WRITE(sc, 0x0b, 0x0000); 524 525 #endif 526 527 DELAY(40); 528 529 printf(" complete\n"); 530 531 532 } 533 534 static void 535 rgephy_reset(struct mii_softc *sc) 536 { 537 mii_phy_reset(sc); 538 DELAY(1000); 539 540 if (sc->mii_mpd_model < 2) 541 rgephy_load_dspcode(sc); 542 else { 543 PHY_WRITE(sc, 0x1F, 0x0001); 544 PHY_WRITE(sc, 0x09, 0x273a); 545 PHY_WRITE(sc, 0x0e, 0x7bfb); 546 PHY_WRITE(sc, 0x1b, 0x841e); 547 548 PHY_WRITE(sc, 0x1F, 0x0002); 549 PHY_WRITE(sc, 0x01, 0x90D0); 550 PHY_WRITE(sc, 0x1F, 0x0000); 551 } 552 553 /* Reset capabilities */ 554 /* Step1: write our capability */ 555 PHY_WRITE(sc, 0x04,0x01e1); /* 10/100 capability */ 556 PHY_WRITE(sc, 0x09,0x0200); /* 1000 capability */ 557 558 #ifdef jrs_notyet 559 /* Step2: Restart NWay */ 560 PHY_WRITE(sc, 0x00, 0x1200); // NWay enable and Restart NWay 561 #endif 562 } 563
Indexes created Thu Oct 02 14:10:14 GMT 2025