rgephy.c revision 1.30
1 /* $NetBSD: rgephy.c,v 1.30 2013/06/06 03:10:48 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 2003 5 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: rgephy.c,v 1.30 2013/06/06 03:10:48 msaitoh Exp $"); 37 38 39 /* 40 * Driver for the RealTek 8169S/8110S internal 10/100/1000 PHY. 41 */ 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/kernel.h> 46 #include <sys/device.h> 47 #include <sys/socket.h> 48 49 50 #include <net/if.h> 51 #include <net/if_media.h> 52 53 #include <dev/mii/mii.h> 54 #include <dev/mii/miivar.h> 55 #include <dev/mii/miidevs.h> 56 57 #include <dev/mii/rgephyreg.h> 58 59 #include <dev/ic/rtl81x9reg.h> 60 61 static int rgephy_match(device_t, cfdata_t, void *); 62 static void rgephy_attach(device_t, device_t, void *); 63 64 struct rgephy_softc { 65 struct mii_softc mii_sc; 66 int mii_revision; 67 }; 68 69 CFATTACH_DECL_NEW(rgephy, sizeof(struct rgephy_softc), 70 rgephy_match, rgephy_attach, mii_phy_detach, mii_phy_activate); 71 72 73 static int rgephy_service(struct mii_softc *, struct mii_data *, int); 74 static void rgephy_status(struct mii_softc *); 75 static int rgephy_mii_phy_auto(struct mii_softc *); 76 static void rgephy_reset(struct mii_softc *); 77 static void rgephy_loop(struct mii_softc *); 78 static void rgephy_load_dspcode(struct mii_softc *); 79 80 static const struct mii_phy_funcs rgephy_funcs = { 81 rgephy_service, rgephy_status, rgephy_reset, 82 }; 83 84 static const struct mii_phydesc rgephys[] = { 85 { MII_OUI_xxREALTEK, MII_MODEL_xxREALTEK_RTL8169S, 86 MII_STR_xxREALTEK_RTL8169S }, 87 88 { MII_OUI_REALTEK, MII_MODEL_REALTEK_RTL8169S, 89 MII_STR_REALTEK_RTL8169S }, 90 91 { 0, 0, 92 NULL } 93 }; 94 95 static int 96 rgephy_match(device_t parent, cfdata_t match, void *aux) 97 { 98 struct mii_attach_args *ma = aux; 99 100 if (mii_phy_match(ma, rgephys) != NULL) 101 return 10; 102 103 return 0; 104 } 105 106 static void 107 rgephy_attach(device_t parent, device_t self, void *aux) 108 { 109 struct rgephy_softc *rsc = device_private(self); 110 struct mii_softc *sc = &rsc->mii_sc; 111 struct mii_attach_args *ma = aux; 112 struct mii_data *mii = ma->mii_data; 113 const struct mii_phydesc *mpd; 114 int rev; 115 const char *sep = ""; 116 117 ma = aux; 118 mii = ma->mii_data; 119 120 rev = MII_REV(ma->mii_id2); 121 mpd = mii_phy_match(ma, rgephys); 122 aprint_naive(": Media interface\n"); 123 aprint_normal(": %s, rev. %d\n", mpd->mpd_name, rev); 124 125 rsc->mii_revision = rev; 126 127 sc->mii_dev = self; 128 sc->mii_inst = mii->mii_instance; 129 sc->mii_phy = ma->mii_phyno; 130 sc->mii_pdata = mii; 131 sc->mii_flags = mii->mii_flags; 132 sc->mii_anegticks = MII_ANEGTICKS_GIGE; 133 134 sc->mii_funcs = &rgephy_funcs; 135 136 #define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL) 137 #define PRINT(n) aprint_normal("%s%s", sep, (n)); sep = ", " 138 139 #ifdef __FreeBSD__ 140 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst), 141 BMCR_LOOP|BMCR_S100); 142 #endif 143 144 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask; 145 sc->mii_capabilities &= ~BMSR_ANEG; 146 147 /* 148 * FreeBSD does not check EXSTAT, but instead adds gigabit 149 * media explicitly. Why? 150 */ 151 aprint_normal_dev(self, ""); 152 if (sc->mii_capabilities & BMSR_EXTSTAT) { 153 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); 154 } 155 mii_phy_add_media(sc); 156 157 /* rtl8169S does not report auto-sense; add manually. */ 158 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), MII_NMEDIA); 159 sep =", "; 160 PRINT("auto"); 161 162 #undef ADD 163 #undef PRINT 164 165 rgephy_reset(sc); 166 aprint_normal("\n"); 167 } 168 169 static int 170 rgephy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 171 { 172 struct rgephy_softc *rsc; 173 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 174 int reg, speed, gig, anar; 175 176 rsc = (struct rgephy_softc *)sc; 177 178 switch (cmd) { 179 case MII_POLLSTAT: 180 /* 181 * If we're not polling our PHY instance, just return. 182 */ 183 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 184 return 0; 185 break; 186 187 case MII_MEDIACHG: 188 /* 189 * If the media indicates a different PHY instance, 190 * isolate ourselves. 191 */ 192 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 193 reg = PHY_READ(sc, MII_BMCR); 194 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO); 195 return 0; 196 } 197 198 /* 199 * If the interface is not up, don't do anything. 200 */ 201 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 202 break; 203 204 rgephy_reset(sc); /* XXX hardware bug work-around */ 205 206 anar = PHY_READ(sc, MII_ANAR); 207 anar &= ~(ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10); 208 209 switch (IFM_SUBTYPE(ife->ifm_media)) { 210 case IFM_AUTO: 211 #ifdef foo 212 /* 213 * If we're already in auto mode, just return. 214 */ 215 if (PHY_READ(sc, MII_BMCR) & BMCR_AUTOEN) 216 return 0; 217 #endif 218 (void)rgephy_mii_phy_auto(sc); 219 break; 220 case IFM_1000_T: 221 speed = BMCR_S1000; 222 goto setit; 223 case IFM_100_TX: 224 speed = BMCR_S100; 225 anar |= ANAR_TX_FD | ANAR_TX; 226 goto setit; 227 case IFM_10_T: 228 speed = BMCR_S10; 229 anar |= ANAR_10_FD | ANAR_10; 230 setit: 231 rgephy_loop(sc); 232 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 233 speed |= BMCR_FDX; 234 gig = GTCR_ADV_1000TFDX; 235 anar &= ~(ANAR_TX | ANAR_10); 236 } else { 237 gig = GTCR_ADV_1000THDX; 238 anar &= ~(ANAR_TX_FD | ANAR_10_FD); 239 } 240 241 if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T) { 242 PHY_WRITE(sc, MII_100T2CR, 0); 243 PHY_WRITE(sc, MII_ANAR, anar); 244 PHY_WRITE(sc, MII_BMCR, speed | 245 BMCR_AUTOEN | BMCR_STARTNEG); 246 break; 247 } 248 249 /* 250 * When setting the link manually, one side must 251 * be the master and the other the slave. However 252 * ifmedia doesn't give us a good way to specify 253 * this, so we fake it by using one of the LINK 254 * flags. If LINK0 is set, we program the PHY to 255 * be a master, otherwise it's a slave. 256 */ 257 if ((mii->mii_ifp->if_flags & IFF_LINK0)) { 258 PHY_WRITE(sc, MII_100T2CR, 259 gig|GTCR_MAN_MS|GTCR_ADV_MS); 260 } else { 261 PHY_WRITE(sc, MII_100T2CR, gig|GTCR_MAN_MS); 262 } 263 PHY_WRITE(sc, MII_BMCR, speed | 264 BMCR_AUTOEN | BMCR_STARTNEG); 265 break; 266 case IFM_NONE: 267 PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN); 268 break; 269 case IFM_100_T4: 270 default: 271 return EINVAL; 272 } 273 break; 274 275 case MII_TICK: 276 /* 277 * If we're not currently selected, just return. 278 */ 279 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 280 return 0; 281 282 /* 283 * Is the interface even up? 284 */ 285 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 286 return 0; 287 288 /* 289 * Only used for autonegotiation. 290 */ 291 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) 292 break; 293 294 /* 295 * Check to see if we have link. If we do, we don't 296 * need to restart the autonegotiation process. Read 297 * the BMSR twice in case it's latched. 298 */ 299 if (rsc->mii_revision >= 2) { 300 /* RTL8211B(L) */ 301 reg = PHY_READ(sc, RGEPHY_MII_SSR); 302 if (reg & RGEPHY_SSR_LINK) { 303 sc->mii_ticks = 0; 304 break; 305 } 306 } else { 307 reg = PHY_READ(sc, RTK_GMEDIASTAT); 308 if ((reg & RTK_GMEDIASTAT_LINK) != 0) { 309 sc->mii_ticks = 0; 310 break; 311 } 312 } 313 314 /* Announce link loss right after it happens. */ 315 if (sc->mii_ticks++ == 0) 316 break; 317 318 /* Only retry autonegotiation every mii_anegticks seconds. */ 319 if (sc->mii_ticks <= sc->mii_anegticks) 320 return 0; 321 322 rgephy_mii_phy_auto(sc); 323 break; 324 } 325 326 /* Update the media status. */ 327 rgephy_status(sc); 328 329 /* 330 * Callback if something changed. Note that we need to poke 331 * the DSP on the RealTek PHYs if the media changes. 332 * 333 */ 334 if (sc->mii_media_active != mii->mii_media_active || 335 sc->mii_media_status != mii->mii_media_status || 336 cmd == MII_MEDIACHG) { 337 rgephy_load_dspcode(sc); 338 } 339 mii_phy_update(sc, cmd); 340 return 0; 341 } 342 343 static void 344 rgephy_status(struct mii_softc *sc) 345 { 346 struct rgephy_softc *rsc; 347 struct mii_data *mii = sc->mii_pdata; 348 int gstat, bmsr, bmcr; 349 uint16_t ssr; 350 351 mii->mii_media_status = IFM_AVALID; 352 mii->mii_media_active = IFM_ETHER; 353 354 rsc = (struct rgephy_softc *)sc; 355 if (rsc->mii_revision >= 2) { 356 ssr = PHY_READ(sc, RGEPHY_MII_SSR); 357 if (ssr & RGEPHY_SSR_LINK) 358 mii->mii_media_status |= IFM_ACTIVE; 359 } else { 360 gstat = PHY_READ(sc, RTK_GMEDIASTAT); 361 if ((gstat & RTK_GMEDIASTAT_LINK) != 0) 362 mii->mii_media_status |= IFM_ACTIVE; 363 } 364 365 bmsr = PHY_READ(sc, MII_BMSR); 366 bmcr = PHY_READ(sc, MII_BMCR); 367 368 if ((bmcr & BMCR_ISO) != 0) { 369 mii->mii_media_active |= IFM_NONE; 370 mii->mii_media_status = 0; 371 return; 372 } 373 374 if ((bmcr & BMCR_LOOP) != 0) 375 mii->mii_media_active |= IFM_LOOP; 376 377 if ((bmcr & BMCR_AUTOEN) != 0) { 378 if ((bmsr & BMSR_ACOMP) == 0) { 379 /* Erg, still trying, I guess... */ 380 mii->mii_media_active |= IFM_NONE; 381 return; 382 } 383 } 384 385 if (rsc->mii_revision >= 2) { 386 ssr = PHY_READ(sc, RGEPHY_MII_SSR); 387 switch (ssr & RGEPHY_SSR_SPD_MASK) { 388 case RGEPHY_SSR_S1000: 389 mii->mii_media_active |= IFM_1000_T; 390 break; 391 case RGEPHY_SSR_S100: 392 mii->mii_media_active |= IFM_100_TX; 393 break; 394 case RGEPHY_SSR_S10: 395 mii->mii_media_active |= IFM_10_T; 396 break; 397 default: 398 mii->mii_media_active |= IFM_NONE; 399 break; 400 } 401 if (ssr & RGEPHY_SSR_FDX) 402 mii->mii_media_active |= mii_phy_flowstatus(sc) | 403 IFM_FDX; 404 else 405 mii->mii_media_active |= IFM_HDX; 406 } else { 407 gstat = PHY_READ(sc, RTK_GMEDIASTAT); 408 if ((gstat & RTK_GMEDIASTAT_1000MBPS) != 0) 409 mii->mii_media_active |= IFM_1000_T; 410 else if ((gstat & RTK_GMEDIASTAT_100MBPS) != 0) 411 mii->mii_media_active |= IFM_100_TX; 412 else if ((gstat & RTK_GMEDIASTAT_10MBPS) != 0) 413 mii->mii_media_active |= IFM_10_T; 414 else 415 mii->mii_media_active |= IFM_NONE; 416 if ((gstat & RTK_GMEDIASTAT_FDX) != 0) 417 mii->mii_media_active |= mii_phy_flowstatus(sc) | 418 IFM_FDX; 419 else 420 mii->mii_media_active |= IFM_HDX; 421 } 422 } 423 424 425 static int 426 rgephy_mii_phy_auto(struct mii_softc *mii) 427 { 428 int anar; 429 430 mii->mii_ticks = 0; 431 rgephy_loop(mii); 432 rgephy_reset(mii); 433 434 anar = BMSR_MEDIA_TO_ANAR(mii->mii_capabilities) | ANAR_CSMA; 435 if (mii->mii_flags & MIIF_DOPAUSE) 436 anar |= ANAR_FC | ANAR_X_PAUSE_ASYM; 437 438 PHY_WRITE(mii, MII_ANAR, anar); 439 DELAY(1000); 440 PHY_WRITE(mii, MII_100T2CR, GTCR_ADV_1000THDX | GTCR_ADV_1000TFDX); 441 DELAY(1000); 442 PHY_WRITE(mii, MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG); 443 DELAY(100); 444 445 return EJUSTRETURN; 446 } 447 448 static void 449 rgephy_loop(struct mii_softc *sc) 450 { 451 struct rgephy_softc *rsc; 452 uint32_t bmsr; 453 int i; 454 455 rsc = (struct rgephy_softc *)sc; 456 if (rsc->mii_revision < 2) { 457 PHY_WRITE(sc, MII_BMCR, BMCR_PDOWN); 458 DELAY(1000); 459 } 460 461 for (i = 0; i < 15000; i++) { 462 bmsr = PHY_READ(sc, MII_BMSR); 463 if ((bmsr & BMSR_LINK) == 0) { 464 #if 0 465 device_printf(sc->mii_dev, "looped %d\n", i); 466 #endif 467 break; 468 } 469 DELAY(10); 470 } 471 } 472 473 #define PHY_SETBIT(x, y, z) \ 474 PHY_WRITE(x, y, (PHY_READ(x, y) | (z))) 475 #define PHY_CLRBIT(x, y, z) \ 476 PHY_WRITE(x, y, (PHY_READ(x, y) & ~(z))) 477 478 /* 479 * Initialize RealTek PHY per the datasheet. The DSP in the PHYs of 480 * existing revisions of the 8169S/8110S chips need to be tuned in 481 * order to reliably negotiate a 1000Mbps link. This is only needed 482 * for rev 0 and rev 1 of the PHY. Later versions work without 483 * any fixups. 484 */ 485 static void 486 rgephy_load_dspcode(struct mii_softc *sc) 487 { 488 struct rgephy_softc *rsc; 489 int val; 490 491 rsc = (struct rgephy_softc *)sc; 492 if (rsc->mii_revision >= 2) 493 return; 494 495 #if 1 496 PHY_WRITE(sc, 31, 0x0001); 497 PHY_WRITE(sc, 21, 0x1000); 498 PHY_WRITE(sc, 24, 0x65C7); 499 PHY_CLRBIT(sc, 4, 0x0800); 500 val = PHY_READ(sc, 4) & 0xFFF; 501 PHY_WRITE(sc, 4, val); 502 PHY_WRITE(sc, 3, 0x00A1); 503 PHY_WRITE(sc, 2, 0x0008); 504 PHY_WRITE(sc, 1, 0x1020); 505 PHY_WRITE(sc, 0, 0x1000); 506 PHY_SETBIT(sc, 4, 0x0800); 507 PHY_CLRBIT(sc, 4, 0x0800); 508 val = (PHY_READ(sc, 4) & 0xFFF) | 0x7000; 509 PHY_WRITE(sc, 4, val); 510 PHY_WRITE(sc, 3, 0xFF41); 511 PHY_WRITE(sc, 2, 0xDE60); 512 PHY_WRITE(sc, 1, 0x0140); 513 PHY_WRITE(sc, 0, 0x0077); 514 val = (PHY_READ(sc, 4) & 0xFFF) | 0xA000; 515 PHY_WRITE(sc, 4, val); 516 PHY_WRITE(sc, 3, 0xDF01); 517 PHY_WRITE(sc, 2, 0xDF20); 518 PHY_WRITE(sc, 1, 0xFF95); 519 PHY_WRITE(sc, 0, 0xFA00); 520 val = (PHY_READ(sc, 4) & 0xFFF) | 0xB000; 521 PHY_WRITE(sc, 4, val); 522 PHY_WRITE(sc, 3, 0xFF41); 523 PHY_WRITE(sc, 2, 0xDE20); 524 PHY_WRITE(sc, 1, 0x0140); 525 PHY_WRITE(sc, 0, 0x00BB); 526 val = (PHY_READ(sc, 4) & 0xFFF) | 0xF000; 527 PHY_WRITE(sc, 4, val); 528 PHY_WRITE(sc, 3, 0xDF01); 529 PHY_WRITE(sc, 2, 0xDF20); 530 PHY_WRITE(sc, 1, 0xFF95); 531 PHY_WRITE(sc, 0, 0xBF00); 532 PHY_SETBIT(sc, 4, 0x0800); 533 PHY_CLRBIT(sc, 4, 0x0800); 534 PHY_WRITE(sc, 31, 0x0000); 535 #else 536 (void)val; 537 PHY_WRITE(sc, 0x1f, 0x0001); 538 PHY_WRITE(sc, 0x15, 0x1000); 539 PHY_WRITE(sc, 0x18, 0x65c7); 540 PHY_WRITE(sc, 0x04, 0x0000); 541 PHY_WRITE(sc, 0x03, 0x00a1); 542 PHY_WRITE(sc, 0x02, 0x0008); 543 PHY_WRITE(sc, 0x01, 0x1020); 544 PHY_WRITE(sc, 0x00, 0x1000); 545 PHY_WRITE(sc, 0x04, 0x0800); 546 PHY_WRITE(sc, 0x04, 0x0000); 547 PHY_WRITE(sc, 0x04, 0x7000); 548 PHY_WRITE(sc, 0x03, 0xff41); 549 PHY_WRITE(sc, 0x02, 0xde60); 550 PHY_WRITE(sc, 0x01, 0x0140); 551 PHY_WRITE(sc, 0x00, 0x0077); 552 PHY_WRITE(sc, 0x04, 0x7800); 553 PHY_WRITE(sc, 0x04, 0x7000); 554 PHY_WRITE(sc, 0x04, 0xa000); 555 PHY_WRITE(sc, 0x03, 0xdf01); 556 PHY_WRITE(sc, 0x02, 0xdf20); 557 PHY_WRITE(sc, 0x01, 0xff95); 558 PHY_WRITE(sc, 0x00, 0xfa00); 559 PHY_WRITE(sc, 0x04, 0xa800); 560 PHY_WRITE(sc, 0x04, 0xa000); 561 PHY_WRITE(sc, 0x04, 0xb000); 562 PHY_WRITE(sc, 0x0e, 0xff41); 563 PHY_WRITE(sc, 0x02, 0xde20); 564 PHY_WRITE(sc, 0x01, 0x0140); 565 PHY_WRITE(sc, 0x00, 0x00bb); 566 PHY_WRITE(sc, 0x04, 0xb800); 567 PHY_WRITE(sc, 0x04, 0xb000); 568 PHY_WRITE(sc, 0x04, 0xf000); 569 PHY_WRITE(sc, 0x03, 0xdf01); 570 PHY_WRITE(sc, 0x02, 0xdf20); 571 PHY_WRITE(sc, 0x01, 0xff95); 572 PHY_WRITE(sc, 0x00, 0xbf00); 573 PHY_WRITE(sc, 0x04, 0xf800); 574 PHY_WRITE(sc, 0x04, 0xf000); 575 PHY_WRITE(sc, 0x04, 0x0000); 576 PHY_WRITE(sc, 0x1f, 0x0000); 577 PHY_WRITE(sc, 0x0b, 0x0000); 578 579 #endif 580 581 DELAY(40); 582 } 583 584 static void 585 rgephy_reset(struct mii_softc *sc) 586 { 587 struct rgephy_softc *rsc; 588 uint16_t ssr; 589 590 mii_phy_reset(sc); 591 DELAY(1000); 592 593 rsc = (struct rgephy_softc *)sc; 594 if (rsc->mii_revision < 2) { 595 rgephy_load_dspcode(sc); 596 } else if (rsc->mii_revision == 3) { 597 /* RTL8211C(L) */ 598 ssr = PHY_READ(sc, RGEPHY_MII_SSR); 599 if ((ssr & RGEPHY_SSR_ALDPS) != 0) { 600 ssr &= ~RGEPHY_SSR_ALDPS; 601 PHY_WRITE(sc, RGEPHY_MII_SSR, ssr); 602 } 603 } else { 604 PHY_WRITE(sc, 0x1F, 0x0000); 605 PHY_WRITE(sc, 0x0e, 0x0000); 606 } 607 608 /* Reset capabilities */ 609 /* Step1: write our capability */ 610 /* 10/100 capability */ 611 PHY_WRITE(sc, MII_ANAR, 612 ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 613 /* 1000 capability */ 614 PHY_WRITE(sc, MII_100T2CR, GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX); 615 616 /* Step2: Restart NWay */ 617 /* NWay enable and Restart NWay */ 618 PHY_WRITE(sc, MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 619 } 620
Indexes created Thu Oct 02 14:10:14 GMT 2025