rgephy.c revision 1.43
1 /* $NetBSD: rgephy.c,v 1.43 2018/06/19 10:36:41 jmcneill Exp $ */ 2 3 /* 4 * Copyright (c) 2003 5 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: rgephy.c,v 1.43 2018/06/19 10:36:41 jmcneill Exp $"); 37 38 39 /* 40 * Driver for the RealTek 8169S/8110S internal 10/100/1000 PHY. 41 */ 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/kernel.h> 46 #include <sys/device.h> 47 #include <sys/socket.h> 48 49 50 #include <net/if.h> 51 #include <net/if_media.h> 52 53 #include <dev/mii/mii.h> 54 #include <dev/mii/miivar.h> 55 #include <dev/mii/miidevs.h> 56 57 #include <dev/mii/rgephyreg.h> 58 59 #include <dev/ic/rtl81x9reg.h> 60 61 static int rgephy_match(device_t, cfdata_t, void *); 62 static void rgephy_attach(device_t, device_t, void *); 63 64 struct rgephy_softc { 65 struct mii_softc mii_sc; 66 bool mii_no_rx_delay; 67 }; 68 69 CFATTACH_DECL_NEW(rgephy, sizeof(struct rgephy_softc), 70 rgephy_match, rgephy_attach, mii_phy_detach, mii_phy_activate); 71 72 73 static int rgephy_service(struct mii_softc *, struct mii_data *, int); 74 static void rgephy_status(struct mii_softc *); 75 static int rgephy_mii_phy_auto(struct mii_softc *); 76 static void rgephy_reset(struct mii_softc *); 77 static void rgephy_loop(struct mii_softc *); 78 static void rgephy_load_dspcode(struct mii_softc *); 79 80 static const struct mii_phy_funcs rgephy_funcs = { 81 rgephy_service, rgephy_status, rgephy_reset, 82 }; 83 84 static const struct mii_phydesc rgephys[] = { 85 { MII_OUI_xxREALTEK, MII_MODEL_xxREALTEK_RTL8169S, 86 MII_STR_xxREALTEK_RTL8169S }, 87 88 { MII_OUI_REALTEK, MII_MODEL_REALTEK_RTL8169S, 89 MII_STR_REALTEK_RTL8169S }, 90 91 { MII_OUI_REALTEK, MII_MODEL_REALTEK_RTL8251, 92 MII_STR_REALTEK_RTL8251 }, 93 94 { 0, 0, 95 NULL } 96 }; 97 98 static int 99 rgephy_match(device_t parent, cfdata_t match, void *aux) 100 { 101 struct mii_attach_args *ma = aux; 102 103 if (mii_phy_match(ma, rgephys) != NULL) 104 return 10; 105 106 return 0; 107 } 108 109 static void 110 rgephy_attach(device_t parent, device_t self, void *aux) 111 { 112 struct rgephy_softc *rsc = device_private(self); 113 prop_dictionary_t prop = device_properties(self); 114 struct mii_softc *sc = &rsc->mii_sc; 115 struct mii_attach_args *ma = aux; 116 struct mii_data *mii = ma->mii_data; 117 const struct mii_phydesc *mpd; 118 int rev; 119 const char *sep = ""; 120 121 ma = aux; 122 mii = ma->mii_data; 123 124 rev = MII_REV(ma->mii_id2); 125 mpd = mii_phy_match(ma, rgephys); 126 aprint_naive(": Media interface\n"); 127 aprint_normal(": %s, rev. %d\n", mpd->mpd_name, rev); 128 129 sc->mii_dev = self; 130 sc->mii_inst = mii->mii_instance; 131 sc->mii_phy = ma->mii_phyno; 132 sc->mii_mpd_oui = MII_OUI(ma->mii_id1, ma->mii_id2); 133 sc->mii_mpd_model = MII_MODEL(ma->mii_id2); 134 sc->mii_mpd_rev = MII_REV(ma->mii_id2); 135 sc->mii_pdata = mii; 136 sc->mii_flags = mii->mii_flags; 137 sc->mii_anegticks = MII_ANEGTICKS_GIGE; 138 139 sc->mii_funcs = &rgephy_funcs; 140 141 prop_dictionary_get_bool(prop, "no-rx-delay", &rsc->mii_no_rx_delay); 142 143 #define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL) 144 #define PRINT(n) aprint_normal("%s%s", sep, (n)); sep = ", " 145 146 #ifdef __FreeBSD__ 147 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst), 148 BMCR_LOOP|BMCR_S100); 149 #endif 150 151 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask; 152 sc->mii_capabilities &= ~BMSR_ANEG; 153 154 /* 155 * FreeBSD does not check EXSTAT, but instead adds gigabit 156 * media explicitly. Why? 157 */ 158 aprint_normal_dev(self, ""); 159 if (sc->mii_capabilities & BMSR_EXTSTAT) { 160 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); 161 } 162 mii_phy_add_media(sc); 163 164 /* rtl8169S does not report auto-sense; add manually. */ 165 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), MII_NMEDIA); 166 sep =", "; 167 PRINT("auto"); 168 169 #undef ADD 170 #undef PRINT 171 172 rgephy_reset(sc); 173 aprint_normal("\n"); 174 } 175 176 static int 177 rgephy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 178 { 179 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 180 int reg, speed, gig, anar; 181 182 switch (cmd) { 183 case MII_POLLSTAT: 184 /* 185 * If we're not polling our PHY instance, just return. 186 */ 187 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 188 return 0; 189 break; 190 191 case MII_MEDIACHG: 192 /* 193 * If the media indicates a different PHY instance, 194 * isolate ourselves. 195 */ 196 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 197 reg = PHY_READ(sc, MII_BMCR); 198 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO); 199 return 0; 200 } 201 202 /* 203 * If the interface is not up, don't do anything. 204 */ 205 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 206 break; 207 208 rgephy_reset(sc); /* XXX hardware bug work-around */ 209 210 anar = PHY_READ(sc, MII_ANAR); 211 anar &= ~(ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10); 212 213 switch (IFM_SUBTYPE(ife->ifm_media)) { 214 case IFM_AUTO: 215 #ifdef foo 216 /* 217 * If we're already in auto mode, just return. 218 */ 219 if (PHY_READ(sc, MII_BMCR) & BMCR_AUTOEN) 220 return 0; 221 #endif 222 (void)rgephy_mii_phy_auto(sc); 223 break; 224 case IFM_1000_T: 225 speed = BMCR_S1000; 226 goto setit; 227 case IFM_100_TX: 228 speed = BMCR_S100; 229 anar |= ANAR_TX_FD | ANAR_TX; 230 goto setit; 231 case IFM_10_T: 232 speed = BMCR_S10; 233 anar |= ANAR_10_FD | ANAR_10; 234 setit: 235 rgephy_loop(sc); 236 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 237 speed |= BMCR_FDX; 238 gig = GTCR_ADV_1000TFDX; 239 anar &= ~(ANAR_TX | ANAR_10); 240 } else { 241 gig = GTCR_ADV_1000THDX; 242 anar &= ~(ANAR_TX_FD | ANAR_10_FD); 243 } 244 245 if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T) { 246 PHY_WRITE(sc, MII_100T2CR, 0); 247 PHY_WRITE(sc, MII_ANAR, anar); 248 PHY_WRITE(sc, MII_BMCR, speed | 249 BMCR_AUTOEN | BMCR_STARTNEG); 250 break; 251 } 252 253 /* 254 * When setting the link manually, one side must 255 * be the master and the other the slave. However 256 * ifmedia doesn't give us a good way to specify 257 * this, so we fake it by using one of the LINK 258 * flags. If LINK0 is set, we program the PHY to 259 * be a master, otherwise it's a slave. 260 */ 261 if ((mii->mii_ifp->if_flags & IFF_LINK0)) { 262 PHY_WRITE(sc, MII_100T2CR, 263 gig|GTCR_MAN_MS|GTCR_ADV_MS); 264 } else { 265 PHY_WRITE(sc, MII_100T2CR, gig|GTCR_MAN_MS); 266 } 267 PHY_WRITE(sc, MII_BMCR, speed | 268 BMCR_AUTOEN | BMCR_STARTNEG); 269 break; 270 case IFM_NONE: 271 PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN); 272 break; 273 case IFM_100_T4: 274 default: 275 return EINVAL; 276 } 277 break; 278 279 case MII_TICK: 280 /* 281 * If we're not currently selected, just return. 282 */ 283 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 284 return 0; 285 286 /* 287 * Is the interface even up? 288 */ 289 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 290 return 0; 291 292 /* 293 * Only used for autonegotiation. 294 */ 295 if ((IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) && 296 (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T)) { 297 /* 298 * Reset autonegotiation timer to 0 to make sure 299 * the future autonegotiation start with 0. 300 */ 301 sc->mii_ticks = 0; 302 break; 303 } 304 305 /* 306 * Check to see if we have link. If we do, we don't 307 * need to restart the autonegotiation process. Read 308 * the BMSR twice in case it's latched. 309 */ 310 if (sc->mii_mpd_rev >= RGEPHY_8211F) { 311 /* RTL8211F */ 312 reg = PHY_READ(sc, RGEPHY_MII_PHYSR); 313 if (reg & RGEPHY_PHYSR_LINK) { 314 sc->mii_ticks = 0; 315 break; 316 } 317 } else if (sc->mii_mpd_rev >= RGEPHY_8211B) { 318 /* RTL8211B(L) */ 319 reg = PHY_READ(sc, RGEPHY_MII_SSR); 320 if (reg & RGEPHY_SSR_LINK) { 321 sc->mii_ticks = 0; 322 break; 323 } 324 } else { 325 reg = PHY_READ(sc, RTK_GMEDIASTAT); 326 if ((reg & RTK_GMEDIASTAT_LINK) != 0) { 327 sc->mii_ticks = 0; 328 break; 329 } 330 } 331 332 /* Announce link loss right after it happens. */ 333 if (sc->mii_ticks++ == 0) 334 break; 335 336 /* Only retry autonegotiation every mii_anegticks seconds. */ 337 if (sc->mii_ticks <= sc->mii_anegticks) 338 return 0; 339 340 rgephy_mii_phy_auto(sc); 341 break; 342 } 343 344 /* Update the media status. */ 345 rgephy_status(sc); 346 347 /* 348 * Callback if something changed. Note that we need to poke 349 * the DSP on the RealTek PHYs if the media changes. 350 * 351 */ 352 if (sc->mii_media_active != mii->mii_media_active || 353 sc->mii_media_status != mii->mii_media_status || 354 cmd == MII_MEDIACHG) { 355 rgephy_load_dspcode(sc); 356 } 357 mii_phy_update(sc, cmd); 358 return 0; 359 } 360 361 static void 362 rgephy_status(struct mii_softc *sc) 363 { 364 struct mii_data *mii = sc->mii_pdata; 365 int gstat, bmsr, bmcr, physr; 366 uint16_t ssr; 367 368 mii->mii_media_status = IFM_AVALID; 369 mii->mii_media_active = IFM_ETHER; 370 371 if (sc->mii_mpd_rev >= RGEPHY_8211F) { 372 physr = PHY_READ(sc, RGEPHY_MII_PHYSR); 373 if (physr & RGEPHY_PHYSR_LINK) 374 mii->mii_media_status |= IFM_ACTIVE; 375 } else if (sc->mii_mpd_rev >= RGEPHY_8211B) { 376 ssr = PHY_READ(sc, RGEPHY_MII_SSR); 377 if (ssr & RGEPHY_SSR_LINK) 378 mii->mii_media_status |= IFM_ACTIVE; 379 } else { 380 gstat = PHY_READ(sc, RTK_GMEDIASTAT); 381 if ((gstat & RTK_GMEDIASTAT_LINK) != 0) 382 mii->mii_media_status |= IFM_ACTIVE; 383 } 384 385 bmsr = PHY_READ(sc, MII_BMSR); 386 bmcr = PHY_READ(sc, MII_BMCR); 387 388 if ((bmcr & BMCR_ISO) != 0) { 389 mii->mii_media_active |= IFM_NONE; 390 mii->mii_media_status = 0; 391 return; 392 } 393 394 if ((bmcr & BMCR_LOOP) != 0) 395 mii->mii_media_active |= IFM_LOOP; 396 397 if ((bmcr & BMCR_AUTOEN) != 0) { 398 if ((bmsr & BMSR_ACOMP) == 0) { 399 /* Erg, still trying, I guess... */ 400 mii->mii_media_active |= IFM_NONE; 401 return; 402 } 403 } 404 405 if (sc->mii_mpd_rev >= RGEPHY_8211F) { 406 physr = PHY_READ(sc, RGEPHY_MII_PHYSR); 407 switch (__SHIFTOUT(physr, RGEPHY_PHYSR_SPEED)) { 408 case RGEPHY_PHYSR_SPEED_1000: 409 mii->mii_media_active |= IFM_1000_T; 410 break; 411 case RGEPHY_PHYSR_SPEED_100: 412 mii->mii_media_active |= IFM_100_TX; 413 break; 414 case RGEPHY_PHYSR_SPEED_10: 415 mii->mii_media_active |= IFM_10_T; 416 break; 417 default: 418 mii->mii_media_active |= IFM_NONE; 419 break; 420 } 421 if (physr & RGEPHY_PHYSR_DUPLEX) 422 mii->mii_media_active |= mii_phy_flowstatus(sc) | 423 IFM_FDX; 424 else 425 mii->mii_media_active |= IFM_HDX; 426 } else if (sc->mii_mpd_rev >= RGEPHY_8211B) { 427 ssr = PHY_READ(sc, RGEPHY_MII_SSR); 428 switch (ssr & RGEPHY_SSR_SPD_MASK) { 429 case RGEPHY_SSR_S1000: 430 mii->mii_media_active |= IFM_1000_T; 431 break; 432 case RGEPHY_SSR_S100: 433 mii->mii_media_active |= IFM_100_TX; 434 break; 435 case RGEPHY_SSR_S10: 436 mii->mii_media_active |= IFM_10_T; 437 break; 438 default: 439 mii->mii_media_active |= IFM_NONE; 440 break; 441 } 442 if (ssr & RGEPHY_SSR_FDX) 443 mii->mii_media_active |= mii_phy_flowstatus(sc) | 444 IFM_FDX; 445 else 446 mii->mii_media_active |= IFM_HDX; 447 } else { 448 gstat = PHY_READ(sc, RTK_GMEDIASTAT); 449 if ((gstat & RTK_GMEDIASTAT_1000MBPS) != 0) 450 mii->mii_media_active |= IFM_1000_T; 451 else if ((gstat & RTK_GMEDIASTAT_100MBPS) != 0) 452 mii->mii_media_active |= IFM_100_TX; 453 else if ((gstat & RTK_GMEDIASTAT_10MBPS) != 0) 454 mii->mii_media_active |= IFM_10_T; 455 else 456 mii->mii_media_active |= IFM_NONE; 457 if ((gstat & RTK_GMEDIASTAT_FDX) != 0) 458 mii->mii_media_active |= mii_phy_flowstatus(sc) | 459 IFM_FDX; 460 else 461 mii->mii_media_active |= IFM_HDX; 462 } 463 } 464 465 466 static int 467 rgephy_mii_phy_auto(struct mii_softc *mii) 468 { 469 int anar; 470 471 mii->mii_ticks = 0; 472 rgephy_loop(mii); 473 rgephy_reset(mii); 474 475 anar = BMSR_MEDIA_TO_ANAR(mii->mii_capabilities) | ANAR_CSMA; 476 if (mii->mii_flags & MIIF_DOPAUSE) 477 anar |= ANAR_FC | ANAR_PAUSE_ASYM; 478 479 PHY_WRITE(mii, MII_ANAR, anar); 480 DELAY(1000); 481 PHY_WRITE(mii, MII_100T2CR, GTCR_ADV_1000THDX | GTCR_ADV_1000TFDX); 482 DELAY(1000); 483 PHY_WRITE(mii, MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG); 484 DELAY(100); 485 486 return EJUSTRETURN; 487 } 488 489 static void 490 rgephy_loop(struct mii_softc *sc) 491 { 492 uint32_t bmsr; 493 int i; 494 495 if (sc->mii_mpd_model != MII_MODEL_REALTEK_RTL8251 && 496 sc->mii_mpd_rev < RGEPHY_8211B) { 497 PHY_WRITE(sc, MII_BMCR, BMCR_PDOWN); 498 DELAY(1000); 499 } 500 501 for (i = 0; i < 15000; i++) { 502 bmsr = PHY_READ(sc, MII_BMSR); 503 if ((bmsr & BMSR_LINK) == 0) { 504 #if 0 505 device_printf(sc->mii_dev, "looped %d\n", i); 506 #endif 507 break; 508 } 509 DELAY(10); 510 } 511 } 512 513 #define PHY_SETBIT(x, y, z) \ 514 PHY_WRITE(x, y, (PHY_READ(x, y) | (z))) 515 #define PHY_CLRBIT(x, y, z) \ 516 PHY_WRITE(x, y, (PHY_READ(x, y) & ~(z))) 517 518 /* 519 * Initialize RealTek PHY per the datasheet. The DSP in the PHYs of 520 * existing revisions of the 8169S/8110S chips need to be tuned in 521 * order to reliably negotiate a 1000Mbps link. This is only needed 522 * for rev 0 and rev 1 of the PHY. Later versions work without 523 * any fixups. 524 */ 525 static void 526 rgephy_load_dspcode(struct mii_softc *sc) 527 { 528 int val; 529 530 if (sc->mii_mpd_model == MII_MODEL_REALTEK_RTL8251 || 531 sc->mii_mpd_rev >= RGEPHY_8211B) 532 return; 533 534 #if 1 535 PHY_WRITE(sc, 31, 0x0001); 536 PHY_WRITE(sc, 21, 0x1000); 537 PHY_WRITE(sc, 24, 0x65C7); 538 PHY_CLRBIT(sc, 4, 0x0800); 539 val = PHY_READ(sc, 4) & 0xFFF; 540 PHY_WRITE(sc, 4, val); 541 PHY_WRITE(sc, 3, 0x00A1); 542 PHY_WRITE(sc, 2, 0x0008); 543 PHY_WRITE(sc, 1, 0x1020); 544 PHY_WRITE(sc, 0, 0x1000); 545 PHY_SETBIT(sc, 4, 0x0800); 546 PHY_CLRBIT(sc, 4, 0x0800); 547 val = (PHY_READ(sc, 4) & 0xFFF) | 0x7000; 548 PHY_WRITE(sc, 4, val); 549 PHY_WRITE(sc, 3, 0xFF41); 550 PHY_WRITE(sc, 2, 0xDE60); 551 PHY_WRITE(sc, 1, 0x0140); 552 PHY_WRITE(sc, 0, 0x0077); 553 val = (PHY_READ(sc, 4) & 0xFFF) | 0xA000; 554 PHY_WRITE(sc, 4, val); 555 PHY_WRITE(sc, 3, 0xDF01); 556 PHY_WRITE(sc, 2, 0xDF20); 557 PHY_WRITE(sc, 1, 0xFF95); 558 PHY_WRITE(sc, 0, 0xFA00); 559 val = (PHY_READ(sc, 4) & 0xFFF) | 0xB000; 560 PHY_WRITE(sc, 4, val); 561 PHY_WRITE(sc, 3, 0xFF41); 562 PHY_WRITE(sc, 2, 0xDE20); 563 PHY_WRITE(sc, 1, 0x0140); 564 PHY_WRITE(sc, 0, 0x00BB); 565 val = (PHY_READ(sc, 4) & 0xFFF) | 0xF000; 566 PHY_WRITE(sc, 4, val); 567 PHY_WRITE(sc, 3, 0xDF01); 568 PHY_WRITE(sc, 2, 0xDF20); 569 PHY_WRITE(sc, 1, 0xFF95); 570 PHY_WRITE(sc, 0, 0xBF00); 571 PHY_SETBIT(sc, 4, 0x0800); 572 PHY_CLRBIT(sc, 4, 0x0800); 573 PHY_WRITE(sc, 31, 0x0000); 574 #else 575 (void)val; 576 PHY_WRITE(sc, 0x1f, 0x0001); 577 PHY_WRITE(sc, 0x15, 0x1000); 578 PHY_WRITE(sc, 0x18, 0x65c7); 579 PHY_WRITE(sc, 0x04, 0x0000); 580 PHY_WRITE(sc, 0x03, 0x00a1); 581 PHY_WRITE(sc, 0x02, 0x0008); 582 PHY_WRITE(sc, 0x01, 0x1020); 583 PHY_WRITE(sc, 0x00, 0x1000); 584 PHY_WRITE(sc, 0x04, 0x0800); 585 PHY_WRITE(sc, 0x04, 0x0000); 586 PHY_WRITE(sc, 0x04, 0x7000); 587 PHY_WRITE(sc, 0x03, 0xff41); 588 PHY_WRITE(sc, 0x02, 0xde60); 589 PHY_WRITE(sc, 0x01, 0x0140); 590 PHY_WRITE(sc, 0x00, 0x0077); 591 PHY_WRITE(sc, 0x04, 0x7800); 592 PHY_WRITE(sc, 0x04, 0x7000); 593 PHY_WRITE(sc, 0x04, 0xa000); 594 PHY_WRITE(sc, 0x03, 0xdf01); 595 PHY_WRITE(sc, 0x02, 0xdf20); 596 PHY_WRITE(sc, 0x01, 0xff95); 597 PHY_WRITE(sc, 0x00, 0xfa00); 598 PHY_WRITE(sc, 0x04, 0xa800); 599 PHY_WRITE(sc, 0x04, 0xa000); 600 PHY_WRITE(sc, 0x04, 0xb000); 601 PHY_WRITE(sc, 0x0e, 0xff41); 602 PHY_WRITE(sc, 0x02, 0xde20); 603 PHY_WRITE(sc, 0x01, 0x0140); 604 PHY_WRITE(sc, 0x00, 0x00bb); 605 PHY_WRITE(sc, 0x04, 0xb800); 606 PHY_WRITE(sc, 0x04, 0xb000); 607 PHY_WRITE(sc, 0x04, 0xf000); 608 PHY_WRITE(sc, 0x03, 0xdf01); 609 PHY_WRITE(sc, 0x02, 0xdf20); 610 PHY_WRITE(sc, 0x01, 0xff95); 611 PHY_WRITE(sc, 0x00, 0xbf00); 612 PHY_WRITE(sc, 0x04, 0xf800); 613 PHY_WRITE(sc, 0x04, 0xf000); 614 PHY_WRITE(sc, 0x04, 0x0000); 615 PHY_WRITE(sc, 0x1f, 0x0000); 616 PHY_WRITE(sc, 0x0b, 0x0000); 617 618 #endif 619 620 DELAY(40); 621 } 622 623 static void 624 rgephy_reset(struct mii_softc *sc) 625 { 626 struct rgephy_softc *rsc = (struct rgephy_softc *)sc; 627 uint16_t ssr, phycr1; 628 629 mii_phy_reset(sc); 630 DELAY(1000); 631 632 if (sc->mii_mpd_model != MII_MODEL_REALTEK_RTL8251 && 633 sc->mii_mpd_rev < RGEPHY_8211B) { 634 rgephy_load_dspcode(sc); 635 } else if (sc->mii_mpd_rev == RGEPHY_8211C) { 636 /* RTL8211C(L) */ 637 ssr = PHY_READ(sc, RGEPHY_MII_SSR); 638 if ((ssr & RGEPHY_SSR_ALDPS) != 0) { 639 ssr &= ~RGEPHY_SSR_ALDPS; 640 PHY_WRITE(sc, RGEPHY_MII_SSR, ssr); 641 } 642 } else if (sc->mii_mpd_rev == RGEPHY_8211E) { 643 /* RTL8211E */ 644 if (rsc->mii_no_rx_delay) { 645 /* Disable RX internal delay (undocumented) */ 646 PHY_WRITE(sc, 0x1f, 0x0007); 647 PHY_WRITE(sc, 0x1e, 0x00a4); 648 PHY_WRITE(sc, 0x1c, 0xb591); 649 PHY_WRITE(sc, 0x1f, 0x0000); 650 } 651 } else if (sc->mii_mpd_rev == RGEPHY_8211F) { 652 /* RTL8211F */ 653 phycr1 = PHY_READ(sc, RGEPHY_MII_PHYCR1); 654 phycr1 &= ~RGEPHY_PHYCR1_MDI_MMCE; 655 phycr1 &= ~RGEPHY_PHYCR1_ALDPS_EN; 656 PHY_WRITE(sc, RGEPHY_MII_PHYCR1, phycr1); 657 } else { 658 PHY_WRITE(sc, 0x1F, 0x0000); 659 PHY_WRITE(sc, 0x0e, 0x0000); 660 } 661 662 /* Reset capabilities */ 663 /* Step1: write our capability */ 664 /* 10/100 capability */ 665 PHY_WRITE(sc, MII_ANAR, 666 ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 667 /* 1000 capability */ 668 PHY_WRITE(sc, MII_100T2CR, GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX); 669 670 /* Step2: Restart NWay */ 671 /* NWay enable and Restart NWay */ 672 PHY_WRITE(sc, MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 673 674 if (sc->mii_mpd_rev == RGEPHY_8211F) { 675 /* RTL8211F */ 676 delay(10000); 677 /* disable EEE */ 678 PHY_WRITE(sc, RGEPHY_MII_MACR, 0x0007); 679 PHY_WRITE(sc, RGEPHY_MII_MAADR, 0x003c); 680 PHY_WRITE(sc, RGEPHY_MII_MACR, 0x4007); 681 PHY_WRITE(sc, RGEPHY_MII_MAADR, 0x0000); 682 } 683 } 684
Indexes created Thu Oct 02 10:09:58 GMT 2025