rgephy.c revision 1.44
1 /* $NetBSD: rgephy.c,v 1.44 2018/06/27 07:51:36 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 2003 5 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: rgephy.c,v 1.44 2018/06/27 07:51:36 msaitoh Exp $"); 37 38 39 /* 40 * Driver for the RealTek 8169S/8110S internal 10/100/1000 PHY. 41 */ 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/kernel.h> 46 #include <sys/device.h> 47 #include <sys/socket.h> 48 49 50 #include <net/if.h> 51 #include <net/if_media.h> 52 53 #include <dev/mii/mii.h> 54 #include <dev/mii/mdio.h> 55 #include <dev/mii/miivar.h> 56 #include <dev/mii/miidevs.h> 57 58 #include <dev/mii/rgephyreg.h> 59 60 #include <dev/ic/rtl81x9reg.h> 61 62 static int rgephy_match(device_t, cfdata_t, void *); 63 static void rgephy_attach(device_t, device_t, void *); 64 65 struct rgephy_softc { 66 struct mii_softc mii_sc; 67 bool mii_no_rx_delay; 68 }; 69 70 CFATTACH_DECL_NEW(rgephy, sizeof(struct rgephy_softc), 71 rgephy_match, rgephy_attach, mii_phy_detach, mii_phy_activate); 72 73 74 static int rgephy_service(struct mii_softc *, struct mii_data *, int); 75 static void rgephy_status(struct mii_softc *); 76 static int rgephy_mii_phy_auto(struct mii_softc *); 77 static void rgephy_reset(struct mii_softc *); 78 static void rgephy_loop(struct mii_softc *); 79 static void rgephy_load_dspcode(struct mii_softc *); 80 81 static const struct mii_phy_funcs rgephy_funcs = { 82 rgephy_service, rgephy_status, rgephy_reset, 83 }; 84 85 static const struct mii_phydesc rgephys[] = { 86 { MII_OUI_xxREALTEK, MII_MODEL_xxREALTEK_RTL8169S, 87 MII_STR_xxREALTEK_RTL8169S }, 88 89 { MII_OUI_REALTEK, MII_MODEL_REALTEK_RTL8169S, 90 MII_STR_REALTEK_RTL8169S }, 91 92 { MII_OUI_REALTEK, MII_MODEL_REALTEK_RTL8251, 93 MII_STR_REALTEK_RTL8251 }, 94 95 { 0, 0, 96 NULL } 97 }; 98 99 static int 100 rgephy_match(device_t parent, cfdata_t match, void *aux) 101 { 102 struct mii_attach_args *ma = aux; 103 104 if (mii_phy_match(ma, rgephys) != NULL) 105 return 10; 106 107 return 0; 108 } 109 110 static void 111 rgephy_attach(device_t parent, device_t self, void *aux) 112 { 113 struct rgephy_softc *rsc = device_private(self); 114 prop_dictionary_t prop = device_properties(self); 115 struct mii_softc *sc = &rsc->mii_sc; 116 struct mii_attach_args *ma = aux; 117 struct mii_data *mii = ma->mii_data; 118 const struct mii_phydesc *mpd; 119 int rev; 120 const char *sep = ""; 121 122 ma = aux; 123 mii = ma->mii_data; 124 125 rev = MII_REV(ma->mii_id2); 126 mpd = mii_phy_match(ma, rgephys); 127 aprint_naive(": Media interface\n"); 128 aprint_normal(": %s, rev. %d\n", mpd->mpd_name, rev); 129 130 sc->mii_dev = self; 131 sc->mii_inst = mii->mii_instance; 132 sc->mii_phy = ma->mii_phyno; 133 sc->mii_mpd_oui = MII_OUI(ma->mii_id1, ma->mii_id2); 134 sc->mii_mpd_model = MII_MODEL(ma->mii_id2); 135 sc->mii_mpd_rev = MII_REV(ma->mii_id2); 136 sc->mii_pdata = mii; 137 sc->mii_flags = mii->mii_flags; 138 sc->mii_anegticks = MII_ANEGTICKS_GIGE; 139 140 sc->mii_funcs = &rgephy_funcs; 141 142 prop_dictionary_get_bool(prop, "no-rx-delay", &rsc->mii_no_rx_delay); 143 144 #define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL) 145 #define PRINT(n) aprint_normal("%s%s", sep, (n)); sep = ", " 146 147 #ifdef __FreeBSD__ 148 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst), 149 BMCR_LOOP|BMCR_S100); 150 #endif 151 152 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask; 153 sc->mii_capabilities &= ~BMSR_ANEG; 154 155 /* 156 * FreeBSD does not check EXSTAT, but instead adds gigabit 157 * media explicitly. Why? 158 */ 159 aprint_normal_dev(self, ""); 160 if (sc->mii_capabilities & BMSR_EXTSTAT) { 161 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); 162 } 163 mii_phy_add_media(sc); 164 165 /* rtl8169S does not report auto-sense; add manually. */ 166 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), MII_NMEDIA); 167 sep =", "; 168 PRINT("auto"); 169 170 #undef ADD 171 #undef PRINT 172 173 rgephy_reset(sc); 174 aprint_normal("\n"); 175 } 176 177 static int 178 rgephy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 179 { 180 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 181 int reg, speed, gig, anar; 182 183 switch (cmd) { 184 case MII_POLLSTAT: 185 /* 186 * If we're not polling our PHY instance, just return. 187 */ 188 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 189 return 0; 190 break; 191 192 case MII_MEDIACHG: 193 /* 194 * If the media indicates a different PHY instance, 195 * isolate ourselves. 196 */ 197 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 198 reg = PHY_READ(sc, MII_BMCR); 199 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO); 200 return 0; 201 } 202 203 /* 204 * If the interface is not up, don't do anything. 205 */ 206 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 207 break; 208 209 rgephy_reset(sc); /* XXX hardware bug work-around */ 210 211 anar = PHY_READ(sc, MII_ANAR); 212 anar &= ~(ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10); 213 214 switch (IFM_SUBTYPE(ife->ifm_media)) { 215 case IFM_AUTO: 216 #ifdef foo 217 /* 218 * If we're already in auto mode, just return. 219 */ 220 if (PHY_READ(sc, MII_BMCR) & BMCR_AUTOEN) 221 return 0; 222 #endif 223 (void)rgephy_mii_phy_auto(sc); 224 break; 225 case IFM_1000_T: 226 speed = BMCR_S1000; 227 goto setit; 228 case IFM_100_TX: 229 speed = BMCR_S100; 230 anar |= ANAR_TX_FD | ANAR_TX; 231 goto setit; 232 case IFM_10_T: 233 speed = BMCR_S10; 234 anar |= ANAR_10_FD | ANAR_10; 235 setit: 236 rgephy_loop(sc); 237 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 238 speed |= BMCR_FDX; 239 gig = GTCR_ADV_1000TFDX; 240 anar &= ~(ANAR_TX | ANAR_10); 241 } else { 242 gig = GTCR_ADV_1000THDX; 243 anar &= ~(ANAR_TX_FD | ANAR_10_FD); 244 } 245 246 if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T) { 247 PHY_WRITE(sc, MII_100T2CR, 0); 248 PHY_WRITE(sc, MII_ANAR, anar); 249 PHY_WRITE(sc, MII_BMCR, speed | 250 BMCR_AUTOEN | BMCR_STARTNEG); 251 break; 252 } 253 254 /* 255 * When setting the link manually, one side must 256 * be the master and the other the slave. However 257 * ifmedia doesn't give us a good way to specify 258 * this, so we fake it by using one of the LINK 259 * flags. If LINK0 is set, we program the PHY to 260 * be a master, otherwise it's a slave. 261 */ 262 if ((mii->mii_ifp->if_flags & IFF_LINK0)) { 263 PHY_WRITE(sc, MII_100T2CR, 264 gig|GTCR_MAN_MS|GTCR_ADV_MS); 265 } else { 266 PHY_WRITE(sc, MII_100T2CR, gig|GTCR_MAN_MS); 267 } 268 PHY_WRITE(sc, MII_BMCR, speed | 269 BMCR_AUTOEN | BMCR_STARTNEG); 270 break; 271 case IFM_NONE: 272 PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN); 273 break; 274 case IFM_100_T4: 275 default: 276 return EINVAL; 277 } 278 break; 279 280 case MII_TICK: 281 /* 282 * If we're not currently selected, just return. 283 */ 284 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 285 return 0; 286 287 /* 288 * Is the interface even up? 289 */ 290 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 291 return 0; 292 293 /* 294 * Only used for autonegotiation. 295 */ 296 if ((IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) && 297 (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T)) { 298 /* 299 * Reset autonegotiation timer to 0 to make sure 300 * the future autonegotiation start with 0. 301 */ 302 sc->mii_ticks = 0; 303 break; 304 } 305 306 /* 307 * Check to see if we have link. If we do, we don't 308 * need to restart the autonegotiation process. Read 309 * the BMSR twice in case it's latched. 310 */ 311 if (sc->mii_mpd_rev >= RGEPHY_8211F) { 312 /* RTL8211F */ 313 reg = PHY_READ(sc, RGEPHY_MII_PHYSR); 314 if (reg & RGEPHY_PHYSR_LINK) { 315 sc->mii_ticks = 0; 316 break; 317 } 318 } else if (sc->mii_mpd_rev >= RGEPHY_8211B) { 319 /* RTL8211B(L) */ 320 reg = PHY_READ(sc, RGEPHY_MII_SSR); 321 if (reg & RGEPHY_SSR_LINK) { 322 sc->mii_ticks = 0; 323 break; 324 } 325 } else { 326 reg = PHY_READ(sc, RTK_GMEDIASTAT); 327 if ((reg & RTK_GMEDIASTAT_LINK) != 0) { 328 sc->mii_ticks = 0; 329 break; 330 } 331 } 332 333 /* Announce link loss right after it happens. */ 334 if (sc->mii_ticks++ == 0) 335 break; 336 337 /* Only retry autonegotiation every mii_anegticks seconds. */ 338 if (sc->mii_ticks <= sc->mii_anegticks) 339 return 0; 340 341 rgephy_mii_phy_auto(sc); 342 break; 343 } 344 345 /* Update the media status. */ 346 rgephy_status(sc); 347 348 /* 349 * Callback if something changed. Note that we need to poke 350 * the DSP on the RealTek PHYs if the media changes. 351 * 352 */ 353 if (sc->mii_media_active != mii->mii_media_active || 354 sc->mii_media_status != mii->mii_media_status || 355 cmd == MII_MEDIACHG) { 356 rgephy_load_dspcode(sc); 357 } 358 mii_phy_update(sc, cmd); 359 return 0; 360 } 361 362 static void 363 rgephy_status(struct mii_softc *sc) 364 { 365 struct mii_data *mii = sc->mii_pdata; 366 int gstat, bmsr, bmcr, physr; 367 uint16_t ssr; 368 369 mii->mii_media_status = IFM_AVALID; 370 mii->mii_media_active = IFM_ETHER; 371 372 if (sc->mii_mpd_rev >= RGEPHY_8211F) { 373 physr = PHY_READ(sc, RGEPHY_MII_PHYSR); 374 if (physr & RGEPHY_PHYSR_LINK) 375 mii->mii_media_status |= IFM_ACTIVE; 376 } else if (sc->mii_mpd_rev >= RGEPHY_8211B) { 377 ssr = PHY_READ(sc, RGEPHY_MII_SSR); 378 if (ssr & RGEPHY_SSR_LINK) 379 mii->mii_media_status |= IFM_ACTIVE; 380 } else { 381 gstat = PHY_READ(sc, RTK_GMEDIASTAT); 382 if ((gstat & RTK_GMEDIASTAT_LINK) != 0) 383 mii->mii_media_status |= IFM_ACTIVE; 384 } 385 386 bmsr = PHY_READ(sc, MII_BMSR); 387 bmcr = PHY_READ(sc, MII_BMCR); 388 389 if ((bmcr & BMCR_ISO) != 0) { 390 mii->mii_media_active |= IFM_NONE; 391 mii->mii_media_status = 0; 392 return; 393 } 394 395 if ((bmcr & BMCR_LOOP) != 0) 396 mii->mii_media_active |= IFM_LOOP; 397 398 if ((bmcr & BMCR_AUTOEN) != 0) { 399 if ((bmsr & BMSR_ACOMP) == 0) { 400 /* Erg, still trying, I guess... */ 401 mii->mii_media_active |= IFM_NONE; 402 return; 403 } 404 } 405 406 if (sc->mii_mpd_rev >= RGEPHY_8211F) { 407 physr = PHY_READ(sc, RGEPHY_MII_PHYSR); 408 switch (__SHIFTOUT(physr, RGEPHY_PHYSR_SPEED)) { 409 case RGEPHY_PHYSR_SPEED_1000: 410 mii->mii_media_active |= IFM_1000_T; 411 break; 412 case RGEPHY_PHYSR_SPEED_100: 413 mii->mii_media_active |= IFM_100_TX; 414 break; 415 case RGEPHY_PHYSR_SPEED_10: 416 mii->mii_media_active |= IFM_10_T; 417 break; 418 default: 419 mii->mii_media_active |= IFM_NONE; 420 break; 421 } 422 if (physr & RGEPHY_PHYSR_DUPLEX) 423 mii->mii_media_active |= mii_phy_flowstatus(sc) | 424 IFM_FDX; 425 else 426 mii->mii_media_active |= IFM_HDX; 427 } else if (sc->mii_mpd_rev >= RGEPHY_8211B) { 428 ssr = PHY_READ(sc, RGEPHY_MII_SSR); 429 switch (ssr & RGEPHY_SSR_SPD_MASK) { 430 case RGEPHY_SSR_S1000: 431 mii->mii_media_active |= IFM_1000_T; 432 break; 433 case RGEPHY_SSR_S100: 434 mii->mii_media_active |= IFM_100_TX; 435 break; 436 case RGEPHY_SSR_S10: 437 mii->mii_media_active |= IFM_10_T; 438 break; 439 default: 440 mii->mii_media_active |= IFM_NONE; 441 break; 442 } 443 if (ssr & RGEPHY_SSR_FDX) 444 mii->mii_media_active |= mii_phy_flowstatus(sc) | 445 IFM_FDX; 446 else 447 mii->mii_media_active |= IFM_HDX; 448 } else { 449 gstat = PHY_READ(sc, RTK_GMEDIASTAT); 450 if ((gstat & RTK_GMEDIASTAT_1000MBPS) != 0) 451 mii->mii_media_active |= IFM_1000_T; 452 else if ((gstat & RTK_GMEDIASTAT_100MBPS) != 0) 453 mii->mii_media_active |= IFM_100_TX; 454 else if ((gstat & RTK_GMEDIASTAT_10MBPS) != 0) 455 mii->mii_media_active |= IFM_10_T; 456 else 457 mii->mii_media_active |= IFM_NONE; 458 if ((gstat & RTK_GMEDIASTAT_FDX) != 0) 459 mii->mii_media_active |= mii_phy_flowstatus(sc) | 460 IFM_FDX; 461 else 462 mii->mii_media_active |= IFM_HDX; 463 } 464 } 465 466 467 static int 468 rgephy_mii_phy_auto(struct mii_softc *mii) 469 { 470 int anar; 471 472 mii->mii_ticks = 0; 473 rgephy_loop(mii); 474 rgephy_reset(mii); 475 476 anar = BMSR_MEDIA_TO_ANAR(mii->mii_capabilities) | ANAR_CSMA; 477 if (mii->mii_flags & MIIF_DOPAUSE) 478 anar |= ANAR_FC | ANAR_PAUSE_ASYM; 479 480 PHY_WRITE(mii, MII_ANAR, anar); 481 DELAY(1000); 482 PHY_WRITE(mii, MII_100T2CR, GTCR_ADV_1000THDX | GTCR_ADV_1000TFDX); 483 DELAY(1000); 484 PHY_WRITE(mii, MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG); 485 DELAY(100); 486 487 return EJUSTRETURN; 488 } 489 490 static void 491 rgephy_loop(struct mii_softc *sc) 492 { 493 uint32_t bmsr; 494 int i; 495 496 if (sc->mii_mpd_model != MII_MODEL_REALTEK_RTL8251 && 497 sc->mii_mpd_rev < RGEPHY_8211B) { 498 PHY_WRITE(sc, MII_BMCR, BMCR_PDOWN); 499 DELAY(1000); 500 } 501 502 for (i = 0; i < 15000; i++) { 503 bmsr = PHY_READ(sc, MII_BMSR); 504 if ((bmsr & BMSR_LINK) == 0) { 505 #if 0 506 device_printf(sc->mii_dev, "looped %d\n", i); 507 #endif 508 break; 509 } 510 DELAY(10); 511 } 512 } 513 514 #define PHY_SETBIT(x, y, z) \ 515 PHY_WRITE(x, y, (PHY_READ(x, y) | (z))) 516 #define PHY_CLRBIT(x, y, z) \ 517 PHY_WRITE(x, y, (PHY_READ(x, y) & ~(z))) 518 519 /* 520 * Initialize RealTek PHY per the datasheet. The DSP in the PHYs of 521 * existing revisions of the 8169S/8110S chips need to be tuned in 522 * order to reliably negotiate a 1000Mbps link. This is only needed 523 * for rev 0 and rev 1 of the PHY. Later versions work without 524 * any fixups. 525 */ 526 static void 527 rgephy_load_dspcode(struct mii_softc *sc) 528 { 529 int val; 530 531 if (sc->mii_mpd_model == MII_MODEL_REALTEK_RTL8251 || 532 sc->mii_mpd_rev >= RGEPHY_8211B) 533 return; 534 535 #if 1 536 PHY_WRITE(sc, 31, 0x0001); 537 PHY_WRITE(sc, 21, 0x1000); 538 PHY_WRITE(sc, 24, 0x65C7); 539 PHY_CLRBIT(sc, 4, 0x0800); 540 val = PHY_READ(sc, 4) & 0xFFF; 541 PHY_WRITE(sc, 4, val); 542 PHY_WRITE(sc, 3, 0x00A1); 543 PHY_WRITE(sc, 2, 0x0008); 544 PHY_WRITE(sc, 1, 0x1020); 545 PHY_WRITE(sc, 0, 0x1000); 546 PHY_SETBIT(sc, 4, 0x0800); 547 PHY_CLRBIT(sc, 4, 0x0800); 548 val = (PHY_READ(sc, 4) & 0xFFF) | 0x7000; 549 PHY_WRITE(sc, 4, val); 550 PHY_WRITE(sc, 3, 0xFF41); 551 PHY_WRITE(sc, 2, 0xDE60); 552 PHY_WRITE(sc, 1, 0x0140); 553 PHY_WRITE(sc, 0, 0x0077); 554 val = (PHY_READ(sc, 4) & 0xFFF) | 0xA000; 555 PHY_WRITE(sc, 4, val); 556 PHY_WRITE(sc, 3, 0xDF01); 557 PHY_WRITE(sc, 2, 0xDF20); 558 PHY_WRITE(sc, 1, 0xFF95); 559 PHY_WRITE(sc, 0, 0xFA00); 560 val = (PHY_READ(sc, 4) & 0xFFF) | 0xB000; 561 PHY_WRITE(sc, 4, val); 562 PHY_WRITE(sc, 3, 0xFF41); 563 PHY_WRITE(sc, 2, 0xDE20); 564 PHY_WRITE(sc, 1, 0x0140); 565 PHY_WRITE(sc, 0, 0x00BB); 566 val = (PHY_READ(sc, 4) & 0xFFF) | 0xF000; 567 PHY_WRITE(sc, 4, val); 568 PHY_WRITE(sc, 3, 0xDF01); 569 PHY_WRITE(sc, 2, 0xDF20); 570 PHY_WRITE(sc, 1, 0xFF95); 571 PHY_WRITE(sc, 0, 0xBF00); 572 PHY_SETBIT(sc, 4, 0x0800); 573 PHY_CLRBIT(sc, 4, 0x0800); 574 PHY_WRITE(sc, 31, 0x0000); 575 #else 576 (void)val; 577 PHY_WRITE(sc, 0x1f, 0x0001); 578 PHY_WRITE(sc, 0x15, 0x1000); 579 PHY_WRITE(sc, 0x18, 0x65c7); 580 PHY_WRITE(sc, 0x04, 0x0000); 581 PHY_WRITE(sc, 0x03, 0x00a1); 582 PHY_WRITE(sc, 0x02, 0x0008); 583 PHY_WRITE(sc, 0x01, 0x1020); 584 PHY_WRITE(sc, 0x00, 0x1000); 585 PHY_WRITE(sc, 0x04, 0x0800); 586 PHY_WRITE(sc, 0x04, 0x0000); 587 PHY_WRITE(sc, 0x04, 0x7000); 588 PHY_WRITE(sc, 0x03, 0xff41); 589 PHY_WRITE(sc, 0x02, 0xde60); 590 PHY_WRITE(sc, 0x01, 0x0140); 591 PHY_WRITE(sc, 0x00, 0x0077); 592 PHY_WRITE(sc, 0x04, 0x7800); 593 PHY_WRITE(sc, 0x04, 0x7000); 594 PHY_WRITE(sc, 0x04, 0xa000); 595 PHY_WRITE(sc, 0x03, 0xdf01); 596 PHY_WRITE(sc, 0x02, 0xdf20); 597 PHY_WRITE(sc, 0x01, 0xff95); 598 PHY_WRITE(sc, 0x00, 0xfa00); 599 PHY_WRITE(sc, 0x04, 0xa800); 600 PHY_WRITE(sc, 0x04, 0xa000); 601 PHY_WRITE(sc, 0x04, 0xb000); 602 PHY_WRITE(sc, 0x0e, 0xff41); 603 PHY_WRITE(sc, 0x02, 0xde20); 604 PHY_WRITE(sc, 0x01, 0x0140); 605 PHY_WRITE(sc, 0x00, 0x00bb); 606 PHY_WRITE(sc, 0x04, 0xb800); 607 PHY_WRITE(sc, 0x04, 0xb000); 608 PHY_WRITE(sc, 0x04, 0xf000); 609 PHY_WRITE(sc, 0x03, 0xdf01); 610 PHY_WRITE(sc, 0x02, 0xdf20); 611 PHY_WRITE(sc, 0x01, 0xff95); 612 PHY_WRITE(sc, 0x00, 0xbf00); 613 PHY_WRITE(sc, 0x04, 0xf800); 614 PHY_WRITE(sc, 0x04, 0xf000); 615 PHY_WRITE(sc, 0x04, 0x0000); 616 PHY_WRITE(sc, 0x1f, 0x0000); 617 PHY_WRITE(sc, 0x0b, 0x0000); 618 619 #endif 620 621 DELAY(40); 622 } 623 624 static void 625 rgephy_reset(struct mii_softc *sc) 626 { 627 struct rgephy_softc *rsc = (struct rgephy_softc *)sc; 628 uint16_t ssr, phycr1; 629 630 mii_phy_reset(sc); 631 DELAY(1000); 632 633 if (sc->mii_mpd_model != MII_MODEL_REALTEK_RTL8251 && 634 sc->mii_mpd_rev < RGEPHY_8211B) { 635 rgephy_load_dspcode(sc); 636 } else if (sc->mii_mpd_rev == RGEPHY_8211C) { 637 /* RTL8211C(L) */ 638 ssr = PHY_READ(sc, RGEPHY_MII_SSR); 639 if ((ssr & RGEPHY_SSR_ALDPS) != 0) { 640 ssr &= ~RGEPHY_SSR_ALDPS; 641 PHY_WRITE(sc, RGEPHY_MII_SSR, ssr); 642 } 643 } else if (sc->mii_mpd_rev == RGEPHY_8211E) { 644 /* RTL8211E */ 645 if (rsc->mii_no_rx_delay) { 646 /* Disable RX internal delay (undocumented) */ 647 PHY_WRITE(sc, 0x1f, 0x0007); 648 PHY_WRITE(sc, 0x1e, 0x00a4); 649 PHY_WRITE(sc, 0x1c, 0xb591); 650 PHY_WRITE(sc, 0x1f, 0x0000); 651 } 652 } else if (sc->mii_mpd_rev == RGEPHY_8211F) { 653 /* RTL8211F */ 654 phycr1 = PHY_READ(sc, RGEPHY_MII_PHYCR1); 655 phycr1 &= ~RGEPHY_PHYCR1_MDI_MMCE; 656 phycr1 &= ~RGEPHY_PHYCR1_ALDPS_EN; 657 PHY_WRITE(sc, RGEPHY_MII_PHYCR1, phycr1); 658 } else { 659 PHY_WRITE(sc, 0x1F, 0x0000); 660 PHY_WRITE(sc, 0x0e, 0x0000); 661 } 662 663 /* Reset capabilities */ 664 /* Step1: write our capability */ 665 /* 10/100 capability */ 666 PHY_WRITE(sc, MII_ANAR, 667 ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 668 /* 1000 capability */ 669 PHY_WRITE(sc, MII_100T2CR, GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX); 670 671 /* Step2: Restart NWay */ 672 /* NWay enable and Restart NWay */ 673 PHY_WRITE(sc, MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 674 675 if (sc->mii_mpd_rev == RGEPHY_8211F) { 676 /* RTL8211F */ 677 delay(10000); 678 /* disable EEE */ 679 PHY_WRITE(sc, MII_MMDACR, MMDACR_FN_ADDRESS | MDIO_MMD_AN); 680 PHY_WRITE(sc, MII_MMDAADR, MDIO_AN_EEEADVERT); 681 PHY_WRITE(sc, MII_MMDACR, MMDACR_FN_DATANPI | MDIO_MMD_AN); 682 PHY_WRITE(sc, MII_MMDAADR, 0x0000); 683 } 684 } 685
Indexes created Thu Oct 02 10:09:58 GMT 2025