rgephy.c revision 1.46
1 /* $NetBSD: rgephy.c,v 1.46 2019/01/22 03:42:27 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 2003 5 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: rgephy.c,v 1.46 2019/01/22 03:42:27 msaitoh Exp $"); 37 38 39 /* 40 * Driver for the RealTek 8169S/8110S internal 10/100/1000 PHY. 41 */ 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/kernel.h> 46 #include <sys/device.h> 47 #include <sys/socket.h> 48 49 50 #include <net/if.h> 51 #include <net/if_media.h> 52 53 #include <dev/mii/mii.h> 54 #include <dev/mii/mdio.h> 55 #include <dev/mii/miivar.h> 56 #include <dev/mii/miidevs.h> 57 58 #include <dev/mii/rgephyreg.h> 59 60 #include <dev/ic/rtl81x9reg.h> 61 62 static int rgephy_match(device_t, cfdata_t, void *); 63 static void rgephy_attach(device_t, device_t, void *); 64 65 struct rgephy_softc { 66 struct mii_softc mii_sc; 67 bool mii_no_rx_delay; 68 }; 69 70 CFATTACH_DECL_NEW(rgephy, sizeof(struct rgephy_softc), 71 rgephy_match, rgephy_attach, mii_phy_detach, mii_phy_activate); 72 73 74 static int rgephy_service(struct mii_softc *, struct mii_data *, int); 75 static void rgephy_status(struct mii_softc *); 76 static int rgephy_mii_phy_auto(struct mii_softc *); 77 static void rgephy_reset(struct mii_softc *); 78 static void rgephy_loop(struct mii_softc *); 79 static void rgephy_load_dspcode(struct mii_softc *); 80 81 static const struct mii_phy_funcs rgephy_funcs = { 82 rgephy_service, rgephy_status, rgephy_reset, 83 }; 84 85 static const struct mii_phydesc rgephys[] = { 86 { MII_OUI_xxREALTEK, MII_MODEL_xxREALTEK_RTL8169S, 87 MII_STR_xxREALTEK_RTL8169S }, 88 89 { MII_OUI_REALTEK, MII_MODEL_REALTEK_RTL8169S, 90 MII_STR_REALTEK_RTL8169S }, 91 92 { MII_OUI_REALTEK, MII_MODEL_REALTEK_RTL8251, 93 MII_STR_REALTEK_RTL8251 }, 94 95 { 0, 0, 96 NULL } 97 }; 98 99 static int 100 rgephy_match(device_t parent, cfdata_t match, void *aux) 101 { 102 struct mii_attach_args *ma = aux; 103 104 if (mii_phy_match(ma, rgephys) != NULL) 105 return 10; 106 107 return 0; 108 } 109 110 static void 111 rgephy_attach(device_t parent, device_t self, void *aux) 112 { 113 struct rgephy_softc *rsc = device_private(self); 114 prop_dictionary_t prop = device_properties(self); 115 struct mii_softc *sc = &rsc->mii_sc; 116 struct mii_attach_args *ma = aux; 117 struct mii_data *mii = ma->mii_data; 118 const struct mii_phydesc *mpd; 119 int rev; 120 const char *sep = ""; 121 122 ma = aux; 123 mii = ma->mii_data; 124 125 rev = MII_REV(ma->mii_id2); 126 mpd = mii_phy_match(ma, rgephys); 127 aprint_naive(": Media interface\n"); 128 aprint_normal(": %s, rev. %d\n", mpd->mpd_name, rev); 129 130 sc->mii_dev = self; 131 sc->mii_inst = mii->mii_instance; 132 sc->mii_phy = ma->mii_phyno; 133 sc->mii_mpd_oui = MII_OUI(ma->mii_id1, ma->mii_id2); 134 sc->mii_mpd_model = MII_MODEL(ma->mii_id2); 135 sc->mii_mpd_rev = MII_REV(ma->mii_id2); 136 sc->mii_pdata = mii; 137 sc->mii_flags = ma->mii_flags; 138 sc->mii_anegticks = MII_ANEGTICKS_GIGE; 139 140 sc->mii_funcs = &rgephy_funcs; 141 142 prop_dictionary_get_bool(prop, "no-rx-delay", &rsc->mii_no_rx_delay); 143 144 #define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL) 145 #define PRINT(n) aprint_normal("%s%s", sep, (n)); sep = ", " 146 147 #ifdef __FreeBSD__ 148 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst), 149 BMCR_LOOP|BMCR_S100); 150 #endif 151 152 PHY_READ(sc, MII_BMSR, &sc->mii_capabilities); 153 sc->mii_capabilities &= ma->mii_capmask; 154 sc->mii_capabilities &= ~BMSR_ANEG; 155 156 /* 157 * FreeBSD does not check EXSTAT, but instead adds gigabit 158 * media explicitly. Why? 159 */ 160 aprint_normal_dev(self, ""); 161 if (sc->mii_capabilities & BMSR_EXTSTAT) 162 PHY_READ(sc, MII_EXTSR, &sc->mii_extcapabilities); 163 164 mii_phy_add_media(sc); 165 166 /* rtl8169S does not report auto-sense; add manually. */ 167 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), MII_NMEDIA); 168 sep =", "; 169 PRINT("auto"); 170 171 #undef ADD 172 #undef PRINT 173 174 rgephy_reset(sc); 175 aprint_normal("\n"); 176 } 177 178 static int 179 rgephy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 180 { 181 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 182 uint16_t reg, speed, gig, anar; 183 184 switch (cmd) { 185 case MII_POLLSTAT: 186 /* 187 * If we're not polling our PHY instance, just return. 188 */ 189 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 190 return 0; 191 break; 192 193 case MII_MEDIACHG: 194 /* 195 * If the media indicates a different PHY instance, 196 * isolate ourselves. 197 */ 198 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 199 PHY_READ(sc, MII_BMCR, ®); 200 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO); 201 return 0; 202 } 203 204 /* 205 * If the interface is not up, don't do anything. 206 */ 207 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 208 break; 209 210 rgephy_reset(sc); /* XXX hardware bug work-around */ 211 212 PHY_READ(sc, MII_ANAR, &anar); 213 anar &= ~(ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10); 214 215 switch (IFM_SUBTYPE(ife->ifm_media)) { 216 case IFM_AUTO: 217 #ifdef foo 218 /* 219 * If we're already in auto mode, just return. 220 */ 221 PHY_READ(sc, MII_BMCR, ®); 222 if (reg & BMCR_AUTOEN) 223 return 0; 224 #endif 225 (void)rgephy_mii_phy_auto(sc); 226 break; 227 case IFM_1000_T: 228 speed = BMCR_S1000; 229 goto setit; 230 case IFM_100_TX: 231 speed = BMCR_S100; 232 anar |= ANAR_TX_FD | ANAR_TX; 233 goto setit; 234 case IFM_10_T: 235 speed = BMCR_S10; 236 anar |= ANAR_10_FD | ANAR_10; 237 setit: 238 rgephy_loop(sc); 239 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 240 speed |= BMCR_FDX; 241 gig = GTCR_ADV_1000TFDX; 242 anar &= ~(ANAR_TX | ANAR_10); 243 } else { 244 gig = GTCR_ADV_1000THDX; 245 anar &= ~(ANAR_TX_FD | ANAR_10_FD); 246 } 247 248 if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T) { 249 PHY_WRITE(sc, MII_100T2CR, 0); 250 PHY_WRITE(sc, MII_ANAR, anar); 251 PHY_WRITE(sc, MII_BMCR, speed | 252 BMCR_AUTOEN | BMCR_STARTNEG); 253 break; 254 } 255 256 /* 257 * When setting the link manually, one side must 258 * be the master and the other the slave. However 259 * ifmedia doesn't give us a good way to specify 260 * this, so we fake it by using one of the LINK 261 * flags. If LINK0 is set, we program the PHY to 262 * be a master, otherwise it's a slave. 263 */ 264 if ((mii->mii_ifp->if_flags & IFF_LINK0)) { 265 PHY_WRITE(sc, MII_100T2CR, 266 gig|GTCR_MAN_MS|GTCR_ADV_MS); 267 } else { 268 PHY_WRITE(sc, MII_100T2CR, gig|GTCR_MAN_MS); 269 } 270 PHY_WRITE(sc, MII_BMCR, speed | 271 BMCR_AUTOEN | BMCR_STARTNEG); 272 break; 273 case IFM_NONE: 274 PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN); 275 break; 276 case IFM_100_T4: 277 default: 278 return EINVAL; 279 } 280 break; 281 282 case MII_TICK: 283 /* 284 * If we're not currently selected, just return. 285 */ 286 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 287 return 0; 288 289 /* 290 * Is the interface even up? 291 */ 292 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 293 return 0; 294 295 /* 296 * Only used for autonegotiation. 297 */ 298 if ((IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) && 299 (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T)) { 300 /* 301 * Reset autonegotiation timer to 0 to make sure 302 * the future autonegotiation start with 0. 303 */ 304 sc->mii_ticks = 0; 305 break; 306 } 307 308 /* 309 * Check to see if we have link. If we do, we don't 310 * need to restart the autonegotiation process. Read 311 * the BMSR twice in case it's latched. 312 */ 313 if (sc->mii_mpd_rev >= RGEPHY_8211F) { 314 /* RTL8211F */ 315 PHY_READ(sc, RGEPHY_MII_PHYSR, ®); 316 if (reg & RGEPHY_PHYSR_LINK) { 317 sc->mii_ticks = 0; 318 break; 319 } 320 } else if (sc->mii_mpd_rev >= RGEPHY_8211B) { 321 /* RTL8211B(L) */ 322 PHY_READ(sc, RGEPHY_MII_SSR, ®); 323 if (reg & RGEPHY_SSR_LINK) { 324 sc->mii_ticks = 0; 325 break; 326 } 327 } else { 328 PHY_READ(sc, RTK_GMEDIASTAT, ®); 329 if ((reg & RTK_GMEDIASTAT_LINK) != 0) { 330 sc->mii_ticks = 0; 331 break; 332 } 333 } 334 335 /* Announce link loss right after it happens. */ 336 if (sc->mii_ticks++ == 0) 337 break; 338 339 /* Only retry autonegotiation every mii_anegticks seconds. */ 340 if (sc->mii_ticks <= sc->mii_anegticks) 341 return 0; 342 343 rgephy_mii_phy_auto(sc); 344 break; 345 } 346 347 /* Update the media status. */ 348 rgephy_status(sc); 349 350 /* 351 * Callback if something changed. Note that we need to poke 352 * the DSP on the RealTek PHYs if the media changes. 353 * 354 */ 355 if (sc->mii_media_active != mii->mii_media_active || 356 sc->mii_media_status != mii->mii_media_status || 357 cmd == MII_MEDIACHG) { 358 rgephy_load_dspcode(sc); 359 } 360 mii_phy_update(sc, cmd); 361 return 0; 362 } 363 364 static void 365 rgephy_status(struct mii_softc *sc) 366 { 367 struct mii_data *mii = sc->mii_pdata; 368 uint16_t gstat, bmsr, bmcr, physr, ssr; 369 370 mii->mii_media_status = IFM_AVALID; 371 mii->mii_media_active = IFM_ETHER; 372 373 if (sc->mii_mpd_rev >= RGEPHY_8211F) { 374 PHY_READ(sc, RGEPHY_MII_PHYSR, &physr); 375 if (physr & RGEPHY_PHYSR_LINK) 376 mii->mii_media_status |= IFM_ACTIVE; 377 } else if (sc->mii_mpd_rev >= RGEPHY_8211B) { 378 PHY_READ(sc, RGEPHY_MII_SSR, &ssr); 379 if (ssr & RGEPHY_SSR_LINK) 380 mii->mii_media_status |= IFM_ACTIVE; 381 } else { 382 PHY_READ(sc, RTK_GMEDIASTAT, &gstat); 383 if ((gstat & RTK_GMEDIASTAT_LINK) != 0) 384 mii->mii_media_status |= IFM_ACTIVE; 385 } 386 387 PHY_READ(sc, MII_BMSR, &bmsr); 388 PHY_READ(sc, MII_BMCR, &bmcr); 389 390 if ((bmcr & BMCR_ISO) != 0) { 391 mii->mii_media_active |= IFM_NONE; 392 mii->mii_media_status = 0; 393 return; 394 } 395 396 if ((bmcr & BMCR_LOOP) != 0) 397 mii->mii_media_active |= IFM_LOOP; 398 399 if ((bmcr & BMCR_AUTOEN) != 0) { 400 if ((bmsr & BMSR_ACOMP) == 0) { 401 /* Erg, still trying, I guess... */ 402 mii->mii_media_active |= IFM_NONE; 403 return; 404 } 405 } 406 407 if (sc->mii_mpd_rev >= RGEPHY_8211F) { 408 PHY_READ(sc, RGEPHY_MII_PHYSR, &physr); 409 switch (__SHIFTOUT(physr, RGEPHY_PHYSR_SPEED)) { 410 case RGEPHY_PHYSR_SPEED_1000: 411 mii->mii_media_active |= IFM_1000_T; 412 break; 413 case RGEPHY_PHYSR_SPEED_100: 414 mii->mii_media_active |= IFM_100_TX; 415 break; 416 case RGEPHY_PHYSR_SPEED_10: 417 mii->mii_media_active |= IFM_10_T; 418 break; 419 default: 420 mii->mii_media_active |= IFM_NONE; 421 break; 422 } 423 if (physr & RGEPHY_PHYSR_DUPLEX) 424 mii->mii_media_active |= mii_phy_flowstatus(sc) | 425 IFM_FDX; 426 else 427 mii->mii_media_active |= IFM_HDX; 428 } else if (sc->mii_mpd_rev >= RGEPHY_8211B) { 429 PHY_READ(sc, RGEPHY_MII_SSR, &ssr); 430 switch (ssr & RGEPHY_SSR_SPD_MASK) { 431 case RGEPHY_SSR_S1000: 432 mii->mii_media_active |= IFM_1000_T; 433 break; 434 case RGEPHY_SSR_S100: 435 mii->mii_media_active |= IFM_100_TX; 436 break; 437 case RGEPHY_SSR_S10: 438 mii->mii_media_active |= IFM_10_T; 439 break; 440 default: 441 mii->mii_media_active |= IFM_NONE; 442 break; 443 } 444 if (ssr & RGEPHY_SSR_FDX) 445 mii->mii_media_active |= mii_phy_flowstatus(sc) | 446 IFM_FDX; 447 else 448 mii->mii_media_active |= IFM_HDX; 449 } else { 450 PHY_READ(sc, RTK_GMEDIASTAT, &gstat); 451 if ((gstat & RTK_GMEDIASTAT_1000MBPS) != 0) 452 mii->mii_media_active |= IFM_1000_T; 453 else if ((gstat & RTK_GMEDIASTAT_100MBPS) != 0) 454 mii->mii_media_active |= IFM_100_TX; 455 else if ((gstat & RTK_GMEDIASTAT_10MBPS) != 0) 456 mii->mii_media_active |= IFM_10_T; 457 else 458 mii->mii_media_active |= IFM_NONE; 459 if ((gstat & RTK_GMEDIASTAT_FDX) != 0) 460 mii->mii_media_active |= mii_phy_flowstatus(sc) | 461 IFM_FDX; 462 else 463 mii->mii_media_active |= IFM_HDX; 464 } 465 } 466 467 468 static int 469 rgephy_mii_phy_auto(struct mii_softc *mii) 470 { 471 int anar; 472 473 mii->mii_ticks = 0; 474 rgephy_loop(mii); 475 rgephy_reset(mii); 476 477 anar = BMSR_MEDIA_TO_ANAR(mii->mii_capabilities) | ANAR_CSMA; 478 if (mii->mii_flags & MIIF_DOPAUSE) 479 anar |= ANAR_FC | ANAR_PAUSE_ASYM; 480 481 PHY_WRITE(mii, MII_ANAR, anar); 482 DELAY(1000); 483 PHY_WRITE(mii, MII_100T2CR, GTCR_ADV_1000THDX | GTCR_ADV_1000TFDX); 484 DELAY(1000); 485 PHY_WRITE(mii, MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG); 486 DELAY(100); 487 488 return EJUSTRETURN; 489 } 490 491 static void 492 rgephy_loop(struct mii_softc *sc) 493 { 494 uint16_t bmsr; 495 int i; 496 497 if (sc->mii_mpd_model != MII_MODEL_REALTEK_RTL8251 && 498 sc->mii_mpd_rev < RGEPHY_8211B) { 499 PHY_WRITE(sc, MII_BMCR, BMCR_PDOWN); 500 DELAY(1000); 501 } 502 503 for (i = 0; i < 15000; i++) { 504 PHY_READ(sc, MII_BMSR, &bmsr); 505 if ((bmsr & BMSR_LINK) == 0) { 506 #if 0 507 device_printf(sc->mii_dev, "looped %d\n", i); 508 #endif 509 break; 510 } 511 DELAY(10); 512 } 513 } 514 515 static inline int 516 PHY_SETBIT(struct mii_softc *sc, int y, uint16_t z) 517 { 518 uint16_t _tmp; 519 int rv; 520 521 if ((rv = PHY_READ(sc, y, &_tmp)) != 0) 522 return rv; 523 return PHY_WRITE(sc, y, _tmp | z); 524 } 525 526 static inline int 527 PHY_CLRBIT(struct mii_softc *sc, int y, uint16_t z) 528 { 529 uint16_t _tmp; 530 int rv; 531 532 if ((rv = PHY_READ(sc, y, &_tmp)) != 0) 533 return rv; 534 return PHY_WRITE(sc, y, _tmp & ~z); 535 } 536 537 /* 538 * Initialize RealTek PHY per the datasheet. The DSP in the PHYs of 539 * existing revisions of the 8169S/8110S chips need to be tuned in 540 * order to reliably negotiate a 1000Mbps link. This is only needed 541 * for rev 0 and rev 1 of the PHY. Later versions work without 542 * any fixups. 543 */ 544 static void 545 rgephy_load_dspcode(struct mii_softc *sc) 546 { 547 uint16_t val; 548 549 if (sc->mii_mpd_model == MII_MODEL_REALTEK_RTL8251 || 550 sc->mii_mpd_rev >= RGEPHY_8211B) 551 return; 552 553 #if 1 554 PHY_WRITE(sc, 31, 0x0001); 555 PHY_WRITE(sc, 21, 0x1000); 556 PHY_WRITE(sc, 24, 0x65C7); 557 PHY_CLRBIT(sc, 4, 0x0800); 558 PHY_READ(sc, 4, &val); 559 val &= 0xFFF; 560 PHY_WRITE(sc, 4, val); 561 PHY_WRITE(sc, 3, 0x00A1); 562 PHY_WRITE(sc, 2, 0x0008); 563 PHY_WRITE(sc, 1, 0x1020); 564 PHY_WRITE(sc, 0, 0x1000); 565 PHY_SETBIT(sc, 4, 0x0800); 566 PHY_CLRBIT(sc, 4, 0x0800); 567 PHY_READ(sc, 4, &val); 568 val = (val & 0xFFF) | 0x7000; 569 PHY_WRITE(sc, 4, val); 570 PHY_WRITE(sc, 3, 0xFF41); 571 PHY_WRITE(sc, 2, 0xDE60); 572 PHY_WRITE(sc, 1, 0x0140); 573 PHY_WRITE(sc, 0, 0x0077); 574 PHY_READ(sc, 4, &val); 575 val = (val & 0xFFF) | 0xA000; 576 PHY_WRITE(sc, 4, val); 577 PHY_WRITE(sc, 3, 0xDF01); 578 PHY_WRITE(sc, 2, 0xDF20); 579 PHY_WRITE(sc, 1, 0xFF95); 580 PHY_WRITE(sc, 0, 0xFA00); 581 PHY_READ(sc, 4, &val); 582 val = (val & 0xFFF) | 0xB000; 583 PHY_WRITE(sc, 4, val); 584 PHY_WRITE(sc, 3, 0xFF41); 585 PHY_WRITE(sc, 2, 0xDE20); 586 PHY_WRITE(sc, 1, 0x0140); 587 PHY_WRITE(sc, 0, 0x00BB); 588 PHY_READ(sc, 4, &val); 589 val = (val & 0xFFF) | 0xF000; 590 PHY_WRITE(sc, 4, val); 591 PHY_WRITE(sc, 3, 0xDF01); 592 PHY_WRITE(sc, 2, 0xDF20); 593 PHY_WRITE(sc, 1, 0xFF95); 594 PHY_WRITE(sc, 0, 0xBF00); 595 PHY_SETBIT(sc, 4, 0x0800); 596 PHY_CLRBIT(sc, 4, 0x0800); 597 PHY_WRITE(sc, 31, 0x0000); 598 #else 599 (void)val; 600 PHY_WRITE(sc, 0x1f, 0x0001); 601 PHY_WRITE(sc, 0x15, 0x1000); 602 PHY_WRITE(sc, 0x18, 0x65c7); 603 PHY_WRITE(sc, 0x04, 0x0000); 604 PHY_WRITE(sc, 0x03, 0x00a1); 605 PHY_WRITE(sc, 0x02, 0x0008); 606 PHY_WRITE(sc, 0x01, 0x1020); 607 PHY_WRITE(sc, 0x00, 0x1000); 608 PHY_WRITE(sc, 0x04, 0x0800); 609 PHY_WRITE(sc, 0x04, 0x0000); 610 PHY_WRITE(sc, 0x04, 0x7000); 611 PHY_WRITE(sc, 0x03, 0xff41); 612 PHY_WRITE(sc, 0x02, 0xde60); 613 PHY_WRITE(sc, 0x01, 0x0140); 614 PHY_WRITE(sc, 0x00, 0x0077); 615 PHY_WRITE(sc, 0x04, 0x7800); 616 PHY_WRITE(sc, 0x04, 0x7000); 617 PHY_WRITE(sc, 0x04, 0xa000); 618 PHY_WRITE(sc, 0x03, 0xdf01); 619 PHY_WRITE(sc, 0x02, 0xdf20); 620 PHY_WRITE(sc, 0x01, 0xff95); 621 PHY_WRITE(sc, 0x00, 0xfa00); 622 PHY_WRITE(sc, 0x04, 0xa800); 623 PHY_WRITE(sc, 0x04, 0xa000); 624 PHY_WRITE(sc, 0x04, 0xb000); 625 PHY_WRITE(sc, 0x0e, 0xff41); 626 PHY_WRITE(sc, 0x02, 0xde20); 627 PHY_WRITE(sc, 0x01, 0x0140); 628 PHY_WRITE(sc, 0x00, 0x00bb); 629 PHY_WRITE(sc, 0x04, 0xb800); 630 PHY_WRITE(sc, 0x04, 0xb000); 631 PHY_WRITE(sc, 0x04, 0xf000); 632 PHY_WRITE(sc, 0x03, 0xdf01); 633 PHY_WRITE(sc, 0x02, 0xdf20); 634 PHY_WRITE(sc, 0x01, 0xff95); 635 PHY_WRITE(sc, 0x00, 0xbf00); 636 PHY_WRITE(sc, 0x04, 0xf800); 637 PHY_WRITE(sc, 0x04, 0xf000); 638 PHY_WRITE(sc, 0x04, 0x0000); 639 PHY_WRITE(sc, 0x1f, 0x0000); 640 PHY_WRITE(sc, 0x0b, 0x0000); 641 642 #endif 643 644 DELAY(40); 645 } 646 647 static void 648 rgephy_reset(struct mii_softc *sc) 649 { 650 struct rgephy_softc *rsc = (struct rgephy_softc *)sc; 651 uint16_t ssr, phycr1; 652 653 mii_phy_reset(sc); 654 DELAY(1000); 655 656 if (sc->mii_mpd_model != MII_MODEL_REALTEK_RTL8251 && 657 sc->mii_mpd_rev < RGEPHY_8211B) { 658 rgephy_load_dspcode(sc); 659 } else if (sc->mii_mpd_rev == RGEPHY_8211C) { 660 /* RTL8211C(L) */ 661 PHY_READ(sc, RGEPHY_MII_SSR, &ssr); 662 if ((ssr & RGEPHY_SSR_ALDPS) != 0) { 663 ssr &= ~RGEPHY_SSR_ALDPS; 664 PHY_WRITE(sc, RGEPHY_MII_SSR, ssr); 665 } 666 } else if (sc->mii_mpd_rev == RGEPHY_8211E) { 667 /* RTL8211E */ 668 if (rsc->mii_no_rx_delay) { 669 /* Disable RX internal delay (undocumented) */ 670 PHY_WRITE(sc, 0x1f, 0x0007); 671 PHY_WRITE(sc, 0x1e, 0x00a4); 672 PHY_WRITE(sc, 0x1c, 0xb591); 673 PHY_WRITE(sc, 0x1f, 0x0000); 674 } 675 } else if (sc->mii_mpd_rev == RGEPHY_8211F) { 676 /* RTL8211F */ 677 PHY_READ(sc, RGEPHY_MII_PHYCR1, &phycr1); 678 phycr1 &= ~RGEPHY_PHYCR1_MDI_MMCE; 679 phycr1 &= ~RGEPHY_PHYCR1_ALDPS_EN; 680 PHY_WRITE(sc, RGEPHY_MII_PHYCR1, phycr1); 681 } else { 682 PHY_WRITE(sc, 0x1F, 0x0000); 683 PHY_WRITE(sc, 0x0e, 0x0000); 684 } 685 686 /* Reset capabilities */ 687 /* Step1: write our capability */ 688 /* 10/100 capability */ 689 PHY_WRITE(sc, MII_ANAR, 690 ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 691 /* 1000 capability */ 692 PHY_WRITE(sc, MII_100T2CR, GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX); 693 694 /* Step2: Restart NWay */ 695 /* NWay enable and Restart NWay */ 696 PHY_WRITE(sc, MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 697 698 if (sc->mii_mpd_rev == RGEPHY_8211F) { 699 /* RTL8211F */ 700 delay(10000); 701 /* disable EEE */ 702 PHY_WRITE(sc, MII_MMDACR, MMDACR_FN_ADDRESS | MDIO_MMD_AN); 703 PHY_WRITE(sc, MII_MMDAADR, MDIO_AN_EEEADVERT); 704 PHY_WRITE(sc, MII_MMDACR, MMDACR_FN_DATANPI | MDIO_MMD_AN); 705 PHY_WRITE(sc, MII_MMDAADR, 0x0000); 706 } 707 } 708
Indexes created Thu Oct 02 14:10:14 GMT 2025