rgephy.c revision 1.47
1 /* $NetBSD: rgephy.c,v 1.47 2019/02/21 15:41:56 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 2003 5 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: rgephy.c,v 1.47 2019/02/21 15:41:56 msaitoh Exp $"); 37 38 39 /* 40 * Driver for the RealTek 8169S/8110S internal 10/100/1000 PHY. 41 */ 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/kernel.h> 46 #include <sys/device.h> 47 #include <sys/socket.h> 48 49 50 #include <net/if.h> 51 #include <net/if_media.h> 52 53 #include <dev/mii/mii.h> 54 #include <dev/mii/mdio.h> 55 #include <dev/mii/miivar.h> 56 #include <dev/mii/miidevs.h> 57 58 #include <dev/mii/rgephyreg.h> 59 60 #include <dev/ic/rtl81x9reg.h> 61 62 static int rgephy_match(device_t, cfdata_t, void *); 63 static void rgephy_attach(device_t, device_t, void *); 64 65 struct rgephy_softc { 66 struct mii_softc mii_sc; 67 bool mii_no_rx_delay; 68 }; 69 70 CFATTACH_DECL_NEW(rgephy, sizeof(struct rgephy_softc), 71 rgephy_match, rgephy_attach, mii_phy_detach, mii_phy_activate); 72 73 74 static int rgephy_service(struct mii_softc *, struct mii_data *, int); 75 static void rgephy_status(struct mii_softc *); 76 static int rgephy_mii_phy_auto(struct mii_softc *); 77 static void rgephy_reset(struct mii_softc *); 78 static void rgephy_loop(struct mii_softc *); 79 static void rgephy_load_dspcode(struct mii_softc *); 80 81 static const struct mii_phy_funcs rgephy_funcs = { 82 rgephy_service, rgephy_status, rgephy_reset, 83 }; 84 85 static const struct mii_phydesc rgephys[] = { 86 { MII_OUI_xxREALTEK, MII_MODEL_xxREALTEK_RTL8169S, 87 MII_STR_xxREALTEK_RTL8169S }, 88 89 { MII_OUI_REALTEK, MII_MODEL_REALTEK_RTL8169S, 90 MII_STR_REALTEK_RTL8169S }, 91 92 { MII_OUI_REALTEK, MII_MODEL_REALTEK_RTL8251, 93 MII_STR_REALTEK_RTL8251 }, 94 95 { 0, 0, 96 NULL } 97 }; 98 99 static int 100 rgephy_match(device_t parent, cfdata_t match, void *aux) 101 { 102 struct mii_attach_args *ma = aux; 103 104 if (mii_phy_match(ma, rgephys) != NULL) 105 return 10; 106 107 return 0; 108 } 109 110 static void 111 rgephy_attach(device_t parent, device_t self, void *aux) 112 { 113 struct rgephy_softc *rsc = device_private(self); 114 prop_dictionary_t prop = device_properties(self); 115 struct mii_softc *sc = &rsc->mii_sc; 116 struct mii_attach_args *ma = aux; 117 struct mii_data *mii = ma->mii_data; 118 const struct mii_phydesc *mpd; 119 int rev; 120 const char *sep = ""; 121 122 ma = aux; 123 mii = ma->mii_data; 124 125 rev = MII_REV(ma->mii_id2); 126 mpd = mii_phy_match(ma, rgephys); 127 aprint_naive(": Media interface\n"); 128 129 sc->mii_dev = self; 130 sc->mii_inst = mii->mii_instance; 131 sc->mii_phy = ma->mii_phyno; 132 sc->mii_mpd_oui = MII_OUI(ma->mii_id1, ma->mii_id2); 133 sc->mii_mpd_model = MII_MODEL(ma->mii_id2); 134 sc->mii_mpd_rev = MII_REV(ma->mii_id2); 135 136 if (sc->mii_mpd_model == MII_MODEL_REALTEK_RTL8169S) { 137 aprint_normal(": RTL8211"); 138 if (sc->mii_mpd_rev != 0) 139 aprint_normal("%c",'@' + sc->mii_mpd_rev); 140 aprint_normal(" 1000BASE-T media interface\n"); 141 } else 142 aprint_normal(": %s, rev. %d\n", mpd->mpd_name, rev); 143 144 sc->mii_pdata = mii; 145 sc->mii_flags = ma->mii_flags; 146 sc->mii_anegticks = MII_ANEGTICKS_GIGE; 147 148 sc->mii_funcs = &rgephy_funcs; 149 150 prop_dictionary_get_bool(prop, "no-rx-delay", &rsc->mii_no_rx_delay); 151 152 #define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL) 153 #define PRINT(n) aprint_normal("%s%s", sep, (n)); sep = ", " 154 155 #ifdef __FreeBSD__ 156 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst), 157 BMCR_LOOP|BMCR_S100); 158 #endif 159 160 PHY_READ(sc, MII_BMSR, &sc->mii_capabilities); 161 sc->mii_capabilities &= ma->mii_capmask; 162 sc->mii_capabilities &= ~BMSR_ANEG; 163 164 /* 165 * FreeBSD does not check EXSTAT, but instead adds gigabit 166 * media explicitly. Why? 167 */ 168 aprint_normal_dev(self, ""); 169 if (sc->mii_capabilities & BMSR_EXTSTAT) 170 PHY_READ(sc, MII_EXTSR, &sc->mii_extcapabilities); 171 172 mii_phy_add_media(sc); 173 174 /* rtl8169S does not report auto-sense; add manually. */ 175 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), MII_NMEDIA); 176 sep =", "; 177 PRINT("auto"); 178 179 #undef ADD 180 #undef PRINT 181 182 rgephy_reset(sc); 183 aprint_normal("\n"); 184 } 185 186 static int 187 rgephy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 188 { 189 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 190 uint16_t reg, speed, gig, anar; 191 192 switch (cmd) { 193 case MII_POLLSTAT: 194 /* 195 * If we're not polling our PHY instance, just return. 196 */ 197 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 198 return 0; 199 break; 200 201 case MII_MEDIACHG: 202 /* 203 * If the media indicates a different PHY instance, 204 * isolate ourselves. 205 */ 206 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 207 PHY_READ(sc, MII_BMCR, ®); 208 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO); 209 return 0; 210 } 211 212 /* 213 * If the interface is not up, don't do anything. 214 */ 215 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 216 break; 217 218 rgephy_reset(sc); /* XXX hardware bug work-around */ 219 220 PHY_READ(sc, MII_ANAR, &anar); 221 anar &= ~(ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10); 222 223 switch (IFM_SUBTYPE(ife->ifm_media)) { 224 case IFM_AUTO: 225 #ifdef foo 226 /* 227 * If we're already in auto mode, just return. 228 */ 229 PHY_READ(sc, MII_BMCR, ®); 230 if (reg & BMCR_AUTOEN) 231 return 0; 232 #endif 233 (void)rgephy_mii_phy_auto(sc); 234 break; 235 case IFM_1000_T: 236 speed = BMCR_S1000; 237 goto setit; 238 case IFM_100_TX: 239 speed = BMCR_S100; 240 anar |= ANAR_TX_FD | ANAR_TX; 241 goto setit; 242 case IFM_10_T: 243 speed = BMCR_S10; 244 anar |= ANAR_10_FD | ANAR_10; 245 setit: 246 rgephy_loop(sc); 247 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 248 speed |= BMCR_FDX; 249 gig = GTCR_ADV_1000TFDX; 250 anar &= ~(ANAR_TX | ANAR_10); 251 } else { 252 gig = GTCR_ADV_1000THDX; 253 anar &= ~(ANAR_TX_FD | ANAR_10_FD); 254 } 255 256 if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T) { 257 PHY_WRITE(sc, MII_100T2CR, 0); 258 PHY_WRITE(sc, MII_ANAR, anar); 259 PHY_WRITE(sc, MII_BMCR, speed | 260 BMCR_AUTOEN | BMCR_STARTNEG); 261 break; 262 } 263 264 /* 265 * When setting the link manually, one side must 266 * be the master and the other the slave. However 267 * ifmedia doesn't give us a good way to specify 268 * this, so we fake it by using one of the LINK 269 * flags. If LINK0 is set, we program the PHY to 270 * be a master, otherwise it's a slave. 271 */ 272 if ((mii->mii_ifp->if_flags & IFF_LINK0)) { 273 PHY_WRITE(sc, MII_100T2CR, 274 gig|GTCR_MAN_MS|GTCR_ADV_MS); 275 } else { 276 PHY_WRITE(sc, MII_100T2CR, gig|GTCR_MAN_MS); 277 } 278 PHY_WRITE(sc, MII_BMCR, speed | 279 BMCR_AUTOEN | BMCR_STARTNEG); 280 break; 281 case IFM_NONE: 282 PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN); 283 break; 284 case IFM_100_T4: 285 default: 286 return EINVAL; 287 } 288 break; 289 290 case MII_TICK: 291 /* 292 * If we're not currently selected, just return. 293 */ 294 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 295 return 0; 296 297 /* 298 * Is the interface even up? 299 */ 300 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 301 return 0; 302 303 /* 304 * Only used for autonegotiation. 305 */ 306 if ((IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) && 307 (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T)) { 308 /* 309 * Reset autonegotiation timer to 0 to make sure 310 * the future autonegotiation start with 0. 311 */ 312 sc->mii_ticks = 0; 313 break; 314 } 315 316 /* 317 * Check to see if we have link. If we do, we don't 318 * need to restart the autonegotiation process. Read 319 * the BMSR twice in case it's latched. 320 */ 321 if (sc->mii_mpd_rev >= RGEPHY_8211F) { 322 /* RTL8211F */ 323 PHY_READ(sc, RGEPHY_MII_PHYSR, ®); 324 if (reg & RGEPHY_PHYSR_LINK) { 325 sc->mii_ticks = 0; 326 break; 327 } 328 } else if (sc->mii_mpd_rev >= RGEPHY_8211B) { 329 /* RTL8211B(L) */ 330 PHY_READ(sc, RGEPHY_MII_SSR, ®); 331 if (reg & RGEPHY_SSR_LINK) { 332 sc->mii_ticks = 0; 333 break; 334 } 335 } else { 336 PHY_READ(sc, RTK_GMEDIASTAT, ®); 337 if ((reg & RTK_GMEDIASTAT_LINK) != 0) { 338 sc->mii_ticks = 0; 339 break; 340 } 341 } 342 343 /* Announce link loss right after it happens. */ 344 if (sc->mii_ticks++ == 0) 345 break; 346 347 /* Only retry autonegotiation every mii_anegticks seconds. */ 348 if (sc->mii_ticks <= sc->mii_anegticks) 349 return 0; 350 351 rgephy_mii_phy_auto(sc); 352 break; 353 } 354 355 /* Update the media status. */ 356 rgephy_status(sc); 357 358 /* 359 * Callback if something changed. Note that we need to poke 360 * the DSP on the RealTek PHYs if the media changes. 361 * 362 */ 363 if (sc->mii_media_active != mii->mii_media_active || 364 sc->mii_media_status != mii->mii_media_status || 365 cmd == MII_MEDIACHG) { 366 rgephy_load_dspcode(sc); 367 } 368 mii_phy_update(sc, cmd); 369 return 0; 370 } 371 372 static void 373 rgephy_status(struct mii_softc *sc) 374 { 375 struct mii_data *mii = sc->mii_pdata; 376 uint16_t gstat, bmsr, bmcr, physr, ssr; 377 378 mii->mii_media_status = IFM_AVALID; 379 mii->mii_media_active = IFM_ETHER; 380 381 if (sc->mii_mpd_rev >= RGEPHY_8211F) { 382 PHY_READ(sc, RGEPHY_MII_PHYSR, &physr); 383 if (physr & RGEPHY_PHYSR_LINK) 384 mii->mii_media_status |= IFM_ACTIVE; 385 } else if (sc->mii_mpd_rev >= RGEPHY_8211B) { 386 PHY_READ(sc, RGEPHY_MII_SSR, &ssr); 387 if (ssr & RGEPHY_SSR_LINK) 388 mii->mii_media_status |= IFM_ACTIVE; 389 } else { 390 PHY_READ(sc, RTK_GMEDIASTAT, &gstat); 391 if ((gstat & RTK_GMEDIASTAT_LINK) != 0) 392 mii->mii_media_status |= IFM_ACTIVE; 393 } 394 395 PHY_READ(sc, MII_BMSR, &bmsr); 396 PHY_READ(sc, MII_BMCR, &bmcr); 397 398 if ((bmcr & BMCR_ISO) != 0) { 399 mii->mii_media_active |= IFM_NONE; 400 mii->mii_media_status = 0; 401 return; 402 } 403 404 if ((bmcr & BMCR_LOOP) != 0) 405 mii->mii_media_active |= IFM_LOOP; 406 407 if ((bmcr & BMCR_AUTOEN) != 0) { 408 if ((bmsr & BMSR_ACOMP) == 0) { 409 /* Erg, still trying, I guess... */ 410 mii->mii_media_active |= IFM_NONE; 411 return; 412 } 413 } 414 415 if (sc->mii_mpd_rev >= RGEPHY_8211F) { 416 PHY_READ(sc, RGEPHY_MII_PHYSR, &physr); 417 switch (__SHIFTOUT(physr, RGEPHY_PHYSR_SPEED)) { 418 case RGEPHY_PHYSR_SPEED_1000: 419 mii->mii_media_active |= IFM_1000_T; 420 break; 421 case RGEPHY_PHYSR_SPEED_100: 422 mii->mii_media_active |= IFM_100_TX; 423 break; 424 case RGEPHY_PHYSR_SPEED_10: 425 mii->mii_media_active |= IFM_10_T; 426 break; 427 default: 428 mii->mii_media_active |= IFM_NONE; 429 break; 430 } 431 if (physr & RGEPHY_PHYSR_DUPLEX) 432 mii->mii_media_active |= mii_phy_flowstatus(sc) | 433 IFM_FDX; 434 else 435 mii->mii_media_active |= IFM_HDX; 436 } else if (sc->mii_mpd_rev >= RGEPHY_8211B) { 437 PHY_READ(sc, RGEPHY_MII_SSR, &ssr); 438 switch (ssr & RGEPHY_SSR_SPD_MASK) { 439 case RGEPHY_SSR_S1000: 440 mii->mii_media_active |= IFM_1000_T; 441 break; 442 case RGEPHY_SSR_S100: 443 mii->mii_media_active |= IFM_100_TX; 444 break; 445 case RGEPHY_SSR_S10: 446 mii->mii_media_active |= IFM_10_T; 447 break; 448 default: 449 mii->mii_media_active |= IFM_NONE; 450 break; 451 } 452 if (ssr & RGEPHY_SSR_FDX) 453 mii->mii_media_active |= mii_phy_flowstatus(sc) | 454 IFM_FDX; 455 else 456 mii->mii_media_active |= IFM_HDX; 457 } else { 458 PHY_READ(sc, RTK_GMEDIASTAT, &gstat); 459 if ((gstat & RTK_GMEDIASTAT_1000MBPS) != 0) 460 mii->mii_media_active |= IFM_1000_T; 461 else if ((gstat & RTK_GMEDIASTAT_100MBPS) != 0) 462 mii->mii_media_active |= IFM_100_TX; 463 else if ((gstat & RTK_GMEDIASTAT_10MBPS) != 0) 464 mii->mii_media_active |= IFM_10_T; 465 else 466 mii->mii_media_active |= IFM_NONE; 467 if ((gstat & RTK_GMEDIASTAT_FDX) != 0) 468 mii->mii_media_active |= mii_phy_flowstatus(sc) | 469 IFM_FDX; 470 else 471 mii->mii_media_active |= IFM_HDX; 472 } 473 } 474 475 476 static int 477 rgephy_mii_phy_auto(struct mii_softc *mii) 478 { 479 int anar; 480 481 mii->mii_ticks = 0; 482 rgephy_loop(mii); 483 rgephy_reset(mii); 484 485 anar = BMSR_MEDIA_TO_ANAR(mii->mii_capabilities) | ANAR_CSMA; 486 if (mii->mii_flags & MIIF_DOPAUSE) 487 anar |= ANAR_FC | ANAR_PAUSE_ASYM; 488 489 PHY_WRITE(mii, MII_ANAR, anar); 490 DELAY(1000); 491 PHY_WRITE(mii, MII_100T2CR, GTCR_ADV_1000THDX | GTCR_ADV_1000TFDX); 492 DELAY(1000); 493 PHY_WRITE(mii, MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG); 494 DELAY(100); 495 496 return EJUSTRETURN; 497 } 498 499 static void 500 rgephy_loop(struct mii_softc *sc) 501 { 502 uint16_t bmsr; 503 int i; 504 505 if (sc->mii_mpd_model != MII_MODEL_REALTEK_RTL8251 && 506 sc->mii_mpd_rev < RGEPHY_8211B) { 507 PHY_WRITE(sc, MII_BMCR, BMCR_PDOWN); 508 DELAY(1000); 509 } 510 511 for (i = 0; i < 15000; i++) { 512 PHY_READ(sc, MII_BMSR, &bmsr); 513 if ((bmsr & BMSR_LINK) == 0) { 514 #if 0 515 device_printf(sc->mii_dev, "looped %d\n", i); 516 #endif 517 break; 518 } 519 DELAY(10); 520 } 521 } 522 523 static inline int 524 PHY_SETBIT(struct mii_softc *sc, int y, uint16_t z) 525 { 526 uint16_t _tmp; 527 int rv; 528 529 if ((rv = PHY_READ(sc, y, &_tmp)) != 0) 530 return rv; 531 return PHY_WRITE(sc, y, _tmp | z); 532 } 533 534 static inline int 535 PHY_CLRBIT(struct mii_softc *sc, int y, uint16_t z) 536 { 537 uint16_t _tmp; 538 int rv; 539 540 if ((rv = PHY_READ(sc, y, &_tmp)) != 0) 541 return rv; 542 return PHY_WRITE(sc, y, _tmp & ~z); 543 } 544 545 /* 546 * Initialize RealTek PHY per the datasheet. The DSP in the PHYs of 547 * existing revisions of the 8169S/8110S chips need to be tuned in 548 * order to reliably negotiate a 1000Mbps link. This is only needed 549 * for rev 0 and rev 1 of the PHY. Later versions work without 550 * any fixups. 551 */ 552 static void 553 rgephy_load_dspcode(struct mii_softc *sc) 554 { 555 uint16_t val; 556 557 if (sc->mii_mpd_model == MII_MODEL_REALTEK_RTL8251 || 558 sc->mii_mpd_rev >= RGEPHY_8211B) 559 return; 560 561 #if 1 562 PHY_WRITE(sc, 31, 0x0001); 563 PHY_WRITE(sc, 21, 0x1000); 564 PHY_WRITE(sc, 24, 0x65C7); 565 PHY_CLRBIT(sc, 4, 0x0800); 566 PHY_READ(sc, 4, &val); 567 val &= 0xFFF; 568 PHY_WRITE(sc, 4, val); 569 PHY_WRITE(sc, 3, 0x00A1); 570 PHY_WRITE(sc, 2, 0x0008); 571 PHY_WRITE(sc, 1, 0x1020); 572 PHY_WRITE(sc, 0, 0x1000); 573 PHY_SETBIT(sc, 4, 0x0800); 574 PHY_CLRBIT(sc, 4, 0x0800); 575 PHY_READ(sc, 4, &val); 576 val = (val & 0xFFF) | 0x7000; 577 PHY_WRITE(sc, 4, val); 578 PHY_WRITE(sc, 3, 0xFF41); 579 PHY_WRITE(sc, 2, 0xDE60); 580 PHY_WRITE(sc, 1, 0x0140); 581 PHY_WRITE(sc, 0, 0x0077); 582 PHY_READ(sc, 4, &val); 583 val = (val & 0xFFF) | 0xA000; 584 PHY_WRITE(sc, 4, val); 585 PHY_WRITE(sc, 3, 0xDF01); 586 PHY_WRITE(sc, 2, 0xDF20); 587 PHY_WRITE(sc, 1, 0xFF95); 588 PHY_WRITE(sc, 0, 0xFA00); 589 PHY_READ(sc, 4, &val); 590 val = (val & 0xFFF) | 0xB000; 591 PHY_WRITE(sc, 4, val); 592 PHY_WRITE(sc, 3, 0xFF41); 593 PHY_WRITE(sc, 2, 0xDE20); 594 PHY_WRITE(sc, 1, 0x0140); 595 PHY_WRITE(sc, 0, 0x00BB); 596 PHY_READ(sc, 4, &val); 597 val = (val & 0xFFF) | 0xF000; 598 PHY_WRITE(sc, 4, val); 599 PHY_WRITE(sc, 3, 0xDF01); 600 PHY_WRITE(sc, 2, 0xDF20); 601 PHY_WRITE(sc, 1, 0xFF95); 602 PHY_WRITE(sc, 0, 0xBF00); 603 PHY_SETBIT(sc, 4, 0x0800); 604 PHY_CLRBIT(sc, 4, 0x0800); 605 PHY_WRITE(sc, 31, 0x0000); 606 #else 607 (void)val; 608 PHY_WRITE(sc, 0x1f, 0x0001); 609 PHY_WRITE(sc, 0x15, 0x1000); 610 PHY_WRITE(sc, 0x18, 0x65c7); 611 PHY_WRITE(sc, 0x04, 0x0000); 612 PHY_WRITE(sc, 0x03, 0x00a1); 613 PHY_WRITE(sc, 0x02, 0x0008); 614 PHY_WRITE(sc, 0x01, 0x1020); 615 PHY_WRITE(sc, 0x00, 0x1000); 616 PHY_WRITE(sc, 0x04, 0x0800); 617 PHY_WRITE(sc, 0x04, 0x0000); 618 PHY_WRITE(sc, 0x04, 0x7000); 619 PHY_WRITE(sc, 0x03, 0xff41); 620 PHY_WRITE(sc, 0x02, 0xde60); 621 PHY_WRITE(sc, 0x01, 0x0140); 622 PHY_WRITE(sc, 0x00, 0x0077); 623 PHY_WRITE(sc, 0x04, 0x7800); 624 PHY_WRITE(sc, 0x04, 0x7000); 625 PHY_WRITE(sc, 0x04, 0xa000); 626 PHY_WRITE(sc, 0x03, 0xdf01); 627 PHY_WRITE(sc, 0x02, 0xdf20); 628 PHY_WRITE(sc, 0x01, 0xff95); 629 PHY_WRITE(sc, 0x00, 0xfa00); 630 PHY_WRITE(sc, 0x04, 0xa800); 631 PHY_WRITE(sc, 0x04, 0xa000); 632 PHY_WRITE(sc, 0x04, 0xb000); 633 PHY_WRITE(sc, 0x0e, 0xff41); 634 PHY_WRITE(sc, 0x02, 0xde20); 635 PHY_WRITE(sc, 0x01, 0x0140); 636 PHY_WRITE(sc, 0x00, 0x00bb); 637 PHY_WRITE(sc, 0x04, 0xb800); 638 PHY_WRITE(sc, 0x04, 0xb000); 639 PHY_WRITE(sc, 0x04, 0xf000); 640 PHY_WRITE(sc, 0x03, 0xdf01); 641 PHY_WRITE(sc, 0x02, 0xdf20); 642 PHY_WRITE(sc, 0x01, 0xff95); 643 PHY_WRITE(sc, 0x00, 0xbf00); 644 PHY_WRITE(sc, 0x04, 0xf800); 645 PHY_WRITE(sc, 0x04, 0xf000); 646 PHY_WRITE(sc, 0x04, 0x0000); 647 PHY_WRITE(sc, 0x1f, 0x0000); 648 PHY_WRITE(sc, 0x0b, 0x0000); 649 650 #endif 651 652 DELAY(40); 653 } 654 655 static void 656 rgephy_reset(struct mii_softc *sc) 657 { 658 struct rgephy_softc *rsc = (struct rgephy_softc *)sc; 659 uint16_t ssr, phycr1; 660 661 mii_phy_reset(sc); 662 DELAY(1000); 663 664 if (sc->mii_mpd_model != MII_MODEL_REALTEK_RTL8251 && 665 sc->mii_mpd_rev < RGEPHY_8211B) { 666 rgephy_load_dspcode(sc); 667 } else if (sc->mii_mpd_rev == RGEPHY_8211C) { 668 /* RTL8211C(L) */ 669 PHY_READ(sc, RGEPHY_MII_SSR, &ssr); 670 if ((ssr & RGEPHY_SSR_ALDPS) != 0) { 671 ssr &= ~RGEPHY_SSR_ALDPS; 672 PHY_WRITE(sc, RGEPHY_MII_SSR, ssr); 673 } 674 } else if (sc->mii_mpd_rev == RGEPHY_8211E) { 675 /* RTL8211E */ 676 if (rsc->mii_no_rx_delay) { 677 /* Disable RX internal delay (undocumented) */ 678 PHY_WRITE(sc, 0x1f, 0x0007); 679 PHY_WRITE(sc, 0x1e, 0x00a4); 680 PHY_WRITE(sc, 0x1c, 0xb591); 681 PHY_WRITE(sc, 0x1f, 0x0000); 682 } 683 } else if (sc->mii_mpd_rev == RGEPHY_8211F) { 684 /* RTL8211F */ 685 PHY_READ(sc, RGEPHY_MII_PHYCR1, &phycr1); 686 phycr1 &= ~RGEPHY_PHYCR1_MDI_MMCE; 687 phycr1 &= ~RGEPHY_PHYCR1_ALDPS_EN; 688 PHY_WRITE(sc, RGEPHY_MII_PHYCR1, phycr1); 689 } else { 690 PHY_WRITE(sc, 0x1F, 0x0000); 691 PHY_WRITE(sc, 0x0e, 0x0000); 692 } 693 694 /* Reset capabilities */ 695 /* Step1: write our capability */ 696 /* 10/100 capability */ 697 PHY_WRITE(sc, MII_ANAR, 698 ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 699 /* 1000 capability */ 700 PHY_WRITE(sc, MII_100T2CR, GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX); 701 702 /* Step2: Restart NWay */ 703 /* NWay enable and Restart NWay */ 704 PHY_WRITE(sc, MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 705 706 if (sc->mii_mpd_rev == RGEPHY_8211F) { 707 /* RTL8211F */ 708 delay(10000); 709 /* disable EEE */ 710 PHY_WRITE(sc, MII_MMDACR, MMDACR_FN_ADDRESS | MDIO_MMD_AN); 711 PHY_WRITE(sc, MII_MMDAADR, MDIO_AN_EEEADVERT); 712 PHY_WRITE(sc, MII_MMDACR, MMDACR_FN_DATANPI | MDIO_MMD_AN); 713 PHY_WRITE(sc, MII_MMDAADR, 0x0000); 714 } 715 } 716
Indexes created Thu Oct 02 14:10:14 GMT 2025