rgephy.c revision 1.49
1 /* $NetBSD: rgephy.c,v 1.49 2019/02/25 06:59:37 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 2003 5 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: rgephy.c,v 1.49 2019/02/25 06:59:37 msaitoh Exp $"); 37 38 39 /* 40 * Driver for the RealTek 8169S/8110S internal 10/100/1000 PHY. 41 */ 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/kernel.h> 46 #include <sys/device.h> 47 #include <sys/socket.h> 48 49 50 #include <net/if.h> 51 #include <net/if_media.h> 52 53 #include <dev/mii/mii.h> 54 #include <dev/mii/mdio.h> 55 #include <dev/mii/miivar.h> 56 #include <dev/mii/miidevs.h> 57 58 #include <dev/mii/rgephyreg.h> 59 60 #include <dev/ic/rtl81x9reg.h> 61 62 static int rgephy_match(device_t, cfdata_t, void *); 63 static void rgephy_attach(device_t, device_t, void *); 64 65 struct rgephy_softc { 66 struct mii_softc mii_sc; 67 bool mii_no_rx_delay; 68 }; 69 70 CFATTACH_DECL_NEW(rgephy, sizeof(struct rgephy_softc), 71 rgephy_match, rgephy_attach, mii_phy_detach, mii_phy_activate); 72 73 74 static int rgephy_service(struct mii_softc *, struct mii_data *, int); 75 static void rgephy_status(struct mii_softc *); 76 static int rgephy_mii_phy_auto(struct mii_softc *); 77 static void rgephy_reset(struct mii_softc *); 78 static void rgephy_loop(struct mii_softc *); 79 static void rgephy_load_dspcode(struct mii_softc *); 80 81 static const struct mii_phy_funcs rgephy_funcs = { 82 rgephy_service, rgephy_status, rgephy_reset, 83 }; 84 85 static const struct mii_phydesc rgephys[] = { 86 MII_PHY_DESC(xxREALTEK, RTL8169S), 87 MII_PHY_DESC(REALTEK, RTL8169S), 88 MII_PHY_DESC(REALTEK, RTL8251), 89 MII_PHY_END, 90 }; 91 92 static int 93 rgephy_match(device_t parent, cfdata_t match, void *aux) 94 { 95 struct mii_attach_args *ma = aux; 96 97 if (mii_phy_match(ma, rgephys) != NULL) 98 return 10; 99 100 return 0; 101 } 102 103 static void 104 rgephy_attach(device_t parent, device_t self, void *aux) 105 { 106 struct rgephy_softc *rsc = device_private(self); 107 prop_dictionary_t prop = device_properties(self); 108 struct mii_softc *sc = &rsc->mii_sc; 109 struct mii_attach_args *ma = aux; 110 struct mii_data *mii = ma->mii_data; 111 const struct mii_phydesc *mpd; 112 int rev; 113 const char *sep = ""; 114 115 ma = aux; 116 mii = ma->mii_data; 117 118 rev = MII_REV(ma->mii_id2); 119 mpd = mii_phy_match(ma, rgephys); 120 aprint_naive(": Media interface\n"); 121 122 sc->mii_dev = self; 123 sc->mii_inst = mii->mii_instance; 124 sc->mii_phy = ma->mii_phyno; 125 sc->mii_mpd_oui = MII_OUI(ma->mii_id1, ma->mii_id2); 126 sc->mii_mpd_model = MII_MODEL(ma->mii_id2); 127 sc->mii_mpd_rev = MII_REV(ma->mii_id2); 128 129 if (sc->mii_mpd_model == MII_MODEL_REALTEK_RTL8169S) { 130 aprint_normal(": RTL8211"); 131 if (sc->mii_mpd_rev != 0) 132 aprint_normal("%c",'@' + sc->mii_mpd_rev); 133 aprint_normal(" 1000BASE-T media interface\n"); 134 } else 135 aprint_normal(": %s, rev. %d\n", mpd->mpd_name, rev); 136 137 sc->mii_pdata = mii; 138 sc->mii_flags = ma->mii_flags; 139 sc->mii_anegticks = MII_ANEGTICKS_GIGE; 140 141 sc->mii_funcs = &rgephy_funcs; 142 143 prop_dictionary_get_bool(prop, "no-rx-delay", &rsc->mii_no_rx_delay); 144 145 #define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL) 146 #define PRINT(n) aprint_normal("%s%s", sep, (n)); sep = ", " 147 148 #ifdef __FreeBSD__ 149 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst), 150 BMCR_LOOP|BMCR_S100); 151 #endif 152 153 PHY_READ(sc, MII_BMSR, &sc->mii_capabilities); 154 sc->mii_capabilities &= ma->mii_capmask; 155 sc->mii_capabilities &= ~BMSR_ANEG; 156 157 /* 158 * FreeBSD does not check EXSTAT, but instead adds gigabit 159 * media explicitly. Why? 160 */ 161 aprint_normal_dev(self, ""); 162 if (sc->mii_capabilities & BMSR_EXTSTAT) 163 PHY_READ(sc, MII_EXTSR, &sc->mii_extcapabilities); 164 165 mii_phy_add_media(sc); 166 167 /* rtl8169S does not report auto-sense; add manually. */ 168 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), MII_NMEDIA); 169 sep =", "; 170 PRINT("auto"); 171 172 #undef ADD 173 #undef PRINT 174 175 rgephy_reset(sc); 176 aprint_normal("\n"); 177 } 178 179 static int 180 rgephy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 181 { 182 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 183 uint16_t reg, speed, gig, anar; 184 185 switch (cmd) { 186 case MII_POLLSTAT: 187 /* 188 * If we're not polling our PHY instance, just return. 189 */ 190 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 191 return 0; 192 break; 193 194 case MII_MEDIACHG: 195 /* 196 * If the media indicates a different PHY instance, 197 * isolate ourselves. 198 */ 199 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 200 PHY_READ(sc, MII_BMCR, ®); 201 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO); 202 return 0; 203 } 204 205 /* 206 * If the interface is not up, don't do anything. 207 */ 208 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 209 break; 210 211 rgephy_reset(sc); /* XXX hardware bug work-around */ 212 213 PHY_READ(sc, MII_ANAR, &anar); 214 anar &= ~(ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10); 215 216 switch (IFM_SUBTYPE(ife->ifm_media)) { 217 case IFM_AUTO: 218 #ifdef foo 219 /* 220 * If we're already in auto mode, just return. 221 */ 222 PHY_READ(sc, MII_BMCR, ®); 223 if (reg & BMCR_AUTOEN) 224 return 0; 225 #endif 226 (void)rgephy_mii_phy_auto(sc); 227 break; 228 case IFM_1000_T: 229 speed = BMCR_S1000; 230 goto setit; 231 case IFM_100_TX: 232 speed = BMCR_S100; 233 anar |= ANAR_TX_FD | ANAR_TX; 234 goto setit; 235 case IFM_10_T: 236 speed = BMCR_S10; 237 anar |= ANAR_10_FD | ANAR_10; 238 setit: 239 rgephy_loop(sc); 240 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 241 speed |= BMCR_FDX; 242 gig = GTCR_ADV_1000TFDX; 243 anar &= ~(ANAR_TX | ANAR_10); 244 } else { 245 gig = GTCR_ADV_1000THDX; 246 anar &= ~(ANAR_TX_FD | ANAR_10_FD); 247 } 248 249 if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T) { 250 PHY_WRITE(sc, MII_100T2CR, 0); 251 PHY_WRITE(sc, MII_ANAR, anar); 252 PHY_WRITE(sc, MII_BMCR, speed | 253 BMCR_AUTOEN | BMCR_STARTNEG); 254 break; 255 } 256 257 /* 258 * When setting the link manually, one side must 259 * be the master and the other the slave. However 260 * ifmedia doesn't give us a good way to specify 261 * this, so we fake it by using one of the LINK 262 * flags. If LINK0 is set, we program the PHY to 263 * be a master, otherwise it's a slave. 264 */ 265 if ((mii->mii_ifp->if_flags & IFF_LINK0)) { 266 PHY_WRITE(sc, MII_100T2CR, 267 gig|GTCR_MAN_MS|GTCR_ADV_MS); 268 } else { 269 PHY_WRITE(sc, MII_100T2CR, gig|GTCR_MAN_MS); 270 } 271 PHY_WRITE(sc, MII_BMCR, speed | 272 BMCR_AUTOEN | BMCR_STARTNEG); 273 break; 274 case IFM_NONE: 275 PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN); 276 break; 277 case IFM_100_T4: 278 default: 279 return EINVAL; 280 } 281 break; 282 283 case MII_TICK: 284 /* 285 * If we're not currently selected, just return. 286 */ 287 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 288 return 0; 289 290 /* 291 * Is the interface even up? 292 */ 293 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 294 return 0; 295 296 /* 297 * Only used for autonegotiation. 298 */ 299 if ((IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) && 300 (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T)) { 301 /* 302 * Reset autonegotiation timer to 0 to make sure 303 * the future autonegotiation start with 0. 304 */ 305 sc->mii_ticks = 0; 306 break; 307 } 308 309 /* 310 * Check to see if we have link. If we do, we don't 311 * need to restart the autonegotiation process. Read 312 * the BMSR twice in case it's latched. 313 */ 314 if (sc->mii_mpd_rev >= RGEPHY_8211F) { 315 /* RTL8211F */ 316 PHY_READ(sc, RGEPHY_MII_PHYSR, ®); 317 if (reg & RGEPHY_PHYSR_LINK) { 318 sc->mii_ticks = 0; 319 break; 320 } 321 } else if (sc->mii_mpd_rev >= RGEPHY_8211B) { 322 /* RTL8211B(L) */ 323 PHY_READ(sc, RGEPHY_MII_SSR, ®); 324 if (reg & RGEPHY_SSR_LINK) { 325 sc->mii_ticks = 0; 326 break; 327 } 328 } else { 329 PHY_READ(sc, RTK_GMEDIASTAT, ®); 330 if ((reg & RTK_GMEDIASTAT_LINK) != 0) { 331 sc->mii_ticks = 0; 332 break; 333 } 334 } 335 336 /* Announce link loss right after it happens. */ 337 if (sc->mii_ticks++ == 0) 338 break; 339 340 /* Only retry autonegotiation every mii_anegticks seconds. */ 341 if (sc->mii_ticks <= sc->mii_anegticks) 342 return 0; 343 344 rgephy_mii_phy_auto(sc); 345 break; 346 } 347 348 /* Update the media status. */ 349 rgephy_status(sc); 350 351 /* 352 * Callback if something changed. Note that we need to poke 353 * the DSP on the RealTek PHYs if the media changes. 354 * 355 */ 356 if (sc->mii_media_active != mii->mii_media_active || 357 sc->mii_media_status != mii->mii_media_status || 358 cmd == MII_MEDIACHG) { 359 rgephy_load_dspcode(sc); 360 } 361 mii_phy_update(sc, cmd); 362 return 0; 363 } 364 365 static void 366 rgephy_status(struct mii_softc *sc) 367 { 368 struct mii_data *mii = sc->mii_pdata; 369 uint16_t gstat, bmsr, bmcr, physr, ssr; 370 371 mii->mii_media_status = IFM_AVALID; 372 mii->mii_media_active = IFM_ETHER; 373 374 if (sc->mii_mpd_rev >= RGEPHY_8211F) { 375 PHY_READ(sc, RGEPHY_MII_PHYSR, &physr); 376 if (physr & RGEPHY_PHYSR_LINK) 377 mii->mii_media_status |= IFM_ACTIVE; 378 } else if (sc->mii_mpd_rev >= RGEPHY_8211B) { 379 PHY_READ(sc, RGEPHY_MII_SSR, &ssr); 380 if (ssr & RGEPHY_SSR_LINK) 381 mii->mii_media_status |= IFM_ACTIVE; 382 } else { 383 PHY_READ(sc, RTK_GMEDIASTAT, &gstat); 384 if ((gstat & RTK_GMEDIASTAT_LINK) != 0) 385 mii->mii_media_status |= IFM_ACTIVE; 386 } 387 388 PHY_READ(sc, MII_BMSR, &bmsr); 389 PHY_READ(sc, MII_BMCR, &bmcr); 390 391 if ((bmcr & BMCR_ISO) != 0) { 392 mii->mii_media_active |= IFM_NONE; 393 mii->mii_media_status = 0; 394 return; 395 } 396 397 if ((bmcr & BMCR_LOOP) != 0) 398 mii->mii_media_active |= IFM_LOOP; 399 400 if ((bmcr & BMCR_AUTOEN) != 0) { 401 if ((bmsr & BMSR_ACOMP) == 0) { 402 /* Erg, still trying, I guess... */ 403 mii->mii_media_active |= IFM_NONE; 404 return; 405 } 406 } 407 408 if (sc->mii_mpd_rev >= RGEPHY_8211F) { 409 PHY_READ(sc, RGEPHY_MII_PHYSR, &physr); 410 switch (__SHIFTOUT(physr, RGEPHY_PHYSR_SPEED)) { 411 case RGEPHY_PHYSR_SPEED_1000: 412 mii->mii_media_active |= IFM_1000_T; 413 break; 414 case RGEPHY_PHYSR_SPEED_100: 415 mii->mii_media_active |= IFM_100_TX; 416 break; 417 case RGEPHY_PHYSR_SPEED_10: 418 mii->mii_media_active |= IFM_10_T; 419 break; 420 default: 421 mii->mii_media_active |= IFM_NONE; 422 break; 423 } 424 if (physr & RGEPHY_PHYSR_DUPLEX) 425 mii->mii_media_active |= mii_phy_flowstatus(sc) | 426 IFM_FDX; 427 else 428 mii->mii_media_active |= IFM_HDX; 429 } else if (sc->mii_mpd_rev >= RGEPHY_8211B) { 430 PHY_READ(sc, RGEPHY_MII_SSR, &ssr); 431 switch (ssr & RGEPHY_SSR_SPD_MASK) { 432 case RGEPHY_SSR_S1000: 433 mii->mii_media_active |= IFM_1000_T; 434 break; 435 case RGEPHY_SSR_S100: 436 mii->mii_media_active |= IFM_100_TX; 437 break; 438 case RGEPHY_SSR_S10: 439 mii->mii_media_active |= IFM_10_T; 440 break; 441 default: 442 mii->mii_media_active |= IFM_NONE; 443 break; 444 } 445 if (ssr & RGEPHY_SSR_FDX) 446 mii->mii_media_active |= mii_phy_flowstatus(sc) | 447 IFM_FDX; 448 else 449 mii->mii_media_active |= IFM_HDX; 450 } else { 451 PHY_READ(sc, RTK_GMEDIASTAT, &gstat); 452 if ((gstat & RTK_GMEDIASTAT_1000MBPS) != 0) 453 mii->mii_media_active |= IFM_1000_T; 454 else if ((gstat & RTK_GMEDIASTAT_100MBPS) != 0) 455 mii->mii_media_active |= IFM_100_TX; 456 else if ((gstat & RTK_GMEDIASTAT_10MBPS) != 0) 457 mii->mii_media_active |= IFM_10_T; 458 else 459 mii->mii_media_active |= IFM_NONE; 460 if ((gstat & RTK_GMEDIASTAT_FDX) != 0) 461 mii->mii_media_active |= mii_phy_flowstatus(sc) | 462 IFM_FDX; 463 else 464 mii->mii_media_active |= IFM_HDX; 465 } 466 } 467 468 469 static int 470 rgephy_mii_phy_auto(struct mii_softc *mii) 471 { 472 int anar; 473 474 mii->mii_ticks = 0; 475 rgephy_loop(mii); 476 rgephy_reset(mii); 477 478 anar = BMSR_MEDIA_TO_ANAR(mii->mii_capabilities) | ANAR_CSMA; 479 if (mii->mii_flags & MIIF_DOPAUSE) 480 anar |= ANAR_FC | ANAR_PAUSE_ASYM; 481 482 PHY_WRITE(mii, MII_ANAR, anar); 483 DELAY(1000); 484 PHY_WRITE(mii, MII_100T2CR, GTCR_ADV_1000THDX | GTCR_ADV_1000TFDX); 485 DELAY(1000); 486 PHY_WRITE(mii, MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG); 487 DELAY(100); 488 489 return EJUSTRETURN; 490 } 491 492 static void 493 rgephy_loop(struct mii_softc *sc) 494 { 495 uint16_t bmsr; 496 int i; 497 498 if (sc->mii_mpd_model != MII_MODEL_REALTEK_RTL8251 && 499 sc->mii_mpd_rev < RGEPHY_8211B) { 500 PHY_WRITE(sc, MII_BMCR, BMCR_PDOWN); 501 DELAY(1000); 502 } 503 504 for (i = 0; i < 15000; i++) { 505 PHY_READ(sc, MII_BMSR, &bmsr); 506 if ((bmsr & BMSR_LINK) == 0) { 507 #if 0 508 device_printf(sc->mii_dev, "looped %d\n", i); 509 #endif 510 break; 511 } 512 DELAY(10); 513 } 514 } 515 516 static inline int 517 PHY_SETBIT(struct mii_softc *sc, int y, uint16_t z) 518 { 519 uint16_t _tmp; 520 int rv; 521 522 if ((rv = PHY_READ(sc, y, &_tmp)) != 0) 523 return rv; 524 return PHY_WRITE(sc, y, _tmp | z); 525 } 526 527 static inline int 528 PHY_CLRBIT(struct mii_softc *sc, int y, uint16_t z) 529 { 530 uint16_t _tmp; 531 int rv; 532 533 if ((rv = PHY_READ(sc, y, &_tmp)) != 0) 534 return rv; 535 return PHY_WRITE(sc, y, _tmp & ~z); 536 } 537 538 /* 539 * Initialize RealTek PHY per the datasheet. The DSP in the PHYs of 540 * existing revisions of the 8169S/8110S chips need to be tuned in 541 * order to reliably negotiate a 1000Mbps link. This is only needed 542 * for rev 0 and rev 1 of the PHY. Later versions work without 543 * any fixups. 544 */ 545 static void 546 rgephy_load_dspcode(struct mii_softc *sc) 547 { 548 uint16_t val; 549 550 if (sc->mii_mpd_model == MII_MODEL_REALTEK_RTL8251 || 551 sc->mii_mpd_rev >= RGEPHY_8211B) 552 return; 553 554 #if 1 555 PHY_WRITE(sc, 31, 0x0001); 556 PHY_WRITE(sc, 21, 0x1000); 557 PHY_WRITE(sc, 24, 0x65C7); 558 PHY_CLRBIT(sc, 4, 0x0800); 559 PHY_READ(sc, 4, &val); 560 val &= 0xFFF; 561 PHY_WRITE(sc, 4, val); 562 PHY_WRITE(sc, 3, 0x00A1); 563 PHY_WRITE(sc, 2, 0x0008); 564 PHY_WRITE(sc, 1, 0x1020); 565 PHY_WRITE(sc, 0, 0x1000); 566 PHY_SETBIT(sc, 4, 0x0800); 567 PHY_CLRBIT(sc, 4, 0x0800); 568 PHY_READ(sc, 4, &val); 569 val = (val & 0xFFF) | 0x7000; 570 PHY_WRITE(sc, 4, val); 571 PHY_WRITE(sc, 3, 0xFF41); 572 PHY_WRITE(sc, 2, 0xDE60); 573 PHY_WRITE(sc, 1, 0x0140); 574 PHY_WRITE(sc, 0, 0x0077); 575 PHY_READ(sc, 4, &val); 576 val = (val & 0xFFF) | 0xA000; 577 PHY_WRITE(sc, 4, val); 578 PHY_WRITE(sc, 3, 0xDF01); 579 PHY_WRITE(sc, 2, 0xDF20); 580 PHY_WRITE(sc, 1, 0xFF95); 581 PHY_WRITE(sc, 0, 0xFA00); 582 PHY_READ(sc, 4, &val); 583 val = (val & 0xFFF) | 0xB000; 584 PHY_WRITE(sc, 4, val); 585 PHY_WRITE(sc, 3, 0xFF41); 586 PHY_WRITE(sc, 2, 0xDE20); 587 PHY_WRITE(sc, 1, 0x0140); 588 PHY_WRITE(sc, 0, 0x00BB); 589 PHY_READ(sc, 4, &val); 590 val = (val & 0xFFF) | 0xF000; 591 PHY_WRITE(sc, 4, val); 592 PHY_WRITE(sc, 3, 0xDF01); 593 PHY_WRITE(sc, 2, 0xDF20); 594 PHY_WRITE(sc, 1, 0xFF95); 595 PHY_WRITE(sc, 0, 0xBF00); 596 PHY_SETBIT(sc, 4, 0x0800); 597 PHY_CLRBIT(sc, 4, 0x0800); 598 PHY_WRITE(sc, 31, 0x0000); 599 #else 600 (void)val; 601 PHY_WRITE(sc, 0x1f, 0x0001); 602 PHY_WRITE(sc, 0x15, 0x1000); 603 PHY_WRITE(sc, 0x18, 0x65c7); 604 PHY_WRITE(sc, 0x04, 0x0000); 605 PHY_WRITE(sc, 0x03, 0x00a1); 606 PHY_WRITE(sc, 0x02, 0x0008); 607 PHY_WRITE(sc, 0x01, 0x1020); 608 PHY_WRITE(sc, 0x00, 0x1000); 609 PHY_WRITE(sc, 0x04, 0x0800); 610 PHY_WRITE(sc, 0x04, 0x0000); 611 PHY_WRITE(sc, 0x04, 0x7000); 612 PHY_WRITE(sc, 0x03, 0xff41); 613 PHY_WRITE(sc, 0x02, 0xde60); 614 PHY_WRITE(sc, 0x01, 0x0140); 615 PHY_WRITE(sc, 0x00, 0x0077); 616 PHY_WRITE(sc, 0x04, 0x7800); 617 PHY_WRITE(sc, 0x04, 0x7000); 618 PHY_WRITE(sc, 0x04, 0xa000); 619 PHY_WRITE(sc, 0x03, 0xdf01); 620 PHY_WRITE(sc, 0x02, 0xdf20); 621 PHY_WRITE(sc, 0x01, 0xff95); 622 PHY_WRITE(sc, 0x00, 0xfa00); 623 PHY_WRITE(sc, 0x04, 0xa800); 624 PHY_WRITE(sc, 0x04, 0xa000); 625 PHY_WRITE(sc, 0x04, 0xb000); 626 PHY_WRITE(sc, 0x0e, 0xff41); 627 PHY_WRITE(sc, 0x02, 0xde20); 628 PHY_WRITE(sc, 0x01, 0x0140); 629 PHY_WRITE(sc, 0x00, 0x00bb); 630 PHY_WRITE(sc, 0x04, 0xb800); 631 PHY_WRITE(sc, 0x04, 0xb000); 632 PHY_WRITE(sc, 0x04, 0xf000); 633 PHY_WRITE(sc, 0x03, 0xdf01); 634 PHY_WRITE(sc, 0x02, 0xdf20); 635 PHY_WRITE(sc, 0x01, 0xff95); 636 PHY_WRITE(sc, 0x00, 0xbf00); 637 PHY_WRITE(sc, 0x04, 0xf800); 638 PHY_WRITE(sc, 0x04, 0xf000); 639 PHY_WRITE(sc, 0x04, 0x0000); 640 PHY_WRITE(sc, 0x1f, 0x0000); 641 PHY_WRITE(sc, 0x0b, 0x0000); 642 643 #endif 644 645 DELAY(40); 646 } 647 648 static void 649 rgephy_reset(struct mii_softc *sc) 650 { 651 struct rgephy_softc *rsc = (struct rgephy_softc *)sc; 652 uint16_t ssr, phycr1; 653 654 mii_phy_reset(sc); 655 DELAY(1000); 656 657 if (sc->mii_mpd_model != MII_MODEL_REALTEK_RTL8251 && 658 sc->mii_mpd_rev < RGEPHY_8211B) { 659 rgephy_load_dspcode(sc); 660 } else if (sc->mii_mpd_rev == RGEPHY_8211C) { 661 /* RTL8211C(L) */ 662 PHY_READ(sc, RGEPHY_MII_SSR, &ssr); 663 if ((ssr & RGEPHY_SSR_ALDPS) != 0) { 664 ssr &= ~RGEPHY_SSR_ALDPS; 665 PHY_WRITE(sc, RGEPHY_MII_SSR, ssr); 666 } 667 } else if (sc->mii_mpd_rev == RGEPHY_8211E) { 668 /* RTL8211E */ 669 if (rsc->mii_no_rx_delay) { 670 /* Disable RX internal delay (undocumented) */ 671 PHY_WRITE(sc, 0x1f, 0x0007); 672 PHY_WRITE(sc, 0x1e, 0x00a4); 673 PHY_WRITE(sc, 0x1c, 0xb591); 674 PHY_WRITE(sc, 0x1f, 0x0000); 675 } 676 } else if (sc->mii_mpd_rev == RGEPHY_8211F) { 677 /* RTL8211F */ 678 PHY_READ(sc, RGEPHY_MII_PHYCR1, &phycr1); 679 phycr1 &= ~RGEPHY_PHYCR1_MDI_MMCE; 680 phycr1 &= ~RGEPHY_PHYCR1_ALDPS_EN; 681 PHY_WRITE(sc, RGEPHY_MII_PHYCR1, phycr1); 682 } else { 683 PHY_WRITE(sc, 0x1F, 0x0000); 684 PHY_WRITE(sc, 0x0e, 0x0000); 685 } 686 687 /* Reset capabilities */ 688 /* Step1: write our capability */ 689 /* 10/100 capability */ 690 PHY_WRITE(sc, MII_ANAR, 691 ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 692 /* 1000 capability */ 693 PHY_WRITE(sc, MII_100T2CR, GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX); 694 695 /* Step2: Restart NWay */ 696 /* NWay enable and Restart NWay */ 697 PHY_WRITE(sc, MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 698 699 if (sc->mii_mpd_rev >= RGEPHY_8211D) { 700 /* RTL8211F */ 701 delay(10000); 702 /* disable EEE */ 703 PHY_WRITE(sc, MII_MMDACR, MMDACR_FN_ADDRESS | MDIO_MMD_AN); 704 PHY_WRITE(sc, MII_MMDAADR, MDIO_AN_EEEADVERT); 705 PHY_WRITE(sc, MII_MMDACR, MMDACR_FN_DATANPI | MDIO_MMD_AN); 706 PHY_WRITE(sc, MII_MMDAADR, 0x0000); 707 } 708 } 709
Indexes created Thu Oct 02 14:10:14 GMT 2025