rgephy.c revision 1.52
1 /* $NetBSD: rgephy.c,v 1.52 2019/03/25 09:20:46 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 2003 5 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: rgephy.c,v 1.52 2019/03/25 09:20:46 msaitoh Exp $"); 37 38 39 /* 40 * Driver for the RealTek 8169S/8110S internal 10/100/1000 PHY. 41 */ 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/kernel.h> 46 #include <sys/device.h> 47 #include <sys/socket.h> 48 49 50 #include <net/if.h> 51 #include <net/if_media.h> 52 53 #include <dev/mii/mii.h> 54 #include <dev/mii/mdio.h> 55 #include <dev/mii/miivar.h> 56 #include <dev/mii/miidevs.h> 57 58 #include <dev/mii/rgephyreg.h> 59 60 #include <dev/ic/rtl81x9reg.h> 61 62 static int rgephy_match(device_t, cfdata_t, void *); 63 static void rgephy_attach(device_t, device_t, void *); 64 65 struct rgephy_softc { 66 struct mii_softc mii_sc; 67 bool mii_no_rx_delay; 68 }; 69 70 CFATTACH_DECL_NEW(rgephy, sizeof(struct rgephy_softc), 71 rgephy_match, rgephy_attach, mii_phy_detach, mii_phy_activate); 72 73 74 static int rgephy_service(struct mii_softc *, struct mii_data *, int); 75 static void rgephy_status(struct mii_softc *); 76 static int rgephy_mii_phy_auto(struct mii_softc *); 77 static void rgephy_reset(struct mii_softc *); 78 static void rgephy_loop(struct mii_softc *); 79 static void rgephy_load_dspcode(struct mii_softc *); 80 81 static const struct mii_phy_funcs rgephy_funcs = { 82 rgephy_service, rgephy_status, rgephy_reset, 83 }; 84 85 static const struct mii_phydesc rgephys[] = { 86 MII_PHY_DESC(xxREALTEK, RTL8169S), 87 MII_PHY_DESC(REALTEK, RTL8169S), 88 MII_PHY_DESC(REALTEK, RTL8251), 89 MII_PHY_END, 90 }; 91 92 static int 93 rgephy_match(device_t parent, cfdata_t match, void *aux) 94 { 95 struct mii_attach_args *ma = aux; 96 97 if (mii_phy_match(ma, rgephys) != NULL) 98 return 10; 99 100 return 0; 101 } 102 103 static void 104 rgephy_attach(device_t parent, device_t self, void *aux) 105 { 106 struct rgephy_softc *rsc = device_private(self); 107 prop_dictionary_t prop = device_properties(self); 108 struct mii_softc *sc = &rsc->mii_sc; 109 struct mii_attach_args *ma = aux; 110 struct mii_data *mii = ma->mii_data; 111 const struct mii_phydesc *mpd; 112 int rev; 113 const char *sep = ""; 114 115 ma = aux; 116 mii = ma->mii_data; 117 118 rev = MII_REV(ma->mii_id2); 119 mpd = mii_phy_match(ma, rgephys); 120 aprint_naive(": Media interface\n"); 121 122 sc->mii_dev = self; 123 sc->mii_inst = mii->mii_instance; 124 sc->mii_phy = ma->mii_phyno; 125 sc->mii_mpd_oui = MII_OUI(ma->mii_id1, ma->mii_id2); 126 sc->mii_mpd_model = MII_MODEL(ma->mii_id2); 127 sc->mii_mpd_rev = MII_REV(ma->mii_id2); 128 129 if (sc->mii_mpd_model == MII_MODEL_REALTEK_RTL8169S) { 130 aprint_normal(": RTL8211"); 131 if (sc->mii_mpd_rev != 0) 132 aprint_normal("%c",'@' + sc->mii_mpd_rev); 133 aprint_normal(" 1000BASE-T media interface\n"); 134 } else 135 aprint_normal(": %s, rev. %d\n", mpd->mpd_name, rev); 136 137 sc->mii_pdata = mii; 138 sc->mii_flags = ma->mii_flags; 139 sc->mii_anegticks = MII_ANEGTICKS_GIGE; 140 141 sc->mii_funcs = &rgephy_funcs; 142 143 prop_dictionary_get_bool(prop, "no-rx-delay", &rsc->mii_no_rx_delay); 144 145 #define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL) 146 #define PRINT(n) aprint_normal("%s%s", sep, (n)); sep = ", " 147 148 #ifdef __FreeBSD__ 149 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst), 150 BMCR_LOOP | BMCR_S100); 151 #endif 152 153 PHY_READ(sc, MII_BMSR, &sc->mii_capabilities); 154 sc->mii_capabilities &= ma->mii_capmask; 155 sc->mii_capabilities &= ~BMSR_ANEG; 156 157 /* 158 * FreeBSD does not check EXSTAT, but instead adds gigabit 159 * media explicitly. Why? 160 */ 161 aprint_normal_dev(self, ""); 162 if (sc->mii_capabilities & BMSR_EXTSTAT) 163 PHY_READ(sc, MII_EXTSR, &sc->mii_extcapabilities); 164 165 mii_phy_add_media(sc); 166 167 /* rtl8169S does not report auto-sense; add manually. */ 168 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), MII_NMEDIA); 169 sep =", "; 170 PRINT("auto"); 171 172 #undef ADD 173 #undef PRINT 174 175 rgephy_reset(sc); 176 aprint_normal("\n"); 177 } 178 179 static int 180 rgephy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 181 { 182 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 183 uint16_t reg, speed, gig, anar; 184 185 switch (cmd) { 186 case MII_POLLSTAT: 187 /* If we're not polling our PHY instance, just return. */ 188 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 189 return 0; 190 break; 191 192 case MII_MEDIACHG: 193 /* 194 * If the media indicates a different PHY instance, 195 * isolate ourselves. 196 */ 197 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 198 PHY_READ(sc, MII_BMCR, ®); 199 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO); 200 return 0; 201 } 202 203 /* If the interface is not up, don't do anything. */ 204 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 205 break; 206 207 rgephy_reset(sc); /* XXX hardware bug work-around */ 208 209 PHY_READ(sc, MII_ANAR, &anar); 210 anar &= ~(ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10); 211 212 switch (IFM_SUBTYPE(ife->ifm_media)) { 213 case IFM_AUTO: 214 #ifdef foo 215 /* If we're already in auto mode, just return. */ 216 PHY_READ(sc, MII_BMCR, ®); 217 if (reg & BMCR_AUTOEN) 218 return 0; 219 #endif 220 (void)rgephy_mii_phy_auto(sc); 221 break; 222 case IFM_1000_T: 223 speed = BMCR_S1000; 224 goto setit; 225 case IFM_100_TX: 226 speed = BMCR_S100; 227 anar |= ANAR_TX_FD | ANAR_TX; 228 goto setit; 229 case IFM_10_T: 230 speed = BMCR_S10; 231 anar |= ANAR_10_FD | ANAR_10; 232 setit: 233 rgephy_loop(sc); 234 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 235 speed |= BMCR_FDX; 236 gig = GTCR_ADV_1000TFDX; 237 anar &= ~(ANAR_TX | ANAR_10); 238 } else { 239 gig = GTCR_ADV_1000THDX; 240 anar &= ~(ANAR_TX_FD | ANAR_10_FD); 241 } 242 243 if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T) { 244 PHY_WRITE(sc, MII_100T2CR, 0); 245 PHY_WRITE(sc, MII_ANAR, anar); 246 PHY_WRITE(sc, MII_BMCR, 247 speed | BMCR_AUTOEN | BMCR_STARTNEG); 248 break; 249 } 250 251 /* 252 * When setting the link manually, one side must be the 253 * master and the other the slave. However ifmedia 254 * doesn't give us a good way to specify this, so we 255 * fake it by using one of the LINK flags. If LINK0 is 256 * set, we program the PHY to be a master, otherwise 257 * it's a slave. 258 */ 259 if ((mii->mii_ifp->if_flags & IFF_LINK0)) { 260 PHY_WRITE(sc, MII_100T2CR, 261 gig | GTCR_MAN_MS | GTCR_ADV_MS); 262 } else { 263 PHY_WRITE(sc, MII_100T2CR, gig | GTCR_MAN_MS); 264 } 265 PHY_WRITE(sc, MII_BMCR, 266 speed | BMCR_AUTOEN | BMCR_STARTNEG); 267 break; 268 case IFM_NONE: 269 PHY_WRITE(sc, MII_BMCR, BMCR_ISO | BMCR_PDOWN); 270 break; 271 case IFM_100_T4: 272 default: 273 return EINVAL; 274 } 275 break; 276 277 case MII_TICK: 278 /* If we're not currently selected, just return. */ 279 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 280 return 0; 281 282 /* Is the interface even up? */ 283 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 284 return 0; 285 286 /* Only used for autonegotiation. */ 287 if ((IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) && 288 (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T)) { 289 /* 290 * Reset autonegotiation timer to 0 to make sure 291 * the future autonegotiation start with 0. 292 */ 293 sc->mii_ticks = 0; 294 break; 295 } 296 297 /* 298 * Check to see if we have link. If we do, we don't 299 * need to restart the autonegotiation process. Read 300 * the BMSR twice in case it's latched. 301 */ 302 if (sc->mii_mpd_rev >= RGEPHY_8211F) { 303 /* RTL8211F */ 304 PHY_READ(sc, RGEPHY_MII_PHYSR, ®); 305 if (reg & RGEPHY_PHYSR_LINK) { 306 sc->mii_ticks = 0; 307 break; 308 } 309 } else if (sc->mii_mpd_rev >= RGEPHY_8211B) { 310 /* RTL8211B(L) */ 311 PHY_READ(sc, RGEPHY_MII_SSR, ®); 312 if (reg & RGEPHY_SSR_LINK) { 313 sc->mii_ticks = 0; 314 break; 315 } 316 } else { 317 PHY_READ(sc, RTK_GMEDIASTAT, ®); 318 if ((reg & RTK_GMEDIASTAT_LINK) != 0) { 319 sc->mii_ticks = 0; 320 break; 321 } 322 } 323 324 /* Announce link loss right after it happens. */ 325 if (sc->mii_ticks++ == 0) 326 break; 327 328 /* Only retry autonegotiation every mii_anegticks seconds. */ 329 if (sc->mii_ticks <= sc->mii_anegticks) 330 return 0; 331 332 rgephy_mii_phy_auto(sc); 333 break; 334 } 335 336 /* Update the media status. */ 337 rgephy_status(sc); 338 339 /* 340 * Callback if something changed. Note that we need to poke 341 * the DSP on the RealTek PHYs if the media changes. 342 * 343 */ 344 if (sc->mii_media_active != mii->mii_media_active || 345 sc->mii_media_status != mii->mii_media_status || 346 cmd == MII_MEDIACHG) { 347 rgephy_load_dspcode(sc); 348 } 349 mii_phy_update(sc, cmd); 350 return 0; 351 } 352 353 static void 354 rgephy_status(struct mii_softc *sc) 355 { 356 struct mii_data *mii = sc->mii_pdata; 357 uint16_t gstat, bmsr, bmcr, physr, ssr; 358 359 mii->mii_media_status = IFM_AVALID; 360 mii->mii_media_active = IFM_ETHER; 361 362 if (sc->mii_mpd_rev >= RGEPHY_8211F) { 363 PHY_READ(sc, RGEPHY_MII_PHYSR, &physr); 364 if (physr & RGEPHY_PHYSR_LINK) 365 mii->mii_media_status |= IFM_ACTIVE; 366 } else if (sc->mii_mpd_rev >= RGEPHY_8211B) { 367 PHY_READ(sc, RGEPHY_MII_SSR, &ssr); 368 if (ssr & RGEPHY_SSR_LINK) 369 mii->mii_media_status |= IFM_ACTIVE; 370 } else { 371 PHY_READ(sc, RTK_GMEDIASTAT, &gstat); 372 if ((gstat & RTK_GMEDIASTAT_LINK) != 0) 373 mii->mii_media_status |= IFM_ACTIVE; 374 } 375 376 PHY_READ(sc, MII_BMSR, &bmsr); 377 PHY_READ(sc, MII_BMCR, &bmcr); 378 379 if ((bmcr & BMCR_ISO) != 0) { 380 mii->mii_media_active |= IFM_NONE; 381 mii->mii_media_status = 0; 382 return; 383 } 384 385 if ((bmcr & BMCR_LOOP) != 0) 386 mii->mii_media_active |= IFM_LOOP; 387 388 if ((bmcr & BMCR_AUTOEN) != 0) { 389 if ((bmsr & BMSR_ACOMP) == 0) { 390 /* Erg, still trying, I guess... */ 391 mii->mii_media_active |= IFM_NONE; 392 return; 393 } 394 } 395 396 if (sc->mii_mpd_rev >= RGEPHY_8211F) { 397 PHY_READ(sc, RGEPHY_MII_PHYSR, &physr); 398 switch (__SHIFTOUT(physr, RGEPHY_PHYSR_SPEED)) { 399 case RGEPHY_PHYSR_SPEED_1000: 400 mii->mii_media_active |= IFM_1000_T; 401 break; 402 case RGEPHY_PHYSR_SPEED_100: 403 mii->mii_media_active |= IFM_100_TX; 404 break; 405 case RGEPHY_PHYSR_SPEED_10: 406 mii->mii_media_active |= IFM_10_T; 407 break; 408 default: 409 mii->mii_media_active |= IFM_NONE; 410 break; 411 } 412 if (physr & RGEPHY_PHYSR_DUPLEX) 413 mii->mii_media_active |= mii_phy_flowstatus(sc) | 414 IFM_FDX; 415 else 416 mii->mii_media_active |= IFM_HDX; 417 } else if (sc->mii_mpd_rev >= RGEPHY_8211B) { 418 PHY_READ(sc, RGEPHY_MII_SSR, &ssr); 419 switch (ssr & RGEPHY_SSR_SPD_MASK) { 420 case RGEPHY_SSR_S1000: 421 mii->mii_media_active |= IFM_1000_T; 422 break; 423 case RGEPHY_SSR_S100: 424 mii->mii_media_active |= IFM_100_TX; 425 break; 426 case RGEPHY_SSR_S10: 427 mii->mii_media_active |= IFM_10_T; 428 break; 429 default: 430 mii->mii_media_active |= IFM_NONE; 431 break; 432 } 433 if (ssr & RGEPHY_SSR_FDX) 434 mii->mii_media_active |= mii_phy_flowstatus(sc) | 435 IFM_FDX; 436 else 437 mii->mii_media_active |= IFM_HDX; 438 } else { 439 PHY_READ(sc, RTK_GMEDIASTAT, &gstat); 440 if ((gstat & RTK_GMEDIASTAT_1000MBPS) != 0) 441 mii->mii_media_active |= IFM_1000_T; 442 else if ((gstat & RTK_GMEDIASTAT_100MBPS) != 0) 443 mii->mii_media_active |= IFM_100_TX; 444 else if ((gstat & RTK_GMEDIASTAT_10MBPS) != 0) 445 mii->mii_media_active |= IFM_10_T; 446 else 447 mii->mii_media_active |= IFM_NONE; 448 if ((gstat & RTK_GMEDIASTAT_FDX) != 0) 449 mii->mii_media_active |= mii_phy_flowstatus(sc) | 450 IFM_FDX; 451 else 452 mii->mii_media_active |= IFM_HDX; 453 } 454 } 455 456 static int 457 rgephy_mii_phy_auto(struct mii_softc *mii) 458 { 459 int anar; 460 461 mii->mii_ticks = 0; 462 rgephy_loop(mii); 463 rgephy_reset(mii); 464 465 anar = BMSR_MEDIA_TO_ANAR(mii->mii_capabilities) | ANAR_CSMA; 466 if (mii->mii_flags & MIIF_DOPAUSE) 467 anar |= ANAR_FC | ANAR_PAUSE_ASYM; 468 469 PHY_WRITE(mii, MII_ANAR, anar); 470 DELAY(1000); 471 PHY_WRITE(mii, MII_100T2CR, GTCR_ADV_1000THDX | GTCR_ADV_1000TFDX); 472 DELAY(1000); 473 PHY_WRITE(mii, MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG); 474 DELAY(100); 475 476 return EJUSTRETURN; 477 } 478 479 static void 480 rgephy_loop(struct mii_softc *sc) 481 { 482 uint16_t bmsr; 483 int i; 484 485 if (sc->mii_mpd_model != MII_MODEL_REALTEK_RTL8251 && 486 sc->mii_mpd_rev < RGEPHY_8211B) { 487 PHY_WRITE(sc, MII_BMCR, BMCR_PDOWN); 488 DELAY(1000); 489 } 490 491 for (i = 0; i < 15000; i++) { 492 PHY_READ(sc, MII_BMSR, &bmsr); 493 if ((bmsr & BMSR_LINK) == 0) { 494 #if 0 495 device_printf(sc->mii_dev, "looped %d\n", i); 496 #endif 497 break; 498 } 499 DELAY(10); 500 } 501 } 502 503 static inline int 504 PHY_SETBIT(struct mii_softc *sc, int y, uint16_t z) 505 { 506 uint16_t _tmp; 507 int rv; 508 509 if ((rv = PHY_READ(sc, y, &_tmp)) != 0) 510 return rv; 511 return PHY_WRITE(sc, y, _tmp | z); 512 } 513 514 static inline int 515 PHY_CLRBIT(struct mii_softc *sc, int y, uint16_t z) 516 { 517 uint16_t _tmp; 518 int rv; 519 520 if ((rv = PHY_READ(sc, y, &_tmp)) != 0) 521 return rv; 522 return PHY_WRITE(sc, y, _tmp & ~z); 523 } 524 525 /* 526 * Initialize RealTek PHY per the datasheet. The DSP in the PHYs of existing 527 * revisions of the 8169S/8110S chips need to be tuned in order to reliably 528 * negotiate a 1000Mbps link. This is only needed for rev 0 and rev 1 of the 529 * PHY. Later versions work without any fixups. 530 */ 531 static void 532 rgephy_load_dspcode(struct mii_softc *sc) 533 { 534 uint16_t val; 535 536 if (sc->mii_mpd_model == MII_MODEL_REALTEK_RTL8251 || 537 sc->mii_mpd_rev >= RGEPHY_8211B) 538 return; 539 540 #if 1 541 PHY_WRITE(sc, 31, 0x0001); 542 PHY_WRITE(sc, 21, 0x1000); 543 PHY_WRITE(sc, 24, 0x65C7); 544 PHY_CLRBIT(sc, 4, 0x0800); 545 PHY_READ(sc, 4, &val); 546 val &= 0xFFF; 547 PHY_WRITE(sc, 4, val); 548 PHY_WRITE(sc, 3, 0x00A1); 549 PHY_WRITE(sc, 2, 0x0008); 550 PHY_WRITE(sc, 1, 0x1020); 551 PHY_WRITE(sc, 0, 0x1000); 552 PHY_SETBIT(sc, 4, 0x0800); 553 PHY_CLRBIT(sc, 4, 0x0800); 554 PHY_READ(sc, 4, &val); 555 val = (val & 0xFFF) | 0x7000; 556 PHY_WRITE(sc, 4, val); 557 PHY_WRITE(sc, 3, 0xFF41); 558 PHY_WRITE(sc, 2, 0xDE60); 559 PHY_WRITE(sc, 1, 0x0140); 560 PHY_WRITE(sc, 0, 0x0077); 561 PHY_READ(sc, 4, &val); 562 val = (val & 0xFFF) | 0xA000; 563 PHY_WRITE(sc, 4, val); 564 PHY_WRITE(sc, 3, 0xDF01); 565 PHY_WRITE(sc, 2, 0xDF20); 566 PHY_WRITE(sc, 1, 0xFF95); 567 PHY_WRITE(sc, 0, 0xFA00); 568 PHY_READ(sc, 4, &val); 569 val = (val & 0xFFF) | 0xB000; 570 PHY_WRITE(sc, 4, val); 571 PHY_WRITE(sc, 3, 0xFF41); 572 PHY_WRITE(sc, 2, 0xDE20); 573 PHY_WRITE(sc, 1, 0x0140); 574 PHY_WRITE(sc, 0, 0x00BB); 575 PHY_READ(sc, 4, &val); 576 val = (val & 0xFFF) | 0xF000; 577 PHY_WRITE(sc, 4, val); 578 PHY_WRITE(sc, 3, 0xDF01); 579 PHY_WRITE(sc, 2, 0xDF20); 580 PHY_WRITE(sc, 1, 0xFF95); 581 PHY_WRITE(sc, 0, 0xBF00); 582 PHY_SETBIT(sc, 4, 0x0800); 583 PHY_CLRBIT(sc, 4, 0x0800); 584 PHY_WRITE(sc, 31, 0x0000); 585 #else 586 (void)val; 587 PHY_WRITE(sc, 0x1f, 0x0001); 588 PHY_WRITE(sc, 0x15, 0x1000); 589 PHY_WRITE(sc, 0x18, 0x65c7); 590 PHY_WRITE(sc, 0x04, 0x0000); 591 PHY_WRITE(sc, 0x03, 0x00a1); 592 PHY_WRITE(sc, 0x02, 0x0008); 593 PHY_WRITE(sc, 0x01, 0x1020); 594 PHY_WRITE(sc, 0x00, 0x1000); 595 PHY_WRITE(sc, 0x04, 0x0800); 596 PHY_WRITE(sc, 0x04, 0x0000); 597 PHY_WRITE(sc, 0x04, 0x7000); 598 PHY_WRITE(sc, 0x03, 0xff41); 599 PHY_WRITE(sc, 0x02, 0xde60); 600 PHY_WRITE(sc, 0x01, 0x0140); 601 PHY_WRITE(sc, 0x00, 0x0077); 602 PHY_WRITE(sc, 0x04, 0x7800); 603 PHY_WRITE(sc, 0x04, 0x7000); 604 PHY_WRITE(sc, 0x04, 0xa000); 605 PHY_WRITE(sc, 0x03, 0xdf01); 606 PHY_WRITE(sc, 0x02, 0xdf20); 607 PHY_WRITE(sc, 0x01, 0xff95); 608 PHY_WRITE(sc, 0x00, 0xfa00); 609 PHY_WRITE(sc, 0x04, 0xa800); 610 PHY_WRITE(sc, 0x04, 0xa000); 611 PHY_WRITE(sc, 0x04, 0xb000); 612 PHY_WRITE(sc, 0x0e, 0xff41); 613 PHY_WRITE(sc, 0x02, 0xde20); 614 PHY_WRITE(sc, 0x01, 0x0140); 615 PHY_WRITE(sc, 0x00, 0x00bb); 616 PHY_WRITE(sc, 0x04, 0xb800); 617 PHY_WRITE(sc, 0x04, 0xb000); 618 PHY_WRITE(sc, 0x04, 0xf000); 619 PHY_WRITE(sc, 0x03, 0xdf01); 620 PHY_WRITE(sc, 0x02, 0xdf20); 621 PHY_WRITE(sc, 0x01, 0xff95); 622 PHY_WRITE(sc, 0x00, 0xbf00); 623 PHY_WRITE(sc, 0x04, 0xf800); 624 PHY_WRITE(sc, 0x04, 0xf000); 625 PHY_WRITE(sc, 0x04, 0x0000); 626 PHY_WRITE(sc, 0x1f, 0x0000); 627 PHY_WRITE(sc, 0x0b, 0x0000); 628 629 #endif 630 631 DELAY(40); 632 } 633 634 static void 635 rgephy_reset(struct mii_softc *sc) 636 { 637 struct rgephy_softc *rsc = (struct rgephy_softc *)sc; 638 uint16_t ssr, phycr1; 639 640 mii_phy_reset(sc); 641 DELAY(1000); 642 643 if (sc->mii_mpd_model != MII_MODEL_REALTEK_RTL8251 && 644 sc->mii_mpd_rev < RGEPHY_8211B) { 645 rgephy_load_dspcode(sc); 646 } else if (sc->mii_mpd_rev == RGEPHY_8211C) { 647 /* RTL8211C(L) */ 648 PHY_READ(sc, RGEPHY_MII_SSR, &ssr); 649 if ((ssr & RGEPHY_SSR_ALDPS) != 0) { 650 ssr &= ~RGEPHY_SSR_ALDPS; 651 PHY_WRITE(sc, RGEPHY_MII_SSR, ssr); 652 } 653 } else if (sc->mii_mpd_rev == RGEPHY_8211E) { 654 /* RTL8211E */ 655 if (rsc->mii_no_rx_delay) { 656 /* Disable RX internal delay (undocumented) */ 657 PHY_WRITE(sc, 0x1f, 0x0007); 658 PHY_WRITE(sc, 0x1e, 0x00a4); 659 PHY_WRITE(sc, 0x1c, 0xb591); 660 PHY_WRITE(sc, 0x1f, 0x0000); 661 } 662 } else if (sc->mii_mpd_rev == RGEPHY_8211F) { 663 /* RTL8211F */ 664 PHY_READ(sc, RGEPHY_MII_PHYCR1, &phycr1); 665 phycr1 &= ~RGEPHY_PHYCR1_MDI_MMCE; 666 phycr1 &= ~RGEPHY_PHYCR1_ALDPS_EN; 667 PHY_WRITE(sc, RGEPHY_MII_PHYCR1, phycr1); 668 } else { 669 PHY_WRITE(sc, 0x1F, 0x0000); 670 PHY_WRITE(sc, 0x0e, 0x0000); 671 } 672 673 /* Reset capabilities */ 674 /* Step1: write our capability */ 675 /* 10/100 capability */ 676 PHY_WRITE(sc, MII_ANAR, 677 ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 678 /* 1000 capability */ 679 PHY_WRITE(sc, MII_100T2CR, GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX); 680 681 /* Step2: Restart NWay */ 682 /* NWay enable and Restart NWay */ 683 PHY_WRITE(sc, MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 684 685 if (sc->mii_mpd_rev >= RGEPHY_8211D) { 686 /* RTL8211F */ 687 delay(10000); 688 /* disable EEE */ 689 MMD_INDIRECT_WRITE(sc, MDIO_MMD_AN | MMDACR_FN_DATA, 690 MDIO_AN_EEEADVERT, 0x0000); 691 } 692 } 693
Indexes created Thu Oct 02 10:09:58 GMT 2025