rgephy.c revision 1.58
1 /* $NetBSD: rgephy.c,v 1.58 2019/11/27 10:19:21 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 2003 5 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: rgephy.c,v 1.58 2019/11/27 10:19:21 msaitoh Exp $"); 37 38 39 /* 40 * Driver for the RealTek 8169S/8110S internal 10/100/1000 PHY. 41 */ 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/kernel.h> 46 #include <sys/device.h> 47 #include <sys/socket.h> 48 49 50 #include <net/if.h> 51 #include <net/if_media.h> 52 53 #include <dev/mii/mii.h> 54 #include <dev/mii/mdio.h> 55 #include <dev/mii/miivar.h> 56 #include <dev/mii/miidevs.h> 57 58 #include <dev/mii/rgephyreg.h> 59 60 #include <dev/ic/rtl81x9reg.h> 61 62 static int rgephy_match(device_t, cfdata_t, void *); 63 static void rgephy_attach(device_t, device_t, void *); 64 65 struct rgephy_softc { 66 struct mii_softc mii_sc; 67 bool mii_no_rx_delay; 68 }; 69 70 CFATTACH_DECL_NEW(rgephy, sizeof(struct rgephy_softc), 71 rgephy_match, rgephy_attach, mii_phy_detach, mii_phy_activate); 72 73 74 static int rgephy_service(struct mii_softc *, struct mii_data *, int); 75 static void rgephy_status(struct mii_softc *); 76 static int rgephy_mii_phy_auto(struct mii_softc *); 77 static void rgephy_reset(struct mii_softc *); 78 static bool rgephy_linkup(struct mii_softc *); 79 static void rgephy_loop(struct mii_softc *); 80 static void rgephy_load_dspcode(struct mii_softc *); 81 82 static const struct mii_phy_funcs rgephy_funcs = { 83 rgephy_service, rgephy_status, rgephy_reset, 84 }; 85 86 static const struct mii_phydesc rgephys[] = { 87 MII_PHY_DESC(xxREALTEK, RTL8169S), 88 MII_PHY_DESC(REALTEK, RTL8169S), 89 MII_PHY_DESC(REALTEK, RTL8251), 90 MII_PHY_END, 91 }; 92 93 static int 94 rgephy_match(device_t parent, cfdata_t match, void *aux) 95 { 96 struct mii_attach_args *ma = aux; 97 98 if (mii_phy_match(ma, rgephys) != NULL) 99 return 10; 100 101 return 0; 102 } 103 104 static void 105 rgephy_attach(device_t parent, device_t self, void *aux) 106 { 107 struct rgephy_softc *rsc = device_private(self); 108 prop_dictionary_t prop = device_properties(self); 109 struct mii_softc *sc = &rsc->mii_sc; 110 struct mii_attach_args *ma = aux; 111 struct mii_data *mii = ma->mii_data; 112 const struct mii_phydesc *mpd; 113 int rev; 114 115 rev = MII_REV(ma->mii_id2); 116 mpd = mii_phy_match(ma, rgephys); 117 aprint_naive(": Media interface\n"); 118 119 sc->mii_dev = self; 120 sc->mii_inst = mii->mii_instance; 121 sc->mii_phy = ma->mii_phyno; 122 sc->mii_mpd_oui = MII_OUI(ma->mii_id1, ma->mii_id2); 123 sc->mii_mpd_model = MII_MODEL(ma->mii_id2); 124 sc->mii_mpd_rev = MII_REV(ma->mii_id2); 125 126 if (sc->mii_mpd_model == MII_MODEL_REALTEK_RTL8169S) { 127 aprint_normal(": RTL8211"); 128 if (sc->mii_mpd_rev != 0) 129 aprint_normal("%c",'@' + sc->mii_mpd_rev); 130 aprint_normal(" 1000BASE-T media interface\n"); 131 } else 132 aprint_normal(": %s, rev. %d\n", mpd->mpd_name, rev); 133 134 sc->mii_pdata = mii; 135 sc->mii_flags = ma->mii_flags; 136 137 sc->mii_funcs = &rgephy_funcs; 138 139 prop_dictionary_get_bool(prop, "no-rx-delay", &rsc->mii_no_rx_delay); 140 141 #ifdef __FreeBSD__ 142 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst), 143 BMCR_LOOP | BMCR_S100); 144 #endif 145 146 PHY_READ(sc, MII_BMSR, &sc->mii_capabilities); 147 sc->mii_capabilities &= ma->mii_capmask; 148 /* RTL8169S does not report auto-sense; add manually. */ 149 sc->mii_capabilities |= BMSR_ANEG; 150 151 /* 152 * FreeBSD does not check EXSTAT, but instead adds gigabit 153 * media explicitly. Why? 154 */ 155 if (sc->mii_capabilities & BMSR_EXTSTAT) 156 PHY_READ(sc, MII_EXTSR, &sc->mii_extcapabilities); 157 158 mii_phy_add_media(sc); 159 160 rgephy_reset(sc); 161 } 162 163 static int 164 rgephy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 165 { 166 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 167 uint16_t reg, speed, gig, anar; 168 169 switch (cmd) { 170 case MII_POLLSTAT: 171 /* If we're not polling our PHY instance, just return. */ 172 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 173 return 0; 174 break; 175 176 case MII_MEDIACHG: 177 /* 178 * If the media indicates a different PHY instance, 179 * isolate ourselves. 180 */ 181 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 182 PHY_READ(sc, MII_BMCR, ®); 183 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO); 184 return 0; 185 } 186 187 /* If the interface is not up, don't do anything. */ 188 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 189 break; 190 191 rgephy_reset(sc); /* XXX hardware bug work-around */ 192 193 PHY_READ(sc, MII_ANAR, &anar); 194 anar &= ~(ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10); 195 196 switch (IFM_SUBTYPE(ife->ifm_media)) { 197 case IFM_AUTO: 198 #ifdef foo 199 /* If we're already in auto mode, just return. */ 200 PHY_READ(sc, MII_BMCR, ®); 201 if (reg & BMCR_AUTOEN) 202 return 0; 203 #endif 204 (void)rgephy_mii_phy_auto(sc); 205 break; 206 case IFM_1000_T: 207 speed = BMCR_S1000; 208 goto setit; 209 case IFM_100_TX: 210 speed = BMCR_S100; 211 anar |= ANAR_TX_FD | ANAR_TX; 212 goto setit; 213 case IFM_10_T: 214 speed = BMCR_S10; 215 anar |= ANAR_10_FD | ANAR_10; 216 setit: 217 rgephy_loop(sc); 218 if ((ife->ifm_media & IFM_FDX) != 0) { 219 speed |= BMCR_FDX; 220 gig = GTCR_ADV_1000TFDX; 221 anar &= ~(ANAR_TX | ANAR_10); 222 } else { 223 gig = GTCR_ADV_1000THDX; 224 anar &= ~(ANAR_TX_FD | ANAR_10_FD); 225 } 226 227 if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T) { 228 PHY_WRITE(sc, MII_100T2CR, 0); 229 PHY_WRITE(sc, MII_ANAR, anar); 230 PHY_WRITE(sc, MII_BMCR, 231 speed | BMCR_AUTOEN | BMCR_STARTNEG); 232 break; 233 } 234 235 /* 236 * When setting the link manually, one side must be the 237 * master and the other the slave. However ifmedia 238 * doesn't give us a good way to specify this, so we 239 * fake it by using one of the LINK flags. If LINK0 is 240 * set, we program the PHY to be a master, otherwise 241 * it's a slave. 242 */ 243 if ((mii->mii_ifp->if_flags & IFF_LINK0)) { 244 PHY_WRITE(sc, MII_100T2CR, 245 gig | GTCR_MAN_MS | GTCR_ADV_MS); 246 } else 247 PHY_WRITE(sc, MII_100T2CR, gig | GTCR_MAN_MS); 248 PHY_WRITE(sc, MII_BMCR, 249 speed | BMCR_AUTOEN | BMCR_STARTNEG); 250 break; 251 case IFM_NONE: 252 PHY_WRITE(sc, MII_BMCR, BMCR_ISO | BMCR_PDOWN); 253 break; 254 case IFM_100_T4: 255 default: 256 return EINVAL; 257 } 258 break; 259 260 case MII_TICK: 261 /* If we're not currently selected, just return. */ 262 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 263 return 0; 264 265 /* Is the interface even up? */ 266 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 267 return 0; 268 269 /* Only used for autonegotiation. */ 270 if ((IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) && 271 (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T)) { 272 /* 273 * Reset autonegotiation timer to 0 to make sure 274 * the future autonegotiation start with 0. 275 */ 276 sc->mii_ticks = 0; 277 break; 278 } 279 280 /* 281 * Check to see if we have link. If we do, we don't 282 * need to restart the autonegotiation process. Read 283 * the BMSR twice in case it's latched. 284 */ 285 if (rgephy_linkup(sc)) { 286 sc->mii_ticks = 0; 287 break; 288 } 289 290 /* Announce link loss right after it happens. */ 291 if (sc->mii_ticks++ == 0) 292 break; 293 294 /* Only retry autonegotiation every mii_anegticks seconds. */ 295 if (sc->mii_ticks <= sc->mii_anegticks) 296 return 0; 297 298 rgephy_mii_phy_auto(sc); 299 break; 300 } 301 302 /* Update the media status. */ 303 rgephy_status(sc); 304 305 /* 306 * Callback if something changed. Note that we need to poke 307 * the DSP on the RealTek PHYs if the media changes. 308 */ 309 if (sc->mii_media_active != mii->mii_media_active || 310 sc->mii_media_status != mii->mii_media_status || 311 cmd == MII_MEDIACHG) { 312 rgephy_load_dspcode(sc); 313 } 314 mii_phy_update(sc, cmd); 315 return 0; 316 } 317 318 static bool 319 rgephy_linkup(struct mii_softc *sc) 320 { 321 bool linkup = false; 322 uint16_t reg; 323 324 if (sc->mii_mpd_rev >= RGEPHY_8211F) { 325 PHY_READ(sc, RGEPHY_MII_PHYSR, ®); 326 if (reg & RGEPHY_PHYSR_LINK) 327 linkup = true; 328 } else if (sc->mii_mpd_rev >= RGEPHY_8211B) { 329 PHY_READ(sc, RGEPHY_MII_SSR, ®); 330 if (reg & RGEPHY_SSR_LINK) 331 linkup = true; 332 } else { 333 PHY_READ(sc, RTK_GMEDIASTAT, ®); 334 if ((reg & RTK_GMEDIASTAT_LINK) != 0) 335 linkup = true; 336 } 337 338 return linkup; 339 } 340 341 static void 342 rgephy_status(struct mii_softc *sc) 343 { 344 struct mii_data *mii = sc->mii_pdata; 345 uint16_t gstat, bmsr, bmcr, gtsr, physr, ssr; 346 347 mii->mii_media_status = IFM_AVALID; 348 mii->mii_media_active = IFM_ETHER; 349 350 if (rgephy_linkup(sc)) 351 mii->mii_media_status |= IFM_ACTIVE; 352 353 PHY_READ(sc, MII_BMSR, &bmsr); 354 PHY_READ(sc, MII_BMCR, &bmcr); 355 356 if ((bmcr & BMCR_ISO) != 0) { 357 mii->mii_media_active |= IFM_NONE; 358 mii->mii_media_status = 0; 359 return; 360 } 361 362 if ((bmcr & BMCR_LOOP) != 0) 363 mii->mii_media_active |= IFM_LOOP; 364 365 if ((bmcr & BMCR_AUTOEN) != 0) { 366 if ((bmsr & BMSR_ACOMP) == 0) { 367 /* Erg, still trying, I guess... */ 368 mii->mii_media_active |= IFM_NONE; 369 return; 370 } 371 } 372 373 if (sc->mii_mpd_rev >= RGEPHY_8211F) { 374 PHY_READ(sc, RGEPHY_MII_PHYSR, &physr); 375 switch (__SHIFTOUT(physr, RGEPHY_PHYSR_SPEED)) { 376 case RGEPHY_PHYSR_SPEED_1000: 377 mii->mii_media_active |= IFM_1000_T; 378 break; 379 case RGEPHY_PHYSR_SPEED_100: 380 mii->mii_media_active |= IFM_100_TX; 381 break; 382 case RGEPHY_PHYSR_SPEED_10: 383 mii->mii_media_active |= IFM_10_T; 384 break; 385 default: 386 mii->mii_media_active |= IFM_NONE; 387 break; 388 } 389 if (physr & RGEPHY_PHYSR_DUPLEX) 390 mii->mii_media_active |= mii_phy_flowstatus(sc) | 391 IFM_FDX; 392 else 393 mii->mii_media_active |= IFM_HDX; 394 } else if (sc->mii_mpd_rev >= RGEPHY_8211B) { 395 PHY_READ(sc, RGEPHY_MII_SSR, &ssr); 396 switch (ssr & RGEPHY_SSR_SPD_MASK) { 397 case RGEPHY_SSR_S1000: 398 mii->mii_media_active |= IFM_1000_T; 399 break; 400 case RGEPHY_SSR_S100: 401 mii->mii_media_active |= IFM_100_TX; 402 break; 403 case RGEPHY_SSR_S10: 404 mii->mii_media_active |= IFM_10_T; 405 break; 406 default: 407 mii->mii_media_active |= IFM_NONE; 408 break; 409 } 410 if (ssr & RGEPHY_SSR_FDX) 411 mii->mii_media_active |= mii_phy_flowstatus(sc) | 412 IFM_FDX; 413 else 414 mii->mii_media_active |= IFM_HDX; 415 } else { 416 PHY_READ(sc, RTK_GMEDIASTAT, &gstat); 417 if ((gstat & RTK_GMEDIASTAT_1000MBPS) != 0) 418 mii->mii_media_active |= IFM_1000_T; 419 else if ((gstat & RTK_GMEDIASTAT_100MBPS) != 0) 420 mii->mii_media_active |= IFM_100_TX; 421 else if ((gstat & RTK_GMEDIASTAT_10MBPS) != 0) 422 mii->mii_media_active |= IFM_10_T; 423 else 424 mii->mii_media_active |= IFM_NONE; 425 if ((gstat & RTK_GMEDIASTAT_FDX) != 0) 426 mii->mii_media_active |= mii_phy_flowstatus(sc) | 427 IFM_FDX; 428 else 429 mii->mii_media_active |= IFM_HDX; 430 } 431 432 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) { 433 PHY_READ(sc, MII_GTSR, >sr); 434 if ((gtsr & GTSR_MS_RES) != 0) 435 mii->mii_media_active |= IFM_ETH_MASTER; 436 } 437 } 438 439 static int 440 rgephy_mii_phy_auto(struct mii_softc *mii) 441 { 442 int anar; 443 444 mii->mii_ticks = 0; 445 rgephy_loop(mii); 446 rgephy_reset(mii); 447 448 anar = BMSR_MEDIA_TO_ANAR(mii->mii_capabilities) | ANAR_CSMA; 449 if (mii->mii_flags & MIIF_DOPAUSE) 450 anar |= ANAR_FC | ANAR_PAUSE_ASYM; 451 452 PHY_WRITE(mii, MII_ANAR, anar); 453 DELAY(1000); 454 PHY_WRITE(mii, MII_100T2CR, GTCR_ADV_1000THDX | GTCR_ADV_1000TFDX); 455 DELAY(1000); 456 PHY_WRITE(mii, MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG); 457 DELAY(100); 458 459 return EJUSTRETURN; 460 } 461 462 static void 463 rgephy_loop(struct mii_softc *sc) 464 { 465 uint16_t bmsr; 466 int i; 467 468 if (sc->mii_mpd_model != MII_MODEL_REALTEK_RTL8251 && 469 sc->mii_mpd_rev < RGEPHY_8211B) { 470 PHY_WRITE(sc, MII_BMCR, BMCR_PDOWN); 471 DELAY(1000); 472 } 473 474 for (i = 0; i < 15000; i++) { 475 PHY_READ(sc, MII_BMSR, &bmsr); 476 if ((bmsr & BMSR_LINK) == 0) { 477 #if 0 478 device_printf(sc->mii_dev, "looped %d\n", i); 479 #endif 480 break; 481 } 482 DELAY(10); 483 } 484 } 485 486 static inline int 487 PHY_SETBIT(struct mii_softc *sc, int y, uint16_t z) 488 { 489 uint16_t _tmp; 490 int rv; 491 492 if ((rv = PHY_READ(sc, y, &_tmp)) != 0) 493 return rv; 494 return PHY_WRITE(sc, y, _tmp | z); 495 } 496 497 static inline int 498 PHY_CLRBIT(struct mii_softc *sc, int y, uint16_t z) 499 { 500 uint16_t _tmp; 501 int rv; 502 503 if ((rv = PHY_READ(sc, y, &_tmp)) != 0) 504 return rv; 505 return PHY_WRITE(sc, y, _tmp & ~z); 506 } 507 508 /* 509 * Initialize RealTek PHY per the datasheet. The DSP in the PHYs of existing 510 * revisions of the 8169S/8110S chips need to be tuned in order to reliably 511 * negotiate a 1000Mbps link. This is only needed for rev 0 and rev 1 of the 512 * PHY. Later versions work without any fixups. 513 */ 514 static void 515 rgephy_load_dspcode(struct mii_softc *sc) 516 { 517 uint16_t val; 518 519 if (sc->mii_mpd_model == MII_MODEL_REALTEK_RTL8251 || 520 sc->mii_mpd_rev >= RGEPHY_8211B) 521 return; 522 523 #if 1 524 PHY_WRITE(sc, 31, 0x0001); 525 PHY_WRITE(sc, 21, 0x1000); 526 PHY_WRITE(sc, 24, 0x65C7); 527 PHY_CLRBIT(sc, 4, 0x0800); 528 PHY_READ(sc, 4, &val); 529 val &= 0xFFF; 530 PHY_WRITE(sc, 4, val); 531 PHY_WRITE(sc, 3, 0x00A1); 532 PHY_WRITE(sc, 2, 0x0008); 533 PHY_WRITE(sc, 1, 0x1020); 534 PHY_WRITE(sc, 0, 0x1000); 535 PHY_SETBIT(sc, 4, 0x0800); 536 PHY_CLRBIT(sc, 4, 0x0800); 537 PHY_READ(sc, 4, &val); 538 val = (val & 0xFFF) | 0x7000; 539 PHY_WRITE(sc, 4, val); 540 PHY_WRITE(sc, 3, 0xFF41); 541 PHY_WRITE(sc, 2, 0xDE60); 542 PHY_WRITE(sc, 1, 0x0140); 543 PHY_WRITE(sc, 0, 0x0077); 544 PHY_READ(sc, 4, &val); 545 val = (val & 0xFFF) | 0xA000; 546 PHY_WRITE(sc, 4, val); 547 PHY_WRITE(sc, 3, 0xDF01); 548 PHY_WRITE(sc, 2, 0xDF20); 549 PHY_WRITE(sc, 1, 0xFF95); 550 PHY_WRITE(sc, 0, 0xFA00); 551 PHY_READ(sc, 4, &val); 552 val = (val & 0xFFF) | 0xB000; 553 PHY_WRITE(sc, 4, val); 554 PHY_WRITE(sc, 3, 0xFF41); 555 PHY_WRITE(sc, 2, 0xDE20); 556 PHY_WRITE(sc, 1, 0x0140); 557 PHY_WRITE(sc, 0, 0x00BB); 558 PHY_READ(sc, 4, &val); 559 val = (val & 0xFFF) | 0xF000; 560 PHY_WRITE(sc, 4, val); 561 PHY_WRITE(sc, 3, 0xDF01); 562 PHY_WRITE(sc, 2, 0xDF20); 563 PHY_WRITE(sc, 1, 0xFF95); 564 PHY_WRITE(sc, 0, 0xBF00); 565 PHY_SETBIT(sc, 4, 0x0800); 566 PHY_CLRBIT(sc, 4, 0x0800); 567 PHY_WRITE(sc, 31, 0x0000); 568 #else 569 (void)val; 570 PHY_WRITE(sc, 0x1f, 0x0001); 571 PHY_WRITE(sc, 0x15, 0x1000); 572 PHY_WRITE(sc, 0x18, 0x65c7); 573 PHY_WRITE(sc, 0x04, 0x0000); 574 PHY_WRITE(sc, 0x03, 0x00a1); 575 PHY_WRITE(sc, 0x02, 0x0008); 576 PHY_WRITE(sc, 0x01, 0x1020); 577 PHY_WRITE(sc, 0x00, 0x1000); 578 PHY_WRITE(sc, 0x04, 0x0800); 579 PHY_WRITE(sc, 0x04, 0x0000); 580 PHY_WRITE(sc, 0x04, 0x7000); 581 PHY_WRITE(sc, 0x03, 0xff41); 582 PHY_WRITE(sc, 0x02, 0xde60); 583 PHY_WRITE(sc, 0x01, 0x0140); 584 PHY_WRITE(sc, 0x00, 0x0077); 585 PHY_WRITE(sc, 0x04, 0x7800); 586 PHY_WRITE(sc, 0x04, 0x7000); 587 PHY_WRITE(sc, 0x04, 0xa000); 588 PHY_WRITE(sc, 0x03, 0xdf01); 589 PHY_WRITE(sc, 0x02, 0xdf20); 590 PHY_WRITE(sc, 0x01, 0xff95); 591 PHY_WRITE(sc, 0x00, 0xfa00); 592 PHY_WRITE(sc, 0x04, 0xa800); 593 PHY_WRITE(sc, 0x04, 0xa000); 594 PHY_WRITE(sc, 0x04, 0xb000); 595 PHY_WRITE(sc, 0x0e, 0xff41); 596 PHY_WRITE(sc, 0x02, 0xde20); 597 PHY_WRITE(sc, 0x01, 0x0140); 598 PHY_WRITE(sc, 0x00, 0x00bb); 599 PHY_WRITE(sc, 0x04, 0xb800); 600 PHY_WRITE(sc, 0x04, 0xb000); 601 PHY_WRITE(sc, 0x04, 0xf000); 602 PHY_WRITE(sc, 0x03, 0xdf01); 603 PHY_WRITE(sc, 0x02, 0xdf20); 604 PHY_WRITE(sc, 0x01, 0xff95); 605 PHY_WRITE(sc, 0x00, 0xbf00); 606 PHY_WRITE(sc, 0x04, 0xf800); 607 PHY_WRITE(sc, 0x04, 0xf000); 608 PHY_WRITE(sc, 0x04, 0x0000); 609 PHY_WRITE(sc, 0x1f, 0x0000); 610 PHY_WRITE(sc, 0x0b, 0x0000); 611 612 #endif 613 614 DELAY(40); 615 } 616 617 static void 618 rgephy_reset(struct mii_softc *sc) 619 { 620 struct rgephy_softc *rsc = (struct rgephy_softc *)sc; 621 uint16_t ssr, phycr1; 622 623 mii_phy_reset(sc); 624 DELAY(1000); 625 626 if (sc->mii_mpd_model != MII_MODEL_REALTEK_RTL8251 && 627 sc->mii_mpd_rev < RGEPHY_8211B) { 628 rgephy_load_dspcode(sc); 629 } else if (sc->mii_mpd_rev == RGEPHY_8211C) { 630 /* RTL8211C(L) */ 631 PHY_READ(sc, RGEPHY_MII_SSR, &ssr); 632 if ((ssr & RGEPHY_SSR_ALDPS) != 0) { 633 ssr &= ~RGEPHY_SSR_ALDPS; 634 PHY_WRITE(sc, RGEPHY_MII_SSR, ssr); 635 } 636 } else if (sc->mii_mpd_rev == RGEPHY_8211E) { 637 /* RTL8211E */ 638 if (rsc->mii_no_rx_delay) { 639 /* Disable RX internal delay (undocumented) */ 640 PHY_WRITE(sc, 0x1f, 0x0007); 641 PHY_WRITE(sc, 0x1e, 0x00a4); 642 PHY_WRITE(sc, 0x1c, 0xb591); 643 PHY_WRITE(sc, 0x1f, 0x0000); 644 } 645 } else if (sc->mii_mpd_rev == RGEPHY_8211F) { 646 /* RTL8211F */ 647 PHY_READ(sc, RGEPHY_MII_PHYCR1, &phycr1); 648 phycr1 &= ~RGEPHY_PHYCR1_MDI_MMCE; 649 phycr1 &= ~RGEPHY_PHYCR1_ALDPS_EN; 650 PHY_WRITE(sc, RGEPHY_MII_PHYCR1, phycr1); 651 } else { 652 PHY_WRITE(sc, 0x1F, 0x0000); 653 PHY_WRITE(sc, 0x0e, 0x0000); 654 } 655 656 /* Reset capabilities */ 657 /* Step1: write our capability */ 658 /* 10/100 capability */ 659 PHY_WRITE(sc, MII_ANAR, 660 ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 661 /* 1000 capability */ 662 PHY_WRITE(sc, MII_100T2CR, GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX); 663 664 /* Step2: Restart NWay */ 665 /* NWay enable and Restart NWay */ 666 PHY_WRITE(sc, MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 667 668 if (sc->mii_mpd_rev >= RGEPHY_8211D) { 669 /* RTL8211F */ 670 delay(10000); 671 /* disable EEE */ 672 MMD_INDIRECT_WRITE(sc, MDIO_MMD_AN | MMDACR_FN_DATA, 673 MDIO_AN_EEEADVERT, 0x0000); 674 } 675 } 676
Indexes created Thu Oct 02 14:10:14 GMT 2025