rgephy.c revision 1.59
1 /* $NetBSD: rgephy.c,v 1.59 2020/03/15 23:04:50 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2003 5 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: rgephy.c,v 1.59 2020/03/15 23:04:50 thorpej Exp $"); 37 38 39 /* 40 * Driver for the RealTek 8169S/8110S internal 10/100/1000 PHY. 41 */ 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/kernel.h> 46 #include <sys/device.h> 47 #include <sys/socket.h> 48 49 50 #include <net/if.h> 51 #include <net/if_media.h> 52 53 #include <dev/mii/mii.h> 54 #include <dev/mii/mdio.h> 55 #include <dev/mii/miivar.h> 56 #include <dev/mii/miidevs.h> 57 58 #include <dev/mii/rgephyreg.h> 59 60 #include <dev/ic/rtl81x9reg.h> 61 62 static int rgephy_match(device_t, cfdata_t, void *); 63 static void rgephy_attach(device_t, device_t, void *); 64 65 struct rgephy_softc { 66 struct mii_softc mii_sc; 67 bool mii_no_rx_delay; 68 }; 69 70 CFATTACH_DECL_NEW(rgephy, sizeof(struct rgephy_softc), 71 rgephy_match, rgephy_attach, mii_phy_detach, mii_phy_activate); 72 73 74 static int rgephy_service(struct mii_softc *, struct mii_data *, int); 75 static void rgephy_status(struct mii_softc *); 76 static int rgephy_mii_phy_auto(struct mii_softc *); 77 static void rgephy_reset(struct mii_softc *); 78 static bool rgephy_linkup(struct mii_softc *); 79 static void rgephy_loop(struct mii_softc *); 80 static void rgephy_load_dspcode(struct mii_softc *); 81 82 static const struct mii_phy_funcs rgephy_funcs = { 83 rgephy_service, rgephy_status, rgephy_reset, 84 }; 85 86 static const struct mii_phydesc rgephys[] = { 87 MII_PHY_DESC(xxREALTEK, RTL8169S), 88 MII_PHY_DESC(REALTEK, RTL8169S), 89 MII_PHY_DESC(REALTEK, RTL8251), 90 MII_PHY_END, 91 }; 92 93 static int 94 rgephy_match(device_t parent, cfdata_t match, void *aux) 95 { 96 struct mii_attach_args *ma = aux; 97 98 if (mii_phy_match(ma, rgephys) != NULL) 99 return 10; 100 101 return 0; 102 } 103 104 static void 105 rgephy_attach(device_t parent, device_t self, void *aux) 106 { 107 struct rgephy_softc *rsc = device_private(self); 108 prop_dictionary_t prop = device_properties(self); 109 struct mii_softc *sc = &rsc->mii_sc; 110 struct mii_attach_args *ma = aux; 111 struct mii_data *mii = ma->mii_data; 112 const struct mii_phydesc *mpd; 113 114 mpd = mii_phy_match(ma, rgephys); 115 aprint_naive(": Media interface\n"); 116 117 sc->mii_dev = self; 118 sc->mii_inst = mii->mii_instance; 119 sc->mii_phy = ma->mii_phyno; 120 sc->mii_funcs = &rgephy_funcs; 121 sc->mii_pdata = mii; 122 sc->mii_flags = ma->mii_flags; 123 124 sc->mii_mpd_oui = MII_OUI(ma->mii_id1, ma->mii_id2); 125 sc->mii_mpd_model = MII_MODEL(ma->mii_id2); 126 sc->mii_mpd_rev = MII_REV(ma->mii_id2); 127 128 if (sc->mii_mpd_model == MII_MODEL_REALTEK_RTL8169S) { 129 aprint_normal(": RTL8211"); 130 if (sc->mii_mpd_rev != 0) 131 aprint_normal("%c",'@' + sc->mii_mpd_rev); 132 aprint_normal(" 1000BASE-T media interface\n"); 133 } else { 134 aprint_normal(": %s, rev. %d\n", mpd->mpd_name, 135 sc->mii_mpd_rev); 136 } 137 138 prop_dictionary_get_bool(prop, "no-rx-delay", &rsc->mii_no_rx_delay); 139 140 #ifdef __FreeBSD__ 141 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst), 142 BMCR_LOOP | BMCR_S100); 143 #endif 144 145 mii_lock(mii); 146 147 PHY_RESET(sc); 148 149 PHY_READ(sc, MII_BMSR, &sc->mii_capabilities); 150 sc->mii_capabilities &= ma->mii_capmask; 151 /* RTL8169S does not report auto-sense; add manually. */ 152 sc->mii_capabilities |= BMSR_ANEG; 153 154 /* 155 * FreeBSD does not check EXSTAT, but instead adds gigabit 156 * media explicitly. Why? 157 */ 158 if (sc->mii_capabilities & BMSR_EXTSTAT) 159 PHY_READ(sc, MII_EXTSR, &sc->mii_extcapabilities); 160 161 mii_unlock(mii); 162 163 mii_phy_add_media(sc); 164 } 165 166 static int 167 rgephy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 168 { 169 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 170 uint16_t reg, speed, gig, anar; 171 172 KASSERT(mii_locked(mii)); 173 174 switch (cmd) { 175 case MII_POLLSTAT: 176 /* If we're not polling our PHY instance, just return. */ 177 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 178 return 0; 179 break; 180 181 case MII_MEDIACHG: 182 /* 183 * If the media indicates a different PHY instance, 184 * isolate ourselves. 185 */ 186 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 187 PHY_READ(sc, MII_BMCR, ®); 188 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO); 189 return 0; 190 } 191 192 /* If the interface is not up, don't do anything. */ 193 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 194 break; 195 196 rgephy_reset(sc); /* XXX hardware bug work-around */ 197 198 PHY_READ(sc, MII_ANAR, &anar); 199 anar &= ~(ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10); 200 201 switch (IFM_SUBTYPE(ife->ifm_media)) { 202 case IFM_AUTO: 203 #ifdef foo 204 /* If we're already in auto mode, just return. */ 205 PHY_READ(sc, MII_BMCR, ®); 206 if (reg & BMCR_AUTOEN) 207 return 0; 208 #endif 209 (void)rgephy_mii_phy_auto(sc); 210 break; 211 case IFM_1000_T: 212 speed = BMCR_S1000; 213 goto setit; 214 case IFM_100_TX: 215 speed = BMCR_S100; 216 anar |= ANAR_TX_FD | ANAR_TX; 217 goto setit; 218 case IFM_10_T: 219 speed = BMCR_S10; 220 anar |= ANAR_10_FD | ANAR_10; 221 setit: 222 rgephy_loop(sc); 223 if ((ife->ifm_media & IFM_FDX) != 0) { 224 speed |= BMCR_FDX; 225 gig = GTCR_ADV_1000TFDX; 226 anar &= ~(ANAR_TX | ANAR_10); 227 } else { 228 gig = GTCR_ADV_1000THDX; 229 anar &= ~(ANAR_TX_FD | ANAR_10_FD); 230 } 231 232 if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T) { 233 PHY_WRITE(sc, MII_100T2CR, 0); 234 PHY_WRITE(sc, MII_ANAR, anar); 235 PHY_WRITE(sc, MII_BMCR, 236 speed | BMCR_AUTOEN | BMCR_STARTNEG); 237 break; 238 } 239 240 /* 241 * When setting the link manually, one side must be the 242 * master and the other the slave. However ifmedia 243 * doesn't give us a good way to specify this, so we 244 * fake it by using one of the LINK flags. If LINK0 is 245 * set, we program the PHY to be a master, otherwise 246 * it's a slave. 247 */ 248 if ((mii->mii_ifp->if_flags & IFF_LINK0)) { 249 PHY_WRITE(sc, MII_100T2CR, 250 gig | GTCR_MAN_MS | GTCR_ADV_MS); 251 } else 252 PHY_WRITE(sc, MII_100T2CR, gig | GTCR_MAN_MS); 253 PHY_WRITE(sc, MII_BMCR, 254 speed | BMCR_AUTOEN | BMCR_STARTNEG); 255 break; 256 case IFM_NONE: 257 PHY_WRITE(sc, MII_BMCR, BMCR_ISO | BMCR_PDOWN); 258 break; 259 case IFM_100_T4: 260 default: 261 return EINVAL; 262 } 263 break; 264 265 case MII_TICK: 266 /* If we're not currently selected, just return. */ 267 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 268 return 0; 269 270 /* Is the interface even up? */ 271 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 272 return 0; 273 274 /* Only used for autonegotiation. */ 275 if ((IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) && 276 (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T)) { 277 /* 278 * Reset autonegotiation timer to 0 to make sure 279 * the future autonegotiation start with 0. 280 */ 281 sc->mii_ticks = 0; 282 break; 283 } 284 285 /* 286 * Check to see if we have link. If we do, we don't 287 * need to restart the autonegotiation process. Read 288 * the BMSR twice in case it's latched. 289 */ 290 if (rgephy_linkup(sc)) { 291 sc->mii_ticks = 0; 292 break; 293 } 294 295 /* Announce link loss right after it happens. */ 296 if (sc->mii_ticks++ == 0) 297 break; 298 299 /* Only retry autonegotiation every mii_anegticks seconds. */ 300 if (sc->mii_ticks <= sc->mii_anegticks) 301 return 0; 302 303 rgephy_mii_phy_auto(sc); 304 break; 305 } 306 307 /* Update the media status. */ 308 rgephy_status(sc); 309 310 /* 311 * Callback if something changed. Note that we need to poke 312 * the DSP on the RealTek PHYs if the media changes. 313 */ 314 if (sc->mii_media_active != mii->mii_media_active || 315 sc->mii_media_status != mii->mii_media_status || 316 cmd == MII_MEDIACHG) { 317 rgephy_load_dspcode(sc); 318 } 319 mii_phy_update(sc, cmd); 320 return 0; 321 } 322 323 static bool 324 rgephy_linkup(struct mii_softc *sc) 325 { 326 bool linkup = false; 327 uint16_t reg; 328 329 if (sc->mii_mpd_rev >= RGEPHY_8211F) { 330 PHY_READ(sc, RGEPHY_MII_PHYSR, ®); 331 if (reg & RGEPHY_PHYSR_LINK) 332 linkup = true; 333 } else if (sc->mii_mpd_rev >= RGEPHY_8211B) { 334 PHY_READ(sc, RGEPHY_MII_SSR, ®); 335 if (reg & RGEPHY_SSR_LINK) 336 linkup = true; 337 } else { 338 PHY_READ(sc, RTK_GMEDIASTAT, ®); 339 if ((reg & RTK_GMEDIASTAT_LINK) != 0) 340 linkup = true; 341 } 342 343 return linkup; 344 } 345 346 static void 347 rgephy_status(struct mii_softc *sc) 348 { 349 struct mii_data *mii = sc->mii_pdata; 350 uint16_t gstat, bmsr, bmcr, gtsr, physr, ssr; 351 352 KASSERT(mii_locked(mii)); 353 354 mii->mii_media_status = IFM_AVALID; 355 mii->mii_media_active = IFM_ETHER; 356 357 if (rgephy_linkup(sc)) 358 mii->mii_media_status |= IFM_ACTIVE; 359 360 PHY_READ(sc, MII_BMSR, &bmsr); 361 PHY_READ(sc, MII_BMCR, &bmcr); 362 363 if ((bmcr & BMCR_ISO) != 0) { 364 mii->mii_media_active |= IFM_NONE; 365 mii->mii_media_status = 0; 366 return; 367 } 368 369 if ((bmcr & BMCR_LOOP) != 0) 370 mii->mii_media_active |= IFM_LOOP; 371 372 if ((bmcr & BMCR_AUTOEN) != 0) { 373 if ((bmsr & BMSR_ACOMP) == 0) { 374 /* Erg, still trying, I guess... */ 375 mii->mii_media_active |= IFM_NONE; 376 return; 377 } 378 } 379 380 if (sc->mii_mpd_rev >= RGEPHY_8211F) { 381 PHY_READ(sc, RGEPHY_MII_PHYSR, &physr); 382 switch (__SHIFTOUT(physr, RGEPHY_PHYSR_SPEED)) { 383 case RGEPHY_PHYSR_SPEED_1000: 384 mii->mii_media_active |= IFM_1000_T; 385 break; 386 case RGEPHY_PHYSR_SPEED_100: 387 mii->mii_media_active |= IFM_100_TX; 388 break; 389 case RGEPHY_PHYSR_SPEED_10: 390 mii->mii_media_active |= IFM_10_T; 391 break; 392 default: 393 mii->mii_media_active |= IFM_NONE; 394 break; 395 } 396 if (physr & RGEPHY_PHYSR_DUPLEX) 397 mii->mii_media_active |= mii_phy_flowstatus(sc) | 398 IFM_FDX; 399 else 400 mii->mii_media_active |= IFM_HDX; 401 } else if (sc->mii_mpd_rev >= RGEPHY_8211B) { 402 PHY_READ(sc, RGEPHY_MII_SSR, &ssr); 403 switch (ssr & RGEPHY_SSR_SPD_MASK) { 404 case RGEPHY_SSR_S1000: 405 mii->mii_media_active |= IFM_1000_T; 406 break; 407 case RGEPHY_SSR_S100: 408 mii->mii_media_active |= IFM_100_TX; 409 break; 410 case RGEPHY_SSR_S10: 411 mii->mii_media_active |= IFM_10_T; 412 break; 413 default: 414 mii->mii_media_active |= IFM_NONE; 415 break; 416 } 417 if (ssr & RGEPHY_SSR_FDX) 418 mii->mii_media_active |= mii_phy_flowstatus(sc) | 419 IFM_FDX; 420 else 421 mii->mii_media_active |= IFM_HDX; 422 } else { 423 PHY_READ(sc, RTK_GMEDIASTAT, &gstat); 424 if ((gstat & RTK_GMEDIASTAT_1000MBPS) != 0) 425 mii->mii_media_active |= IFM_1000_T; 426 else if ((gstat & RTK_GMEDIASTAT_100MBPS) != 0) 427 mii->mii_media_active |= IFM_100_TX; 428 else if ((gstat & RTK_GMEDIASTAT_10MBPS) != 0) 429 mii->mii_media_active |= IFM_10_T; 430 else 431 mii->mii_media_active |= IFM_NONE; 432 if ((gstat & RTK_GMEDIASTAT_FDX) != 0) 433 mii->mii_media_active |= mii_phy_flowstatus(sc) | 434 IFM_FDX; 435 else 436 mii->mii_media_active |= IFM_HDX; 437 } 438 439 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) { 440 PHY_READ(sc, MII_GTSR, >sr); 441 if ((gtsr & GTSR_MS_RES) != 0) 442 mii->mii_media_active |= IFM_ETH_MASTER; 443 } 444 } 445 446 static int 447 rgephy_mii_phy_auto(struct mii_softc *mii) 448 { 449 int anar; 450 451 mii->mii_ticks = 0; 452 rgephy_loop(mii); 453 rgephy_reset(mii); 454 455 anar = BMSR_MEDIA_TO_ANAR(mii->mii_capabilities) | ANAR_CSMA; 456 if (mii->mii_flags & MIIF_DOPAUSE) 457 anar |= ANAR_FC | ANAR_PAUSE_ASYM; 458 459 PHY_WRITE(mii, MII_ANAR, anar); 460 DELAY(1000); 461 PHY_WRITE(mii, MII_100T2CR, GTCR_ADV_1000THDX | GTCR_ADV_1000TFDX); 462 DELAY(1000); 463 PHY_WRITE(mii, MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG); 464 DELAY(100); 465 466 return EJUSTRETURN; 467 } 468 469 static void 470 rgephy_loop(struct mii_softc *sc) 471 { 472 uint16_t bmsr; 473 int i; 474 475 if (sc->mii_mpd_model != MII_MODEL_REALTEK_RTL8251 && 476 sc->mii_mpd_rev < RGEPHY_8211B) { 477 PHY_WRITE(sc, MII_BMCR, BMCR_PDOWN); 478 DELAY(1000); 479 } 480 481 for (i = 0; i < 15000; i++) { 482 PHY_READ(sc, MII_BMSR, &bmsr); 483 if ((bmsr & BMSR_LINK) == 0) { 484 #if 0 485 device_printf(sc->mii_dev, "looped %d\n", i); 486 #endif 487 break; 488 } 489 DELAY(10); 490 } 491 } 492 493 static inline int 494 PHY_SETBIT(struct mii_softc *sc, int y, uint16_t z) 495 { 496 uint16_t _tmp; 497 int rv; 498 499 if ((rv = PHY_READ(sc, y, &_tmp)) != 0) 500 return rv; 501 return PHY_WRITE(sc, y, _tmp | z); 502 } 503 504 static inline int 505 PHY_CLRBIT(struct mii_softc *sc, int y, uint16_t z) 506 { 507 uint16_t _tmp; 508 int rv; 509 510 if ((rv = PHY_READ(sc, y, &_tmp)) != 0) 511 return rv; 512 return PHY_WRITE(sc, y, _tmp & ~z); 513 } 514 515 /* 516 * Initialize RealTek PHY per the datasheet. The DSP in the PHYs of existing 517 * revisions of the 8169S/8110S chips need to be tuned in order to reliably 518 * negotiate a 1000Mbps link. This is only needed for rev 0 and rev 1 of the 519 * PHY. Later versions work without any fixups. 520 */ 521 static void 522 rgephy_load_dspcode(struct mii_softc *sc) 523 { 524 uint16_t val; 525 526 if (sc->mii_mpd_model == MII_MODEL_REALTEK_RTL8251 || 527 sc->mii_mpd_rev >= RGEPHY_8211B) 528 return; 529 530 #if 1 531 PHY_WRITE(sc, 31, 0x0001); 532 PHY_WRITE(sc, 21, 0x1000); 533 PHY_WRITE(sc, 24, 0x65C7); 534 PHY_CLRBIT(sc, 4, 0x0800); 535 PHY_READ(sc, 4, &val); 536 val &= 0xFFF; 537 PHY_WRITE(sc, 4, val); 538 PHY_WRITE(sc, 3, 0x00A1); 539 PHY_WRITE(sc, 2, 0x0008); 540 PHY_WRITE(sc, 1, 0x1020); 541 PHY_WRITE(sc, 0, 0x1000); 542 PHY_SETBIT(sc, 4, 0x0800); 543 PHY_CLRBIT(sc, 4, 0x0800); 544 PHY_READ(sc, 4, &val); 545 val = (val & 0xFFF) | 0x7000; 546 PHY_WRITE(sc, 4, val); 547 PHY_WRITE(sc, 3, 0xFF41); 548 PHY_WRITE(sc, 2, 0xDE60); 549 PHY_WRITE(sc, 1, 0x0140); 550 PHY_WRITE(sc, 0, 0x0077); 551 PHY_READ(sc, 4, &val); 552 val = (val & 0xFFF) | 0xA000; 553 PHY_WRITE(sc, 4, val); 554 PHY_WRITE(sc, 3, 0xDF01); 555 PHY_WRITE(sc, 2, 0xDF20); 556 PHY_WRITE(sc, 1, 0xFF95); 557 PHY_WRITE(sc, 0, 0xFA00); 558 PHY_READ(sc, 4, &val); 559 val = (val & 0xFFF) | 0xB000; 560 PHY_WRITE(sc, 4, val); 561 PHY_WRITE(sc, 3, 0xFF41); 562 PHY_WRITE(sc, 2, 0xDE20); 563 PHY_WRITE(sc, 1, 0x0140); 564 PHY_WRITE(sc, 0, 0x00BB); 565 PHY_READ(sc, 4, &val); 566 val = (val & 0xFFF) | 0xF000; 567 PHY_WRITE(sc, 4, val); 568 PHY_WRITE(sc, 3, 0xDF01); 569 PHY_WRITE(sc, 2, 0xDF20); 570 PHY_WRITE(sc, 1, 0xFF95); 571 PHY_WRITE(sc, 0, 0xBF00); 572 PHY_SETBIT(sc, 4, 0x0800); 573 PHY_CLRBIT(sc, 4, 0x0800); 574 PHY_WRITE(sc, 31, 0x0000); 575 #else 576 (void)val; 577 PHY_WRITE(sc, 0x1f, 0x0001); 578 PHY_WRITE(sc, 0x15, 0x1000); 579 PHY_WRITE(sc, 0x18, 0x65c7); 580 PHY_WRITE(sc, 0x04, 0x0000); 581 PHY_WRITE(sc, 0x03, 0x00a1); 582 PHY_WRITE(sc, 0x02, 0x0008); 583 PHY_WRITE(sc, 0x01, 0x1020); 584 PHY_WRITE(sc, 0x00, 0x1000); 585 PHY_WRITE(sc, 0x04, 0x0800); 586 PHY_WRITE(sc, 0x04, 0x0000); 587 PHY_WRITE(sc, 0x04, 0x7000); 588 PHY_WRITE(sc, 0x03, 0xff41); 589 PHY_WRITE(sc, 0x02, 0xde60); 590 PHY_WRITE(sc, 0x01, 0x0140); 591 PHY_WRITE(sc, 0x00, 0x0077); 592 PHY_WRITE(sc, 0x04, 0x7800); 593 PHY_WRITE(sc, 0x04, 0x7000); 594 PHY_WRITE(sc, 0x04, 0xa000); 595 PHY_WRITE(sc, 0x03, 0xdf01); 596 PHY_WRITE(sc, 0x02, 0xdf20); 597 PHY_WRITE(sc, 0x01, 0xff95); 598 PHY_WRITE(sc, 0x00, 0xfa00); 599 PHY_WRITE(sc, 0x04, 0xa800); 600 PHY_WRITE(sc, 0x04, 0xa000); 601 PHY_WRITE(sc, 0x04, 0xb000); 602 PHY_WRITE(sc, 0x0e, 0xff41); 603 PHY_WRITE(sc, 0x02, 0xde20); 604 PHY_WRITE(sc, 0x01, 0x0140); 605 PHY_WRITE(sc, 0x00, 0x00bb); 606 PHY_WRITE(sc, 0x04, 0xb800); 607 PHY_WRITE(sc, 0x04, 0xb000); 608 PHY_WRITE(sc, 0x04, 0xf000); 609 PHY_WRITE(sc, 0x03, 0xdf01); 610 PHY_WRITE(sc, 0x02, 0xdf20); 611 PHY_WRITE(sc, 0x01, 0xff95); 612 PHY_WRITE(sc, 0x00, 0xbf00); 613 PHY_WRITE(sc, 0x04, 0xf800); 614 PHY_WRITE(sc, 0x04, 0xf000); 615 PHY_WRITE(sc, 0x04, 0x0000); 616 PHY_WRITE(sc, 0x1f, 0x0000); 617 PHY_WRITE(sc, 0x0b, 0x0000); 618 619 #endif 620 621 DELAY(40); 622 } 623 624 static void 625 rgephy_reset(struct mii_softc *sc) 626 { 627 struct rgephy_softc *rsc = (struct rgephy_softc *)sc; 628 uint16_t ssr, phycr1; 629 630 KASSERT(mii_locked(sc->mii_pdata)); 631 632 mii_phy_reset(sc); 633 DELAY(1000); 634 635 if (sc->mii_mpd_model != MII_MODEL_REALTEK_RTL8251 && 636 sc->mii_mpd_rev < RGEPHY_8211B) { 637 rgephy_load_dspcode(sc); 638 } else if (sc->mii_mpd_rev == RGEPHY_8211C) { 639 /* RTL8211C(L) */ 640 PHY_READ(sc, RGEPHY_MII_SSR, &ssr); 641 if ((ssr & RGEPHY_SSR_ALDPS) != 0) { 642 ssr &= ~RGEPHY_SSR_ALDPS; 643 PHY_WRITE(sc, RGEPHY_MII_SSR, ssr); 644 } 645 } else if (sc->mii_mpd_rev == RGEPHY_8211E) { 646 /* RTL8211E */ 647 if (rsc->mii_no_rx_delay) { 648 /* Disable RX internal delay (undocumented) */ 649 PHY_WRITE(sc, 0x1f, 0x0007); 650 PHY_WRITE(sc, 0x1e, 0x00a4); 651 PHY_WRITE(sc, 0x1c, 0xb591); 652 PHY_WRITE(sc, 0x1f, 0x0000); 653 } 654 } else if (sc->mii_mpd_rev == RGEPHY_8211F) { 655 /* RTL8211F */ 656 PHY_READ(sc, RGEPHY_MII_PHYCR1, &phycr1); 657 phycr1 &= ~RGEPHY_PHYCR1_MDI_MMCE; 658 phycr1 &= ~RGEPHY_PHYCR1_ALDPS_EN; 659 PHY_WRITE(sc, RGEPHY_MII_PHYCR1, phycr1); 660 } else { 661 PHY_WRITE(sc, 0x1F, 0x0000); 662 PHY_WRITE(sc, 0x0e, 0x0000); 663 } 664 665 /* Reset capabilities */ 666 /* Step1: write our capability */ 667 /* 10/100 capability */ 668 PHY_WRITE(sc, MII_ANAR, 669 ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 670 /* 1000 capability */ 671 PHY_WRITE(sc, MII_100T2CR, GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX); 672 673 /* Step2: Restart NWay */ 674 /* NWay enable and Restart NWay */ 675 PHY_WRITE(sc, MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 676 677 if (sc->mii_mpd_rev >= RGEPHY_8211D) { 678 /* RTL8211F */ 679 delay(10000); 680 /* disable EEE */ 681 MMD_INDIRECT_WRITE(sc, MDIO_MMD_AN | MMDACR_FN_DATA, 682 MDIO_AN_EEEADVERT, 0x0000); 683 } 684 } 685
Indexes created Thu Oct 02 10:09:58 GMT 2025