rgephy.c revision 1.6
1 /* $NetBSD: rgephy.c,v 1.6 2005/03/23 13:27:20 wiz Exp $ */ 2 3 /* 4 * Copyright (c) 2003 5 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: rgephy.c,v 1.6 2005/03/23 13:27:20 wiz Exp $"); 37 38 39 /* 40 * Driver for the RealTek 8169S/8110S internal 10/100/1000 PHY. 41 */ 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/kernel.h> 46 #include <sys/socket.h> 47 48 49 #include <net/if.h> 50 #include <net/if_media.h> 51 52 #include <dev/mii/mii.h> 53 #include <dev/mii/miivar.h> 54 #include <dev/mii/miidevs.h> 55 56 #include <dev/mii/rgephyreg.h> 57 58 #include <dev/ic/rtl81x9reg.h> 59 60 static int rgephy_match(struct device *, struct cfdata *, void *); 61 static void rgephy_attach(struct device *, struct device *, void *); 62 63 CFATTACH_DECL(rgephy, sizeof(struct mii_softc), 64 rgephy_match, rgephy_attach, mii_phy_detach, mii_phy_activate); 65 66 67 static int rgephy_service(struct mii_softc *, struct mii_data *, int); 68 static void rgephy_status(struct mii_softc *); 69 static int rgephy_mii_phy_auto(struct mii_softc *); 70 static void rgephy_reset(struct mii_softc *); 71 static void rgephy_loop(struct mii_softc *); 72 static void rgephy_load_dspcode(struct mii_softc *); 73 static int rgephy_mii_model; 74 75 static const struct mii_phy_funcs rgephy_funcs = { 76 rgephy_service, rgephy_status, rgephy_reset, 77 }; 78 79 static const struct mii_phydesc rgephys[] = { 80 { MII_OUI_xxREALTEK, MII_MODEL_xxREALTEK_RTL8169S, 81 MII_STR_xxREALTEK_RTL8169S }, 82 83 { MII_OUI_REALTEK, MII_MODEL_REALTEK_RTL8169S, 84 MII_STR_REALTEK_RTL8169S }, 85 86 { 0, 0, 87 NULL } 88 }; 89 90 static int 91 rgephy_match(struct device *parent, struct cfdata *match, void *aux) 92 { 93 struct mii_attach_args *ma = aux; 94 95 if (mii_phy_match(ma, rgephys) != NULL) 96 return (10); 97 98 return (0); 99 } 100 101 static void 102 rgephy_attach(struct device *parent, struct device *self, void *aux) 103 { 104 struct mii_softc *sc = (struct mii_softc *)self; 105 struct mii_attach_args *ma = aux; 106 struct mii_data *mii = ma->mii_data; 107 const struct mii_phydesc *mpd; 108 int rev; 109 const char *sep = ""; 110 111 rev = MII_REV(ma->mii_id2); 112 mpd = mii_phy_match(ma, rgephys); 113 aprint_naive(": Media interface\n"); 114 aprint_normal(": %s, rev. %d\n", mpd->mpd_name, rev); 115 116 sc->mii_mpd_model = rev; /* XXX miivar.h comment vs usage? */ 117 sc->mii_inst = mii->mii_instance; 118 sc->mii_phy = ma->mii_phyno; 119 sc->mii_pdata = mii; 120 sc->mii_flags = mii->mii_flags; 121 sc->mii_anegticks = 5; 122 123 sc->mii_funcs = &rgephy_funcs; 124 125 /* Don't do isolate on this PHY. */ 126 sc->mii_flags |= MIIF_NOISOLATE; 127 128 #define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL) 129 #define PRINT(n) aprint_normal("%s%s", sep, (n)); sep = ", " 130 131 #if 0 132 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, sc->mii_inst), 133 BMCR_ISO); 134 #endif 135 #ifdef __FreeBSD__ 136 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst), 137 BMCR_LOOP|BMCR_S100); 138 #endif 139 140 rgephy_mii_model = MII_MODEL(ma->mii_id2); 141 PHY_RESET(sc); 142 143 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask; 144 sc->mii_capabilities &= ~BMSR_ANEG; 145 146 /* 147 * FreeBSD does not check EXSTAT, but instead adds gigabit 148 * media explicitly. Why? 149 */ 150 aprint_normal("%s: ", sc->mii_dev.dv_xname); 151 #ifdef __FreeBSD__ 152 mii_phy_add_media(sc); 153 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, 0, sc->mii_inst), 154 RGEPHY_BMCR_FDX); 155 PRINT(", 1000baseTX"); 156 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, IFM_FDX, sc->mii_inst), 0); 157 PRINT("1000baseTX-FDX"); 158 #else 159 if (sc->mii_capabilities & BMSR_EXTSTAT) { 160 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); 161 } 162 mii_phy_add_media(sc); 163 #endif 164 /* rtl8169S does not report auto-sense; add manually. */ 165 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), MII_NMEDIA); 166 sep =", "; 167 PRINT("auto"); 168 169 #undef ADD 170 #undef PRINT 171 172 aprint_normal("\n"); 173 } 174 175 static int 176 rgephy_service(sc, mii, cmd) 177 struct mii_softc *sc; 178 struct mii_data *mii; 179 int cmd; 180 { 181 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 182 int reg, speed, gig; 183 184 switch (cmd) { 185 case MII_POLLSTAT: 186 /* 187 * If we're not polling our PHY instance, just return. 188 */ 189 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 190 return (0); 191 break; 192 193 case MII_MEDIACHG: 194 /* 195 * If the media indicates a different PHY instance, 196 * isolate ourselves. 197 */ 198 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 199 reg = PHY_READ(sc, MII_BMCR); 200 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO); 201 return (0); 202 } 203 204 /* 205 * If the interface is not up, don't do anything. 206 */ 207 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 208 break; 209 210 PHY_RESET(sc); /* XXX hardware bug work-around */ 211 212 switch (IFM_SUBTYPE(ife->ifm_media)) { 213 case IFM_AUTO: 214 #ifdef foo 215 /* 216 * If we're already in auto mode, just return. 217 */ 218 if (PHY_READ(sc, RGEPHY_MII_BMCR) & RGEPHY_BMCR_AUTOEN) 219 return (0); 220 #endif 221 (void) rgephy_mii_phy_auto(sc); 222 break; 223 case IFM_1000_T: 224 speed = RGEPHY_S1000; 225 goto setit; 226 case IFM_100_TX: 227 speed = RGEPHY_S100; 228 goto setit; 229 case IFM_10_T: 230 speed = RGEPHY_S10; 231 setit: 232 rgephy_loop(sc); 233 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 234 speed |= RGEPHY_BMCR_FDX; 235 gig = RGEPHY_1000CTL_AFD; 236 } else { 237 gig = RGEPHY_1000CTL_AHD; 238 } 239 240 PHY_WRITE(sc, RGEPHY_MII_1000CTL, 0); 241 PHY_WRITE(sc, RGEPHY_MII_BMCR, speed); 242 PHY_WRITE(sc, RGEPHY_MII_ANAR, RGEPHY_SEL_TYPE); 243 244 if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T) 245 break; 246 247 PHY_WRITE(sc, RGEPHY_MII_1000CTL, gig); 248 PHY_WRITE(sc, RGEPHY_MII_BMCR, 249 speed|RGEPHY_BMCR_AUTOEN|RGEPHY_BMCR_STARTNEG); 250 251 /* 252 * When settning the link manually, one side must 253 * be the master and the other the slave. However 254 * ifmedia doesn't give us a good way to specify 255 * this, so we fake it by using one of the LINK 256 * flags. If LINK0 is set, we program the PHY to 257 * be a master, otherwise it's a slave. 258 */ 259 if ((mii->mii_ifp->if_flags & IFF_LINK0)) { 260 PHY_WRITE(sc, RGEPHY_MII_1000CTL, 261 gig|RGEPHY_1000CTL_MSE|RGEPHY_1000CTL_MSC); 262 } else { 263 PHY_WRITE(sc, RGEPHY_MII_1000CTL, 264 gig|RGEPHY_1000CTL_MSE); 265 } 266 break; 267 #ifdef foo 268 case IFM_NONE: 269 PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN); 270 break; 271 #endif 272 case IFM_100_T4: 273 default: 274 return (EINVAL); 275 } 276 break; 277 278 case MII_TICK: 279 /* 280 * If we're not currently selected, just return. 281 */ 282 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 283 return (0); 284 285 /* 286 * Is the interface even up? 287 */ 288 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 289 return (0); 290 291 /* 292 * Only used for autonegotiation. 293 */ 294 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) 295 break; 296 297 /* 298 * Check to see if we have link. If we do, we don't 299 * need to restart the autonegotiation process. Read 300 * the BMSR twice in case it's latched. 301 */ 302 reg = PHY_READ(sc, RTK_GMEDIASTAT); 303 if (reg & RTK_GMEDIASTAT_LINK) 304 break; 305 306 /* 307 * Only retry autonegotiation every 5 seconds. 308 */ 309 if (++sc->mii_ticks <= 5/*10*/) 310 break; 311 312 sc->mii_ticks = 0; 313 rgephy_mii_phy_auto(sc); 314 return (0); 315 } 316 317 /* Update the media status. */ 318 rgephy_status(sc); 319 320 /* 321 * Callback if something changed. Note that we need to poke 322 * the DSP on the RealTek PHYs if the media changes. 323 * 324 */ 325 if (sc->mii_media_active != mii->mii_media_active || 326 sc->mii_media_status != mii->mii_media_status || 327 cmd == MII_MEDIACHG) { 328 /* XXX only for v0/v1 phys. */ 329 if (sc->mii_mpd_model < 2) 330 rgephy_load_dspcode(sc); 331 } 332 mii_phy_update(sc, cmd); 333 return (0); 334 } 335 336 static void 337 rgephy_status(sc) 338 struct mii_softc *sc; 339 { 340 struct mii_data *mii = sc->mii_pdata; 341 int bmsr, bmcr; 342 343 mii->mii_media_status = IFM_AVALID; 344 mii->mii_media_active = IFM_ETHER; 345 346 bmsr = PHY_READ(sc, RTK_GMEDIASTAT); 347 348 if (bmsr & RTK_GMEDIASTAT_LINK) 349 mii->mii_media_status |= IFM_ACTIVE; 350 bmsr = PHY_READ(sc, RGEPHY_MII_BMSR); 351 352 bmcr = PHY_READ(sc, RGEPHY_MII_BMCR); 353 354 if (bmcr & RGEPHY_BMCR_ISO) { 355 mii->mii_media_active |= IFM_NONE; 356 mii->mii_media_status = 0; 357 return; 358 } 359 360 if (bmcr & RGEPHY_BMCR_LOOP) 361 mii->mii_media_active |= IFM_LOOP; 362 363 if (bmcr & RGEPHY_BMCR_AUTOEN) { 364 if ((bmsr & RGEPHY_BMSR_ACOMP) == 0) { 365 /* Erg, still trying, I guess... */ 366 mii->mii_media_active |= IFM_NONE; 367 return; 368 } 369 } 370 371 bmsr = PHY_READ(sc, RTK_GMEDIASTAT); 372 if (bmsr & RTK_GMEDIASTAT_10MBPS) 373 mii->mii_media_active |= IFM_10_T; 374 if (bmsr & RTK_GMEDIASTAT_100MBPS) 375 mii->mii_media_active |= IFM_100_TX; 376 if (bmsr & RTK_GMEDIASTAT_1000MBPS) 377 mii->mii_media_active |= IFM_1000_T; 378 if (bmsr & RTK_GMEDIASTAT_FDX) 379 mii->mii_media_active |= IFM_FDX; 380 381 return; 382 } 383 384 385 static int 386 rgephy_mii_phy_auto(mii) 387 struct mii_softc *mii; 388 { 389 rgephy_loop(mii); 390 PHY_RESET(mii); 391 392 PHY_WRITE(mii, RGEPHY_MII_ANAR, 393 BMSR_MEDIA_TO_ANAR(mii->mii_capabilities) | ANAR_CSMA); 394 DELAY(1000); 395 PHY_WRITE(mii, RGEPHY_MII_1000CTL, RGEPHY_1000CTL_AFD); 396 DELAY(1000); 397 PHY_WRITE(mii, RGEPHY_MII_BMCR, 398 RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG); 399 DELAY(100); 400 401 return (EJUSTRETURN); 402 } 403 404 static void 405 rgephy_loop(struct mii_softc *sc) 406 { 407 u_int32_t bmsr; 408 int i; 409 410 PHY_WRITE(sc, RGEPHY_MII_BMCR, RGEPHY_BMCR_PDOWN); 411 DELAY(1000); 412 413 for (i = 0; i < 15000; i++) { 414 bmsr = PHY_READ(sc, RGEPHY_MII_BMSR); 415 if (!(bmsr & RGEPHY_BMSR_LINK)) { 416 #if 0 417 device_printf(sc->mii_dev, "looped %d\n", i); 418 #endif 419 break; 420 } 421 DELAY(10); 422 } 423 } 424 425 #define PHY_SETBIT(x, y, z) \ 426 PHY_WRITE(x, y, (PHY_READ(x, y) | (z))) 427 #define PHY_CLRBIT(x, y, z) \ 428 PHY_WRITE(x, y, (PHY_READ(x, y) & ~(z))) 429 430 /* 431 * Initialize RealTek PHY per the datasheet. The DSP in the PHYs of 432 * existing revisions of the 8169S/8110S chips need to be tuned in 433 * order to reliably negotiate a 1000Mbps link. Later revs of the 434 * chips may not require this software tuning. 435 */ 436 static void 437 rgephy_load_dspcode(struct mii_softc *sc) 438 { 439 int val; 440 441 #if 1 442 PHY_WRITE(sc, 31, 0x0001); 443 PHY_WRITE(sc, 21, 0x1000); 444 PHY_WRITE(sc, 24, 0x65C7); 445 PHY_CLRBIT(sc, 4, 0x0800); 446 val = PHY_READ(sc, 4) & 0xFFF; 447 PHY_WRITE(sc, 4, val); 448 PHY_WRITE(sc, 3, 0x00A1); 449 PHY_WRITE(sc, 2, 0x0008); 450 PHY_WRITE(sc, 1, 0x1020); 451 PHY_WRITE(sc, 0, 0x1000); 452 PHY_SETBIT(sc, 4, 0x0800); 453 PHY_CLRBIT(sc, 4, 0x0800); 454 val = (PHY_READ(sc, 4) & 0xFFF) | 0x7000; 455 PHY_WRITE(sc, 4, val); 456 PHY_WRITE(sc, 3, 0xFF41); 457 PHY_WRITE(sc, 2, 0xDE60); 458 PHY_WRITE(sc, 1, 0x0140); 459 PHY_WRITE(sc, 0, 0x0077); 460 val = (PHY_READ(sc, 4) & 0xFFF) | 0xA000; 461 PHY_WRITE(sc, 4, val); 462 PHY_WRITE(sc, 3, 0xDF01); 463 PHY_WRITE(sc, 2, 0xDF20); 464 PHY_WRITE(sc, 1, 0xFF95); 465 PHY_WRITE(sc, 0, 0xFA00); 466 val = (PHY_READ(sc, 4) & 0xFFF) | 0xB000; 467 PHY_WRITE(sc, 4, val); 468 PHY_WRITE(sc, 3, 0xFF41); 469 PHY_WRITE(sc, 2, 0xDE20); 470 PHY_WRITE(sc, 1, 0x0140); 471 PHY_WRITE(sc, 0, 0x00BB); 472 val = (PHY_READ(sc, 4) & 0xFFF) | 0xF000; 473 PHY_WRITE(sc, 4, val); 474 PHY_WRITE(sc, 3, 0xDF01); 475 PHY_WRITE(sc, 2, 0xDF20); 476 PHY_WRITE(sc, 1, 0xFF95); 477 PHY_WRITE(sc, 0, 0xBF00); 478 PHY_SETBIT(sc, 4, 0x0800); 479 PHY_CLRBIT(sc, 4, 0x0800); 480 PHY_WRITE(sc, 31, 0x0000); 481 #else 482 (void)val; 483 PHY_WRITE(sc, 0x1f, 0x0001); 484 PHY_WRITE(sc, 0x15, 0x1000); 485 PHY_WRITE(sc, 0x18, 0x65c7); 486 PHY_WRITE(sc, 0x04, 0x0000); 487 PHY_WRITE(sc, 0x03, 0x00a1); 488 PHY_WRITE(sc, 0x02, 0x0008); 489 PHY_WRITE(sc, 0x01, 0x1020); 490 PHY_WRITE(sc, 0x00, 0x1000); 491 PHY_WRITE(sc, 0x04, 0x0800); 492 PHY_WRITE(sc, 0x04, 0x0000); 493 PHY_WRITE(sc, 0x04, 0x7000); 494 PHY_WRITE(sc, 0x03, 0xff41); 495 PHY_WRITE(sc, 0x02, 0xde60); 496 PHY_WRITE(sc, 0x01, 0x0140); 497 PHY_WRITE(sc, 0x00, 0x0077); 498 PHY_WRITE(sc, 0x04, 0x7800); 499 PHY_WRITE(sc, 0x04, 0x7000); 500 PHY_WRITE(sc, 0x04, 0xa000); 501 PHY_WRITE(sc, 0x03, 0xdf01); 502 PHY_WRITE(sc, 0x02, 0xdf20); 503 PHY_WRITE(sc, 0x01, 0xff95); 504 PHY_WRITE(sc, 0x00, 0xfa00); 505 PHY_WRITE(sc, 0x04, 0xa800); 506 PHY_WRITE(sc, 0x04, 0xa000); 507 PHY_WRITE(sc, 0x04, 0xb000); 508 PHY_WRITE(sc, 0x0e, 0xff41); 509 PHY_WRITE(sc, 0x02, 0xde20); 510 PHY_WRITE(sc, 0x01, 0x0140); 511 PHY_WRITE(sc, 0x00, 0x00bb); 512 PHY_WRITE(sc, 0x04, 0xb800); 513 PHY_WRITE(sc, 0x04, 0xb000); 514 PHY_WRITE(sc, 0x04, 0xf000); 515 PHY_WRITE(sc, 0x03, 0xdf01); 516 PHY_WRITE(sc, 0x02, 0xdf20); 517 PHY_WRITE(sc, 0x01, 0xff95); 518 PHY_WRITE(sc, 0x00, 0xbf00); 519 PHY_WRITE(sc, 0x04, 0xf800); 520 PHY_WRITE(sc, 0x04, 0xf000); 521 PHY_WRITE(sc, 0x04, 0x0000); 522 PHY_WRITE(sc, 0x1f, 0x0000); 523 PHY_WRITE(sc, 0x0b, 0x0000); 524 525 #endif 526 527 DELAY(40); 528 } 529 530 static void 531 rgephy_reset(struct mii_softc *sc) 532 { 533 mii_phy_reset(sc); 534 DELAY(1000); 535 536 if (sc->mii_mpd_model < 2) 537 rgephy_load_dspcode(sc); 538 else { 539 PHY_WRITE(sc, 0x1F, 0x0001); 540 PHY_WRITE(sc, 0x09, 0x273a); 541 PHY_WRITE(sc, 0x0e, 0x7bfb); 542 PHY_WRITE(sc, 0x1b, 0x841e); 543 544 PHY_WRITE(sc, 0x1F, 0x0002); 545 PHY_WRITE(sc, 0x01, 0x90D0); 546 PHY_WRITE(sc, 0x1F, 0x0000); 547 } 548 549 /* Reset capabilities */ 550 /* Step1: write our capability */ 551 PHY_WRITE(sc, 0x04,0x01e1); /* 10/100 capability */ 552 PHY_WRITE(sc, 0x09,0x0200); /* 1000 capability */ 553 554 #ifdef jrs_notyet 555 /* Step2: Restart NWay */ 556 PHY_WRITE(sc, 0x00, 0x1200); // NWay enable and Restart NWay 557 #endif 558 } 559
Indexes created Fri Oct 03 02:09:57 GMT 2025