rgephy.c revision 1.9
1 /* $NetBSD: rgephy.c,v 1.9 2006/10/12 01:31:25 christos Exp $ */ 2 3 /* 4 * Copyright (c) 2003 5 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: rgephy.c,v 1.9 2006/10/12 01:31:25 christos Exp $"); 37 38 39 /* 40 * Driver for the RealTek 8169S/8110S internal 10/100/1000 PHY. 41 */ 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/kernel.h> 46 #include <sys/socket.h> 47 48 49 #include <net/if.h> 50 #include <net/if_media.h> 51 52 #include <dev/mii/mii.h> 53 #include <dev/mii/miivar.h> 54 #include <dev/mii/miidevs.h> 55 56 #include <dev/mii/rgephyreg.h> 57 58 #include <dev/ic/rtl81x9reg.h> 59 60 static int rgephy_match(struct device *, struct cfdata *, void *); 61 static void rgephy_attach(struct device *, struct device *, void *); 62 63 CFATTACH_DECL(rgephy, sizeof(struct mii_softc), 64 rgephy_match, rgephy_attach, mii_phy_detach, mii_phy_activate); 65 66 67 static int rgephy_service(struct mii_softc *, struct mii_data *, int); 68 static void rgephy_status(struct mii_softc *); 69 static int rgephy_mii_phy_auto(struct mii_softc *); 70 static void rgephy_reset(struct mii_softc *); 71 static void rgephy_loop(struct mii_softc *); 72 static void rgephy_load_dspcode(struct mii_softc *); 73 static int rgephy_mii_model; 74 75 static const struct mii_phy_funcs rgephy_funcs = { 76 rgephy_service, rgephy_status, rgephy_reset, 77 }; 78 79 static const struct mii_phydesc rgephys[] = { 80 { MII_OUI_xxREALTEK, MII_MODEL_xxREALTEK_RTL8169S, 81 MII_STR_xxREALTEK_RTL8169S }, 82 83 { MII_OUI_REALTEK, MII_MODEL_REALTEK_RTL8169S, 84 MII_STR_REALTEK_RTL8169S }, 85 86 { 0, 0, 87 NULL } 88 }; 89 90 static int 91 rgephy_match(struct device *parent __unused, struct cfdata *match __unused, 92 void *aux) 93 { 94 struct mii_attach_args *ma = aux; 95 96 if (mii_phy_match(ma, rgephys) != NULL) 97 return (10); 98 99 return (0); 100 } 101 102 static void 103 rgephy_attach(struct device *parent __unused, struct device *self, void *aux) 104 { 105 struct mii_softc *sc = device_private(self); 106 struct mii_attach_args *ma = aux; 107 struct mii_data *mii = ma->mii_data; 108 const struct mii_phydesc *mpd; 109 int rev; 110 const char *sep = ""; 111 112 rev = MII_REV(ma->mii_id2); 113 mpd = mii_phy_match(ma, rgephys); 114 aprint_naive(": Media interface\n"); 115 aprint_normal(": %s, rev. %d\n", mpd->mpd_name, rev); 116 117 sc->mii_mpd_model = rev; /* XXX miivar.h comment vs usage? */ 118 sc->mii_inst = mii->mii_instance; 119 sc->mii_phy = ma->mii_phyno; 120 sc->mii_pdata = mii; 121 sc->mii_flags = mii->mii_flags; 122 sc->mii_anegticks = 5; 123 124 sc->mii_funcs = &rgephy_funcs; 125 126 /* Don't do isolate on this PHY. */ 127 sc->mii_flags |= MIIF_NOISOLATE; 128 129 #define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL) 130 #define PRINT(n) aprint_normal("%s%s", sep, (n)); sep = ", " 131 132 #if 0 133 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, sc->mii_inst), 134 BMCR_ISO); 135 #endif 136 #ifdef __FreeBSD__ 137 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst), 138 BMCR_LOOP|BMCR_S100); 139 #endif 140 141 rgephy_mii_model = MII_MODEL(ma->mii_id2); 142 PHY_RESET(sc); 143 144 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask; 145 sc->mii_capabilities &= ~BMSR_ANEG; 146 147 /* 148 * FreeBSD does not check EXSTAT, but instead adds gigabit 149 * media explicitly. Why? 150 */ 151 aprint_normal("%s: ", sc->mii_dev.dv_xname); 152 #ifdef __FreeBSD__ 153 mii_phy_add_media(sc); 154 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, 0, sc->mii_inst), 155 RGEPHY_BMCR_FDX); 156 PRINT(", 1000baseTX"); 157 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, IFM_FDX, sc->mii_inst), 0); 158 PRINT("1000baseTX-FDX"); 159 #else 160 if (sc->mii_capabilities & BMSR_EXTSTAT) { 161 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); 162 } 163 mii_phy_add_media(sc); 164 #endif 165 /* rtl8169S does not report auto-sense; add manually. */ 166 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), MII_NMEDIA); 167 sep =", "; 168 PRINT("auto"); 169 170 #undef ADD 171 #undef PRINT 172 173 aprint_normal("\n"); 174 } 175 176 static int 177 rgephy_service(sc, mii, cmd) 178 struct mii_softc *sc; 179 struct mii_data *mii; 180 int cmd; 181 { 182 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 183 int reg, speed, gig; 184 185 switch (cmd) { 186 case MII_POLLSTAT: 187 /* 188 * If we're not polling our PHY instance, just return. 189 */ 190 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 191 return (0); 192 break; 193 194 case MII_MEDIACHG: 195 /* 196 * If the media indicates a different PHY instance, 197 * isolate ourselves. 198 */ 199 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 200 reg = PHY_READ(sc, MII_BMCR); 201 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO); 202 return (0); 203 } 204 205 /* 206 * If the interface is not up, don't do anything. 207 */ 208 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 209 break; 210 211 PHY_RESET(sc); /* XXX hardware bug work-around */ 212 213 switch (IFM_SUBTYPE(ife->ifm_media)) { 214 case IFM_AUTO: 215 #ifdef foo 216 /* 217 * If we're already in auto mode, just return. 218 */ 219 if (PHY_READ(sc, RGEPHY_MII_BMCR) & RGEPHY_BMCR_AUTOEN) 220 return (0); 221 #endif 222 (void) rgephy_mii_phy_auto(sc); 223 break; 224 case IFM_1000_T: 225 speed = RGEPHY_S1000; 226 goto setit; 227 case IFM_100_TX: 228 speed = RGEPHY_S100; 229 goto setit; 230 case IFM_10_T: 231 speed = RGEPHY_S10; 232 setit: 233 rgephy_loop(sc); 234 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 235 speed |= RGEPHY_BMCR_FDX; 236 gig = RGEPHY_1000CTL_AFD; 237 } else { 238 gig = RGEPHY_1000CTL_AHD; 239 } 240 241 PHY_WRITE(sc, RGEPHY_MII_1000CTL, 0); 242 PHY_WRITE(sc, RGEPHY_MII_BMCR, speed); 243 PHY_WRITE(sc, RGEPHY_MII_ANAR, RGEPHY_SEL_TYPE); 244 245 if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T) 246 break; 247 248 PHY_WRITE(sc, RGEPHY_MII_1000CTL, gig); 249 PHY_WRITE(sc, RGEPHY_MII_BMCR, 250 speed|RGEPHY_BMCR_AUTOEN|RGEPHY_BMCR_STARTNEG); 251 252 /* 253 * When settning the link manually, one side must 254 * be the master and the other the slave. However 255 * ifmedia doesn't give us a good way to specify 256 * this, so we fake it by using one of the LINK 257 * flags. If LINK0 is set, we program the PHY to 258 * be a master, otherwise it's a slave. 259 */ 260 if ((mii->mii_ifp->if_flags & IFF_LINK0)) { 261 PHY_WRITE(sc, RGEPHY_MII_1000CTL, 262 gig|RGEPHY_1000CTL_MSE|RGEPHY_1000CTL_MSC); 263 } else { 264 PHY_WRITE(sc, RGEPHY_MII_1000CTL, 265 gig|RGEPHY_1000CTL_MSE); 266 } 267 break; 268 #ifdef foo 269 case IFM_NONE: 270 PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN); 271 break; 272 #endif 273 case IFM_100_T4: 274 default: 275 return (EINVAL); 276 } 277 break; 278 279 case MII_TICK: 280 /* 281 * If we're not currently selected, just return. 282 */ 283 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 284 return (0); 285 286 /* 287 * Is the interface even up? 288 */ 289 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 290 return (0); 291 292 /* 293 * Only used for autonegotiation. 294 */ 295 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) 296 break; 297 298 /* 299 * Check to see if we have link. If we do, we don't 300 * need to restart the autonegotiation process. Read 301 * the BMSR twice in case it's latched. 302 */ 303 reg = PHY_READ(sc, RTK_GMEDIASTAT); 304 if (reg & RTK_GMEDIASTAT_LINK) 305 break; 306 307 /* 308 * Only retry autonegotiation every 5 seconds. 309 */ 310 if (++sc->mii_ticks <= 5/*10*/) 311 break; 312 313 sc->mii_ticks = 0; 314 rgephy_mii_phy_auto(sc); 315 return (0); 316 } 317 318 /* Update the media status. */ 319 rgephy_status(sc); 320 321 /* 322 * Callback if something changed. Note that we need to poke 323 * the DSP on the RealTek PHYs if the media changes. 324 * 325 */ 326 if (sc->mii_media_active != mii->mii_media_active || 327 sc->mii_media_status != mii->mii_media_status || 328 cmd == MII_MEDIACHG) { 329 /* XXX only for v0/v1 phys. */ 330 if (sc->mii_mpd_model < 2) 331 rgephy_load_dspcode(sc); 332 } 333 mii_phy_update(sc, cmd); 334 return (0); 335 } 336 337 static void 338 rgephy_status(sc) 339 struct mii_softc *sc; 340 { 341 struct mii_data *mii = sc->mii_pdata; 342 int bmsr, bmcr; 343 344 mii->mii_media_status = IFM_AVALID; 345 mii->mii_media_active = IFM_ETHER; 346 347 bmsr = PHY_READ(sc, RTK_GMEDIASTAT); 348 349 if (bmsr & RTK_GMEDIASTAT_LINK) 350 mii->mii_media_status |= IFM_ACTIVE; 351 bmsr = PHY_READ(sc, RGEPHY_MII_BMSR); 352 353 bmcr = PHY_READ(sc, RGEPHY_MII_BMCR); 354 355 if (bmcr & RGEPHY_BMCR_ISO) { 356 mii->mii_media_active |= IFM_NONE; 357 mii->mii_media_status = 0; 358 return; 359 } 360 361 if (bmcr & RGEPHY_BMCR_LOOP) 362 mii->mii_media_active |= IFM_LOOP; 363 364 if (bmcr & RGEPHY_BMCR_AUTOEN) { 365 if ((bmsr & RGEPHY_BMSR_ACOMP) == 0) { 366 /* Erg, still trying, I guess... */ 367 mii->mii_media_active |= IFM_NONE; 368 return; 369 } 370 } 371 372 bmsr = PHY_READ(sc, RTK_GMEDIASTAT); 373 if (bmsr & RTK_GMEDIASTAT_10MBPS) 374 mii->mii_media_active |= IFM_10_T; 375 if (bmsr & RTK_GMEDIASTAT_100MBPS) 376 mii->mii_media_active |= IFM_100_TX; 377 if (bmsr & RTK_GMEDIASTAT_1000MBPS) 378 mii->mii_media_active |= IFM_1000_T; 379 if (bmsr & RTK_GMEDIASTAT_FDX) 380 mii->mii_media_active |= IFM_FDX; 381 382 return; 383 } 384 385 386 static int 387 rgephy_mii_phy_auto(mii) 388 struct mii_softc *mii; 389 { 390 rgephy_loop(mii); 391 PHY_RESET(mii); 392 393 PHY_WRITE(mii, RGEPHY_MII_ANAR, 394 BMSR_MEDIA_TO_ANAR(mii->mii_capabilities) | ANAR_CSMA); 395 DELAY(1000); 396 PHY_WRITE(mii, RGEPHY_MII_1000CTL, RGEPHY_1000CTL_AFD); 397 DELAY(1000); 398 PHY_WRITE(mii, RGEPHY_MII_BMCR, 399 RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG); 400 DELAY(100); 401 402 return (EJUSTRETURN); 403 } 404 405 static void 406 rgephy_loop(struct mii_softc *sc) 407 { 408 u_int32_t bmsr; 409 int i; 410 411 PHY_WRITE(sc, RGEPHY_MII_BMCR, RGEPHY_BMCR_PDOWN); 412 DELAY(1000); 413 414 for (i = 0; i < 15000; i++) { 415 bmsr = PHY_READ(sc, RGEPHY_MII_BMSR); 416 if (!(bmsr & RGEPHY_BMSR_LINK)) { 417 #if 0 418 device_printf(sc->mii_dev, "looped %d\n", i); 419 #endif 420 break; 421 } 422 DELAY(10); 423 } 424 } 425 426 #define PHY_SETBIT(x, y, z) \ 427 PHY_WRITE(x, y, (PHY_READ(x, y) | (z))) 428 #define PHY_CLRBIT(x, y, z) \ 429 PHY_WRITE(x, y, (PHY_READ(x, y) & ~(z))) 430 431 /* 432 * Initialize RealTek PHY per the datasheet. The DSP in the PHYs of 433 * existing revisions of the 8169S/8110S chips need to be tuned in 434 * order to reliably negotiate a 1000Mbps link. Later revs of the 435 * chips may not require this software tuning. 436 */ 437 static void 438 rgephy_load_dspcode(struct mii_softc *sc) 439 { 440 int val; 441 442 #if 1 443 PHY_WRITE(sc, 31, 0x0001); 444 PHY_WRITE(sc, 21, 0x1000); 445 PHY_WRITE(sc, 24, 0x65C7); 446 PHY_CLRBIT(sc, 4, 0x0800); 447 val = PHY_READ(sc, 4) & 0xFFF; 448 PHY_WRITE(sc, 4, val); 449 PHY_WRITE(sc, 3, 0x00A1); 450 PHY_WRITE(sc, 2, 0x0008); 451 PHY_WRITE(sc, 1, 0x1020); 452 PHY_WRITE(sc, 0, 0x1000); 453 PHY_SETBIT(sc, 4, 0x0800); 454 PHY_CLRBIT(sc, 4, 0x0800); 455 val = (PHY_READ(sc, 4) & 0xFFF) | 0x7000; 456 PHY_WRITE(sc, 4, val); 457 PHY_WRITE(sc, 3, 0xFF41); 458 PHY_WRITE(sc, 2, 0xDE60); 459 PHY_WRITE(sc, 1, 0x0140); 460 PHY_WRITE(sc, 0, 0x0077); 461 val = (PHY_READ(sc, 4) & 0xFFF) | 0xA000; 462 PHY_WRITE(sc, 4, val); 463 PHY_WRITE(sc, 3, 0xDF01); 464 PHY_WRITE(sc, 2, 0xDF20); 465 PHY_WRITE(sc, 1, 0xFF95); 466 PHY_WRITE(sc, 0, 0xFA00); 467 val = (PHY_READ(sc, 4) & 0xFFF) | 0xB000; 468 PHY_WRITE(sc, 4, val); 469 PHY_WRITE(sc, 3, 0xFF41); 470 PHY_WRITE(sc, 2, 0xDE20); 471 PHY_WRITE(sc, 1, 0x0140); 472 PHY_WRITE(sc, 0, 0x00BB); 473 val = (PHY_READ(sc, 4) & 0xFFF) | 0xF000; 474 PHY_WRITE(sc, 4, val); 475 PHY_WRITE(sc, 3, 0xDF01); 476 PHY_WRITE(sc, 2, 0xDF20); 477 PHY_WRITE(sc, 1, 0xFF95); 478 PHY_WRITE(sc, 0, 0xBF00); 479 PHY_SETBIT(sc, 4, 0x0800); 480 PHY_CLRBIT(sc, 4, 0x0800); 481 PHY_WRITE(sc, 31, 0x0000); 482 #else 483 (void)val; 484 PHY_WRITE(sc, 0x1f, 0x0001); 485 PHY_WRITE(sc, 0x15, 0x1000); 486 PHY_WRITE(sc, 0x18, 0x65c7); 487 PHY_WRITE(sc, 0x04, 0x0000); 488 PHY_WRITE(sc, 0x03, 0x00a1); 489 PHY_WRITE(sc, 0x02, 0x0008); 490 PHY_WRITE(sc, 0x01, 0x1020); 491 PHY_WRITE(sc, 0x00, 0x1000); 492 PHY_WRITE(sc, 0x04, 0x0800); 493 PHY_WRITE(sc, 0x04, 0x0000); 494 PHY_WRITE(sc, 0x04, 0x7000); 495 PHY_WRITE(sc, 0x03, 0xff41); 496 PHY_WRITE(sc, 0x02, 0xde60); 497 PHY_WRITE(sc, 0x01, 0x0140); 498 PHY_WRITE(sc, 0x00, 0x0077); 499 PHY_WRITE(sc, 0x04, 0x7800); 500 PHY_WRITE(sc, 0x04, 0x7000); 501 PHY_WRITE(sc, 0x04, 0xa000); 502 PHY_WRITE(sc, 0x03, 0xdf01); 503 PHY_WRITE(sc, 0x02, 0xdf20); 504 PHY_WRITE(sc, 0x01, 0xff95); 505 PHY_WRITE(sc, 0x00, 0xfa00); 506 PHY_WRITE(sc, 0x04, 0xa800); 507 PHY_WRITE(sc, 0x04, 0xa000); 508 PHY_WRITE(sc, 0x04, 0xb000); 509 PHY_WRITE(sc, 0x0e, 0xff41); 510 PHY_WRITE(sc, 0x02, 0xde20); 511 PHY_WRITE(sc, 0x01, 0x0140); 512 PHY_WRITE(sc, 0x00, 0x00bb); 513 PHY_WRITE(sc, 0x04, 0xb800); 514 PHY_WRITE(sc, 0x04, 0xb000); 515 PHY_WRITE(sc, 0x04, 0xf000); 516 PHY_WRITE(sc, 0x03, 0xdf01); 517 PHY_WRITE(sc, 0x02, 0xdf20); 518 PHY_WRITE(sc, 0x01, 0xff95); 519 PHY_WRITE(sc, 0x00, 0xbf00); 520 PHY_WRITE(sc, 0x04, 0xf800); 521 PHY_WRITE(sc, 0x04, 0xf000); 522 PHY_WRITE(sc, 0x04, 0x0000); 523 PHY_WRITE(sc, 0x1f, 0x0000); 524 PHY_WRITE(sc, 0x0b, 0x0000); 525 526 #endif 527 528 DELAY(40); 529 } 530 531 static void 532 rgephy_reset(struct mii_softc *sc) 533 { 534 mii_phy_reset(sc); 535 DELAY(1000); 536 537 if (sc->mii_mpd_model < 2) 538 rgephy_load_dspcode(sc); 539 else { 540 PHY_WRITE(sc, 0x1F, 0x0001); 541 PHY_WRITE(sc, 0x09, 0x273a); 542 PHY_WRITE(sc, 0x0e, 0x7bfb); 543 PHY_WRITE(sc, 0x1b, 0x841e); 544 545 PHY_WRITE(sc, 0x1F, 0x0002); 546 PHY_WRITE(sc, 0x01, 0x90D0); 547 PHY_WRITE(sc, 0x1F, 0x0000); 548 } 549 550 /* Reset capabilities */ 551 /* Step1: write our capability */ 552 PHY_WRITE(sc, 0x04,0x01e1); /* 10/100 capability */ 553 PHY_WRITE(sc, 0x09,0x0200); /* 1000 capability */ 554 555 #ifdef jrs_notyet 556 /* Step2: Restart NWay */ 557 PHY_WRITE(sc, 0x00, 0x1200); // NWay enable and Restart NWay 558 #endif 559 } 560
Indexes created Fri Oct 03 02:09:57 GMT 2025