memcreg.h revision 1.2
1 /* $NetBSD: memcreg.h,v 1.2 2004/02/13 11:36:22 wiz Exp $ */ 2 3 /*- 4 * Copyright (c) 2000, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Steve C. Woodford. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Register definitions for the MEMECC and MEMC040 devices. 41 */ 42 #ifndef _MVME_MEMCREG_H 43 #define _MVME_MEMCREG_H 44 45 /* 46 * Size, in bytes, of the memory controller's register set 47 * (Actually, the MEMC040's register set is only 0x20 bytes in size, but 48 * we go with the larger of the two). 49 */ 50 #define MEMC_REGSIZE 0x80 51 52 /* Both memory controllers share some registers in common */ 53 #define MEMC_REG_CHIP_ID 0x00 54 #define MEMC_CHIP_ID_MEMC040 0x80 /* It's a MEMC040 */ 55 #define MEMC_CHIP_ID_MEMECC 0x81 /* It's a MEMECC */ 56 57 /* Revision of the ASIC */ 58 #define MEMC_REG_CHIP_REVISION 0x04 59 60 /* Configuration of the memory block controlled by this ASIC */ 61 #define MEMC_REG_MEMORY_CONFIG 0x08 62 #define MEMC_MEMORY_CONFIG_2_BYTES(x) (0x400000 << ((x) & 0x07)) 63 #define MEMC_MEMORY_CONFIG_2_MB(x) (4 << ((x) & 0x07)) 64 #define MEMC040_MEMORY_CONFIG_EXTPEN (1u << 3) /* External parity enabled */ 65 #define MEMC040_MEMORY_CONFIG_WPB (1u << 4) /* Write Per Bit mode */ 66 #define MEMC_MEMORY_CONFIG_FSTRD (1u << 5) /* Fast RAM Read enabled */ 67 68 /* Where, in the CPU's address space, does this memory appear? */ 69 #define MEMC_REG_BASE_ADDRESS_HI 0x14 70 #define MEMC_REG_BASE_ADDRESS_LO 0x18 71 #define MEMC_BASE_ADDRESS(hi,lo) (((hi) << 24) | (((lo) & 0xc0) << 22)) 72 73 /* Tells the memory controller what the board's Bus Clock frequency is */ 74 #define MEMC_REG_BUS_CLOCK 0x1c 75 76 77 /* Register offsets and definitions for the Parity Memory Controller */ 78 #define MEMC040_REG_ALT_STATUS 0x0c /* Not used */ 79 #define MEMC040_REG_ALT_CONTROL 0x10 /* Not used */ 80 81 /* Memory Control Register */ 82 #define MEMC040_REG_RAM_CONTROL 0x18 83 #define MEMC040_RAM_CONTROL_RAMEN (1u << 0) 84 #define MEMC040_RAM_CONTROL_PAREN (1u << 1) 85 #define MEMC040_RAM_CONTROL_PARINT (1u << 2) 86 #define MEMC040_RAM_CONTROL_WWP (1u << 3) 87 #define MEMC040_RAM_CONTROL_SWAIT (1u << 4) 88 #define MEMC040_RAM_CONTROL_DMCTL (1u << 5) 89 90 91 /* Register offsets and definitions for the ECC Memory Controller */ 92 #define MEMECC_REG_DRAM_CONTROL 0x18 93 #define MEMECC_DRAM_CONTROL_RAMEN (1u << 0) 94 #define MEMECC_DRAM_CONTROL_NCEBEN (1u << 1) 95 #define MEMECC_DRAM_CONTROL_NCEIEN (1u << 2) 96 #define MEMECC_DRAM_CONTROL_RWB3 (1u << 3) 97 #define MEMECC_DRAM_CONTROL_SWAIT (1u << 4) 98 #define MEMECC_DRAM_CONTROL_RWB5 (1u << 5) 99 #define MEMECC_DRAM_CONTROL_BAD22 (1u << 6) 100 #define MEMECC_DRAM_CONTROL_BAD23 (1u << 7) 101 102 #define MEMECC_REG_DATA_CONTROL 0x20 103 #define MEMECC_DATA_CONTROL_RWCKB (1u << 3) 104 #define MEMECC_DATA_CONTROL_ZFILL (1u << 4) 105 #define MEMECC_DATA_CONTROL_DERC (1u << 5) 106 107 #define MEMECC_REG_SCRUB_CONTROL 0x24 108 #define MEMECC_SCRUB_CONTROL_IDIS (1u << 0) 109 #define MEMECC_SCRUB_CONTROL_SBEIEN (1u << 1) 110 #define MEMECC_SCRUB_CONTROL_SCRBEN (1u << 3) 111 #define MEMECC_SCRUB_CONTROL_SCRB (1u << 4) 112 #define MEMECC_SCRUB_CONTROL_HITDIS (1u << 5) 113 #define MEMECC_SCRUB_CONTROL_RADATA (1u << 6) 114 #define MEMECC_SCRUB_CONTROL_RACODE (1u << 7) 115 116 #define MEMECC_REG_SCRUB_PERIOD_HI 0x28 117 #define MEMECC_SCRUB_PERIOD_HI(secs) (((secs) / 2) >> 8) 118 #define MEMECC_REG_SCRUB_PERIOD_LO 0x2c 119 #define MEMECC_SCRUB_PERIOD_LO(secs) (((secs) / 2) & 0xffu) 120 121 #define MEMECC_REG_CHIP_PRESCALE 0x30 122 123 #define MEMECC_REG_SCRUB_TIME_ONOFF 0x34 124 #define MEMECC_SCRUB_TIME_ONOFF_MASK 0x07u 125 #define MEMECC_SCRUB_TIME_OFF_0 0u 126 #define MEMECC_SCRUB_TIME_OFF_16 1u 127 #define MEMECC_SCRUB_TIME_OFF_32 2u 128 #define MEMECC_SCRUB_TIME_OFF_64 3u 129 #define MEMECC_SCRUB_TIME_OFF_128 4u 130 #define MEMECC_SCRUB_TIME_OFF_256 5u 131 #define MEMECC_SCRUB_TIME_OFF_512 6u 132 #define MEMECC_SCRUB_TIME_OFF_NEVER 7u 133 #define MEMECC_SCRUB_TIME_ON_1 (0u << 3) 134 #define MEMECC_SCRUB_TIME_ON_16 (1u << 3) 135 #define MEMECC_SCRUB_TIME_ON_32 (2u << 3) 136 #define MEMECC_SCRUB_TIME_ON_64 (3u << 3) 137 #define MEMECC_SCRUB_TIME_ON_128 (4u << 3) 138 #define MEMECC_SCRUB_TIME_ON_256 (5u << 3) 139 #define MEMECC_SCRUB_TIME_ON_512 (6u << 3) 140 #define MEMECC_SCRUB_TIME_ON_ALWAYS (7u << 3) 141 #define MEMECC_SCRUB_TIME_SRDIS (1u << 7) 142 143 #define MEMECC_REG_SCRUB_PRESCALE_HI 0x38 144 #define MEMECC_REG_SCRUB_PRESCALE_MID 0x3c 145 #define MEMECC_REG_SCRUB_PRESCALE_LO 0x40 146 147 #define MEMECC_REG_SCRUB_TIMER_HI 0x44 148 #define MEMECC_REG_SCRUB_TIMER_LO 0x48 149 150 #define MEMECC_REG_SCRUB_ADDR_CNTR_HIHI 0x4c 151 #define MEMECC_REG_SCRUB_ADDR_CNTR_HI 0x50 152 #define MEMECC_REG_SCRUB_ADDR_CNTR_MID 0x54 153 #define MEMECC_REG_SCRUB_ADDR_CNTR_LO 0x58 154 155 #define MEMECC_REG_ERROR_LOGGER 0x5c 156 #define MEMECC_ERROR_LOGGER_MASK 0x7fu 157 #define MEMECC_ERROR_LOGGER_SBE (1u << 0) 158 #define MEMECC_ERROR_LOGGER_MBE (1u << 1) 159 #define MEMECC_ERROR_LOGGER_EALT (1u << 3) 160 #define MEMECC_ERROR_LOGGER_ERA (1u << 4) 161 #define MEMECC_ERROR_LOGGER_ESCRB (1u << 5) 162 #define MEMECC_ERROR_LOGGER_ERD (1u << 6) 163 #define MEMECC_ERROR_LOGGER_ERRLOG (1u << 7) 164 165 #define MEMECC_REG_ERROR_ADDRESS_HIHI 0x60 166 #define MEMECC_REG_ERROR_ADDRESS_HI 0x64 167 #define MEMECC_REG_ERROR_ADDRESS_MID 0x68 168 #define MEMECC_REG_ERROR_ADDRESS_LO 0x6c 169 170 #define MEMECC_REG_ERROR_SYNDROME 0x70 171 172 #define MEMECC_REG_DEFAULTS1 0x74 173 #define MEMECC_REG_DEFAULTS2 0x78 174 175 #define MEMECC_REG_SDRAM_CONFIG 0x7c 176 177 #endif /* _MVME_MEMCREG_H */ 178
Indexes created Fri Sep 26 20:09:58 GMT 2025