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vme_two_isr.c revision 1.1.2.2
      1  1.1.2.2  nathanw /*	$NetBSD: vme_two_isr.c,v 1.1.2.2 2002/02/28 04:13:55 nathanw Exp $	*/
      2  1.1.2.2  nathanw 
      3  1.1.2.2  nathanw /*-
      4  1.1.2.2  nathanw  * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc.
      5  1.1.2.2  nathanw  * All rights reserved.
      6  1.1.2.2  nathanw  *
      7  1.1.2.2  nathanw  * This code is derived from software contributed to The NetBSD Foundation
      8  1.1.2.2  nathanw  * by Steve C. Woodford.
      9  1.1.2.2  nathanw  *
     10  1.1.2.2  nathanw  * Redistribution and use in source and binary forms, with or without
     11  1.1.2.2  nathanw  * modification, are permitted provided that the following conditions
     12  1.1.2.2  nathanw  * are met:
     13  1.1.2.2  nathanw  * 1. Redistributions of source code must retain the above copyright
     14  1.1.2.2  nathanw  *    notice, this list of conditions and the following disclaimer.
     15  1.1.2.2  nathanw  * 2. Redistributions in binary form must reproduce the above copyright
     16  1.1.2.2  nathanw  *    notice, this list of conditions and the following disclaimer in the
     17  1.1.2.2  nathanw  *    documentation and/or other materials provided with the distribution.
     18  1.1.2.2  nathanw  * 3. All advertising materials mentioning features or use of this software
     19  1.1.2.2  nathanw  *    must display the following acknowledgement:
     20  1.1.2.2  nathanw  *        This product includes software developed by the NetBSD
     21  1.1.2.2  nathanw  *        Foundation, Inc. and its contributors.
     22  1.1.2.2  nathanw  * 4. Neither the name of The NetBSD Foundation nor the names of its
     23  1.1.2.2  nathanw  *    contributors may be used to endorse or promote products derived
     24  1.1.2.2  nathanw  *    from this software without specific prior written permission.
     25  1.1.2.2  nathanw  *
     26  1.1.2.2  nathanw  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     27  1.1.2.2  nathanw  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     28  1.1.2.2  nathanw  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     29  1.1.2.2  nathanw  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     30  1.1.2.2  nathanw  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     31  1.1.2.2  nathanw  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     32  1.1.2.2  nathanw  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     33  1.1.2.2  nathanw  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     34  1.1.2.2  nathanw  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     35  1.1.2.2  nathanw  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     36  1.1.2.2  nathanw  * POSSIBILITY OF SUCH DAMAGE.
     37  1.1.2.2  nathanw  */
     38  1.1.2.2  nathanw 
     39  1.1.2.2  nathanw /*
     40  1.1.2.2  nathanw  * Split off from vme_two.c specifically to deal with hardware assisted
     41  1.1.2.2  nathanw  * soft interrupts when the user hasn't specified `vmetwo0' in the
     42  1.1.2.2  nathanw  * kernel config file (mvme1[67]2 only).
     43  1.1.2.2  nathanw  */
     44  1.1.2.2  nathanw 
     45  1.1.2.2  nathanw #include "vmetwo.h"
     46  1.1.2.2  nathanw 
     47  1.1.2.2  nathanw #include <sys/param.h>
     48  1.1.2.2  nathanw #include <sys/kernel.h>
     49  1.1.2.2  nathanw #include <sys/systm.h>
     50  1.1.2.2  nathanw #include <sys/device.h>
     51  1.1.2.2  nathanw #include <sys/malloc.h>
     52  1.1.2.2  nathanw 
     53  1.1.2.2  nathanw #include <machine/cpu.h>
     54  1.1.2.2  nathanw #include <machine/bus.h>
     55  1.1.2.2  nathanw 
     56  1.1.2.2  nathanw #include <dev/vme/vmereg.h>
     57  1.1.2.2  nathanw #include <dev/vme/vmevar.h>
     58  1.1.2.2  nathanw 
     59  1.1.2.2  nathanw #include <dev/mvme/mvmebus.h>
     60  1.1.2.2  nathanw #include <dev/mvme/vme_tworeg.h>
     61  1.1.2.2  nathanw #include <dev/mvme/vme_twovar.h>
     62  1.1.2.2  nathanw 
     63  1.1.2.2  nathanw /*
     64  1.1.2.2  nathanw  * Non-zero if there is no VMEChip2 on this board.
     65  1.1.2.2  nathanw  */
     66  1.1.2.2  nathanw int vmetwo_not_present;
     67  1.1.2.2  nathanw 
     68  1.1.2.2  nathanw /*
     69  1.1.2.2  nathanw  * Array of interrupt handlers registered with us for the non-VMEbus
     70  1.1.2.2  nathanw  * vectored interrupts. Eg. ABORT Switch, SYSFAIL etc.
     71  1.1.2.2  nathanw  *
     72  1.1.2.2  nathanw  * We can't just install a caller's handler directly, since these
     73  1.1.2.2  nathanw  * interrupts have to be manually cleared, so we have a trampoline
     74  1.1.2.2  nathanw  * which does the clearing automatically.
     75  1.1.2.2  nathanw  */
     76  1.1.2.2  nathanw static struct vme_two_handler {
     77  1.1.2.2  nathanw 	int (*isr_hand) __P((void *));
     78  1.1.2.2  nathanw 	void *isr_arg;
     79  1.1.2.2  nathanw } vme_two_handlers[(VME2_VECTOR_LOCAL_MAX - VME2_VECTOR_LOCAL_MIN) + 1];
     80  1.1.2.2  nathanw 
     81  1.1.2.2  nathanw #define VMETWO_HANDLERS_SZ	(sizeof(vme_two_handlers) /	\
     82  1.1.2.2  nathanw 				 sizeof(struct vme_two_handler))
     83  1.1.2.2  nathanw 
     84  1.1.2.2  nathanw static	int  vmetwo_local_isr_trampoline(void *);
     85  1.1.2.2  nathanw static	void vmetwo_softintr_assert(void);
     86  1.1.2.2  nathanw 
     87  1.1.2.2  nathanw static	struct vmetwo_softc *vmetwo_sc;
     88  1.1.2.2  nathanw 
     89  1.1.2.2  nathanw int
     90  1.1.2.2  nathanw vmetwo_probe(bus_space_tag_t bt, bus_addr_t offset)
     91  1.1.2.2  nathanw {
     92  1.1.2.2  nathanw 	bus_space_handle_t bh;
     93  1.1.2.2  nathanw 
     94  1.1.2.2  nathanw 	bus_space_map(bt, offset + VME2REG_LCSR_OFFSET, VME2LCSR_SIZE, 0, &bh);
     95  1.1.2.2  nathanw 
     96  1.1.2.2  nathanw 	if (bus_space_peek_4(bt, bh, VME2LCSR_MISC_STATUS, NULL) != 0) {
     97  1.1.2.2  nathanw #if defined(MVME162) || defined(MVME172)
     98  1.1.2.2  nathanw #if defined(MVME167) || defined(MVME177)
     99  1.1.2.2  nathanw 		if (machineid == MVME_162 || machineid == MVME_172)
    100  1.1.2.2  nathanw #endif
    101  1.1.2.2  nathanw 		{
    102  1.1.2.2  nathanw 			/*
    103  1.1.2.2  nathanw 			 * No VMEChip2 on mvme162/172 is not too big a
    104  1.1.2.2  nathanw 			 * deal; we can fall back on timer4 in the
    105  1.1.2.2  nathanw 			 * mcchip for h/w assisted soft interrupts...
    106  1.1.2.2  nathanw 			 */
    107  1.1.2.2  nathanw 			extern void pcctwosoftintrinit(void);
    108  1.1.2.2  nathanw 			bus_space_unmap(bt, bh, VME2LCSR_SIZE);
    109  1.1.2.2  nathanw 			vmetwo_not_present = 1;
    110  1.1.2.2  nathanw 			pcctwosoftintrinit();
    111  1.1.2.2  nathanw 			return (0);
    112  1.1.2.2  nathanw 		}
    113  1.1.2.2  nathanw #endif
    114  1.1.2.2  nathanw #if defined(MVME167) || defined(MVME177) || defined(MVME88K)
    115  1.1.2.2  nathanw 		/*
    116  1.1.2.2  nathanw 		 * No VMEChip2 on mvme167/177, however, is a Big Deal.
    117  1.1.2.2  nathanw 		 * In fact, it means the hardware's shot since the
    118  1.1.2.2  nathanw 		 * VMEChip2 is not a `build-option' on those boards.
    119  1.1.2.2  nathanw 		 */
    120  1.1.2.2  nathanw 		panic("VMEChip2 not responding! Faulty board?");
    121  1.1.2.2  nathanw 		/* NOTREACHED */
    122  1.1.2.2  nathanw #endif
    123  1.1.2.2  nathanw #if defined(MVMEPPC)
    124  1.1.2.2  nathanw 		/*
    125  1.1.2.2  nathanw 		 * No VMEChip2 on mvmeppc is no big deal.
    126  1.1.2.2  nathanw 		 */
    127  1.1.2.2  nathanw 		bus_space_unmap(bt, bh, VME2LCSR_SIZE);
    128  1.1.2.2  nathanw 		vmetwo_not_present = 1;
    129  1.1.2.2  nathanw 		return (0);
    130  1.1.2.2  nathanw #endif
    131  1.1.2.2  nathanw 	}
    132  1.1.2.2  nathanw #if NVMETWO == 0
    133  1.1.2.2  nathanw 	else {
    134  1.1.2.2  nathanw 		/*
    135  1.1.2.2  nathanw 		 * The kernel config file has no `vmetwo0' device, but
    136  1.1.2.2  nathanw 		 * there is a VMEChip2 on the board. Fix up things
    137  1.1.2.2  nathanw 		 * just enough to hook VMEChip2 local interrupts.
    138  1.1.2.2  nathanw 		 */
    139  1.1.2.2  nathanw 		struct vmetwo_softc *sc;
    140  1.1.2.2  nathanw 
    141  1.1.2.2  nathanw 		/* XXX Should check sc != NULL here... */
    142  1.1.2.2  nathanw 		MALLOC(sc, struct vmetwo_softc *, sizeof(*sc), M_DEVBUF,
    143  1.1.2.2  nathanw 		    M_NOWAIT);
    144  1.1.2.2  nathanw 
    145  1.1.2.2  nathanw 		sc->sc_mvmebus.sc_bust = bt;
    146  1.1.2.2  nathanw 		sc->sc_lcrh = bh;
    147  1.1.2.2  nathanw 		vmetwo_intr_init(sc);
    148  1.1.2.2  nathanw 		return 0;
    149  1.1.2.2  nathanw 	}
    150  1.1.2.2  nathanw #else
    151  1.1.2.2  nathanw 	bus_space_unmap(bt, bh, VME2LCSR_SIZE);
    152  1.1.2.2  nathanw 	return (1);
    153  1.1.2.2  nathanw #endif
    154  1.1.2.2  nathanw }
    155  1.1.2.2  nathanw 
    156  1.1.2.2  nathanw void
    157  1.1.2.2  nathanw vmetwo_intr_init(struct vmetwo_softc *sc)
    158  1.1.2.2  nathanw {
    159  1.1.2.2  nathanw 	u_int32_t reg;
    160  1.1.2.2  nathanw 	int i;
    161  1.1.2.2  nathanw 
    162  1.1.2.2  nathanw 	vmetwo_sc = sc;
    163  1.1.2.2  nathanw 
    164  1.1.2.2  nathanw 	/* Clear out the ISR handler array */
    165  1.1.2.2  nathanw 	for (i = 0; i < VMETWO_HANDLERS_SZ; i++)
    166  1.1.2.2  nathanw 		vme_two_handlers[i].isr_hand = NULL;
    167  1.1.2.2  nathanw 
    168  1.1.2.2  nathanw 	/*
    169  1.1.2.2  nathanw 	 * Initialize the chip.
    170  1.1.2.2  nathanw 	 * Firstly, disable all VMEChip2 Interrupts
    171  1.1.2.2  nathanw 	 */
    172  1.1.2.2  nathanw 	reg = vme2_lcsr_read(sc, VME2LCSR_MISC_STATUS) & ~VME2_MISC_STATUS_MIEN;
    173  1.1.2.2  nathanw 	vme2_lcsr_write(sc, VME2LCSR_MISC_STATUS, reg);
    174  1.1.2.2  nathanw 	vme2_lcsr_write(sc, VME2LCSR_LOCAL_INTERRUPT_ENABLE, 0);
    175  1.1.2.2  nathanw 	vme2_lcsr_write(sc, VME2LCSR_LOCAL_INTERRUPT_CLEAR,
    176  1.1.2.2  nathanw 	    VME2_LOCAL_INTERRUPT_CLEAR_ALL);
    177  1.1.2.2  nathanw 
    178  1.1.2.2  nathanw 	/* Zap all the IRQ level registers */
    179  1.1.2.2  nathanw 	for (i = 0; i < VME2_NUM_IL_REGS; i++)
    180  1.1.2.2  nathanw 		vme2_lcsr_write(sc, VME2LCSR_INTERRUPT_LEVEL_BASE + (i * 4), 0);
    181  1.1.2.2  nathanw 
    182  1.1.2.2  nathanw 	/* Disable the tick timers */
    183  1.1.2.2  nathanw 	reg = vme2_lcsr_read(sc, VME2LCSR_TIMER_CONTROL);
    184  1.1.2.2  nathanw 	reg &= ~VME2_TIMER_CONTROL_EN(0);
    185  1.1.2.2  nathanw 	reg &= ~VME2_TIMER_CONTROL_EN(1);
    186  1.1.2.2  nathanw 	vme2_lcsr_write(sc, VME2LCSR_TIMER_CONTROL, reg);
    187  1.1.2.2  nathanw 
    188  1.1.2.2  nathanw 	/* Set the VMEChip2's vector base register to the required value */
    189  1.1.2.2  nathanw 	reg = vme2_lcsr_read(sc, VME2LCSR_VECTOR_BASE);
    190  1.1.2.2  nathanw 	reg &= ~VME2_VECTOR_BASE_MASK;
    191  1.1.2.2  nathanw 	reg |= VME2_VECTOR_BASE_REG_VALUE;
    192  1.1.2.2  nathanw 	vme2_lcsr_write(sc, VME2LCSR_VECTOR_BASE, reg);
    193  1.1.2.2  nathanw 
    194  1.1.2.2  nathanw 	/* Set the Master Interrupt Enable bit now */
    195  1.1.2.2  nathanw 	reg = vme2_lcsr_read(sc, VME2LCSR_MISC_STATUS) | VME2_MISC_STATUS_MIEN;
    196  1.1.2.2  nathanw 	vme2_lcsr_write(sc, VME2LCSR_MISC_STATUS, reg);
    197  1.1.2.2  nathanw 
    198  1.1.2.2  nathanw #if defined(MVME167) || defined(MVME177)
    199  1.1.2.2  nathanw #if defined(MVME162) || defined(MVME172)
    200  1.1.2.2  nathanw 	if (machineid != MVME_162 && machineid != MVME_172)
    201  1.1.2.2  nathanw #endif
    202  1.1.2.2  nathanw 	{
    203  1.1.2.2  nathanw 		/*
    204  1.1.2.2  nathanw 		 * Let the NMI handler deal with level 7 ABORT switch
    205  1.1.2.2  nathanw 		 * interrupts
    206  1.1.2.2  nathanw 		 */
    207  1.1.2.2  nathanw 		vmetwo_intr_establish(sc, 7, 7, VME2_VEC_ABORT, 1,
    208  1.1.2.2  nathanw 		    nmihand, NULL, NULL);
    209  1.1.2.2  nathanw 	}
    210  1.1.2.2  nathanw #endif
    211  1.1.2.2  nathanw 
    212  1.1.2.2  nathanw 	/* Setup hardware assisted soft interrupts */
    213  1.1.2.2  nathanw 	vmetwo_intr_establish(sc, 1, 1, VME2_VEC_SOFT0, 1,
    214  1.1.2.2  nathanw 	    (int (*)(void *))softintr_dispatch, NULL, NULL);
    215  1.1.2.2  nathanw 	_softintr_chipset_assert = vmetwo_softintr_assert;
    216  1.1.2.2  nathanw }
    217  1.1.2.2  nathanw 
    218  1.1.2.2  nathanw static int
    219  1.1.2.2  nathanw vmetwo_local_isr_trampoline(arg)
    220  1.1.2.2  nathanw 	void *arg;
    221  1.1.2.2  nathanw {
    222  1.1.2.2  nathanw 	struct vme_two_handler *isr;
    223  1.1.2.2  nathanw 	int vec;
    224  1.1.2.2  nathanw 
    225  1.1.2.2  nathanw 	vec = (int) arg;	/* 0x08 <= vec <= 0x1f */
    226  1.1.2.2  nathanw 
    227  1.1.2.2  nathanw 	/* Clear the interrupt source */
    228  1.1.2.2  nathanw 	vme2_lcsr_write(vmetwo_sc, VME2LCSR_LOCAL_INTERRUPT_CLEAR,
    229  1.1.2.2  nathanw 	    VME2_LOCAL_INTERRUPT(vec));
    230  1.1.2.2  nathanw 
    231  1.1.2.2  nathanw 	isr = &vme_two_handlers[vec - VME2_VECTOR_LOCAL_OFFSET];
    232  1.1.2.2  nathanw 	if (isr->isr_hand)
    233  1.1.2.2  nathanw 		(void) (*isr->isr_hand) (isr->isr_arg);
    234  1.1.2.2  nathanw 	else
    235  1.1.2.2  nathanw 		printf("vmetwo: Spurious local interrupt, vector 0x%x\n", vec);
    236  1.1.2.2  nathanw 
    237  1.1.2.2  nathanw 	return (1);
    238  1.1.2.2  nathanw }
    239  1.1.2.2  nathanw 
    240  1.1.2.2  nathanw void
    241  1.1.2.2  nathanw vmetwo_local_intr_establish(pri, vec, hand, arg, evcnt)
    242  1.1.2.2  nathanw 	int pri, vec;
    243  1.1.2.2  nathanw 	int (*hand)(void *);
    244  1.1.2.2  nathanw 	void *arg;
    245  1.1.2.2  nathanw 	struct evcnt *evcnt;
    246  1.1.2.2  nathanw {
    247  1.1.2.2  nathanw 
    248  1.1.2.2  nathanw 	vmetwo_intr_establish(vmetwo_sc, pri, pri, vec, 1, hand, arg, evcnt);
    249  1.1.2.2  nathanw }
    250  1.1.2.2  nathanw 
    251  1.1.2.2  nathanw /* ARGSUSED */
    252  1.1.2.2  nathanw void
    253  1.1.2.2  nathanw vmetwo_intr_establish(csc, prior, lvl, vec, first, hand, arg, evcnt)
    254  1.1.2.2  nathanw 	void *csc;
    255  1.1.2.2  nathanw 	int prior, lvl, vec, first;
    256  1.1.2.2  nathanw 	int (*hand)(void *);
    257  1.1.2.2  nathanw 	void *arg;
    258  1.1.2.2  nathanw 	struct evcnt *evcnt;
    259  1.1.2.2  nathanw {
    260  1.1.2.2  nathanw 	struct vmetwo_softc *sc = csc;
    261  1.1.2.2  nathanw 	u_int32_t reg;
    262  1.1.2.2  nathanw 	int bitoff;
    263  1.1.2.2  nathanw 	int iloffset, ilshift;
    264  1.1.2.2  nathanw 	int s;
    265  1.1.2.2  nathanw 
    266  1.1.2.2  nathanw 	s = splhigh();
    267  1.1.2.2  nathanw 
    268  1.1.2.2  nathanw #if NVMETWO > 0
    269  1.1.2.2  nathanw 	/*
    270  1.1.2.2  nathanw 	 * Sort out interrupts generated locally by the VMEChip2 from
    271  1.1.2.2  nathanw 	 * those generated by VMEbus devices...
    272  1.1.2.2  nathanw 	 */
    273  1.1.2.2  nathanw 	if (vec >= VME2_VECTOR_LOCAL_MIN && vec <= VME2_VECTOR_LOCAL_MAX) {
    274  1.1.2.2  nathanw #endif
    275  1.1.2.2  nathanw 		/*
    276  1.1.2.2  nathanw 		 * Local interrupts need to be bounced through some
    277  1.1.2.2  nathanw 		 * trampoline code which acknowledges/clears them.
    278  1.1.2.2  nathanw 		 */
    279  1.1.2.2  nathanw 		vme_two_handlers[vec - VME2_VECTOR_LOCAL_MIN].isr_hand = hand;
    280  1.1.2.2  nathanw 		vme_two_handlers[vec - VME2_VECTOR_LOCAL_MIN].isr_arg = arg;
    281  1.1.2.2  nathanw 		hand = vmetwo_local_isr_trampoline;
    282  1.1.2.2  nathanw 		arg = (void *) (vec - VME2_VECTOR_BASE);
    283  1.1.2.2  nathanw 
    284  1.1.2.2  nathanw 		/*
    285  1.1.2.2  nathanw 		 * Interrupt enable/clear bit offset is 0x08 - 0x1f
    286  1.1.2.2  nathanw 		 */
    287  1.1.2.2  nathanw 		bitoff = vec - VME2_VECTOR_BASE;
    288  1.1.2.2  nathanw #if NVMETWO > 0
    289  1.1.2.2  nathanw 		first = 1;	/* Force the interrupt to be enabled */
    290  1.1.2.2  nathanw 	} else {
    291  1.1.2.2  nathanw 		/*
    292  1.1.2.2  nathanw 		 * Interrupts originating from the VMEbus are
    293  1.1.2.2  nathanw 		 * controlled by an offset of 0x00 - 0x07
    294  1.1.2.2  nathanw 		 */
    295  1.1.2.2  nathanw 		bitoff = lvl - 1;
    296  1.1.2.2  nathanw 	}
    297  1.1.2.2  nathanw #endif
    298  1.1.2.2  nathanw 
    299  1.1.2.2  nathanw 	/* Hook the interrupt */
    300  1.1.2.2  nathanw 	(*sc->sc_isrlink)(sc->sc_isrcookie, hand, arg, prior, vec, evcnt);
    301  1.1.2.2  nathanw 
    302  1.1.2.2  nathanw 	/*
    303  1.1.2.2  nathanw 	 * Do we need to tell the VMEChip2 to let the interrupt through?
    304  1.1.2.2  nathanw 	 * (This is always true for locally-generated interrupts, but only
    305  1.1.2.2  nathanw 	 * needs doing once for each VMEbus interrupt level which is hooked)
    306  1.1.2.2  nathanw 	 */
    307  1.1.2.2  nathanw #if NVMETWO > 0
    308  1.1.2.2  nathanw 	if (first) {
    309  1.1.2.2  nathanw 		if (evcnt)
    310  1.1.2.2  nathanw 			evcnt_attach_dynamic(evcnt, EVCNT_TYPE_INTR,
    311  1.1.2.2  nathanw 			    (*sc->sc_isrevcnt)(sc->sc_isrcookie, prior),
    312  1.1.2.2  nathanw 			    sc->sc_mvmebus.sc_dev.dv_xname,
    313  1.1.2.2  nathanw 			    mvmebus_irq_name[lvl]);
    314  1.1.2.2  nathanw #endif
    315  1.1.2.2  nathanw 		iloffset = VME2_ILOFFSET_FROM_VECTOR(bitoff) +
    316  1.1.2.2  nathanw 		    VME2LCSR_INTERRUPT_LEVEL_BASE;
    317  1.1.2.2  nathanw 		ilshift = VME2_ILSHIFT_FROM_VECTOR(bitoff);
    318  1.1.2.2  nathanw 
    319  1.1.2.2  nathanw 		/* Program the specified interrupt to signal at 'prior' */
    320  1.1.2.2  nathanw 		reg = vme2_lcsr_read(sc, iloffset);
    321  1.1.2.2  nathanw 		reg &= ~(VME2_INTERRUPT_LEVEL_MASK << ilshift);
    322  1.1.2.2  nathanw 		reg |= (prior << ilshift);
    323  1.1.2.2  nathanw 		vme2_lcsr_write(sc, iloffset, reg);
    324  1.1.2.2  nathanw 
    325  1.1.2.2  nathanw 		/* Clear it */
    326  1.1.2.2  nathanw 		vme2_lcsr_write(sc, VME2LCSR_LOCAL_INTERRUPT_CLEAR,
    327  1.1.2.2  nathanw 		    VME2_LOCAL_INTERRUPT(bitoff));
    328  1.1.2.2  nathanw 
    329  1.1.2.2  nathanw 		/* Enable it. */
    330  1.1.2.2  nathanw 		reg = vme2_lcsr_read(sc, VME2LCSR_LOCAL_INTERRUPT_ENABLE);
    331  1.1.2.2  nathanw 		reg |= VME2_LOCAL_INTERRUPT(bitoff);
    332  1.1.2.2  nathanw 		vme2_lcsr_write(sc, VME2LCSR_LOCAL_INTERRUPT_ENABLE, reg);
    333  1.1.2.2  nathanw #if NVMETWO > 0
    334  1.1.2.2  nathanw 	}
    335  1.1.2.2  nathanw #ifdef DIAGNOSTIC
    336  1.1.2.2  nathanw 	else {
    337  1.1.2.2  nathanw 		/* Verify the interrupt priority is the same */
    338  1.1.2.2  nathanw 		iloffset = VME2_ILOFFSET_FROM_VECTOR(bitoff) +
    339  1.1.2.2  nathanw 		    VME2LCSR_INTERRUPT_LEVEL_BASE;
    340  1.1.2.2  nathanw 		ilshift = VME2_ILSHIFT_FROM_VECTOR(bitoff);
    341  1.1.2.2  nathanw 
    342  1.1.2.2  nathanw 		reg = vme2_lcsr_read(sc, iloffset);
    343  1.1.2.2  nathanw 		reg &= (VME2_INTERRUPT_LEVEL_MASK << ilshift);
    344  1.1.2.2  nathanw 
    345  1.1.2.2  nathanw 		if ((prior << ilshift) != reg)
    346  1.1.2.2  nathanw 			panic("vmetwo_intr_establish: priority mismatch!");
    347  1.1.2.2  nathanw 	}
    348  1.1.2.2  nathanw #endif
    349  1.1.2.2  nathanw #endif
    350  1.1.2.2  nathanw 	splx(s);
    351  1.1.2.2  nathanw }
    352  1.1.2.2  nathanw 
    353  1.1.2.2  nathanw void
    354  1.1.2.2  nathanw vmetwo_intr_disestablish(csc, lvl, vec, last, evcnt)
    355  1.1.2.2  nathanw 	void *csc;
    356  1.1.2.2  nathanw 	int lvl, vec, last;
    357  1.1.2.2  nathanw 	struct evcnt *evcnt;
    358  1.1.2.2  nathanw {
    359  1.1.2.2  nathanw 	struct vmetwo_softc *sc = csc;
    360  1.1.2.2  nathanw 	u_int32_t reg;
    361  1.1.2.2  nathanw 	int iloffset, ilshift;
    362  1.1.2.2  nathanw 	int bitoff;
    363  1.1.2.2  nathanw 	int s;
    364  1.1.2.2  nathanw 
    365  1.1.2.2  nathanw 	s = splhigh();
    366  1.1.2.2  nathanw 
    367  1.1.2.2  nathanw #if NVMETWO > 0
    368  1.1.2.2  nathanw 	/*
    369  1.1.2.2  nathanw 	 * Sort out interrupts generated locally by the VMEChip2 from
    370  1.1.2.2  nathanw 	 * those generated by VMEbus devices...
    371  1.1.2.2  nathanw 	 */
    372  1.1.2.2  nathanw 	if (vec >= VME2_VECTOR_LOCAL_MIN && vec <= VME2_VECTOR_LOCAL_MAX) {
    373  1.1.2.2  nathanw #endif
    374  1.1.2.2  nathanw 		/*
    375  1.1.2.2  nathanw 		 * Interrupt enable/clear bit offset is 0x08 - 0x1f
    376  1.1.2.2  nathanw 		 */
    377  1.1.2.2  nathanw 		bitoff = vec - VME2_VECTOR_BASE;
    378  1.1.2.2  nathanw 		vme_two_handlers[vec - VME2_VECTOR_LOCAL_MIN].isr_hand = NULL;
    379  1.1.2.2  nathanw 		last = 1; /* Force the interrupt to be cleared */
    380  1.1.2.2  nathanw #if NVMETWO > 0
    381  1.1.2.2  nathanw 	} else {
    382  1.1.2.2  nathanw 		/*
    383  1.1.2.2  nathanw 		 * Interrupts originating from the VMEbus are
    384  1.1.2.2  nathanw 		 * controlled by an offset of 0x00 - 0x07
    385  1.1.2.2  nathanw 		 */
    386  1.1.2.2  nathanw 		bitoff = lvl - 1;
    387  1.1.2.2  nathanw 	}
    388  1.1.2.2  nathanw #endif
    389  1.1.2.2  nathanw 
    390  1.1.2.2  nathanw 	/*
    391  1.1.2.2  nathanw 	 * Do we need to tell the VMEChip2 to block the interrupt?
    392  1.1.2.2  nathanw 	 * (This is always true for locally-generated interrupts, but only
    393  1.1.2.2  nathanw 	 * needs doing once when the last VMEbus handler for any given level
    394  1.1.2.2  nathanw 	 * has been unhooked.)
    395  1.1.2.2  nathanw 	 */
    396  1.1.2.2  nathanw 	if (last) {
    397  1.1.2.2  nathanw 		iloffset = VME2_ILOFFSET_FROM_VECTOR(bitoff) +
    398  1.1.2.2  nathanw 		    VME2LCSR_INTERRUPT_LEVEL_BASE;
    399  1.1.2.2  nathanw 		ilshift = VME2_ILSHIFT_FROM_VECTOR(bitoff);
    400  1.1.2.2  nathanw 
    401  1.1.2.2  nathanw 		/* Disable it. */
    402  1.1.2.2  nathanw 		reg = vme2_lcsr_read(sc, VME2LCSR_LOCAL_INTERRUPT_ENABLE);
    403  1.1.2.2  nathanw 		reg &= ~VME2_LOCAL_INTERRUPT(bitoff);
    404  1.1.2.2  nathanw 		vme2_lcsr_write(sc, VME2LCSR_LOCAL_INTERRUPT_ENABLE, reg);
    405  1.1.2.2  nathanw 
    406  1.1.2.2  nathanw 		/* Set the interrupt's level to zero */
    407  1.1.2.2  nathanw 		reg = vme2_lcsr_read(sc, iloffset);
    408  1.1.2.2  nathanw 		reg &= ~(VME2_INTERRUPT_LEVEL_MASK << ilshift);
    409  1.1.2.2  nathanw 		vme2_lcsr_write(sc, iloffset, reg);
    410  1.1.2.2  nathanw 
    411  1.1.2.2  nathanw 		/* Clear it */
    412  1.1.2.2  nathanw 		vme2_lcsr_write(sc, VME2LCSR_LOCAL_INTERRUPT_CLEAR,
    413  1.1.2.2  nathanw 		    VME2_LOCAL_INTERRUPT(vec));
    414  1.1.2.2  nathanw 
    415  1.1.2.2  nathanw 		if (evcnt)
    416  1.1.2.2  nathanw 			evcnt_detach(evcnt);
    417  1.1.2.2  nathanw 	}
    418  1.1.2.2  nathanw 	/* Un-hook it */
    419  1.1.2.2  nathanw 	(*sc->sc_isrunlink)(sc->sc_isrcookie, vec);
    420  1.1.2.2  nathanw 
    421  1.1.2.2  nathanw 	splx(s);
    422  1.1.2.2  nathanw }
    423  1.1.2.2  nathanw 
    424  1.1.2.2  nathanw static void
    425  1.1.2.2  nathanw vmetwo_softintr_assert(void)
    426  1.1.2.2  nathanw {
    427  1.1.2.2  nathanw 
    428  1.1.2.2  nathanw 	vme2_lcsr_write(vmetwo_sc, VME2LCSR_SOFTINT_SET, VME2_SOFTINT_SET(0));
    429  1.1.2.2  nathanw }
    430