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vme_two_isr.c revision 1.14
      1  1.14     dsl /*	$NetBSD: vme_two_isr.c,v 1.14 2009/03/14 21:04:21 dsl Exp $	*/
      2   1.1     scw 
      3   1.1     scw /*-
      4   1.1     scw  * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc.
      5   1.1     scw  * All rights reserved.
      6   1.1     scw  *
      7   1.1     scw  * This code is derived from software contributed to The NetBSD Foundation
      8   1.1     scw  * by Steve C. Woodford.
      9   1.1     scw  *
     10   1.1     scw  * Redistribution and use in source and binary forms, with or without
     11   1.1     scw  * modification, are permitted provided that the following conditions
     12   1.1     scw  * are met:
     13   1.1     scw  * 1. Redistributions of source code must retain the above copyright
     14   1.1     scw  *    notice, this list of conditions and the following disclaimer.
     15   1.1     scw  * 2. Redistributions in binary form must reproduce the above copyright
     16   1.1     scw  *    notice, this list of conditions and the following disclaimer in the
     17   1.1     scw  *    documentation and/or other materials provided with the distribution.
     18   1.1     scw  *
     19   1.1     scw  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     20   1.1     scw  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     21   1.1     scw  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     22   1.1     scw  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     23   1.1     scw  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     24   1.1     scw  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     25   1.1     scw  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     26   1.1     scw  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     27   1.1     scw  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     28   1.1     scw  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     29   1.1     scw  * POSSIBILITY OF SUCH DAMAGE.
     30   1.1     scw  */
     31   1.1     scw 
     32   1.1     scw /*
     33   1.1     scw  * Split off from vme_two.c specifically to deal with hardware assisted
     34   1.1     scw  * soft interrupts when the user hasn't specified `vmetwo0' in the
     35   1.1     scw  * kernel config file (mvme1[67]2 only).
     36   1.1     scw  */
     37   1.4   lukem 
     38   1.4   lukem #include <sys/cdefs.h>
     39  1.14     dsl __KERNEL_RCSID(0, "$NetBSD: vme_two_isr.c,v 1.14 2009/03/14 21:04:21 dsl Exp $");
     40   1.1     scw 
     41   1.1     scw #include "vmetwo.h"
     42   1.1     scw 
     43   1.1     scw #include <sys/param.h>
     44   1.1     scw #include <sys/kernel.h>
     45   1.1     scw #include <sys/systm.h>
     46   1.1     scw #include <sys/device.h>
     47   1.1     scw #include <sys/malloc.h>
     48   1.7      ad #include <sys/cpu.h>
     49   1.7      ad #include <sys/bus.h>
     50   1.1     scw 
     51   1.1     scw #include <dev/vme/vmereg.h>
     52   1.1     scw #include <dev/vme/vmevar.h>
     53   1.1     scw 
     54   1.1     scw #include <dev/mvme/mvmebus.h>
     55   1.1     scw #include <dev/mvme/vme_tworeg.h>
     56   1.1     scw #include <dev/mvme/vme_twovar.h>
     57   1.1     scw 
     58   1.1     scw /*
     59   1.1     scw  * Non-zero if there is no VMEChip2 on this board.
     60   1.1     scw  */
     61   1.1     scw int vmetwo_not_present;
     62   1.1     scw 
     63   1.1     scw /*
     64   1.1     scw  * Array of interrupt handlers registered with us for the non-VMEbus
     65   1.1     scw  * vectored interrupts. Eg. ABORT Switch, SYSFAIL etc.
     66   1.1     scw  *
     67   1.1     scw  * We can't just install a caller's handler directly, since these
     68   1.1     scw  * interrupts have to be manually cleared, so we have a trampoline
     69   1.1     scw  * which does the clearing automatically.
     70   1.1     scw  */
     71   1.1     scw static struct vme_two_handler {
     72   1.5   perry 	int (*isr_hand)(void *);
     73   1.1     scw 	void *isr_arg;
     74   1.1     scw } vme_two_handlers[(VME2_VECTOR_LOCAL_MAX - VME2_VECTOR_LOCAL_MIN) + 1];
     75   1.1     scw 
     76   1.1     scw #define VMETWO_HANDLERS_SZ	(sizeof(vme_two_handlers) /	\
     77   1.1     scw 				 sizeof(struct vme_two_handler))
     78   1.1     scw 
     79   1.1     scw static	int  vmetwo_local_isr_trampoline(void *);
     80   1.8      ad #ifdef notyet
     81   1.1     scw static	void vmetwo_softintr_assert(void);
     82   1.8      ad #endif
     83   1.1     scw 
     84   1.1     scw static	struct vmetwo_softc *vmetwo_sc;
     85   1.1     scw 
     86   1.1     scw int
     87   1.1     scw vmetwo_probe(bus_space_tag_t bt, bus_addr_t offset)
     88   1.1     scw {
     89   1.1     scw 	bus_space_handle_t bh;
     90   1.1     scw 
     91   1.1     scw 	bus_space_map(bt, offset + VME2REG_LCSR_OFFSET, VME2LCSR_SIZE, 0, &bh);
     92   1.1     scw 
     93   1.1     scw 	if (bus_space_peek_4(bt, bh, VME2LCSR_MISC_STATUS, NULL) != 0) {
     94   1.1     scw #if defined(MVME162) || defined(MVME172)
     95   1.1     scw #if defined(MVME167) || defined(MVME177)
     96   1.1     scw 		if (machineid == MVME_162 || machineid == MVME_172)
     97   1.1     scw #endif
     98   1.1     scw 		{
     99   1.1     scw 			/*
    100   1.1     scw 			 * No VMEChip2 on mvme162/172 is not too big a
    101   1.1     scw 			 * deal; we can fall back on timer4 in the
    102   1.1     scw 			 * mcchip for h/w assisted soft interrupts...
    103   1.1     scw 			 */
    104   1.1     scw 			extern void pcctwosoftintrinit(void);
    105   1.1     scw 			bus_space_unmap(bt, bh, VME2LCSR_SIZE);
    106   1.1     scw 			vmetwo_not_present = 1;
    107   1.1     scw 			pcctwosoftintrinit();
    108   1.1     scw 			return (0);
    109   1.1     scw 		}
    110   1.1     scw #endif
    111   1.1     scw #if defined(MVME167) || defined(MVME177) || defined(MVME88K)
    112   1.1     scw 		/*
    113   1.1     scw 		 * No VMEChip2 on mvme167/177, however, is a Big Deal.
    114   1.1     scw 		 * In fact, it means the hardware's shot since the
    115   1.1     scw 		 * VMEChip2 is not a `build-option' on those boards.
    116   1.1     scw 		 */
    117   1.1     scw 		panic("VMEChip2 not responding! Faulty board?");
    118   1.1     scw 		/* NOTREACHED */
    119   1.1     scw #endif
    120   1.1     scw #if defined(MVMEPPC)
    121   1.1     scw 		/*
    122   1.1     scw 		 * No VMEChip2 on mvmeppc is no big deal.
    123   1.1     scw 		 */
    124   1.1     scw 		bus_space_unmap(bt, bh, VME2LCSR_SIZE);
    125   1.1     scw 		vmetwo_not_present = 1;
    126   1.1     scw 		return (0);
    127   1.1     scw #endif
    128   1.1     scw 	}
    129   1.1     scw #if NVMETWO == 0
    130   1.1     scw 	else {
    131   1.1     scw 		/*
    132   1.1     scw 		 * The kernel config file has no `vmetwo0' device, but
    133   1.1     scw 		 * there is a VMEChip2 on the board. Fix up things
    134   1.1     scw 		 * just enough to hook VMEChip2 local interrupts.
    135   1.1     scw 		 */
    136   1.1     scw 		struct vmetwo_softc *sc;
    137   1.1     scw 
    138   1.1     scw 		/* XXX Should check sc != NULL here... */
    139  1.12      he 		sc = malloc(sizeof(*sc), M_DEVBUF, M_NOWAIT);
    140   1.1     scw 
    141   1.1     scw 		sc->sc_mvmebus.sc_bust = bt;
    142   1.1     scw 		sc->sc_lcrh = bh;
    143   1.1     scw 		vmetwo_intr_init(sc);
    144   1.1     scw 		return 0;
    145   1.1     scw 	}
    146   1.1     scw #else
    147   1.1     scw 	bus_space_unmap(bt, bh, VME2LCSR_SIZE);
    148   1.1     scw 	return (1);
    149   1.1     scw #endif
    150   1.1     scw }
    151   1.1     scw 
    152   1.1     scw void
    153   1.1     scw vmetwo_intr_init(struct vmetwo_softc *sc)
    154   1.1     scw {
    155   1.1     scw 	u_int32_t reg;
    156   1.1     scw 	int i;
    157   1.1     scw 
    158   1.1     scw 	vmetwo_sc = sc;
    159   1.1     scw 
    160   1.1     scw 	/* Clear out the ISR handler array */
    161   1.1     scw 	for (i = 0; i < VMETWO_HANDLERS_SZ; i++)
    162   1.1     scw 		vme_two_handlers[i].isr_hand = NULL;
    163   1.1     scw 
    164   1.1     scw 	/*
    165   1.1     scw 	 * Initialize the chip.
    166   1.1     scw 	 * Firstly, disable all VMEChip2 Interrupts
    167   1.1     scw 	 */
    168   1.1     scw 	reg = vme2_lcsr_read(sc, VME2LCSR_MISC_STATUS) & ~VME2_MISC_STATUS_MIEN;
    169   1.1     scw 	vme2_lcsr_write(sc, VME2LCSR_MISC_STATUS, reg);
    170   1.1     scw 	vme2_lcsr_write(sc, VME2LCSR_LOCAL_INTERRUPT_ENABLE, 0);
    171   1.1     scw 	vme2_lcsr_write(sc, VME2LCSR_LOCAL_INTERRUPT_CLEAR,
    172   1.1     scw 	    VME2_LOCAL_INTERRUPT_CLEAR_ALL);
    173   1.1     scw 
    174   1.1     scw 	/* Zap all the IRQ level registers */
    175   1.1     scw 	for (i = 0; i < VME2_NUM_IL_REGS; i++)
    176   1.1     scw 		vme2_lcsr_write(sc, VME2LCSR_INTERRUPT_LEVEL_BASE + (i * 4), 0);
    177   1.1     scw 
    178   1.1     scw 	/* Disable the tick timers */
    179   1.1     scw 	reg = vme2_lcsr_read(sc, VME2LCSR_TIMER_CONTROL);
    180   1.1     scw 	reg &= ~VME2_TIMER_CONTROL_EN(0);
    181   1.1     scw 	reg &= ~VME2_TIMER_CONTROL_EN(1);
    182   1.1     scw 	vme2_lcsr_write(sc, VME2LCSR_TIMER_CONTROL, reg);
    183   1.1     scw 
    184   1.1     scw 	/* Set the VMEChip2's vector base register to the required value */
    185   1.1     scw 	reg = vme2_lcsr_read(sc, VME2LCSR_VECTOR_BASE);
    186   1.1     scw 	reg &= ~VME2_VECTOR_BASE_MASK;
    187   1.1     scw 	reg |= VME2_VECTOR_BASE_REG_VALUE;
    188   1.1     scw 	vme2_lcsr_write(sc, VME2LCSR_VECTOR_BASE, reg);
    189   1.1     scw 
    190   1.1     scw 	/* Set the Master Interrupt Enable bit now */
    191   1.1     scw 	reg = vme2_lcsr_read(sc, VME2LCSR_MISC_STATUS) | VME2_MISC_STATUS_MIEN;
    192   1.1     scw 	vme2_lcsr_write(sc, VME2LCSR_MISC_STATUS, reg);
    193   1.2     scw 
    194   1.2     scw 	/* Allow the MD code the chance to do some initialising */
    195   1.2     scw 	vmetwo_md_intr_init(sc);
    196   1.1     scw 
    197   1.1     scw #if defined(MVME167) || defined(MVME177)
    198   1.1     scw #if defined(MVME162) || defined(MVME172)
    199   1.1     scw 	if (machineid != MVME_162 && machineid != MVME_172)
    200   1.1     scw #endif
    201   1.1     scw 	{
    202   1.1     scw 		/*
    203   1.1     scw 		 * Let the NMI handler deal with level 7 ABORT switch
    204   1.1     scw 		 * interrupts
    205   1.1     scw 		 */
    206   1.1     scw 		vmetwo_intr_establish(sc, 7, 7, VME2_VEC_ABORT, 1,
    207   1.1     scw 		    nmihand, NULL, NULL);
    208   1.1     scw 	}
    209   1.1     scw #endif
    210   1.1     scw 
    211   1.1     scw 	/* Setup hardware assisted soft interrupts */
    212   1.8      ad #ifdef notyet
    213   1.1     scw 	vmetwo_intr_establish(sc, 1, 1, VME2_VEC_SOFT0, 1,
    214   1.1     scw 	    (int (*)(void *))softintr_dispatch, NULL, NULL);
    215   1.1     scw 	_softintr_chipset_assert = vmetwo_softintr_assert;
    216   1.8      ad #endif
    217   1.1     scw }
    218   1.1     scw 
    219   1.1     scw static int
    220  1.13     dsl vmetwo_local_isr_trampoline(void *arg)
    221   1.1     scw {
    222   1.1     scw 	struct vme_two_handler *isr;
    223   1.1     scw 	int vec;
    224   1.1     scw 
    225   1.1     scw 	vec = (int) arg;	/* 0x08 <= vec <= 0x1f */
    226   1.1     scw 
    227   1.1     scw 	/* Clear the interrupt source */
    228   1.1     scw 	vme2_lcsr_write(vmetwo_sc, VME2LCSR_LOCAL_INTERRUPT_CLEAR,
    229   1.1     scw 	    VME2_LOCAL_INTERRUPT(vec));
    230   1.1     scw 
    231   1.1     scw 	isr = &vme_two_handlers[vec - VME2_VECTOR_LOCAL_OFFSET];
    232   1.1     scw 	if (isr->isr_hand)
    233   1.1     scw 		(void) (*isr->isr_hand) (isr->isr_arg);
    234   1.1     scw 	else
    235   1.1     scw 		printf("vmetwo: Spurious local interrupt, vector 0x%x\n", vec);
    236   1.1     scw 
    237   1.1     scw 	return (1);
    238   1.1     scw }
    239   1.1     scw 
    240   1.1     scw void
    241   1.1     scw vmetwo_local_intr_establish(pri, vec, hand, arg, evcnt)
    242   1.1     scw 	int pri, vec;
    243   1.1     scw 	int (*hand)(void *);
    244   1.1     scw 	void *arg;
    245   1.1     scw 	struct evcnt *evcnt;
    246   1.1     scw {
    247   1.1     scw 
    248   1.1     scw 	vmetwo_intr_establish(vmetwo_sc, pri, pri, vec, 1, hand, arg, evcnt);
    249   1.1     scw }
    250   1.1     scw 
    251   1.1     scw /* ARGSUSED */
    252   1.1     scw void
    253   1.1     scw vmetwo_intr_establish(csc, prior, lvl, vec, first, hand, arg, evcnt)
    254   1.1     scw 	void *csc;
    255   1.1     scw 	int prior, lvl, vec, first;
    256   1.1     scw 	int (*hand)(void *);
    257   1.1     scw 	void *arg;
    258   1.1     scw 	struct evcnt *evcnt;
    259   1.1     scw {
    260   1.1     scw 	struct vmetwo_softc *sc = csc;
    261   1.1     scw 	u_int32_t reg;
    262   1.1     scw 	int bitoff;
    263   1.1     scw 	int iloffset, ilshift;
    264   1.1     scw 	int s;
    265   1.1     scw 
    266   1.1     scw 	s = splhigh();
    267   1.1     scw 
    268   1.1     scw #if NVMETWO > 0
    269   1.1     scw 	/*
    270   1.1     scw 	 * Sort out interrupts generated locally by the VMEChip2 from
    271   1.1     scw 	 * those generated by VMEbus devices...
    272   1.1     scw 	 */
    273   1.1     scw 	if (vec >= VME2_VECTOR_LOCAL_MIN && vec <= VME2_VECTOR_LOCAL_MAX) {
    274   1.1     scw #endif
    275   1.1     scw 		/*
    276   1.1     scw 		 * Local interrupts need to be bounced through some
    277   1.1     scw 		 * trampoline code which acknowledges/clears them.
    278   1.1     scw 		 */
    279   1.1     scw 		vme_two_handlers[vec - VME2_VECTOR_LOCAL_MIN].isr_hand = hand;
    280   1.1     scw 		vme_two_handlers[vec - VME2_VECTOR_LOCAL_MIN].isr_arg = arg;
    281   1.1     scw 		hand = vmetwo_local_isr_trampoline;
    282   1.1     scw 		arg = (void *) (vec - VME2_VECTOR_BASE);
    283   1.1     scw 
    284   1.1     scw 		/*
    285   1.1     scw 		 * Interrupt enable/clear bit offset is 0x08 - 0x1f
    286   1.1     scw 		 */
    287   1.1     scw 		bitoff = vec - VME2_VECTOR_BASE;
    288   1.1     scw #if NVMETWO > 0
    289   1.1     scw 		first = 1;	/* Force the interrupt to be enabled */
    290   1.1     scw 	} else {
    291   1.1     scw 		/*
    292   1.1     scw 		 * Interrupts originating from the VMEbus are
    293   1.1     scw 		 * controlled by an offset of 0x00 - 0x07
    294   1.1     scw 		 */
    295   1.1     scw 		bitoff = lvl - 1;
    296   1.1     scw 	}
    297   1.1     scw #endif
    298   1.1     scw 
    299   1.1     scw 	/* Hook the interrupt */
    300   1.1     scw 	(*sc->sc_isrlink)(sc->sc_isrcookie, hand, arg, prior, vec, evcnt);
    301   1.1     scw 
    302   1.1     scw 	/*
    303   1.1     scw 	 * Do we need to tell the VMEChip2 to let the interrupt through?
    304   1.1     scw 	 * (This is always true for locally-generated interrupts, but only
    305   1.1     scw 	 * needs doing once for each VMEbus interrupt level which is hooked)
    306   1.1     scw 	 */
    307   1.1     scw #if NVMETWO > 0
    308   1.1     scw 	if (first) {
    309   1.1     scw 		if (evcnt)
    310   1.1     scw 			evcnt_attach_dynamic(evcnt, EVCNT_TYPE_INTR,
    311   1.1     scw 			    (*sc->sc_isrevcnt)(sc->sc_isrcookie, prior),
    312  1.10  cegger 			    device_xname(&sc->sc_mvmebus.sc_dev),
    313   1.1     scw 			    mvmebus_irq_name[lvl]);
    314   1.1     scw #endif
    315   1.1     scw 		iloffset = VME2_ILOFFSET_FROM_VECTOR(bitoff) +
    316   1.1     scw 		    VME2LCSR_INTERRUPT_LEVEL_BASE;
    317   1.1     scw 		ilshift = VME2_ILSHIFT_FROM_VECTOR(bitoff);
    318   1.1     scw 
    319   1.1     scw 		/* Program the specified interrupt to signal at 'prior' */
    320   1.1     scw 		reg = vme2_lcsr_read(sc, iloffset);
    321   1.1     scw 		reg &= ~(VME2_INTERRUPT_LEVEL_MASK << ilshift);
    322   1.1     scw 		reg |= (prior << ilshift);
    323   1.1     scw 		vme2_lcsr_write(sc, iloffset, reg);
    324   1.1     scw 
    325   1.1     scw 		/* Clear it */
    326   1.1     scw 		vme2_lcsr_write(sc, VME2LCSR_LOCAL_INTERRUPT_CLEAR,
    327   1.1     scw 		    VME2_LOCAL_INTERRUPT(bitoff));
    328   1.1     scw 
    329   1.1     scw 		/* Enable it. */
    330   1.1     scw 		reg = vme2_lcsr_read(sc, VME2LCSR_LOCAL_INTERRUPT_ENABLE);
    331   1.1     scw 		reg |= VME2_LOCAL_INTERRUPT(bitoff);
    332   1.1     scw 		vme2_lcsr_write(sc, VME2LCSR_LOCAL_INTERRUPT_ENABLE, reg);
    333   1.1     scw #if NVMETWO > 0
    334   1.1     scw 	}
    335   1.1     scw #ifdef DIAGNOSTIC
    336   1.1     scw 	else {
    337   1.1     scw 		/* Verify the interrupt priority is the same */
    338   1.1     scw 		iloffset = VME2_ILOFFSET_FROM_VECTOR(bitoff) +
    339   1.1     scw 		    VME2LCSR_INTERRUPT_LEVEL_BASE;
    340   1.1     scw 		ilshift = VME2_ILSHIFT_FROM_VECTOR(bitoff);
    341   1.1     scw 
    342   1.1     scw 		reg = vme2_lcsr_read(sc, iloffset);
    343   1.1     scw 		reg &= (VME2_INTERRUPT_LEVEL_MASK << ilshift);
    344   1.1     scw 
    345   1.1     scw 		if ((prior << ilshift) != reg)
    346   1.1     scw 			panic("vmetwo_intr_establish: priority mismatch!");
    347   1.1     scw 	}
    348   1.1     scw #endif
    349   1.1     scw #endif
    350   1.1     scw 	splx(s);
    351   1.1     scw }
    352   1.1     scw 
    353   1.1     scw void
    354  1.14     dsl vmetwo_intr_disestablish(void *csc, int lvl, int vec, int last, struct evcnt *evcnt)
    355   1.1     scw {
    356   1.1     scw 	struct vmetwo_softc *sc = csc;
    357   1.1     scw 	u_int32_t reg;
    358   1.1     scw 	int iloffset, ilshift;
    359   1.1     scw 	int bitoff;
    360   1.1     scw 	int s;
    361   1.1     scw 
    362   1.1     scw 	s = splhigh();
    363   1.1     scw 
    364   1.1     scw #if NVMETWO > 0
    365   1.1     scw 	/*
    366   1.1     scw 	 * Sort out interrupts generated locally by the VMEChip2 from
    367   1.1     scw 	 * those generated by VMEbus devices...
    368   1.1     scw 	 */
    369   1.1     scw 	if (vec >= VME2_VECTOR_LOCAL_MIN && vec <= VME2_VECTOR_LOCAL_MAX) {
    370   1.1     scw #endif
    371   1.1     scw 		/*
    372   1.1     scw 		 * Interrupt enable/clear bit offset is 0x08 - 0x1f
    373   1.1     scw 		 */
    374   1.1     scw 		bitoff = vec - VME2_VECTOR_BASE;
    375   1.1     scw 		vme_two_handlers[vec - VME2_VECTOR_LOCAL_MIN].isr_hand = NULL;
    376   1.1     scw 		last = 1; /* Force the interrupt to be cleared */
    377   1.1     scw #if NVMETWO > 0
    378   1.1     scw 	} else {
    379   1.1     scw 		/*
    380   1.1     scw 		 * Interrupts originating from the VMEbus are
    381   1.1     scw 		 * controlled by an offset of 0x00 - 0x07
    382   1.1     scw 		 */
    383   1.1     scw 		bitoff = lvl - 1;
    384   1.1     scw 	}
    385   1.1     scw #endif
    386   1.1     scw 
    387   1.1     scw 	/*
    388   1.1     scw 	 * Do we need to tell the VMEChip2 to block the interrupt?
    389   1.1     scw 	 * (This is always true for locally-generated interrupts, but only
    390   1.1     scw 	 * needs doing once when the last VMEbus handler for any given level
    391   1.1     scw 	 * has been unhooked.)
    392   1.1     scw 	 */
    393   1.1     scw 	if (last) {
    394   1.1     scw 		iloffset = VME2_ILOFFSET_FROM_VECTOR(bitoff) +
    395   1.1     scw 		    VME2LCSR_INTERRUPT_LEVEL_BASE;
    396   1.1     scw 		ilshift = VME2_ILSHIFT_FROM_VECTOR(bitoff);
    397   1.1     scw 
    398   1.1     scw 		/* Disable it. */
    399   1.1     scw 		reg = vme2_lcsr_read(sc, VME2LCSR_LOCAL_INTERRUPT_ENABLE);
    400   1.1     scw 		reg &= ~VME2_LOCAL_INTERRUPT(bitoff);
    401   1.1     scw 		vme2_lcsr_write(sc, VME2LCSR_LOCAL_INTERRUPT_ENABLE, reg);
    402   1.1     scw 
    403   1.1     scw 		/* Set the interrupt's level to zero */
    404   1.1     scw 		reg = vme2_lcsr_read(sc, iloffset);
    405   1.1     scw 		reg &= ~(VME2_INTERRUPT_LEVEL_MASK << ilshift);
    406   1.1     scw 		vme2_lcsr_write(sc, iloffset, reg);
    407   1.1     scw 
    408   1.1     scw 		/* Clear it */
    409   1.1     scw 		vme2_lcsr_write(sc, VME2LCSR_LOCAL_INTERRUPT_CLEAR,
    410   1.1     scw 		    VME2_LOCAL_INTERRUPT(vec));
    411   1.1     scw 
    412   1.1     scw 		if (evcnt)
    413   1.1     scw 			evcnt_detach(evcnt);
    414   1.1     scw 	}
    415   1.1     scw 	/* Un-hook it */
    416   1.1     scw 	(*sc->sc_isrunlink)(sc->sc_isrcookie, vec);
    417   1.1     scw 
    418   1.1     scw 	splx(s);
    419   1.1     scw }
    420   1.1     scw 
    421   1.8      ad #ifdef notyet
    422   1.1     scw static void
    423   1.1     scw vmetwo_softintr_assert(void)
    424   1.1     scw {
    425   1.1     scw 
    426   1.1     scw 	vme2_lcsr_write(vmetwo_sc, VME2LCSR_SOFTINT_SET, VME2_SOFTINT_SET(0));
    427   1.1     scw }
    428   1.8      ad #endif
    429