vme_two_isr.c revision 1.8 1 1.8 ad /* $NetBSD: vme_two_isr.c,v 1.8 2007/12/03 15:34:32 ad Exp $ */
2 1.1 scw
3 1.1 scw /*-
4 1.1 scw * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc.
5 1.1 scw * All rights reserved.
6 1.1 scw *
7 1.1 scw * This code is derived from software contributed to The NetBSD Foundation
8 1.1 scw * by Steve C. Woodford.
9 1.1 scw *
10 1.1 scw * Redistribution and use in source and binary forms, with or without
11 1.1 scw * modification, are permitted provided that the following conditions
12 1.1 scw * are met:
13 1.1 scw * 1. Redistributions of source code must retain the above copyright
14 1.1 scw * notice, this list of conditions and the following disclaimer.
15 1.1 scw * 2. Redistributions in binary form must reproduce the above copyright
16 1.1 scw * notice, this list of conditions and the following disclaimer in the
17 1.1 scw * documentation and/or other materials provided with the distribution.
18 1.1 scw * 3. All advertising materials mentioning features or use of this software
19 1.1 scw * must display the following acknowledgement:
20 1.1 scw * This product includes software developed by the NetBSD
21 1.1 scw * Foundation, Inc. and its contributors.
22 1.1 scw * 4. Neither the name of The NetBSD Foundation nor the names of its
23 1.1 scw * contributors may be used to endorse or promote products derived
24 1.1 scw * from this software without specific prior written permission.
25 1.1 scw *
26 1.1 scw * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
27 1.1 scw * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28 1.1 scw * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 1.1 scw * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
30 1.1 scw * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31 1.1 scw * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32 1.1 scw * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33 1.1 scw * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34 1.1 scw * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35 1.1 scw * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36 1.1 scw * POSSIBILITY OF SUCH DAMAGE.
37 1.1 scw */
38 1.1 scw
39 1.1 scw /*
40 1.1 scw * Split off from vme_two.c specifically to deal with hardware assisted
41 1.1 scw * soft interrupts when the user hasn't specified `vmetwo0' in the
42 1.1 scw * kernel config file (mvme1[67]2 only).
43 1.1 scw */
44 1.4 lukem
45 1.4 lukem #include <sys/cdefs.h>
46 1.8 ad __KERNEL_RCSID(0, "$NetBSD: vme_two_isr.c,v 1.8 2007/12/03 15:34:32 ad Exp $");
47 1.1 scw
48 1.1 scw #include "vmetwo.h"
49 1.1 scw
50 1.1 scw #include <sys/param.h>
51 1.1 scw #include <sys/kernel.h>
52 1.1 scw #include <sys/systm.h>
53 1.1 scw #include <sys/device.h>
54 1.1 scw #include <sys/malloc.h>
55 1.3 he #include <sys/lock.h>
56 1.1 scw
57 1.7 ad #include <sys/cpu.h>
58 1.7 ad #include <sys/bus.h>
59 1.1 scw
60 1.1 scw #include <dev/vme/vmereg.h>
61 1.1 scw #include <dev/vme/vmevar.h>
62 1.1 scw
63 1.1 scw #include <dev/mvme/mvmebus.h>
64 1.1 scw #include <dev/mvme/vme_tworeg.h>
65 1.1 scw #include <dev/mvme/vme_twovar.h>
66 1.1 scw
67 1.1 scw /*
68 1.1 scw * Non-zero if there is no VMEChip2 on this board.
69 1.1 scw */
70 1.1 scw int vmetwo_not_present;
71 1.1 scw
72 1.1 scw /*
73 1.1 scw * Array of interrupt handlers registered with us for the non-VMEbus
74 1.1 scw * vectored interrupts. Eg. ABORT Switch, SYSFAIL etc.
75 1.1 scw *
76 1.1 scw * We can't just install a caller's handler directly, since these
77 1.1 scw * interrupts have to be manually cleared, so we have a trampoline
78 1.1 scw * which does the clearing automatically.
79 1.1 scw */
80 1.1 scw static struct vme_two_handler {
81 1.5 perry int (*isr_hand)(void *);
82 1.1 scw void *isr_arg;
83 1.1 scw } vme_two_handlers[(VME2_VECTOR_LOCAL_MAX - VME2_VECTOR_LOCAL_MIN) + 1];
84 1.1 scw
85 1.1 scw #define VMETWO_HANDLERS_SZ (sizeof(vme_two_handlers) / \
86 1.1 scw sizeof(struct vme_two_handler))
87 1.1 scw
88 1.1 scw static int vmetwo_local_isr_trampoline(void *);
89 1.8 ad #ifdef notyet
90 1.1 scw static void vmetwo_softintr_assert(void);
91 1.8 ad #endif
92 1.1 scw
93 1.1 scw static struct vmetwo_softc *vmetwo_sc;
94 1.1 scw
95 1.1 scw int
96 1.1 scw vmetwo_probe(bus_space_tag_t bt, bus_addr_t offset)
97 1.1 scw {
98 1.1 scw bus_space_handle_t bh;
99 1.1 scw
100 1.1 scw bus_space_map(bt, offset + VME2REG_LCSR_OFFSET, VME2LCSR_SIZE, 0, &bh);
101 1.1 scw
102 1.1 scw if (bus_space_peek_4(bt, bh, VME2LCSR_MISC_STATUS, NULL) != 0) {
103 1.1 scw #if defined(MVME162) || defined(MVME172)
104 1.1 scw #if defined(MVME167) || defined(MVME177)
105 1.1 scw if (machineid == MVME_162 || machineid == MVME_172)
106 1.1 scw #endif
107 1.1 scw {
108 1.1 scw /*
109 1.1 scw * No VMEChip2 on mvme162/172 is not too big a
110 1.1 scw * deal; we can fall back on timer4 in the
111 1.1 scw * mcchip for h/w assisted soft interrupts...
112 1.1 scw */
113 1.1 scw extern void pcctwosoftintrinit(void);
114 1.1 scw bus_space_unmap(bt, bh, VME2LCSR_SIZE);
115 1.1 scw vmetwo_not_present = 1;
116 1.1 scw pcctwosoftintrinit();
117 1.1 scw return (0);
118 1.1 scw }
119 1.1 scw #endif
120 1.1 scw #if defined(MVME167) || defined(MVME177) || defined(MVME88K)
121 1.1 scw /*
122 1.1 scw * No VMEChip2 on mvme167/177, however, is a Big Deal.
123 1.1 scw * In fact, it means the hardware's shot since the
124 1.1 scw * VMEChip2 is not a `build-option' on those boards.
125 1.1 scw */
126 1.1 scw panic("VMEChip2 not responding! Faulty board?");
127 1.1 scw /* NOTREACHED */
128 1.1 scw #endif
129 1.1 scw #if defined(MVMEPPC)
130 1.1 scw /*
131 1.1 scw * No VMEChip2 on mvmeppc is no big deal.
132 1.1 scw */
133 1.1 scw bus_space_unmap(bt, bh, VME2LCSR_SIZE);
134 1.1 scw vmetwo_not_present = 1;
135 1.1 scw return (0);
136 1.1 scw #endif
137 1.1 scw }
138 1.1 scw #if NVMETWO == 0
139 1.1 scw else {
140 1.1 scw /*
141 1.1 scw * The kernel config file has no `vmetwo0' device, but
142 1.1 scw * there is a VMEChip2 on the board. Fix up things
143 1.1 scw * just enough to hook VMEChip2 local interrupts.
144 1.1 scw */
145 1.1 scw struct vmetwo_softc *sc;
146 1.1 scw
147 1.1 scw /* XXX Should check sc != NULL here... */
148 1.1 scw MALLOC(sc, struct vmetwo_softc *, sizeof(*sc), M_DEVBUF,
149 1.1 scw M_NOWAIT);
150 1.1 scw
151 1.1 scw sc->sc_mvmebus.sc_bust = bt;
152 1.1 scw sc->sc_lcrh = bh;
153 1.1 scw vmetwo_intr_init(sc);
154 1.1 scw return 0;
155 1.1 scw }
156 1.1 scw #else
157 1.1 scw bus_space_unmap(bt, bh, VME2LCSR_SIZE);
158 1.1 scw return (1);
159 1.1 scw #endif
160 1.1 scw }
161 1.1 scw
162 1.1 scw void
163 1.1 scw vmetwo_intr_init(struct vmetwo_softc *sc)
164 1.1 scw {
165 1.1 scw u_int32_t reg;
166 1.1 scw int i;
167 1.1 scw
168 1.1 scw vmetwo_sc = sc;
169 1.1 scw
170 1.1 scw /* Clear out the ISR handler array */
171 1.1 scw for (i = 0; i < VMETWO_HANDLERS_SZ; i++)
172 1.1 scw vme_two_handlers[i].isr_hand = NULL;
173 1.1 scw
174 1.1 scw /*
175 1.1 scw * Initialize the chip.
176 1.1 scw * Firstly, disable all VMEChip2 Interrupts
177 1.1 scw */
178 1.1 scw reg = vme2_lcsr_read(sc, VME2LCSR_MISC_STATUS) & ~VME2_MISC_STATUS_MIEN;
179 1.1 scw vme2_lcsr_write(sc, VME2LCSR_MISC_STATUS, reg);
180 1.1 scw vme2_lcsr_write(sc, VME2LCSR_LOCAL_INTERRUPT_ENABLE, 0);
181 1.1 scw vme2_lcsr_write(sc, VME2LCSR_LOCAL_INTERRUPT_CLEAR,
182 1.1 scw VME2_LOCAL_INTERRUPT_CLEAR_ALL);
183 1.1 scw
184 1.1 scw /* Zap all the IRQ level registers */
185 1.1 scw for (i = 0; i < VME2_NUM_IL_REGS; i++)
186 1.1 scw vme2_lcsr_write(sc, VME2LCSR_INTERRUPT_LEVEL_BASE + (i * 4), 0);
187 1.1 scw
188 1.1 scw /* Disable the tick timers */
189 1.1 scw reg = vme2_lcsr_read(sc, VME2LCSR_TIMER_CONTROL);
190 1.1 scw reg &= ~VME2_TIMER_CONTROL_EN(0);
191 1.1 scw reg &= ~VME2_TIMER_CONTROL_EN(1);
192 1.1 scw vme2_lcsr_write(sc, VME2LCSR_TIMER_CONTROL, reg);
193 1.1 scw
194 1.1 scw /* Set the VMEChip2's vector base register to the required value */
195 1.1 scw reg = vme2_lcsr_read(sc, VME2LCSR_VECTOR_BASE);
196 1.1 scw reg &= ~VME2_VECTOR_BASE_MASK;
197 1.1 scw reg |= VME2_VECTOR_BASE_REG_VALUE;
198 1.1 scw vme2_lcsr_write(sc, VME2LCSR_VECTOR_BASE, reg);
199 1.1 scw
200 1.1 scw /* Set the Master Interrupt Enable bit now */
201 1.1 scw reg = vme2_lcsr_read(sc, VME2LCSR_MISC_STATUS) | VME2_MISC_STATUS_MIEN;
202 1.1 scw vme2_lcsr_write(sc, VME2LCSR_MISC_STATUS, reg);
203 1.2 scw
204 1.2 scw /* Allow the MD code the chance to do some initialising */
205 1.2 scw vmetwo_md_intr_init(sc);
206 1.1 scw
207 1.1 scw #if defined(MVME167) || defined(MVME177)
208 1.1 scw #if defined(MVME162) || defined(MVME172)
209 1.1 scw if (machineid != MVME_162 && machineid != MVME_172)
210 1.1 scw #endif
211 1.1 scw {
212 1.1 scw /*
213 1.1 scw * Let the NMI handler deal with level 7 ABORT switch
214 1.1 scw * interrupts
215 1.1 scw */
216 1.1 scw vmetwo_intr_establish(sc, 7, 7, VME2_VEC_ABORT, 1,
217 1.1 scw nmihand, NULL, NULL);
218 1.1 scw }
219 1.1 scw #endif
220 1.1 scw
221 1.1 scw /* Setup hardware assisted soft interrupts */
222 1.8 ad #ifdef notyet
223 1.1 scw vmetwo_intr_establish(sc, 1, 1, VME2_VEC_SOFT0, 1,
224 1.1 scw (int (*)(void *))softintr_dispatch, NULL, NULL);
225 1.1 scw _softintr_chipset_assert = vmetwo_softintr_assert;
226 1.8 ad #endif
227 1.1 scw }
228 1.1 scw
229 1.1 scw static int
230 1.1 scw vmetwo_local_isr_trampoline(arg)
231 1.1 scw void *arg;
232 1.1 scw {
233 1.1 scw struct vme_two_handler *isr;
234 1.1 scw int vec;
235 1.1 scw
236 1.1 scw vec = (int) arg; /* 0x08 <= vec <= 0x1f */
237 1.1 scw
238 1.1 scw /* Clear the interrupt source */
239 1.1 scw vme2_lcsr_write(vmetwo_sc, VME2LCSR_LOCAL_INTERRUPT_CLEAR,
240 1.1 scw VME2_LOCAL_INTERRUPT(vec));
241 1.1 scw
242 1.1 scw isr = &vme_two_handlers[vec - VME2_VECTOR_LOCAL_OFFSET];
243 1.1 scw if (isr->isr_hand)
244 1.1 scw (void) (*isr->isr_hand) (isr->isr_arg);
245 1.1 scw else
246 1.1 scw printf("vmetwo: Spurious local interrupt, vector 0x%x\n", vec);
247 1.1 scw
248 1.1 scw return (1);
249 1.1 scw }
250 1.1 scw
251 1.1 scw void
252 1.1 scw vmetwo_local_intr_establish(pri, vec, hand, arg, evcnt)
253 1.1 scw int pri, vec;
254 1.1 scw int (*hand)(void *);
255 1.1 scw void *arg;
256 1.1 scw struct evcnt *evcnt;
257 1.1 scw {
258 1.1 scw
259 1.1 scw vmetwo_intr_establish(vmetwo_sc, pri, pri, vec, 1, hand, arg, evcnt);
260 1.1 scw }
261 1.1 scw
262 1.1 scw /* ARGSUSED */
263 1.1 scw void
264 1.1 scw vmetwo_intr_establish(csc, prior, lvl, vec, first, hand, arg, evcnt)
265 1.1 scw void *csc;
266 1.1 scw int prior, lvl, vec, first;
267 1.1 scw int (*hand)(void *);
268 1.1 scw void *arg;
269 1.1 scw struct evcnt *evcnt;
270 1.1 scw {
271 1.1 scw struct vmetwo_softc *sc = csc;
272 1.1 scw u_int32_t reg;
273 1.1 scw int bitoff;
274 1.1 scw int iloffset, ilshift;
275 1.1 scw int s;
276 1.1 scw
277 1.1 scw s = splhigh();
278 1.1 scw
279 1.1 scw #if NVMETWO > 0
280 1.1 scw /*
281 1.1 scw * Sort out interrupts generated locally by the VMEChip2 from
282 1.1 scw * those generated by VMEbus devices...
283 1.1 scw */
284 1.1 scw if (vec >= VME2_VECTOR_LOCAL_MIN && vec <= VME2_VECTOR_LOCAL_MAX) {
285 1.1 scw #endif
286 1.1 scw /*
287 1.1 scw * Local interrupts need to be bounced through some
288 1.1 scw * trampoline code which acknowledges/clears them.
289 1.1 scw */
290 1.1 scw vme_two_handlers[vec - VME2_VECTOR_LOCAL_MIN].isr_hand = hand;
291 1.1 scw vme_two_handlers[vec - VME2_VECTOR_LOCAL_MIN].isr_arg = arg;
292 1.1 scw hand = vmetwo_local_isr_trampoline;
293 1.1 scw arg = (void *) (vec - VME2_VECTOR_BASE);
294 1.1 scw
295 1.1 scw /*
296 1.1 scw * Interrupt enable/clear bit offset is 0x08 - 0x1f
297 1.1 scw */
298 1.1 scw bitoff = vec - VME2_VECTOR_BASE;
299 1.1 scw #if NVMETWO > 0
300 1.1 scw first = 1; /* Force the interrupt to be enabled */
301 1.1 scw } else {
302 1.1 scw /*
303 1.1 scw * Interrupts originating from the VMEbus are
304 1.1 scw * controlled by an offset of 0x00 - 0x07
305 1.1 scw */
306 1.1 scw bitoff = lvl - 1;
307 1.1 scw }
308 1.1 scw #endif
309 1.1 scw
310 1.1 scw /* Hook the interrupt */
311 1.1 scw (*sc->sc_isrlink)(sc->sc_isrcookie, hand, arg, prior, vec, evcnt);
312 1.1 scw
313 1.1 scw /*
314 1.1 scw * Do we need to tell the VMEChip2 to let the interrupt through?
315 1.1 scw * (This is always true for locally-generated interrupts, but only
316 1.1 scw * needs doing once for each VMEbus interrupt level which is hooked)
317 1.1 scw */
318 1.1 scw #if NVMETWO > 0
319 1.1 scw if (first) {
320 1.1 scw if (evcnt)
321 1.1 scw evcnt_attach_dynamic(evcnt, EVCNT_TYPE_INTR,
322 1.1 scw (*sc->sc_isrevcnt)(sc->sc_isrcookie, prior),
323 1.1 scw sc->sc_mvmebus.sc_dev.dv_xname,
324 1.1 scw mvmebus_irq_name[lvl]);
325 1.1 scw #endif
326 1.1 scw iloffset = VME2_ILOFFSET_FROM_VECTOR(bitoff) +
327 1.1 scw VME2LCSR_INTERRUPT_LEVEL_BASE;
328 1.1 scw ilshift = VME2_ILSHIFT_FROM_VECTOR(bitoff);
329 1.1 scw
330 1.1 scw /* Program the specified interrupt to signal at 'prior' */
331 1.1 scw reg = vme2_lcsr_read(sc, iloffset);
332 1.1 scw reg &= ~(VME2_INTERRUPT_LEVEL_MASK << ilshift);
333 1.1 scw reg |= (prior << ilshift);
334 1.1 scw vme2_lcsr_write(sc, iloffset, reg);
335 1.1 scw
336 1.1 scw /* Clear it */
337 1.1 scw vme2_lcsr_write(sc, VME2LCSR_LOCAL_INTERRUPT_CLEAR,
338 1.1 scw VME2_LOCAL_INTERRUPT(bitoff));
339 1.1 scw
340 1.1 scw /* Enable it. */
341 1.1 scw reg = vme2_lcsr_read(sc, VME2LCSR_LOCAL_INTERRUPT_ENABLE);
342 1.1 scw reg |= VME2_LOCAL_INTERRUPT(bitoff);
343 1.1 scw vme2_lcsr_write(sc, VME2LCSR_LOCAL_INTERRUPT_ENABLE, reg);
344 1.1 scw #if NVMETWO > 0
345 1.1 scw }
346 1.1 scw #ifdef DIAGNOSTIC
347 1.1 scw else {
348 1.1 scw /* Verify the interrupt priority is the same */
349 1.1 scw iloffset = VME2_ILOFFSET_FROM_VECTOR(bitoff) +
350 1.1 scw VME2LCSR_INTERRUPT_LEVEL_BASE;
351 1.1 scw ilshift = VME2_ILSHIFT_FROM_VECTOR(bitoff);
352 1.1 scw
353 1.1 scw reg = vme2_lcsr_read(sc, iloffset);
354 1.1 scw reg &= (VME2_INTERRUPT_LEVEL_MASK << ilshift);
355 1.1 scw
356 1.1 scw if ((prior << ilshift) != reg)
357 1.1 scw panic("vmetwo_intr_establish: priority mismatch!");
358 1.1 scw }
359 1.1 scw #endif
360 1.1 scw #endif
361 1.1 scw splx(s);
362 1.1 scw }
363 1.1 scw
364 1.1 scw void
365 1.1 scw vmetwo_intr_disestablish(csc, lvl, vec, last, evcnt)
366 1.1 scw void *csc;
367 1.1 scw int lvl, vec, last;
368 1.1 scw struct evcnt *evcnt;
369 1.1 scw {
370 1.1 scw struct vmetwo_softc *sc = csc;
371 1.1 scw u_int32_t reg;
372 1.1 scw int iloffset, ilshift;
373 1.1 scw int bitoff;
374 1.1 scw int s;
375 1.1 scw
376 1.1 scw s = splhigh();
377 1.1 scw
378 1.1 scw #if NVMETWO > 0
379 1.1 scw /*
380 1.1 scw * Sort out interrupts generated locally by the VMEChip2 from
381 1.1 scw * those generated by VMEbus devices...
382 1.1 scw */
383 1.1 scw if (vec >= VME2_VECTOR_LOCAL_MIN && vec <= VME2_VECTOR_LOCAL_MAX) {
384 1.1 scw #endif
385 1.1 scw /*
386 1.1 scw * Interrupt enable/clear bit offset is 0x08 - 0x1f
387 1.1 scw */
388 1.1 scw bitoff = vec - VME2_VECTOR_BASE;
389 1.1 scw vme_two_handlers[vec - VME2_VECTOR_LOCAL_MIN].isr_hand = NULL;
390 1.1 scw last = 1; /* Force the interrupt to be cleared */
391 1.1 scw #if NVMETWO > 0
392 1.1 scw } else {
393 1.1 scw /*
394 1.1 scw * Interrupts originating from the VMEbus are
395 1.1 scw * controlled by an offset of 0x00 - 0x07
396 1.1 scw */
397 1.1 scw bitoff = lvl - 1;
398 1.1 scw }
399 1.1 scw #endif
400 1.1 scw
401 1.1 scw /*
402 1.1 scw * Do we need to tell the VMEChip2 to block the interrupt?
403 1.1 scw * (This is always true for locally-generated interrupts, but only
404 1.1 scw * needs doing once when the last VMEbus handler for any given level
405 1.1 scw * has been unhooked.)
406 1.1 scw */
407 1.1 scw if (last) {
408 1.1 scw iloffset = VME2_ILOFFSET_FROM_VECTOR(bitoff) +
409 1.1 scw VME2LCSR_INTERRUPT_LEVEL_BASE;
410 1.1 scw ilshift = VME2_ILSHIFT_FROM_VECTOR(bitoff);
411 1.1 scw
412 1.1 scw /* Disable it. */
413 1.1 scw reg = vme2_lcsr_read(sc, VME2LCSR_LOCAL_INTERRUPT_ENABLE);
414 1.1 scw reg &= ~VME2_LOCAL_INTERRUPT(bitoff);
415 1.1 scw vme2_lcsr_write(sc, VME2LCSR_LOCAL_INTERRUPT_ENABLE, reg);
416 1.1 scw
417 1.1 scw /* Set the interrupt's level to zero */
418 1.1 scw reg = vme2_lcsr_read(sc, iloffset);
419 1.1 scw reg &= ~(VME2_INTERRUPT_LEVEL_MASK << ilshift);
420 1.1 scw vme2_lcsr_write(sc, iloffset, reg);
421 1.1 scw
422 1.1 scw /* Clear it */
423 1.1 scw vme2_lcsr_write(sc, VME2LCSR_LOCAL_INTERRUPT_CLEAR,
424 1.1 scw VME2_LOCAL_INTERRUPT(vec));
425 1.1 scw
426 1.1 scw if (evcnt)
427 1.1 scw evcnt_detach(evcnt);
428 1.1 scw }
429 1.1 scw /* Un-hook it */
430 1.1 scw (*sc->sc_isrunlink)(sc->sc_isrcookie, vec);
431 1.1 scw
432 1.1 scw splx(s);
433 1.1 scw }
434 1.1 scw
435 1.8 ad #ifdef notyet
436 1.1 scw static void
437 1.1 scw vmetwo_softintr_assert(void)
438 1.1 scw {
439 1.1 scw
440 1.1 scw vme2_lcsr_write(vmetwo_sc, VME2LCSR_SOFTINT_SET, VME2_SOFTINT_SET(0));
441 1.1 scw }
442 1.8 ad #endif
443