vme_two_isr.c revision 1.7.2.2
1 /* $NetBSD: vme_two_isr.c,v 1.7.2.2 2008/02/18 21:05:55 mjf Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Steve C. Woodford. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Split off from vme_two.c specifically to deal with hardware assisted 41 * soft interrupts when the user hasn't specified `vmetwo0' in the 42 * kernel config file (mvme1[67]2 only). 43 */ 44 45 #include <sys/cdefs.h> 46 __KERNEL_RCSID(0, "$NetBSD: vme_two_isr.c,v 1.7.2.2 2008/02/18 21:05:55 mjf Exp $"); 47 48 #include "vmetwo.h" 49 50 #include <sys/param.h> 51 #include <sys/kernel.h> 52 #include <sys/systm.h> 53 #include <sys/device.h> 54 #include <sys/malloc.h> 55 #include <sys/cpu.h> 56 #include <sys/bus.h> 57 58 #include <dev/vme/vmereg.h> 59 #include <dev/vme/vmevar.h> 60 61 #include <dev/mvme/mvmebus.h> 62 #include <dev/mvme/vme_tworeg.h> 63 #include <dev/mvme/vme_twovar.h> 64 65 /* 66 * Non-zero if there is no VMEChip2 on this board. 67 */ 68 int vmetwo_not_present; 69 70 /* 71 * Array of interrupt handlers registered with us for the non-VMEbus 72 * vectored interrupts. Eg. ABORT Switch, SYSFAIL etc. 73 * 74 * We can't just install a caller's handler directly, since these 75 * interrupts have to be manually cleared, so we have a trampoline 76 * which does the clearing automatically. 77 */ 78 static struct vme_two_handler { 79 int (*isr_hand)(void *); 80 void *isr_arg; 81 } vme_two_handlers[(VME2_VECTOR_LOCAL_MAX - VME2_VECTOR_LOCAL_MIN) + 1]; 82 83 #define VMETWO_HANDLERS_SZ (sizeof(vme_two_handlers) / \ 84 sizeof(struct vme_two_handler)) 85 86 static int vmetwo_local_isr_trampoline(void *); 87 #ifdef notyet 88 static void vmetwo_softintr_assert(void); 89 #endif 90 91 static struct vmetwo_softc *vmetwo_sc; 92 93 int 94 vmetwo_probe(bus_space_tag_t bt, bus_addr_t offset) 95 { 96 bus_space_handle_t bh; 97 98 bus_space_map(bt, offset + VME2REG_LCSR_OFFSET, VME2LCSR_SIZE, 0, &bh); 99 100 if (bus_space_peek_4(bt, bh, VME2LCSR_MISC_STATUS, NULL) != 0) { 101 #if defined(MVME162) || defined(MVME172) 102 #if defined(MVME167) || defined(MVME177) 103 if (machineid == MVME_162 || machineid == MVME_172) 104 #endif 105 { 106 /* 107 * No VMEChip2 on mvme162/172 is not too big a 108 * deal; we can fall back on timer4 in the 109 * mcchip for h/w assisted soft interrupts... 110 */ 111 extern void pcctwosoftintrinit(void); 112 bus_space_unmap(bt, bh, VME2LCSR_SIZE); 113 vmetwo_not_present = 1; 114 pcctwosoftintrinit(); 115 return (0); 116 } 117 #endif 118 #if defined(MVME167) || defined(MVME177) || defined(MVME88K) 119 /* 120 * No VMEChip2 on mvme167/177, however, is a Big Deal. 121 * In fact, it means the hardware's shot since the 122 * VMEChip2 is not a `build-option' on those boards. 123 */ 124 panic("VMEChip2 not responding! Faulty board?"); 125 /* NOTREACHED */ 126 #endif 127 #if defined(MVMEPPC) 128 /* 129 * No VMEChip2 on mvmeppc is no big deal. 130 */ 131 bus_space_unmap(bt, bh, VME2LCSR_SIZE); 132 vmetwo_not_present = 1; 133 return (0); 134 #endif 135 } 136 #if NVMETWO == 0 137 else { 138 /* 139 * The kernel config file has no `vmetwo0' device, but 140 * there is a VMEChip2 on the board. Fix up things 141 * just enough to hook VMEChip2 local interrupts. 142 */ 143 struct vmetwo_softc *sc; 144 145 /* XXX Should check sc != NULL here... */ 146 MALLOC(sc, struct vmetwo_softc *, sizeof(*sc), M_DEVBUF, 147 M_NOWAIT); 148 149 sc->sc_mvmebus.sc_bust = bt; 150 sc->sc_lcrh = bh; 151 vmetwo_intr_init(sc); 152 return 0; 153 } 154 #else 155 bus_space_unmap(bt, bh, VME2LCSR_SIZE); 156 return (1); 157 #endif 158 } 159 160 void 161 vmetwo_intr_init(struct vmetwo_softc *sc) 162 { 163 u_int32_t reg; 164 int i; 165 166 vmetwo_sc = sc; 167 168 /* Clear out the ISR handler array */ 169 for (i = 0; i < VMETWO_HANDLERS_SZ; i++) 170 vme_two_handlers[i].isr_hand = NULL; 171 172 /* 173 * Initialize the chip. 174 * Firstly, disable all VMEChip2 Interrupts 175 */ 176 reg = vme2_lcsr_read(sc, VME2LCSR_MISC_STATUS) & ~VME2_MISC_STATUS_MIEN; 177 vme2_lcsr_write(sc, VME2LCSR_MISC_STATUS, reg); 178 vme2_lcsr_write(sc, VME2LCSR_LOCAL_INTERRUPT_ENABLE, 0); 179 vme2_lcsr_write(sc, VME2LCSR_LOCAL_INTERRUPT_CLEAR, 180 VME2_LOCAL_INTERRUPT_CLEAR_ALL); 181 182 /* Zap all the IRQ level registers */ 183 for (i = 0; i < VME2_NUM_IL_REGS; i++) 184 vme2_lcsr_write(sc, VME2LCSR_INTERRUPT_LEVEL_BASE + (i * 4), 0); 185 186 /* Disable the tick timers */ 187 reg = vme2_lcsr_read(sc, VME2LCSR_TIMER_CONTROL); 188 reg &= ~VME2_TIMER_CONTROL_EN(0); 189 reg &= ~VME2_TIMER_CONTROL_EN(1); 190 vme2_lcsr_write(sc, VME2LCSR_TIMER_CONTROL, reg); 191 192 /* Set the VMEChip2's vector base register to the required value */ 193 reg = vme2_lcsr_read(sc, VME2LCSR_VECTOR_BASE); 194 reg &= ~VME2_VECTOR_BASE_MASK; 195 reg |= VME2_VECTOR_BASE_REG_VALUE; 196 vme2_lcsr_write(sc, VME2LCSR_VECTOR_BASE, reg); 197 198 /* Set the Master Interrupt Enable bit now */ 199 reg = vme2_lcsr_read(sc, VME2LCSR_MISC_STATUS) | VME2_MISC_STATUS_MIEN; 200 vme2_lcsr_write(sc, VME2LCSR_MISC_STATUS, reg); 201 202 /* Allow the MD code the chance to do some initialising */ 203 vmetwo_md_intr_init(sc); 204 205 #if defined(MVME167) || defined(MVME177) 206 #if defined(MVME162) || defined(MVME172) 207 if (machineid != MVME_162 && machineid != MVME_172) 208 #endif 209 { 210 /* 211 * Let the NMI handler deal with level 7 ABORT switch 212 * interrupts 213 */ 214 vmetwo_intr_establish(sc, 7, 7, VME2_VEC_ABORT, 1, 215 nmihand, NULL, NULL); 216 } 217 #endif 218 219 /* Setup hardware assisted soft interrupts */ 220 #ifdef notyet 221 vmetwo_intr_establish(sc, 1, 1, VME2_VEC_SOFT0, 1, 222 (int (*)(void *))softintr_dispatch, NULL, NULL); 223 _softintr_chipset_assert = vmetwo_softintr_assert; 224 #endif 225 } 226 227 static int 228 vmetwo_local_isr_trampoline(arg) 229 void *arg; 230 { 231 struct vme_two_handler *isr; 232 int vec; 233 234 vec = (int) arg; /* 0x08 <= vec <= 0x1f */ 235 236 /* Clear the interrupt source */ 237 vme2_lcsr_write(vmetwo_sc, VME2LCSR_LOCAL_INTERRUPT_CLEAR, 238 VME2_LOCAL_INTERRUPT(vec)); 239 240 isr = &vme_two_handlers[vec - VME2_VECTOR_LOCAL_OFFSET]; 241 if (isr->isr_hand) 242 (void) (*isr->isr_hand) (isr->isr_arg); 243 else 244 printf("vmetwo: Spurious local interrupt, vector 0x%x\n", vec); 245 246 return (1); 247 } 248 249 void 250 vmetwo_local_intr_establish(pri, vec, hand, arg, evcnt) 251 int pri, vec; 252 int (*hand)(void *); 253 void *arg; 254 struct evcnt *evcnt; 255 { 256 257 vmetwo_intr_establish(vmetwo_sc, pri, pri, vec, 1, hand, arg, evcnt); 258 } 259 260 /* ARGSUSED */ 261 void 262 vmetwo_intr_establish(csc, prior, lvl, vec, first, hand, arg, evcnt) 263 void *csc; 264 int prior, lvl, vec, first; 265 int (*hand)(void *); 266 void *arg; 267 struct evcnt *evcnt; 268 { 269 struct vmetwo_softc *sc = csc; 270 u_int32_t reg; 271 int bitoff; 272 int iloffset, ilshift; 273 int s; 274 275 s = splhigh(); 276 277 #if NVMETWO > 0 278 /* 279 * Sort out interrupts generated locally by the VMEChip2 from 280 * those generated by VMEbus devices... 281 */ 282 if (vec >= VME2_VECTOR_LOCAL_MIN && vec <= VME2_VECTOR_LOCAL_MAX) { 283 #endif 284 /* 285 * Local interrupts need to be bounced through some 286 * trampoline code which acknowledges/clears them. 287 */ 288 vme_two_handlers[vec - VME2_VECTOR_LOCAL_MIN].isr_hand = hand; 289 vme_two_handlers[vec - VME2_VECTOR_LOCAL_MIN].isr_arg = arg; 290 hand = vmetwo_local_isr_trampoline; 291 arg = (void *) (vec - VME2_VECTOR_BASE); 292 293 /* 294 * Interrupt enable/clear bit offset is 0x08 - 0x1f 295 */ 296 bitoff = vec - VME2_VECTOR_BASE; 297 #if NVMETWO > 0 298 first = 1; /* Force the interrupt to be enabled */ 299 } else { 300 /* 301 * Interrupts originating from the VMEbus are 302 * controlled by an offset of 0x00 - 0x07 303 */ 304 bitoff = lvl - 1; 305 } 306 #endif 307 308 /* Hook the interrupt */ 309 (*sc->sc_isrlink)(sc->sc_isrcookie, hand, arg, prior, vec, evcnt); 310 311 /* 312 * Do we need to tell the VMEChip2 to let the interrupt through? 313 * (This is always true for locally-generated interrupts, but only 314 * needs doing once for each VMEbus interrupt level which is hooked) 315 */ 316 #if NVMETWO > 0 317 if (first) { 318 if (evcnt) 319 evcnt_attach_dynamic(evcnt, EVCNT_TYPE_INTR, 320 (*sc->sc_isrevcnt)(sc->sc_isrcookie, prior), 321 sc->sc_mvmebus.sc_dev.dv_xname, 322 mvmebus_irq_name[lvl]); 323 #endif 324 iloffset = VME2_ILOFFSET_FROM_VECTOR(bitoff) + 325 VME2LCSR_INTERRUPT_LEVEL_BASE; 326 ilshift = VME2_ILSHIFT_FROM_VECTOR(bitoff); 327 328 /* Program the specified interrupt to signal at 'prior' */ 329 reg = vme2_lcsr_read(sc, iloffset); 330 reg &= ~(VME2_INTERRUPT_LEVEL_MASK << ilshift); 331 reg |= (prior << ilshift); 332 vme2_lcsr_write(sc, iloffset, reg); 333 334 /* Clear it */ 335 vme2_lcsr_write(sc, VME2LCSR_LOCAL_INTERRUPT_CLEAR, 336 VME2_LOCAL_INTERRUPT(bitoff)); 337 338 /* Enable it. */ 339 reg = vme2_lcsr_read(sc, VME2LCSR_LOCAL_INTERRUPT_ENABLE); 340 reg |= VME2_LOCAL_INTERRUPT(bitoff); 341 vme2_lcsr_write(sc, VME2LCSR_LOCAL_INTERRUPT_ENABLE, reg); 342 #if NVMETWO > 0 343 } 344 #ifdef DIAGNOSTIC 345 else { 346 /* Verify the interrupt priority is the same */ 347 iloffset = VME2_ILOFFSET_FROM_VECTOR(bitoff) + 348 VME2LCSR_INTERRUPT_LEVEL_BASE; 349 ilshift = VME2_ILSHIFT_FROM_VECTOR(bitoff); 350 351 reg = vme2_lcsr_read(sc, iloffset); 352 reg &= (VME2_INTERRUPT_LEVEL_MASK << ilshift); 353 354 if ((prior << ilshift) != reg) 355 panic("vmetwo_intr_establish: priority mismatch!"); 356 } 357 #endif 358 #endif 359 splx(s); 360 } 361 362 void 363 vmetwo_intr_disestablish(csc, lvl, vec, last, evcnt) 364 void *csc; 365 int lvl, vec, last; 366 struct evcnt *evcnt; 367 { 368 struct vmetwo_softc *sc = csc; 369 u_int32_t reg; 370 int iloffset, ilshift; 371 int bitoff; 372 int s; 373 374 s = splhigh(); 375 376 #if NVMETWO > 0 377 /* 378 * Sort out interrupts generated locally by the VMEChip2 from 379 * those generated by VMEbus devices... 380 */ 381 if (vec >= VME2_VECTOR_LOCAL_MIN && vec <= VME2_VECTOR_LOCAL_MAX) { 382 #endif 383 /* 384 * Interrupt enable/clear bit offset is 0x08 - 0x1f 385 */ 386 bitoff = vec - VME2_VECTOR_BASE; 387 vme_two_handlers[vec - VME2_VECTOR_LOCAL_MIN].isr_hand = NULL; 388 last = 1; /* Force the interrupt to be cleared */ 389 #if NVMETWO > 0 390 } else { 391 /* 392 * Interrupts originating from the VMEbus are 393 * controlled by an offset of 0x00 - 0x07 394 */ 395 bitoff = lvl - 1; 396 } 397 #endif 398 399 /* 400 * Do we need to tell the VMEChip2 to block the interrupt? 401 * (This is always true for locally-generated interrupts, but only 402 * needs doing once when the last VMEbus handler for any given level 403 * has been unhooked.) 404 */ 405 if (last) { 406 iloffset = VME2_ILOFFSET_FROM_VECTOR(bitoff) + 407 VME2LCSR_INTERRUPT_LEVEL_BASE; 408 ilshift = VME2_ILSHIFT_FROM_VECTOR(bitoff); 409 410 /* Disable it. */ 411 reg = vme2_lcsr_read(sc, VME2LCSR_LOCAL_INTERRUPT_ENABLE); 412 reg &= ~VME2_LOCAL_INTERRUPT(bitoff); 413 vme2_lcsr_write(sc, VME2LCSR_LOCAL_INTERRUPT_ENABLE, reg); 414 415 /* Set the interrupt's level to zero */ 416 reg = vme2_lcsr_read(sc, iloffset); 417 reg &= ~(VME2_INTERRUPT_LEVEL_MASK << ilshift); 418 vme2_lcsr_write(sc, iloffset, reg); 419 420 /* Clear it */ 421 vme2_lcsr_write(sc, VME2LCSR_LOCAL_INTERRUPT_CLEAR, 422 VME2_LOCAL_INTERRUPT(vec)); 423 424 if (evcnt) 425 evcnt_detach(evcnt); 426 } 427 /* Un-hook it */ 428 (*sc->sc_isrunlink)(sc->sc_isrcookie, vec); 429 430 splx(s); 431 } 432 433 #ifdef notyet 434 static void 435 vmetwo_softintr_assert(void) 436 { 437 438 vme2_lcsr_write(vmetwo_sc, VME2LCSR_SOFTINT_SET, VME2_SOFTINT_SET(0)); 439 } 440 #endif 441
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