vme_two_isr.c revision 1.9.6.2
1 /* $NetBSD: vme_two_isr.c,v 1.9.6.2 2009/01/17 13:28:58 mjf Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Steve C. Woodford. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Split off from vme_two.c specifically to deal with hardware assisted 34 * soft interrupts when the user hasn't specified `vmetwo0' in the 35 * kernel config file (mvme1[67]2 only). 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: vme_two_isr.c,v 1.9.6.2 2009/01/17 13:28:58 mjf Exp $"); 40 41 #include "vmetwo.h" 42 43 #include <sys/param.h> 44 #include <sys/kernel.h> 45 #include <sys/systm.h> 46 #include <sys/device.h> 47 #include <sys/malloc.h> 48 #include <sys/cpu.h> 49 #include <sys/bus.h> 50 51 #include <dev/vme/vmereg.h> 52 #include <dev/vme/vmevar.h> 53 54 #include <dev/mvme/mvmebus.h> 55 #include <dev/mvme/vme_tworeg.h> 56 #include <dev/mvme/vme_twovar.h> 57 58 /* 59 * Non-zero if there is no VMEChip2 on this board. 60 */ 61 int vmetwo_not_present; 62 63 /* 64 * Array of interrupt handlers registered with us for the non-VMEbus 65 * vectored interrupts. Eg. ABORT Switch, SYSFAIL etc. 66 * 67 * We can't just install a caller's handler directly, since these 68 * interrupts have to be manually cleared, so we have a trampoline 69 * which does the clearing automatically. 70 */ 71 static struct vme_two_handler { 72 int (*isr_hand)(void *); 73 void *isr_arg; 74 } vme_two_handlers[(VME2_VECTOR_LOCAL_MAX - VME2_VECTOR_LOCAL_MIN) + 1]; 75 76 #define VMETWO_HANDLERS_SZ (sizeof(vme_two_handlers) / \ 77 sizeof(struct vme_two_handler)) 78 79 static int vmetwo_local_isr_trampoline(void *); 80 #ifdef notyet 81 static void vmetwo_softintr_assert(void); 82 #endif 83 84 static struct vmetwo_softc *vmetwo_sc; 85 86 int 87 vmetwo_probe(bus_space_tag_t bt, bus_addr_t offset) 88 { 89 bus_space_handle_t bh; 90 91 bus_space_map(bt, offset + VME2REG_LCSR_OFFSET, VME2LCSR_SIZE, 0, &bh); 92 93 if (bus_space_peek_4(bt, bh, VME2LCSR_MISC_STATUS, NULL) != 0) { 94 #if defined(MVME162) || defined(MVME172) 95 #if defined(MVME167) || defined(MVME177) 96 if (machineid == MVME_162 || machineid == MVME_172) 97 #endif 98 { 99 /* 100 * No VMEChip2 on mvme162/172 is not too big a 101 * deal; we can fall back on timer4 in the 102 * mcchip for h/w assisted soft interrupts... 103 */ 104 extern void pcctwosoftintrinit(void); 105 bus_space_unmap(bt, bh, VME2LCSR_SIZE); 106 vmetwo_not_present = 1; 107 pcctwosoftintrinit(); 108 return (0); 109 } 110 #endif 111 #if defined(MVME167) || defined(MVME177) || defined(MVME88K) 112 /* 113 * No VMEChip2 on mvme167/177, however, is a Big Deal. 114 * In fact, it means the hardware's shot since the 115 * VMEChip2 is not a `build-option' on those boards. 116 */ 117 panic("VMEChip2 not responding! Faulty board?"); 118 /* NOTREACHED */ 119 #endif 120 #if defined(MVMEPPC) 121 /* 122 * No VMEChip2 on mvmeppc is no big deal. 123 */ 124 bus_space_unmap(bt, bh, VME2LCSR_SIZE); 125 vmetwo_not_present = 1; 126 return (0); 127 #endif 128 } 129 #if NVMETWO == 0 130 else { 131 /* 132 * The kernel config file has no `vmetwo0' device, but 133 * there is a VMEChip2 on the board. Fix up things 134 * just enough to hook VMEChip2 local interrupts. 135 */ 136 struct vmetwo_softc *sc; 137 138 /* XXX Should check sc != NULL here... */ 139 sc = malloc(sizeof(*sc), M_DEVBUF, M_NOWAIT); 140 141 sc->sc_mvmebus.sc_bust = bt; 142 sc->sc_lcrh = bh; 143 vmetwo_intr_init(sc); 144 return 0; 145 } 146 #else 147 bus_space_unmap(bt, bh, VME2LCSR_SIZE); 148 return (1); 149 #endif 150 } 151 152 void 153 vmetwo_intr_init(struct vmetwo_softc *sc) 154 { 155 u_int32_t reg; 156 int i; 157 158 vmetwo_sc = sc; 159 160 /* Clear out the ISR handler array */ 161 for (i = 0; i < VMETWO_HANDLERS_SZ; i++) 162 vme_two_handlers[i].isr_hand = NULL; 163 164 /* 165 * Initialize the chip. 166 * Firstly, disable all VMEChip2 Interrupts 167 */ 168 reg = vme2_lcsr_read(sc, VME2LCSR_MISC_STATUS) & ~VME2_MISC_STATUS_MIEN; 169 vme2_lcsr_write(sc, VME2LCSR_MISC_STATUS, reg); 170 vme2_lcsr_write(sc, VME2LCSR_LOCAL_INTERRUPT_ENABLE, 0); 171 vme2_lcsr_write(sc, VME2LCSR_LOCAL_INTERRUPT_CLEAR, 172 VME2_LOCAL_INTERRUPT_CLEAR_ALL); 173 174 /* Zap all the IRQ level registers */ 175 for (i = 0; i < VME2_NUM_IL_REGS; i++) 176 vme2_lcsr_write(sc, VME2LCSR_INTERRUPT_LEVEL_BASE + (i * 4), 0); 177 178 /* Disable the tick timers */ 179 reg = vme2_lcsr_read(sc, VME2LCSR_TIMER_CONTROL); 180 reg &= ~VME2_TIMER_CONTROL_EN(0); 181 reg &= ~VME2_TIMER_CONTROL_EN(1); 182 vme2_lcsr_write(sc, VME2LCSR_TIMER_CONTROL, reg); 183 184 /* Set the VMEChip2's vector base register to the required value */ 185 reg = vme2_lcsr_read(sc, VME2LCSR_VECTOR_BASE); 186 reg &= ~VME2_VECTOR_BASE_MASK; 187 reg |= VME2_VECTOR_BASE_REG_VALUE; 188 vme2_lcsr_write(sc, VME2LCSR_VECTOR_BASE, reg); 189 190 /* Set the Master Interrupt Enable bit now */ 191 reg = vme2_lcsr_read(sc, VME2LCSR_MISC_STATUS) | VME2_MISC_STATUS_MIEN; 192 vme2_lcsr_write(sc, VME2LCSR_MISC_STATUS, reg); 193 194 /* Allow the MD code the chance to do some initialising */ 195 vmetwo_md_intr_init(sc); 196 197 #if defined(MVME167) || defined(MVME177) 198 #if defined(MVME162) || defined(MVME172) 199 if (machineid != MVME_162 && machineid != MVME_172) 200 #endif 201 { 202 /* 203 * Let the NMI handler deal with level 7 ABORT switch 204 * interrupts 205 */ 206 vmetwo_intr_establish(sc, 7, 7, VME2_VEC_ABORT, 1, 207 nmihand, NULL, NULL); 208 } 209 #endif 210 211 /* Setup hardware assisted soft interrupts */ 212 #ifdef notyet 213 vmetwo_intr_establish(sc, 1, 1, VME2_VEC_SOFT0, 1, 214 (int (*)(void *))softintr_dispatch, NULL, NULL); 215 _softintr_chipset_assert = vmetwo_softintr_assert; 216 #endif 217 } 218 219 static int 220 vmetwo_local_isr_trampoline(arg) 221 void *arg; 222 { 223 struct vme_two_handler *isr; 224 int vec; 225 226 vec = (int) arg; /* 0x08 <= vec <= 0x1f */ 227 228 /* Clear the interrupt source */ 229 vme2_lcsr_write(vmetwo_sc, VME2LCSR_LOCAL_INTERRUPT_CLEAR, 230 VME2_LOCAL_INTERRUPT(vec)); 231 232 isr = &vme_two_handlers[vec - VME2_VECTOR_LOCAL_OFFSET]; 233 if (isr->isr_hand) 234 (void) (*isr->isr_hand) (isr->isr_arg); 235 else 236 printf("vmetwo: Spurious local interrupt, vector 0x%x\n", vec); 237 238 return (1); 239 } 240 241 void 242 vmetwo_local_intr_establish(pri, vec, hand, arg, evcnt) 243 int pri, vec; 244 int (*hand)(void *); 245 void *arg; 246 struct evcnt *evcnt; 247 { 248 249 vmetwo_intr_establish(vmetwo_sc, pri, pri, vec, 1, hand, arg, evcnt); 250 } 251 252 /* ARGSUSED */ 253 void 254 vmetwo_intr_establish(csc, prior, lvl, vec, first, hand, arg, evcnt) 255 void *csc; 256 int prior, lvl, vec, first; 257 int (*hand)(void *); 258 void *arg; 259 struct evcnt *evcnt; 260 { 261 struct vmetwo_softc *sc = csc; 262 u_int32_t reg; 263 int bitoff; 264 int iloffset, ilshift; 265 int s; 266 267 s = splhigh(); 268 269 #if NVMETWO > 0 270 /* 271 * Sort out interrupts generated locally by the VMEChip2 from 272 * those generated by VMEbus devices... 273 */ 274 if (vec >= VME2_VECTOR_LOCAL_MIN && vec <= VME2_VECTOR_LOCAL_MAX) { 275 #endif 276 /* 277 * Local interrupts need to be bounced through some 278 * trampoline code which acknowledges/clears them. 279 */ 280 vme_two_handlers[vec - VME2_VECTOR_LOCAL_MIN].isr_hand = hand; 281 vme_two_handlers[vec - VME2_VECTOR_LOCAL_MIN].isr_arg = arg; 282 hand = vmetwo_local_isr_trampoline; 283 arg = (void *) (vec - VME2_VECTOR_BASE); 284 285 /* 286 * Interrupt enable/clear bit offset is 0x08 - 0x1f 287 */ 288 bitoff = vec - VME2_VECTOR_BASE; 289 #if NVMETWO > 0 290 first = 1; /* Force the interrupt to be enabled */ 291 } else { 292 /* 293 * Interrupts originating from the VMEbus are 294 * controlled by an offset of 0x00 - 0x07 295 */ 296 bitoff = lvl - 1; 297 } 298 #endif 299 300 /* Hook the interrupt */ 301 (*sc->sc_isrlink)(sc->sc_isrcookie, hand, arg, prior, vec, evcnt); 302 303 /* 304 * Do we need to tell the VMEChip2 to let the interrupt through? 305 * (This is always true for locally-generated interrupts, but only 306 * needs doing once for each VMEbus interrupt level which is hooked) 307 */ 308 #if NVMETWO > 0 309 if (first) { 310 if (evcnt) 311 evcnt_attach_dynamic(evcnt, EVCNT_TYPE_INTR, 312 (*sc->sc_isrevcnt)(sc->sc_isrcookie, prior), 313 device_xname(&sc->sc_mvmebus.sc_dev), 314 mvmebus_irq_name[lvl]); 315 #endif 316 iloffset = VME2_ILOFFSET_FROM_VECTOR(bitoff) + 317 VME2LCSR_INTERRUPT_LEVEL_BASE; 318 ilshift = VME2_ILSHIFT_FROM_VECTOR(bitoff); 319 320 /* Program the specified interrupt to signal at 'prior' */ 321 reg = vme2_lcsr_read(sc, iloffset); 322 reg &= ~(VME2_INTERRUPT_LEVEL_MASK << ilshift); 323 reg |= (prior << ilshift); 324 vme2_lcsr_write(sc, iloffset, reg); 325 326 /* Clear it */ 327 vme2_lcsr_write(sc, VME2LCSR_LOCAL_INTERRUPT_CLEAR, 328 VME2_LOCAL_INTERRUPT(bitoff)); 329 330 /* Enable it. */ 331 reg = vme2_lcsr_read(sc, VME2LCSR_LOCAL_INTERRUPT_ENABLE); 332 reg |= VME2_LOCAL_INTERRUPT(bitoff); 333 vme2_lcsr_write(sc, VME2LCSR_LOCAL_INTERRUPT_ENABLE, reg); 334 #if NVMETWO > 0 335 } 336 #ifdef DIAGNOSTIC 337 else { 338 /* Verify the interrupt priority is the same */ 339 iloffset = VME2_ILOFFSET_FROM_VECTOR(bitoff) + 340 VME2LCSR_INTERRUPT_LEVEL_BASE; 341 ilshift = VME2_ILSHIFT_FROM_VECTOR(bitoff); 342 343 reg = vme2_lcsr_read(sc, iloffset); 344 reg &= (VME2_INTERRUPT_LEVEL_MASK << ilshift); 345 346 if ((prior << ilshift) != reg) 347 panic("vmetwo_intr_establish: priority mismatch!"); 348 } 349 #endif 350 #endif 351 splx(s); 352 } 353 354 void 355 vmetwo_intr_disestablish(csc, lvl, vec, last, evcnt) 356 void *csc; 357 int lvl, vec, last; 358 struct evcnt *evcnt; 359 { 360 struct vmetwo_softc *sc = csc; 361 u_int32_t reg; 362 int iloffset, ilshift; 363 int bitoff; 364 int s; 365 366 s = splhigh(); 367 368 #if NVMETWO > 0 369 /* 370 * Sort out interrupts generated locally by the VMEChip2 from 371 * those generated by VMEbus devices... 372 */ 373 if (vec >= VME2_VECTOR_LOCAL_MIN && vec <= VME2_VECTOR_LOCAL_MAX) { 374 #endif 375 /* 376 * Interrupt enable/clear bit offset is 0x08 - 0x1f 377 */ 378 bitoff = vec - VME2_VECTOR_BASE; 379 vme_two_handlers[vec - VME2_VECTOR_LOCAL_MIN].isr_hand = NULL; 380 last = 1; /* Force the interrupt to be cleared */ 381 #if NVMETWO > 0 382 } else { 383 /* 384 * Interrupts originating from the VMEbus are 385 * controlled by an offset of 0x00 - 0x07 386 */ 387 bitoff = lvl - 1; 388 } 389 #endif 390 391 /* 392 * Do we need to tell the VMEChip2 to block the interrupt? 393 * (This is always true for locally-generated interrupts, but only 394 * needs doing once when the last VMEbus handler for any given level 395 * has been unhooked.) 396 */ 397 if (last) { 398 iloffset = VME2_ILOFFSET_FROM_VECTOR(bitoff) + 399 VME2LCSR_INTERRUPT_LEVEL_BASE; 400 ilshift = VME2_ILSHIFT_FROM_VECTOR(bitoff); 401 402 /* Disable it. */ 403 reg = vme2_lcsr_read(sc, VME2LCSR_LOCAL_INTERRUPT_ENABLE); 404 reg &= ~VME2_LOCAL_INTERRUPT(bitoff); 405 vme2_lcsr_write(sc, VME2LCSR_LOCAL_INTERRUPT_ENABLE, reg); 406 407 /* Set the interrupt's level to zero */ 408 reg = vme2_lcsr_read(sc, iloffset); 409 reg &= ~(VME2_INTERRUPT_LEVEL_MASK << ilshift); 410 vme2_lcsr_write(sc, iloffset, reg); 411 412 /* Clear it */ 413 vme2_lcsr_write(sc, VME2LCSR_LOCAL_INTERRUPT_CLEAR, 414 VME2_LOCAL_INTERRUPT(vec)); 415 416 if (evcnt) 417 evcnt_detach(evcnt); 418 } 419 /* Un-hook it */ 420 (*sc->sc_isrunlink)(sc->sc_isrcookie, vec); 421 422 splx(s); 423 } 424 425 #ifdef notyet 426 static void 427 vmetwo_softintr_assert(void) 428 { 429 430 vme2_lcsr_write(vmetwo_sc, VME2LCSR_SOFTINT_SET, VME2_SOFTINT_SET(0)); 431 } 432 #endif 433
Indexes created Sun Oct 12 02:09:55 GMT 2025