nvmm_ioctl.h revision 1.11 1 1.11 maxv /* $NetBSD: nvmm_ioctl.h,v 1.11 2020/09/05 07:22:25 maxv Exp $ */
2 1.1 maxv
3 1.1 maxv /*
4 1.11 maxv * Copyright (c) 2018-2020 Maxime Villard, m00nbsd.net
5 1.1 maxv * All rights reserved.
6 1.1 maxv *
7 1.11 maxv * This code is part of the NVMM hypervisor.
8 1.1 maxv *
9 1.1 maxv * Redistribution and use in source and binary forms, with or without
10 1.1 maxv * modification, are permitted provided that the following conditions
11 1.1 maxv * are met:
12 1.1 maxv * 1. Redistributions of source code must retain the above copyright
13 1.1 maxv * notice, this list of conditions and the following disclaimer.
14 1.1 maxv * 2. Redistributions in binary form must reproduce the above copyright
15 1.1 maxv * notice, this list of conditions and the following disclaimer in the
16 1.1 maxv * documentation and/or other materials provided with the distribution.
17 1.1 maxv *
18 1.11 maxv * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 1.11 maxv * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 1.11 maxv * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 1.11 maxv * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 1.11 maxv * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
23 1.11 maxv * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
24 1.11 maxv * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
25 1.11 maxv * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
26 1.11 maxv * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 1.11 maxv * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 1.11 maxv * SUCH DAMAGE.
29 1.1 maxv */
30 1.1 maxv
31 1.1 maxv #ifndef _NVMM_IOCTL_H_
32 1.1 maxv #define _NVMM_IOCTL_H_
33 1.1 maxv
34 1.1 maxv #include <dev/nvmm/nvmm.h>
35 1.1 maxv
36 1.1 maxv struct nvmm_ioc_capability {
37 1.1 maxv struct nvmm_capability cap;
38 1.1 maxv };
39 1.1 maxv
40 1.1 maxv struct nvmm_ioc_machine_create {
41 1.1 maxv nvmm_machid_t machid;
42 1.1 maxv };
43 1.1 maxv
44 1.1 maxv struct nvmm_ioc_machine_destroy {
45 1.1 maxv nvmm_machid_t machid;
46 1.1 maxv };
47 1.1 maxv
48 1.1 maxv struct nvmm_ioc_machine_configure {
49 1.1 maxv nvmm_machid_t machid;
50 1.1 maxv uint64_t op;
51 1.1 maxv void *conf;
52 1.1 maxv };
53 1.1 maxv
54 1.1 maxv struct nvmm_ioc_vcpu_create {
55 1.1 maxv nvmm_machid_t machid;
56 1.1 maxv nvmm_cpuid_t cpuid;
57 1.1 maxv };
58 1.1 maxv
59 1.1 maxv struct nvmm_ioc_vcpu_destroy {
60 1.1 maxv nvmm_machid_t machid;
61 1.1 maxv nvmm_cpuid_t cpuid;
62 1.1 maxv };
63 1.1 maxv
64 1.8 maxv struct nvmm_ioc_vcpu_configure {
65 1.8 maxv nvmm_machid_t machid;
66 1.8 maxv nvmm_cpuid_t cpuid;
67 1.8 maxv uint64_t op;
68 1.8 maxv void *conf;
69 1.8 maxv };
70 1.8 maxv
71 1.1 maxv struct nvmm_ioc_vcpu_setstate {
72 1.1 maxv nvmm_machid_t machid;
73 1.1 maxv nvmm_cpuid_t cpuid;
74 1.1 maxv };
75 1.1 maxv
76 1.1 maxv struct nvmm_ioc_vcpu_getstate {
77 1.1 maxv nvmm_machid_t machid;
78 1.1 maxv nvmm_cpuid_t cpuid;
79 1.1 maxv };
80 1.1 maxv
81 1.1 maxv struct nvmm_ioc_vcpu_inject {
82 1.1 maxv nvmm_machid_t machid;
83 1.1 maxv nvmm_cpuid_t cpuid;
84 1.1 maxv };
85 1.1 maxv
86 1.1 maxv struct nvmm_ioc_vcpu_run {
87 1.1 maxv /* input */
88 1.1 maxv nvmm_machid_t machid;
89 1.1 maxv nvmm_cpuid_t cpuid;
90 1.1 maxv /* output */
91 1.8 maxv struct nvmm_vcpu_exit exit;
92 1.1 maxv };
93 1.1 maxv
94 1.2 maxv struct nvmm_ioc_hva_map {
95 1.2 maxv nvmm_machid_t machid;
96 1.2 maxv uintptr_t hva;
97 1.2 maxv size_t size;
98 1.2 maxv int flags;
99 1.2 maxv };
100 1.2 maxv
101 1.2 maxv struct nvmm_ioc_hva_unmap {
102 1.2 maxv nvmm_machid_t machid;
103 1.2 maxv uintptr_t hva;
104 1.2 maxv size_t size;
105 1.2 maxv int flags;
106 1.2 maxv };
107 1.2 maxv
108 1.1 maxv struct nvmm_ioc_gpa_map {
109 1.1 maxv nvmm_machid_t machid;
110 1.1 maxv uintptr_t hva;
111 1.1 maxv gpaddr_t gpa;
112 1.1 maxv size_t size;
113 1.4 maxv int prot;
114 1.1 maxv };
115 1.1 maxv
116 1.1 maxv struct nvmm_ioc_gpa_unmap {
117 1.1 maxv nvmm_machid_t machid;
118 1.1 maxv gpaddr_t gpa;
119 1.1 maxv size_t size;
120 1.1 maxv };
121 1.1 maxv
122 1.5 maxv struct nvmm_ctl_mach_info {
123 1.10 maxv /* input */
124 1.5 maxv nvmm_machid_t machid;
125 1.10 maxv /* output */
126 1.9 maxv uint32_t nvcpus;
127 1.9 maxv uint64_t nram;
128 1.5 maxv pid_t pid;
129 1.5 maxv time_t time;
130 1.5 maxv };
131 1.5 maxv
132 1.5 maxv struct nvmm_ioc_ctl {
133 1.5 maxv int op;
134 1.5 maxv #define NVMM_CTL_MACH_INFO 0
135 1.5 maxv
136 1.5 maxv void *data;
137 1.5 maxv size_t size;
138 1.5 maxv };
139 1.5 maxv
140 1.1 maxv #define NVMM_IOC_CAPABILITY _IOR ('N', 0, struct nvmm_ioc_capability)
141 1.1 maxv #define NVMM_IOC_MACHINE_CREATE _IOWR('N', 1, struct nvmm_ioc_machine_create)
142 1.1 maxv #define NVMM_IOC_MACHINE_DESTROY _IOW ('N', 2, struct nvmm_ioc_machine_destroy)
143 1.1 maxv #define NVMM_IOC_MACHINE_CONFIGURE _IOW ('N', 3, struct nvmm_ioc_machine_configure)
144 1.1 maxv #define NVMM_IOC_VCPU_CREATE _IOW ('N', 4, struct nvmm_ioc_vcpu_create)
145 1.1 maxv #define NVMM_IOC_VCPU_DESTROY _IOW ('N', 5, struct nvmm_ioc_vcpu_destroy)
146 1.8 maxv #define NVMM_IOC_VCPU_CONFIGURE _IOW ('N', 6, struct nvmm_ioc_vcpu_configure)
147 1.8 maxv #define NVMM_IOC_VCPU_SETSTATE _IOW ('N', 7, struct nvmm_ioc_vcpu_setstate)
148 1.8 maxv #define NVMM_IOC_VCPU_GETSTATE _IOW ('N', 8, struct nvmm_ioc_vcpu_getstate)
149 1.8 maxv #define NVMM_IOC_VCPU_INJECT _IOW ('N', 9, struct nvmm_ioc_vcpu_inject)
150 1.8 maxv #define NVMM_IOC_VCPU_RUN _IOWR('N', 10, struct nvmm_ioc_vcpu_run)
151 1.8 maxv #define NVMM_IOC_GPA_MAP _IOW ('N', 11, struct nvmm_ioc_gpa_map)
152 1.8 maxv #define NVMM_IOC_GPA_UNMAP _IOW ('N', 12, struct nvmm_ioc_gpa_unmap)
153 1.8 maxv #define NVMM_IOC_HVA_MAP _IOW ('N', 13, struct nvmm_ioc_hva_map)
154 1.8 maxv #define NVMM_IOC_HVA_UNMAP _IOW ('N', 14, struct nvmm_ioc_hva_unmap)
155 1.5 maxv #define NVMM_IOC_CTL _IOW ('N', 20, struct nvmm_ioc_ctl)
156 1.5 maxv
157 1.1 maxv #endif /* _NVMM_IOCTL_H_ */
158