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nvmm_x86.h revision 1.1
      1  1.1  maxv /*	$NetBSD: nvmm_x86.h,v 1.1 2018/11/07 07:43:08 maxv Exp $	*/
      2  1.1  maxv 
      3  1.1  maxv /*
      4  1.1  maxv  * Copyright (c) 2018 The NetBSD Foundation, Inc.
      5  1.1  maxv  * All rights reserved.
      6  1.1  maxv  *
      7  1.1  maxv  * This code is derived from software contributed to The NetBSD Foundation
      8  1.1  maxv  * by Maxime Villard.
      9  1.1  maxv  *
     10  1.1  maxv  * Redistribution and use in source and binary forms, with or without
     11  1.1  maxv  * modification, are permitted provided that the following conditions
     12  1.1  maxv  * are met:
     13  1.1  maxv  * 1. Redistributions of source code must retain the above copyright
     14  1.1  maxv  *    notice, this list of conditions and the following disclaimer.
     15  1.1  maxv  * 2. Redistributions in binary form must reproduce the above copyright
     16  1.1  maxv  *    notice, this list of conditions and the following disclaimer in the
     17  1.1  maxv  *    documentation and/or other materials provided with the distribution.
     18  1.1  maxv  *
     19  1.1  maxv  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     20  1.1  maxv  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     21  1.1  maxv  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     22  1.1  maxv  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     23  1.1  maxv  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     24  1.1  maxv  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     25  1.1  maxv  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     26  1.1  maxv  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     27  1.1  maxv  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     28  1.1  maxv  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     29  1.1  maxv  * POSSIBILITY OF SUCH DAMAGE.
     30  1.1  maxv  */
     31  1.1  maxv 
     32  1.1  maxv #ifndef _NVMM_X86_H_
     33  1.1  maxv #define _NVMM_X86_H_
     34  1.1  maxv 
     35  1.1  maxv /* Segments. */
     36  1.1  maxv #define NVMM_X64_SEG_CS			0
     37  1.1  maxv #define NVMM_X64_SEG_DS			1
     38  1.1  maxv #define NVMM_X64_SEG_ES			2
     39  1.1  maxv #define NVMM_X64_SEG_FS			3
     40  1.1  maxv #define NVMM_X64_SEG_GS			4
     41  1.1  maxv #define NVMM_X64_SEG_SS			5
     42  1.1  maxv #define NVMM_X64_SEG_GDT		6
     43  1.1  maxv #define NVMM_X64_SEG_IDT		7
     44  1.1  maxv #define NVMM_X64_SEG_LDT		8
     45  1.1  maxv #define NVMM_X64_SEG_TR			9
     46  1.1  maxv #define NVMM_X64_NSEG			10
     47  1.1  maxv 
     48  1.1  maxv /* General Purpose Registers. */
     49  1.1  maxv #define NVMM_X64_GPR_RAX		0
     50  1.1  maxv #define NVMM_X64_GPR_RBX		1
     51  1.1  maxv #define NVMM_X64_GPR_RCX		2
     52  1.1  maxv #define NVMM_X64_GPR_RDX		3
     53  1.1  maxv #define NVMM_X64_GPR_R8			4
     54  1.1  maxv #define NVMM_X64_GPR_R9			5
     55  1.1  maxv #define NVMM_X64_GPR_R10		6
     56  1.1  maxv #define NVMM_X64_GPR_R11		7
     57  1.1  maxv #define NVMM_X64_GPR_R12		8
     58  1.1  maxv #define NVMM_X64_GPR_R13		9
     59  1.1  maxv #define NVMM_X64_GPR_R14		10
     60  1.1  maxv #define NVMM_X64_GPR_R15		11
     61  1.1  maxv #define NVMM_X64_GPR_RDI		12
     62  1.1  maxv #define NVMM_X64_GPR_RSI		13
     63  1.1  maxv #define NVMM_X64_GPR_RBP		14
     64  1.1  maxv #define NVMM_X64_GPR_RSP		15
     65  1.1  maxv #define NVMM_X64_GPR_RIP		16
     66  1.1  maxv #define NVMM_X64_GPR_RFLAGS		17
     67  1.1  maxv #define NVMM_X64_NGPR			18
     68  1.1  maxv 
     69  1.1  maxv /* Control Registers. */
     70  1.1  maxv #define NVMM_X64_CR_CR0			0
     71  1.1  maxv #define NVMM_X64_CR_CR2			1
     72  1.1  maxv #define NVMM_X64_CR_CR3			2
     73  1.1  maxv #define NVMM_X64_CR_CR4			3
     74  1.1  maxv #define NVMM_X64_CR_CR8			4
     75  1.1  maxv #define NVMM_X64_CR_XCR0		5
     76  1.1  maxv #define NVMM_X64_NCR			6
     77  1.1  maxv 
     78  1.1  maxv /* Debug Registers. */
     79  1.1  maxv #define NVMM_X64_DR_DR0			0
     80  1.1  maxv #define NVMM_X64_DR_DR1			1
     81  1.1  maxv #define NVMM_X64_DR_DR2			2
     82  1.1  maxv #define NVMM_X64_DR_DR3			3
     83  1.1  maxv #define NVMM_X64_DR_DR6			4
     84  1.1  maxv #define NVMM_X64_DR_DR7			5
     85  1.1  maxv #define NVMM_X64_NDR			6
     86  1.1  maxv 
     87  1.1  maxv /* MSRs. */
     88  1.1  maxv #define NVMM_X64_MSR_EFER		0
     89  1.1  maxv #define NVMM_X64_MSR_STAR		1
     90  1.1  maxv #define NVMM_X64_MSR_LSTAR		2
     91  1.1  maxv #define NVMM_X64_MSR_CSTAR		3
     92  1.1  maxv #define NVMM_X64_MSR_SFMASK		4
     93  1.1  maxv #define NVMM_X64_MSR_KERNELGSBASE	5
     94  1.1  maxv #define NVMM_X64_MSR_SYSENTER_CS	6
     95  1.1  maxv #define NVMM_X64_MSR_SYSENTER_ESP	7
     96  1.1  maxv #define NVMM_X64_MSR_SYSENTER_EIP	8
     97  1.1  maxv #define NVMM_X64_MSR_PAT		9
     98  1.1  maxv #define NVMM_X64_NMSR			10
     99  1.1  maxv 
    100  1.1  maxv /* Misc. */
    101  1.1  maxv #define NVMM_X64_MISC_CPL		0
    102  1.1  maxv #define NVMM_X64_NMISC			1
    103  1.1  maxv 
    104  1.1  maxv #ifndef ASM_NVMM
    105  1.1  maxv 
    106  1.1  maxv #include <sys/types.h>
    107  1.1  maxv #include <x86/cpu_extended_state.h>
    108  1.1  maxv 
    109  1.1  maxv struct nvmm_x64_state_seg {
    110  1.1  maxv 	uint64_t selector;
    111  1.1  maxv 	struct {		/* hidden */
    112  1.1  maxv 		uint64_t type:5;
    113  1.1  maxv 		uint64_t dpl:2;
    114  1.1  maxv 		uint64_t p:1;
    115  1.1  maxv 		uint64_t avl:1;
    116  1.1  maxv 		uint64_t lng:1;
    117  1.1  maxv 		uint64_t def32:1;
    118  1.1  maxv 		uint64_t gran:1;
    119  1.1  maxv 		uint64_t rsvd:52;
    120  1.1  maxv 	} attrib;
    121  1.1  maxv 	uint64_t limit;		/* hidden */
    122  1.1  maxv 	uint64_t base;		/* hidden */
    123  1.1  maxv };
    124  1.1  maxv 
    125  1.1  maxv /* VM exit state indexes. */
    126  1.1  maxv #define NVMM_X64_EXITSTATE_CR8	0
    127  1.1  maxv 
    128  1.1  maxv /* Flags. */
    129  1.1  maxv #define NVMM_X64_STATE_SEGS	0x01
    130  1.1  maxv #define NVMM_X64_STATE_GPRS	0x02
    131  1.1  maxv #define NVMM_X64_STATE_CRS	0x04
    132  1.1  maxv #define NVMM_X64_STATE_DRS	0x08
    133  1.1  maxv #define NVMM_X64_STATE_MSRS	0x10
    134  1.1  maxv #define NVMM_X64_STATE_MISC	0x20
    135  1.1  maxv #define NVMM_X64_STATE_FPU	0x40
    136  1.1  maxv #define NVMM_X64_STATE_ALL	\
    137  1.1  maxv 	(NVMM_X64_STATE_SEGS | NVMM_X64_STATE_GPRS | NVMM_X64_STATE_CRS | \
    138  1.1  maxv 	 NVMM_X64_STATE_DRS | NVMM_X64_STATE_MSRS | NVMM_X64_STATE_MISC | \
    139  1.1  maxv 	 NVMM_X64_STATE_FPU)
    140  1.1  maxv 
    141  1.1  maxv struct nvmm_x64_state {
    142  1.1  maxv 	struct nvmm_x64_state_seg segs[NVMM_X64_NSEG];
    143  1.1  maxv 	uint64_t gprs[NVMM_X64_NGPR];
    144  1.1  maxv 	uint64_t crs[NVMM_X64_NCR];
    145  1.1  maxv 	uint64_t drs[NVMM_X64_NDR];
    146  1.1  maxv 	uint64_t msrs[NVMM_X64_NMSR];
    147  1.1  maxv 	uint64_t misc[NVMM_X64_NMISC];
    148  1.1  maxv 	struct fxsave fpu;
    149  1.1  maxv };
    150  1.1  maxv 
    151  1.1  maxv #define NVMM_X86_CONF_CPUID	0
    152  1.1  maxv #define NVMM_X86_NCONF		1
    153  1.1  maxv 
    154  1.1  maxv struct nvmm_x86_conf_cpuid {
    155  1.1  maxv 	uint32_t leaf;
    156  1.1  maxv 	struct {
    157  1.1  maxv 		uint32_t eax;
    158  1.1  maxv 		uint32_t ebx;
    159  1.1  maxv 		uint32_t ecx;
    160  1.1  maxv 		uint32_t edx;
    161  1.1  maxv 	} set;
    162  1.1  maxv 	struct {
    163  1.1  maxv 		uint32_t eax;
    164  1.1  maxv 		uint32_t ebx;
    165  1.1  maxv 		uint32_t ecx;
    166  1.1  maxv 		uint32_t edx;
    167  1.1  maxv 	} del;
    168  1.1  maxv };
    169  1.1  maxv 
    170  1.1  maxv #endif /* ASM_NVMM */
    171  1.1  maxv 
    172  1.1  maxv #endif /* _NVMM_X86_H_ */
    173