nvmm_x86.h revision 1.20 1 1.20 maxv /* $NetBSD: nvmm_x86.h,v 1.20 2020/09/05 07:22:26 maxv Exp $ */
2 1.1 maxv
3 1.1 maxv /*
4 1.20 maxv * Copyright (c) 2018-2020 Maxime Villard, m00nbsd.net
5 1.1 maxv * All rights reserved.
6 1.1 maxv *
7 1.20 maxv * This code is part of the NVMM hypervisor.
8 1.1 maxv *
9 1.1 maxv * Redistribution and use in source and binary forms, with or without
10 1.1 maxv * modification, are permitted provided that the following conditions
11 1.1 maxv * are met:
12 1.1 maxv * 1. Redistributions of source code must retain the above copyright
13 1.1 maxv * notice, this list of conditions and the following disclaimer.
14 1.1 maxv * 2. Redistributions in binary form must reproduce the above copyright
15 1.1 maxv * notice, this list of conditions and the following disclaimer in the
16 1.1 maxv * documentation and/or other materials provided with the distribution.
17 1.1 maxv *
18 1.20 maxv * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 1.20 maxv * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 1.20 maxv * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 1.20 maxv * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 1.20 maxv * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
23 1.20 maxv * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
24 1.20 maxv * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
25 1.20 maxv * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
26 1.20 maxv * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 1.20 maxv * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 1.20 maxv * SUCH DAMAGE.
29 1.1 maxv */
30 1.1 maxv
31 1.1 maxv #ifndef _NVMM_X86_H_
32 1.1 maxv #define _NVMM_X86_H_
33 1.1 maxv
34 1.16 maxv /* -------------------------------------------------------------------------- */
35 1.12 maxv
36 1.12 maxv #ifndef ASM_NVMM
37 1.12 maxv
38 1.16 maxv struct nvmm_x86_exit_memory {
39 1.12 maxv int prot;
40 1.12 maxv gpaddr_t gpa;
41 1.12 maxv uint8_t inst_len;
42 1.12 maxv uint8_t inst_bytes[15];
43 1.12 maxv };
44 1.12 maxv
45 1.16 maxv struct nvmm_x86_exit_io {
46 1.16 maxv bool in;
47 1.12 maxv uint16_t port;
48 1.16 maxv int8_t seg;
49 1.12 maxv uint8_t address_size;
50 1.12 maxv uint8_t operand_size;
51 1.12 maxv bool rep;
52 1.12 maxv bool str;
53 1.12 maxv uint64_t npc;
54 1.12 maxv };
55 1.12 maxv
56 1.16 maxv struct nvmm_x86_exit_rdmsr {
57 1.16 maxv uint32_t msr;
58 1.16 maxv uint64_t npc;
59 1.12 maxv };
60 1.12 maxv
61 1.16 maxv struct nvmm_x86_exit_wrmsr {
62 1.16 maxv uint32_t msr;
63 1.12 maxv uint64_t val;
64 1.12 maxv uint64_t npc;
65 1.12 maxv };
66 1.12 maxv
67 1.16 maxv struct nvmm_x86_exit_insn {
68 1.12 maxv uint64_t npc;
69 1.12 maxv };
70 1.12 maxv
71 1.16 maxv struct nvmm_x86_exit_invalid {
72 1.12 maxv uint64_t hwcode;
73 1.12 maxv };
74 1.12 maxv
75 1.16 maxv /* Generic. */
76 1.16 maxv #define NVMM_VCPU_EXIT_NONE 0x0000000000000000ULL
77 1.16 maxv #define NVMM_VCPU_EXIT_INVALID 0xFFFFFFFFFFFFFFFFULL
78 1.16 maxv /* x86: operations. */
79 1.16 maxv #define NVMM_VCPU_EXIT_MEMORY 0x0000000000000001ULL
80 1.16 maxv #define NVMM_VCPU_EXIT_IO 0x0000000000000002ULL
81 1.16 maxv /* x86: changes in VCPU state. */
82 1.16 maxv #define NVMM_VCPU_EXIT_SHUTDOWN 0x0000000000001000ULL
83 1.16 maxv #define NVMM_VCPU_EXIT_INT_READY 0x0000000000001001ULL
84 1.16 maxv #define NVMM_VCPU_EXIT_NMI_READY 0x0000000000001002ULL
85 1.16 maxv #define NVMM_VCPU_EXIT_HALTED 0x0000000000001003ULL
86 1.17 maxv #define NVMM_VCPU_EXIT_TPR_CHANGED 0x0000000000001004ULL
87 1.16 maxv /* x86: instructions. */
88 1.16 maxv #define NVMM_VCPU_EXIT_RDMSR 0x0000000000002000ULL
89 1.16 maxv #define NVMM_VCPU_EXIT_WRMSR 0x0000000000002001ULL
90 1.16 maxv #define NVMM_VCPU_EXIT_MONITOR 0x0000000000002002ULL
91 1.16 maxv #define NVMM_VCPU_EXIT_MWAIT 0x0000000000002003ULL
92 1.16 maxv #define NVMM_VCPU_EXIT_CPUID 0x0000000000002004ULL
93 1.16 maxv
94 1.16 maxv struct nvmm_x86_exit {
95 1.16 maxv uint64_t reason;
96 1.16 maxv union {
97 1.16 maxv struct nvmm_x86_exit_memory mem;
98 1.16 maxv struct nvmm_x86_exit_io io;
99 1.16 maxv struct nvmm_x86_exit_rdmsr rdmsr;
100 1.16 maxv struct nvmm_x86_exit_wrmsr wrmsr;
101 1.16 maxv struct nvmm_x86_exit_insn insn;
102 1.16 maxv struct nvmm_x86_exit_invalid inv;
103 1.16 maxv } u;
104 1.18 maxv struct {
105 1.18 maxv uint64_t rflags;
106 1.18 maxv uint64_t cr8;
107 1.18 maxv uint64_t int_shadow:1;
108 1.18 maxv uint64_t int_window_exiting:1;
109 1.18 maxv uint64_t nmi_window_exiting:1;
110 1.18 maxv uint64_t evt_pending:1;
111 1.18 maxv uint64_t rsvd:60;
112 1.18 maxv } exitstate;
113 1.16 maxv };
114 1.16 maxv
115 1.16 maxv #define NVMM_VCPU_EVENT_EXCP 0
116 1.16 maxv #define NVMM_VCPU_EVENT_INTR 1
117 1.16 maxv
118 1.16 maxv struct nvmm_x86_event {
119 1.16 maxv u_int type;
120 1.16 maxv uint8_t vector;
121 1.16 maxv union {
122 1.16 maxv struct {
123 1.16 maxv uint64_t error;
124 1.16 maxv } excp;
125 1.16 maxv } u;
126 1.12 maxv };
127 1.12 maxv
128 1.12 maxv struct nvmm_cap_md {
129 1.17 maxv uint64_t mach_conf_support;
130 1.17 maxv
131 1.17 maxv uint64_t vcpu_conf_support;
132 1.17 maxv #define NVMM_CAP_ARCH_VCPU_CONF_CPUID __BIT(0)
133 1.17 maxv #define NVMM_CAP_ARCH_VCPU_CONF_TPR __BIT(1)
134 1.17 maxv
135 1.12 maxv uint64_t xcr0_mask;
136 1.16 maxv uint32_t mxcsr_mask;
137 1.16 maxv uint32_t conf_cpuid_maxops;
138 1.18 maxv uint64_t rsvd[6];
139 1.12 maxv };
140 1.12 maxv
141 1.12 maxv #endif
142 1.12 maxv
143 1.16 maxv /* -------------------------------------------------------------------------- */
144 1.16 maxv
145 1.16 maxv /*
146 1.16 maxv * Segment state indexes. We use X64 as naming convention, not to confuse with
147 1.16 maxv * X86 which originally implied 32bit.
148 1.16 maxv */
149 1.12 maxv
150 1.1 maxv /* Segments. */
151 1.7 maxv #define NVMM_X64_SEG_ES 0
152 1.7 maxv #define NVMM_X64_SEG_CS 1
153 1.7 maxv #define NVMM_X64_SEG_SS 2
154 1.7 maxv #define NVMM_X64_SEG_DS 3
155 1.7 maxv #define NVMM_X64_SEG_FS 4
156 1.7 maxv #define NVMM_X64_SEG_GS 5
157 1.1 maxv #define NVMM_X64_SEG_GDT 6
158 1.1 maxv #define NVMM_X64_SEG_IDT 7
159 1.1 maxv #define NVMM_X64_SEG_LDT 8
160 1.1 maxv #define NVMM_X64_SEG_TR 9
161 1.1 maxv #define NVMM_X64_NSEG 10
162 1.1 maxv
163 1.1 maxv /* General Purpose Registers. */
164 1.1 maxv #define NVMM_X64_GPR_RAX 0
165 1.4 maxv #define NVMM_X64_GPR_RCX 1
166 1.4 maxv #define NVMM_X64_GPR_RDX 2
167 1.4 maxv #define NVMM_X64_GPR_RBX 3
168 1.4 maxv #define NVMM_X64_GPR_RSP 4
169 1.4 maxv #define NVMM_X64_GPR_RBP 5
170 1.4 maxv #define NVMM_X64_GPR_RSI 6
171 1.4 maxv #define NVMM_X64_GPR_RDI 7
172 1.4 maxv #define NVMM_X64_GPR_R8 8
173 1.4 maxv #define NVMM_X64_GPR_R9 9
174 1.4 maxv #define NVMM_X64_GPR_R10 10
175 1.4 maxv #define NVMM_X64_GPR_R11 11
176 1.4 maxv #define NVMM_X64_GPR_R12 12
177 1.4 maxv #define NVMM_X64_GPR_R13 13
178 1.4 maxv #define NVMM_X64_GPR_R14 14
179 1.4 maxv #define NVMM_X64_GPR_R15 15
180 1.1 maxv #define NVMM_X64_GPR_RIP 16
181 1.1 maxv #define NVMM_X64_GPR_RFLAGS 17
182 1.1 maxv #define NVMM_X64_NGPR 18
183 1.1 maxv
184 1.1 maxv /* Control Registers. */
185 1.1 maxv #define NVMM_X64_CR_CR0 0
186 1.1 maxv #define NVMM_X64_CR_CR2 1
187 1.1 maxv #define NVMM_X64_CR_CR3 2
188 1.1 maxv #define NVMM_X64_CR_CR4 3
189 1.1 maxv #define NVMM_X64_CR_CR8 4
190 1.1 maxv #define NVMM_X64_CR_XCR0 5
191 1.1 maxv #define NVMM_X64_NCR 6
192 1.1 maxv
193 1.1 maxv /* Debug Registers. */
194 1.1 maxv #define NVMM_X64_DR_DR0 0
195 1.1 maxv #define NVMM_X64_DR_DR1 1
196 1.1 maxv #define NVMM_X64_DR_DR2 2
197 1.1 maxv #define NVMM_X64_DR_DR3 3
198 1.1 maxv #define NVMM_X64_DR_DR6 4
199 1.1 maxv #define NVMM_X64_DR_DR7 5
200 1.1 maxv #define NVMM_X64_NDR 6
201 1.1 maxv
202 1.1 maxv /* MSRs. */
203 1.1 maxv #define NVMM_X64_MSR_EFER 0
204 1.1 maxv #define NVMM_X64_MSR_STAR 1
205 1.1 maxv #define NVMM_X64_MSR_LSTAR 2
206 1.1 maxv #define NVMM_X64_MSR_CSTAR 3
207 1.1 maxv #define NVMM_X64_MSR_SFMASK 4
208 1.1 maxv #define NVMM_X64_MSR_KERNELGSBASE 5
209 1.1 maxv #define NVMM_X64_MSR_SYSENTER_CS 6
210 1.1 maxv #define NVMM_X64_MSR_SYSENTER_ESP 7
211 1.1 maxv #define NVMM_X64_MSR_SYSENTER_EIP 8
212 1.1 maxv #define NVMM_X64_MSR_PAT 9
213 1.9 maxv #define NVMM_X64_MSR_TSC 10
214 1.9 maxv #define NVMM_X64_NMSR 11
215 1.1 maxv
216 1.1 maxv #ifndef ASM_NVMM
217 1.1 maxv
218 1.1 maxv #include <sys/types.h>
219 1.1 maxv #include <x86/cpu_extended_state.h>
220 1.1 maxv
221 1.1 maxv struct nvmm_x64_state_seg {
222 1.7 maxv uint16_t selector;
223 1.1 maxv struct { /* hidden */
224 1.7 maxv uint16_t type:4;
225 1.7 maxv uint16_t s:1;
226 1.7 maxv uint16_t dpl:2;
227 1.7 maxv uint16_t p:1;
228 1.7 maxv uint16_t avl:1;
229 1.7 maxv uint16_t l:1;
230 1.7 maxv uint16_t def:1;
231 1.7 maxv uint16_t g:1;
232 1.7 maxv uint16_t rsvd:4;
233 1.1 maxv } attrib;
234 1.7 maxv uint32_t limit; /* hidden */
235 1.1 maxv uint64_t base; /* hidden */
236 1.1 maxv };
237 1.1 maxv
238 1.11 maxv struct nvmm_x64_state_intr {
239 1.11 maxv uint64_t int_shadow:1;
240 1.11 maxv uint64_t int_window_exiting:1;
241 1.11 maxv uint64_t nmi_window_exiting:1;
242 1.11 maxv uint64_t evt_pending:1;
243 1.11 maxv uint64_t rsvd:60;
244 1.11 maxv };
245 1.11 maxv
246 1.1 maxv /* Flags. */
247 1.1 maxv #define NVMM_X64_STATE_SEGS 0x01
248 1.1 maxv #define NVMM_X64_STATE_GPRS 0x02
249 1.1 maxv #define NVMM_X64_STATE_CRS 0x04
250 1.1 maxv #define NVMM_X64_STATE_DRS 0x08
251 1.1 maxv #define NVMM_X64_STATE_MSRS 0x10
252 1.11 maxv #define NVMM_X64_STATE_INTR 0x20
253 1.1 maxv #define NVMM_X64_STATE_FPU 0x40
254 1.1 maxv #define NVMM_X64_STATE_ALL \
255 1.1 maxv (NVMM_X64_STATE_SEGS | NVMM_X64_STATE_GPRS | NVMM_X64_STATE_CRS | \
256 1.11 maxv NVMM_X64_STATE_DRS | NVMM_X64_STATE_MSRS | NVMM_X64_STATE_INTR | \
257 1.1 maxv NVMM_X64_STATE_FPU)
258 1.1 maxv
259 1.1 maxv struct nvmm_x64_state {
260 1.1 maxv struct nvmm_x64_state_seg segs[NVMM_X64_NSEG];
261 1.1 maxv uint64_t gprs[NVMM_X64_NGPR];
262 1.1 maxv uint64_t crs[NVMM_X64_NCR];
263 1.1 maxv uint64_t drs[NVMM_X64_NDR];
264 1.1 maxv uint64_t msrs[NVMM_X64_NMSR];
265 1.11 maxv struct nvmm_x64_state_intr intr;
266 1.1 maxv struct fxsave fpu;
267 1.1 maxv };
268 1.1 maxv
269 1.16 maxv #define NVMM_VCPU_CONF_CPUID NVMM_VCPU_CONF_MD_BEGIN
270 1.17 maxv #define NVMM_VCPU_CONF_TPR (NVMM_VCPU_CONF_MD_BEGIN + 1)
271 1.14 maxv
272 1.16 maxv struct nvmm_vcpu_conf_cpuid {
273 1.16 maxv /* The options. */
274 1.16 maxv uint32_t mask:1;
275 1.16 maxv uint32_t exit:1;
276 1.16 maxv uint32_t rsvd:30;
277 1.1 maxv
278 1.16 maxv /* The leaf. */
279 1.1 maxv uint32_t leaf;
280 1.16 maxv
281 1.16 maxv /* The params. */
282 1.16 maxv union {
283 1.16 maxv struct {
284 1.16 maxv struct {
285 1.16 maxv uint32_t eax;
286 1.16 maxv uint32_t ebx;
287 1.16 maxv uint32_t ecx;
288 1.16 maxv uint32_t edx;
289 1.16 maxv } set;
290 1.16 maxv struct {
291 1.16 maxv uint32_t eax;
292 1.16 maxv uint32_t ebx;
293 1.16 maxv uint32_t ecx;
294 1.16 maxv uint32_t edx;
295 1.16 maxv } del;
296 1.16 maxv } mask;
297 1.16 maxv } u;
298 1.16 maxv };
299 1.16 maxv
300 1.17 maxv struct nvmm_vcpu_conf_tpr {
301 1.17 maxv uint32_t exit_changed:1;
302 1.17 maxv uint32_t rsvd:31;
303 1.17 maxv };
304 1.17 maxv
305 1.16 maxv #define nvmm_vcpu_exit nvmm_x86_exit
306 1.16 maxv #define nvmm_vcpu_event nvmm_x86_event
307 1.16 maxv #define nvmm_vcpu_state nvmm_x64_state
308 1.1 maxv
309 1.6 maxv #ifdef _KERNEL
310 1.16 maxv #define NVMM_X86_MACH_NCONF 0
311 1.17 maxv #define NVMM_X86_VCPU_NCONF 2
312 1.8 maxv struct nvmm_x86_cpuid_mask {
313 1.8 maxv uint32_t eax;
314 1.8 maxv uint32_t ebx;
315 1.8 maxv uint32_t ecx;
316 1.8 maxv uint32_t edx;
317 1.8 maxv };
318 1.6 maxv extern const struct nvmm_x64_state nvmm_x86_reset_state;
319 1.8 maxv extern const struct nvmm_x86_cpuid_mask nvmm_cpuid_00000001;
320 1.8 maxv extern const struct nvmm_x86_cpuid_mask nvmm_cpuid_00000007;
321 1.8 maxv extern const struct nvmm_x86_cpuid_mask nvmm_cpuid_80000001;
322 1.19 maxv extern const struct nvmm_x86_cpuid_mask nvmm_cpuid_80000007;
323 1.19 maxv extern const struct nvmm_x86_cpuid_mask nvmm_cpuid_80000008;
324 1.10 maxv bool nvmm_x86_pat_validate(uint64_t);
325 1.6 maxv #endif
326 1.6 maxv
327 1.1 maxv #endif /* ASM_NVMM */
328 1.1 maxv
329 1.1 maxv #endif /* _NVMM_X86_H_ */
330