nvmm_x86.h revision 1.1
1 /* $NetBSD: nvmm_x86.h,v 1.1 2018/11/07 07:43:08 maxv Exp $ */ 2 3 /* 4 * Copyright (c) 2018 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Maxime Villard. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _NVMM_X86_H_ 33 #define _NVMM_X86_H_ 34 35 /* Segments. */ 36 #define NVMM_X64_SEG_CS 0 37 #define NVMM_X64_SEG_DS 1 38 #define NVMM_X64_SEG_ES 2 39 #define NVMM_X64_SEG_FS 3 40 #define NVMM_X64_SEG_GS 4 41 #define NVMM_X64_SEG_SS 5 42 #define NVMM_X64_SEG_GDT 6 43 #define NVMM_X64_SEG_IDT 7 44 #define NVMM_X64_SEG_LDT 8 45 #define NVMM_X64_SEG_TR 9 46 #define NVMM_X64_NSEG 10 47 48 /* General Purpose Registers. */ 49 #define NVMM_X64_GPR_RAX 0 50 #define NVMM_X64_GPR_RBX 1 51 #define NVMM_X64_GPR_RCX 2 52 #define NVMM_X64_GPR_RDX 3 53 #define NVMM_X64_GPR_R8 4 54 #define NVMM_X64_GPR_R9 5 55 #define NVMM_X64_GPR_R10 6 56 #define NVMM_X64_GPR_R11 7 57 #define NVMM_X64_GPR_R12 8 58 #define NVMM_X64_GPR_R13 9 59 #define NVMM_X64_GPR_R14 10 60 #define NVMM_X64_GPR_R15 11 61 #define NVMM_X64_GPR_RDI 12 62 #define NVMM_X64_GPR_RSI 13 63 #define NVMM_X64_GPR_RBP 14 64 #define NVMM_X64_GPR_RSP 15 65 #define NVMM_X64_GPR_RIP 16 66 #define NVMM_X64_GPR_RFLAGS 17 67 #define NVMM_X64_NGPR 18 68 69 /* Control Registers. */ 70 #define NVMM_X64_CR_CR0 0 71 #define NVMM_X64_CR_CR2 1 72 #define NVMM_X64_CR_CR3 2 73 #define NVMM_X64_CR_CR4 3 74 #define NVMM_X64_CR_CR8 4 75 #define NVMM_X64_CR_XCR0 5 76 #define NVMM_X64_NCR 6 77 78 /* Debug Registers. */ 79 #define NVMM_X64_DR_DR0 0 80 #define NVMM_X64_DR_DR1 1 81 #define NVMM_X64_DR_DR2 2 82 #define NVMM_X64_DR_DR3 3 83 #define NVMM_X64_DR_DR6 4 84 #define NVMM_X64_DR_DR7 5 85 #define NVMM_X64_NDR 6 86 87 /* MSRs. */ 88 #define NVMM_X64_MSR_EFER 0 89 #define NVMM_X64_MSR_STAR 1 90 #define NVMM_X64_MSR_LSTAR 2 91 #define NVMM_X64_MSR_CSTAR 3 92 #define NVMM_X64_MSR_SFMASK 4 93 #define NVMM_X64_MSR_KERNELGSBASE 5 94 #define NVMM_X64_MSR_SYSENTER_CS 6 95 #define NVMM_X64_MSR_SYSENTER_ESP 7 96 #define NVMM_X64_MSR_SYSENTER_EIP 8 97 #define NVMM_X64_MSR_PAT 9 98 #define NVMM_X64_NMSR 10 99 100 /* Misc. */ 101 #define NVMM_X64_MISC_CPL 0 102 #define NVMM_X64_NMISC 1 103 104 #ifndef ASM_NVMM 105 106 #include <sys/types.h> 107 #include <x86/cpu_extended_state.h> 108 109 struct nvmm_x64_state_seg { 110 uint64_t selector; 111 struct { /* hidden */ 112 uint64_t type:5; 113 uint64_t dpl:2; 114 uint64_t p:1; 115 uint64_t avl:1; 116 uint64_t lng:1; 117 uint64_t def32:1; 118 uint64_t gran:1; 119 uint64_t rsvd:52; 120 } attrib; 121 uint64_t limit; /* hidden */ 122 uint64_t base; /* hidden */ 123 }; 124 125 /* VM exit state indexes. */ 126 #define NVMM_X64_EXITSTATE_CR8 0 127 128 /* Flags. */ 129 #define NVMM_X64_STATE_SEGS 0x01 130 #define NVMM_X64_STATE_GPRS 0x02 131 #define NVMM_X64_STATE_CRS 0x04 132 #define NVMM_X64_STATE_DRS 0x08 133 #define NVMM_X64_STATE_MSRS 0x10 134 #define NVMM_X64_STATE_MISC 0x20 135 #define NVMM_X64_STATE_FPU 0x40 136 #define NVMM_X64_STATE_ALL \ 137 (NVMM_X64_STATE_SEGS | NVMM_X64_STATE_GPRS | NVMM_X64_STATE_CRS | \ 138 NVMM_X64_STATE_DRS | NVMM_X64_STATE_MSRS | NVMM_X64_STATE_MISC | \ 139 NVMM_X64_STATE_FPU) 140 141 struct nvmm_x64_state { 142 struct nvmm_x64_state_seg segs[NVMM_X64_NSEG]; 143 uint64_t gprs[NVMM_X64_NGPR]; 144 uint64_t crs[NVMM_X64_NCR]; 145 uint64_t drs[NVMM_X64_NDR]; 146 uint64_t msrs[NVMM_X64_NMSR]; 147 uint64_t misc[NVMM_X64_NMISC]; 148 struct fxsave fpu; 149 }; 150 151 #define NVMM_X86_CONF_CPUID 0 152 #define NVMM_X86_NCONF 1 153 154 struct nvmm_x86_conf_cpuid { 155 uint32_t leaf; 156 struct { 157 uint32_t eax; 158 uint32_t ebx; 159 uint32_t ecx; 160 uint32_t edx; 161 } set; 162 struct { 163 uint32_t eax; 164 uint32_t ebx; 165 uint32_t ecx; 166 uint32_t edx; 167 } del; 168 }; 169 170 #endif /* ASM_NVMM */ 171 172 #endif /* _NVMM_X86_H_ */ 173
Indexes created Wed Oct 01 19:09:53 GMT 2025