nvmm_x86.h revision 1.11
1 /* $NetBSD: nvmm_x86.h,v 1.11 2019/04/06 11:49:53 maxv Exp $ */ 2 3 /* 4 * Copyright (c) 2018 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Maxime Villard. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _NVMM_X86_H_ 33 #define _NVMM_X86_H_ 34 35 /* Segments. */ 36 #define NVMM_X64_SEG_ES 0 37 #define NVMM_X64_SEG_CS 1 38 #define NVMM_X64_SEG_SS 2 39 #define NVMM_X64_SEG_DS 3 40 #define NVMM_X64_SEG_FS 4 41 #define NVMM_X64_SEG_GS 5 42 #define NVMM_X64_SEG_GDT 6 43 #define NVMM_X64_SEG_IDT 7 44 #define NVMM_X64_SEG_LDT 8 45 #define NVMM_X64_SEG_TR 9 46 #define NVMM_X64_NSEG 10 47 48 /* General Purpose Registers. */ 49 #define NVMM_X64_GPR_RAX 0 50 #define NVMM_X64_GPR_RCX 1 51 #define NVMM_X64_GPR_RDX 2 52 #define NVMM_X64_GPR_RBX 3 53 #define NVMM_X64_GPR_RSP 4 54 #define NVMM_X64_GPR_RBP 5 55 #define NVMM_X64_GPR_RSI 6 56 #define NVMM_X64_GPR_RDI 7 57 #define NVMM_X64_GPR_R8 8 58 #define NVMM_X64_GPR_R9 9 59 #define NVMM_X64_GPR_R10 10 60 #define NVMM_X64_GPR_R11 11 61 #define NVMM_X64_GPR_R12 12 62 #define NVMM_X64_GPR_R13 13 63 #define NVMM_X64_GPR_R14 14 64 #define NVMM_X64_GPR_R15 15 65 #define NVMM_X64_GPR_RIP 16 66 #define NVMM_X64_GPR_RFLAGS 17 67 #define NVMM_X64_NGPR 18 68 69 /* Control Registers. */ 70 #define NVMM_X64_CR_CR0 0 71 #define NVMM_X64_CR_CR2 1 72 #define NVMM_X64_CR_CR3 2 73 #define NVMM_X64_CR_CR4 3 74 #define NVMM_X64_CR_CR8 4 75 #define NVMM_X64_CR_XCR0 5 76 #define NVMM_X64_NCR 6 77 78 /* Debug Registers. */ 79 #define NVMM_X64_DR_DR0 0 80 #define NVMM_X64_DR_DR1 1 81 #define NVMM_X64_DR_DR2 2 82 #define NVMM_X64_DR_DR3 3 83 #define NVMM_X64_DR_DR6 4 84 #define NVMM_X64_DR_DR7 5 85 #define NVMM_X64_NDR 6 86 87 /* MSRs. */ 88 #define NVMM_X64_MSR_EFER 0 89 #define NVMM_X64_MSR_STAR 1 90 #define NVMM_X64_MSR_LSTAR 2 91 #define NVMM_X64_MSR_CSTAR 3 92 #define NVMM_X64_MSR_SFMASK 4 93 #define NVMM_X64_MSR_KERNELGSBASE 5 94 #define NVMM_X64_MSR_SYSENTER_CS 6 95 #define NVMM_X64_MSR_SYSENTER_ESP 7 96 #define NVMM_X64_MSR_SYSENTER_EIP 8 97 #define NVMM_X64_MSR_PAT 9 98 #define NVMM_X64_MSR_TSC 10 99 #define NVMM_X64_NMSR 11 100 101 #ifndef ASM_NVMM 102 103 #include <sys/types.h> 104 #include <x86/cpu_extended_state.h> 105 106 struct nvmm_x64_state_seg { 107 uint16_t selector; 108 struct { /* hidden */ 109 uint16_t type:4; 110 uint16_t s:1; 111 uint16_t dpl:2; 112 uint16_t p:1; 113 uint16_t avl:1; 114 uint16_t l:1; 115 uint16_t def:1; 116 uint16_t g:1; 117 uint16_t rsvd:4; 118 } attrib; 119 uint32_t limit; /* hidden */ 120 uint64_t base; /* hidden */ 121 }; 122 123 struct nvmm_x64_state_intr { 124 uint64_t int_shadow:1; 125 uint64_t int_window_exiting:1; 126 uint64_t nmi_window_exiting:1; 127 uint64_t evt_pending:1; 128 uint64_t rsvd:60; 129 }; 130 131 /* VM exit state indexes. */ 132 #define NVMM_X64_EXITSTATE_CR8 0 133 #define NVMM_X64_EXITSTATE_RFLAGS 1 134 #define NVMM_X64_EXITSTATE_INT_SHADOW 2 135 #define NVMM_X64_EXITSTATE_INT_WINDOW_EXIT 3 136 #define NVMM_X64_EXITSTATE_NMI_WINDOW_EXIT 4 137 #define NVMM_X64_EXITSTATE_EVT_PENDING 5 138 139 /* Flags. */ 140 #define NVMM_X64_STATE_SEGS 0x01 141 #define NVMM_X64_STATE_GPRS 0x02 142 #define NVMM_X64_STATE_CRS 0x04 143 #define NVMM_X64_STATE_DRS 0x08 144 #define NVMM_X64_STATE_MSRS 0x10 145 #define NVMM_X64_STATE_INTR 0x20 146 #define NVMM_X64_STATE_FPU 0x40 147 #define NVMM_X64_STATE_ALL \ 148 (NVMM_X64_STATE_SEGS | NVMM_X64_STATE_GPRS | NVMM_X64_STATE_CRS | \ 149 NVMM_X64_STATE_DRS | NVMM_X64_STATE_MSRS | NVMM_X64_STATE_INTR | \ 150 NVMM_X64_STATE_FPU) 151 152 struct nvmm_x64_state { 153 struct nvmm_x64_state_seg segs[NVMM_X64_NSEG]; 154 uint64_t gprs[NVMM_X64_NGPR]; 155 uint64_t crs[NVMM_X64_NCR]; 156 uint64_t drs[NVMM_X64_NDR]; 157 uint64_t msrs[NVMM_X64_NMSR]; 158 struct nvmm_x64_state_intr intr; 159 struct fxsave fpu; 160 }; 161 162 #define NVMM_X86_CONF_CPUID 0 163 #define NVMM_X86_NCONF 1 164 165 struct nvmm_x86_conf_cpuid { 166 uint32_t leaf; 167 struct { 168 uint32_t eax; 169 uint32_t ebx; 170 uint32_t ecx; 171 uint32_t edx; 172 } set; 173 struct { 174 uint32_t eax; 175 uint32_t ebx; 176 uint32_t ecx; 177 uint32_t edx; 178 } del; 179 }; 180 181 #ifdef _KERNEL 182 struct nvmm_x86_cpuid_mask { 183 uint32_t eax; 184 uint32_t ebx; 185 uint32_t ecx; 186 uint32_t edx; 187 }; 188 extern const struct nvmm_x64_state nvmm_x86_reset_state; 189 extern const struct nvmm_x86_cpuid_mask nvmm_cpuid_00000001; 190 extern const struct nvmm_x86_cpuid_mask nvmm_cpuid_00000007; 191 extern const struct nvmm_x86_cpuid_mask nvmm_cpuid_80000001; 192 bool nvmm_x86_pat_validate(uint64_t); 193 #endif 194 195 #endif /* ASM_NVMM */ 196 197 #endif /* _NVMM_X86_H_ */ 198
Indexes created Thu Oct 02 01:09:59 GMT 2025