nvmm_x86_svm.c revision 1.18
1 /* $NetBSD: nvmm_x86_svm.c,v 1.18 2019/01/26 15:12:20 maxv Exp $ */ 2 3 /* 4 * Copyright (c) 2018 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Maxime Villard. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: nvmm_x86_svm.c,v 1.18 2019/01/26 15:12:20 maxv Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/kmem.h> 39 #include <sys/cpu.h> 40 #include <sys/xcall.h> 41 42 #include <uvm/uvm.h> 43 #include <uvm/uvm_page.h> 44 45 #include <x86/cputypes.h> 46 #include <x86/specialreg.h> 47 #include <x86/pmap.h> 48 #include <x86/dbregs.h> 49 #include <machine/cpuvar.h> 50 51 #include <dev/nvmm/nvmm.h> 52 #include <dev/nvmm/nvmm_internal.h> 53 #include <dev/nvmm/x86/nvmm_x86.h> 54 55 int svm_vmrun(paddr_t, uint64_t *); 56 57 #define MSR_VM_HSAVE_PA 0xC0010117 58 59 /* -------------------------------------------------------------------------- */ 60 61 #define VMCB_EXITCODE_CR0_READ 0x0000 62 #define VMCB_EXITCODE_CR1_READ 0x0001 63 #define VMCB_EXITCODE_CR2_READ 0x0002 64 #define VMCB_EXITCODE_CR3_READ 0x0003 65 #define VMCB_EXITCODE_CR4_READ 0x0004 66 #define VMCB_EXITCODE_CR5_READ 0x0005 67 #define VMCB_EXITCODE_CR6_READ 0x0006 68 #define VMCB_EXITCODE_CR7_READ 0x0007 69 #define VMCB_EXITCODE_CR8_READ 0x0008 70 #define VMCB_EXITCODE_CR9_READ 0x0009 71 #define VMCB_EXITCODE_CR10_READ 0x000A 72 #define VMCB_EXITCODE_CR11_READ 0x000B 73 #define VMCB_EXITCODE_CR12_READ 0x000C 74 #define VMCB_EXITCODE_CR13_READ 0x000D 75 #define VMCB_EXITCODE_CR14_READ 0x000E 76 #define VMCB_EXITCODE_CR15_READ 0x000F 77 #define VMCB_EXITCODE_CR0_WRITE 0x0010 78 #define VMCB_EXITCODE_CR1_WRITE 0x0011 79 #define VMCB_EXITCODE_CR2_WRITE 0x0012 80 #define VMCB_EXITCODE_CR3_WRITE 0x0013 81 #define VMCB_EXITCODE_CR4_WRITE 0x0014 82 #define VMCB_EXITCODE_CR5_WRITE 0x0015 83 #define VMCB_EXITCODE_CR6_WRITE 0x0016 84 #define VMCB_EXITCODE_CR7_WRITE 0x0017 85 #define VMCB_EXITCODE_CR8_WRITE 0x0018 86 #define VMCB_EXITCODE_CR9_WRITE 0x0019 87 #define VMCB_EXITCODE_CR10_WRITE 0x001A 88 #define VMCB_EXITCODE_CR11_WRITE 0x001B 89 #define VMCB_EXITCODE_CR12_WRITE 0x001C 90 #define VMCB_EXITCODE_CR13_WRITE 0x001D 91 #define VMCB_EXITCODE_CR14_WRITE 0x001E 92 #define VMCB_EXITCODE_CR15_WRITE 0x001F 93 #define VMCB_EXITCODE_DR0_READ 0x0020 94 #define VMCB_EXITCODE_DR1_READ 0x0021 95 #define VMCB_EXITCODE_DR2_READ 0x0022 96 #define VMCB_EXITCODE_DR3_READ 0x0023 97 #define VMCB_EXITCODE_DR4_READ 0x0024 98 #define VMCB_EXITCODE_DR5_READ 0x0025 99 #define VMCB_EXITCODE_DR6_READ 0x0026 100 #define VMCB_EXITCODE_DR7_READ 0x0027 101 #define VMCB_EXITCODE_DR8_READ 0x0028 102 #define VMCB_EXITCODE_DR9_READ 0x0029 103 #define VMCB_EXITCODE_DR10_READ 0x002A 104 #define VMCB_EXITCODE_DR11_READ 0x002B 105 #define VMCB_EXITCODE_DR12_READ 0x002C 106 #define VMCB_EXITCODE_DR13_READ 0x002D 107 #define VMCB_EXITCODE_DR14_READ 0x002E 108 #define VMCB_EXITCODE_DR15_READ 0x002F 109 #define VMCB_EXITCODE_DR0_WRITE 0x0030 110 #define VMCB_EXITCODE_DR1_WRITE 0x0031 111 #define VMCB_EXITCODE_DR2_WRITE 0x0032 112 #define VMCB_EXITCODE_DR3_WRITE 0x0033 113 #define VMCB_EXITCODE_DR4_WRITE 0x0034 114 #define VMCB_EXITCODE_DR5_WRITE 0x0035 115 #define VMCB_EXITCODE_DR6_WRITE 0x0036 116 #define VMCB_EXITCODE_DR7_WRITE 0x0037 117 #define VMCB_EXITCODE_DR8_WRITE 0x0038 118 #define VMCB_EXITCODE_DR9_WRITE 0x0039 119 #define VMCB_EXITCODE_DR10_WRITE 0x003A 120 #define VMCB_EXITCODE_DR11_WRITE 0x003B 121 #define VMCB_EXITCODE_DR12_WRITE 0x003C 122 #define VMCB_EXITCODE_DR13_WRITE 0x003D 123 #define VMCB_EXITCODE_DR14_WRITE 0x003E 124 #define VMCB_EXITCODE_DR15_WRITE 0x003F 125 #define VMCB_EXITCODE_EXCP0 0x0040 126 #define VMCB_EXITCODE_EXCP1 0x0041 127 #define VMCB_EXITCODE_EXCP2 0x0042 128 #define VMCB_EXITCODE_EXCP3 0x0043 129 #define VMCB_EXITCODE_EXCP4 0x0044 130 #define VMCB_EXITCODE_EXCP5 0x0045 131 #define VMCB_EXITCODE_EXCP6 0x0046 132 #define VMCB_EXITCODE_EXCP7 0x0047 133 #define VMCB_EXITCODE_EXCP8 0x0048 134 #define VMCB_EXITCODE_EXCP9 0x0049 135 #define VMCB_EXITCODE_EXCP10 0x004A 136 #define VMCB_EXITCODE_EXCP11 0x004B 137 #define VMCB_EXITCODE_EXCP12 0x004C 138 #define VMCB_EXITCODE_EXCP13 0x004D 139 #define VMCB_EXITCODE_EXCP14 0x004E 140 #define VMCB_EXITCODE_EXCP15 0x004F 141 #define VMCB_EXITCODE_EXCP16 0x0050 142 #define VMCB_EXITCODE_EXCP17 0x0051 143 #define VMCB_EXITCODE_EXCP18 0x0052 144 #define VMCB_EXITCODE_EXCP19 0x0053 145 #define VMCB_EXITCODE_EXCP20 0x0054 146 #define VMCB_EXITCODE_EXCP21 0x0055 147 #define VMCB_EXITCODE_EXCP22 0x0056 148 #define VMCB_EXITCODE_EXCP23 0x0057 149 #define VMCB_EXITCODE_EXCP24 0x0058 150 #define VMCB_EXITCODE_EXCP25 0x0059 151 #define VMCB_EXITCODE_EXCP26 0x005A 152 #define VMCB_EXITCODE_EXCP27 0x005B 153 #define VMCB_EXITCODE_EXCP28 0x005C 154 #define VMCB_EXITCODE_EXCP29 0x005D 155 #define VMCB_EXITCODE_EXCP30 0x005E 156 #define VMCB_EXITCODE_EXCP31 0x005F 157 #define VMCB_EXITCODE_INTR 0x0060 158 #define VMCB_EXITCODE_NMI 0x0061 159 #define VMCB_EXITCODE_SMI 0x0062 160 #define VMCB_EXITCODE_INIT 0x0063 161 #define VMCB_EXITCODE_VINTR 0x0064 162 #define VMCB_EXITCODE_CR0_SEL_WRITE 0x0065 163 #define VMCB_EXITCODE_IDTR_READ 0x0066 164 #define VMCB_EXITCODE_GDTR_READ 0x0067 165 #define VMCB_EXITCODE_LDTR_READ 0x0068 166 #define VMCB_EXITCODE_TR_READ 0x0069 167 #define VMCB_EXITCODE_IDTR_WRITE 0x006A 168 #define VMCB_EXITCODE_GDTR_WRITE 0x006B 169 #define VMCB_EXITCODE_LDTR_WRITE 0x006C 170 #define VMCB_EXITCODE_TR_WRITE 0x006D 171 #define VMCB_EXITCODE_RDTSC 0x006E 172 #define VMCB_EXITCODE_RDPMC 0x006F 173 #define VMCB_EXITCODE_PUSHF 0x0070 174 #define VMCB_EXITCODE_POPF 0x0071 175 #define VMCB_EXITCODE_CPUID 0x0072 176 #define VMCB_EXITCODE_RSM 0x0073 177 #define VMCB_EXITCODE_IRET 0x0074 178 #define VMCB_EXITCODE_SWINT 0x0075 179 #define VMCB_EXITCODE_INVD 0x0076 180 #define VMCB_EXITCODE_PAUSE 0x0077 181 #define VMCB_EXITCODE_HLT 0x0078 182 #define VMCB_EXITCODE_INVLPG 0x0079 183 #define VMCB_EXITCODE_INVLPGA 0x007A 184 #define VMCB_EXITCODE_IOIO 0x007B 185 #define VMCB_EXITCODE_MSR 0x007C 186 #define VMCB_EXITCODE_TASK_SWITCH 0x007D 187 #define VMCB_EXITCODE_FERR_FREEZE 0x007E 188 #define VMCB_EXITCODE_SHUTDOWN 0x007F 189 #define VMCB_EXITCODE_VMRUN 0x0080 190 #define VMCB_EXITCODE_VMMCALL 0x0081 191 #define VMCB_EXITCODE_VMLOAD 0x0082 192 #define VMCB_EXITCODE_VMSAVE 0x0083 193 #define VMCB_EXITCODE_STGI 0x0084 194 #define VMCB_EXITCODE_CLGI 0x0085 195 #define VMCB_EXITCODE_SKINIT 0x0086 196 #define VMCB_EXITCODE_RDTSCP 0x0087 197 #define VMCB_EXITCODE_ICEBP 0x0088 198 #define VMCB_EXITCODE_WBINVD 0x0089 199 #define VMCB_EXITCODE_MONITOR 0x008A 200 #define VMCB_EXITCODE_MWAIT 0x008B 201 #define VMCB_EXITCODE_MWAIT_CONDITIONAL 0x008C 202 #define VMCB_EXITCODE_XSETBV 0x008D 203 #define VMCB_EXITCODE_EFER_WRITE_TRAP 0x008F 204 #define VMCB_EXITCODE_CR0_WRITE_TRAP 0x0090 205 #define VMCB_EXITCODE_CR1_WRITE_TRAP 0x0091 206 #define VMCB_EXITCODE_CR2_WRITE_TRAP 0x0092 207 #define VMCB_EXITCODE_CR3_WRITE_TRAP 0x0093 208 #define VMCB_EXITCODE_CR4_WRITE_TRAP 0x0094 209 #define VMCB_EXITCODE_CR5_WRITE_TRAP 0x0095 210 #define VMCB_EXITCODE_CR6_WRITE_TRAP 0x0096 211 #define VMCB_EXITCODE_CR7_WRITE_TRAP 0x0097 212 #define VMCB_EXITCODE_CR8_WRITE_TRAP 0x0098 213 #define VMCB_EXITCODE_CR9_WRITE_TRAP 0x0099 214 #define VMCB_EXITCODE_CR10_WRITE_TRAP 0x009A 215 #define VMCB_EXITCODE_CR11_WRITE_TRAP 0x009B 216 #define VMCB_EXITCODE_CR12_WRITE_TRAP 0x009C 217 #define VMCB_EXITCODE_CR13_WRITE_TRAP 0x009D 218 #define VMCB_EXITCODE_CR14_WRITE_TRAP 0x009E 219 #define VMCB_EXITCODE_CR15_WRITE_TRAP 0x009F 220 #define VMCB_EXITCODE_NPF 0x0400 221 #define VMCB_EXITCODE_AVIC_INCOMP_IPI 0x0401 222 #define VMCB_EXITCODE_AVIC_NOACCEL 0x0402 223 #define VMCB_EXITCODE_VMGEXIT 0x0403 224 #define VMCB_EXITCODE_INVALID -1 225 226 /* -------------------------------------------------------------------------- */ 227 228 struct vmcb_ctrl { 229 uint32_t intercept_cr; 230 #define VMCB_CTRL_INTERCEPT_RCR(x) __BIT( 0 + x) 231 #define VMCB_CTRL_INTERCEPT_WCR(x) __BIT(16 + x) 232 233 uint32_t intercept_dr; 234 #define VMCB_CTRL_INTERCEPT_RDR(x) __BIT( 0 + x) 235 #define VMCB_CTRL_INTERCEPT_WDR(x) __BIT(16 + x) 236 237 uint32_t intercept_vec; 238 #define VMCB_CTRL_INTERCEPT_VEC(x) __BIT(x) 239 240 uint32_t intercept_misc1; 241 #define VMCB_CTRL_INTERCEPT_INTR __BIT(0) 242 #define VMCB_CTRL_INTERCEPT_NMI __BIT(1) 243 #define VMCB_CTRL_INTERCEPT_SMI __BIT(2) 244 #define VMCB_CTRL_INTERCEPT_INIT __BIT(3) 245 #define VMCB_CTRL_INTERCEPT_VINTR __BIT(4) 246 #define VMCB_CTRL_INTERCEPT_CR0_SPEC __BIT(5) 247 #define VMCB_CTRL_INTERCEPT_RIDTR __BIT(6) 248 #define VMCB_CTRL_INTERCEPT_RGDTR __BIT(7) 249 #define VMCB_CTRL_INTERCEPT_RLDTR __BIT(8) 250 #define VMCB_CTRL_INTERCEPT_RTR __BIT(9) 251 #define VMCB_CTRL_INTERCEPT_WIDTR __BIT(10) 252 #define VMCB_CTRL_INTERCEPT_WGDTR __BIT(11) 253 #define VMCB_CTRL_INTERCEPT_WLDTR __BIT(12) 254 #define VMCB_CTRL_INTERCEPT_WTR __BIT(13) 255 #define VMCB_CTRL_INTERCEPT_RDTSC __BIT(14) 256 #define VMCB_CTRL_INTERCEPT_RDPMC __BIT(15) 257 #define VMCB_CTRL_INTERCEPT_PUSHF __BIT(16) 258 #define VMCB_CTRL_INTERCEPT_POPF __BIT(17) 259 #define VMCB_CTRL_INTERCEPT_CPUID __BIT(18) 260 #define VMCB_CTRL_INTERCEPT_RSM __BIT(19) 261 #define VMCB_CTRL_INTERCEPT_IRET __BIT(20) 262 #define VMCB_CTRL_INTERCEPT_INTN __BIT(21) 263 #define VMCB_CTRL_INTERCEPT_INVD __BIT(22) 264 #define VMCB_CTRL_INTERCEPT_PAUSE __BIT(23) 265 #define VMCB_CTRL_INTERCEPT_HLT __BIT(24) 266 #define VMCB_CTRL_INTERCEPT_INVLPG __BIT(25) 267 #define VMCB_CTRL_INTERCEPT_INVLPGA __BIT(26) 268 #define VMCB_CTRL_INTERCEPT_IOIO_PROT __BIT(27) 269 #define VMCB_CTRL_INTERCEPT_MSR_PROT __BIT(28) 270 #define VMCB_CTRL_INTERCEPT_TASKSW __BIT(29) 271 #define VMCB_CTRL_INTERCEPT_FERR_FREEZE __BIT(30) 272 #define VMCB_CTRL_INTERCEPT_SHUTDOWN __BIT(31) 273 274 uint32_t intercept_misc2; 275 #define VMCB_CTRL_INTERCEPT_VMRUN __BIT(0) 276 #define VMCB_CTRL_INTERCEPT_VMMCALL __BIT(1) 277 #define VMCB_CTRL_INTERCEPT_VMLOAD __BIT(2) 278 #define VMCB_CTRL_INTERCEPT_VMSAVE __BIT(3) 279 #define VMCB_CTRL_INTERCEPT_STGI __BIT(4) 280 #define VMCB_CTRL_INTERCEPT_CLGI __BIT(5) 281 #define VMCB_CTRL_INTERCEPT_SKINIT __BIT(6) 282 #define VMCB_CTRL_INTERCEPT_RDTSCP __BIT(7) 283 #define VMCB_CTRL_INTERCEPT_ICEBP __BIT(8) 284 #define VMCB_CTRL_INTERCEPT_WBINVD __BIT(9) 285 #define VMCB_CTRL_INTERCEPT_MONITOR __BIT(10) 286 #define VMCB_CTRL_INTERCEPT_MWAIT __BIT(12) 287 #define VMCB_CTRL_INTERCEPT_XSETBV __BIT(13) 288 #define VMCB_CTRL_INTERCEPT_EFER_SPEC __BIT(15) 289 #define VMCB_CTRL_INTERCEPT_WCR_SPEC(x) __BIT(16 + x) 290 291 uint8_t rsvd1[40]; 292 uint16_t pause_filt_thresh; 293 uint16_t pause_filt_cnt; 294 uint64_t iopm_base_pa; 295 uint64_t msrpm_base_pa; 296 uint64_t tsc_offset; 297 uint32_t guest_asid; 298 299 uint32_t tlb_ctrl; 300 #define VMCB_CTRL_TLB_CTRL_FLUSH_ALL 0x01 301 #define VMCB_CTRL_TLB_CTRL_FLUSH_GUEST 0x03 302 #define VMCB_CTRL_TLB_CTRL_FLUSH_GUEST_NONGLOBAL 0x07 303 304 uint64_t v; 305 #define VMCB_CTRL_V_TPR __BITS(7,0) 306 #define VMCB_CTRL_V_IRQ __BIT(8) 307 #define VMCB_CTRL_V_VGIF __BIT(9) 308 #define VMCB_CTRL_V_INTR_PRIO __BITS(19,16) 309 #define VMCB_CTRL_V_IGN_TPR __BIT(20) 310 #define VMCB_CTRL_V_INTR_MASKING __BIT(24) 311 #define VMCB_CTRL_V_GUEST_VGIF __BIT(25) 312 #define VMCB_CTRL_V_AVIC_EN __BIT(31) 313 #define VMCB_CTRL_V_INTR_VECTOR __BITS(39,32) 314 315 uint64_t intr; 316 #define VMCB_CTRL_INTR_SHADOW __BIT(0) 317 318 uint64_t exitcode; 319 uint64_t exitinfo1; 320 uint64_t exitinfo2; 321 322 uint64_t exitintinfo; 323 #define VMCB_CTRL_EXITINTINFO_VECTOR __BITS(7,0) 324 #define VMCB_CTRL_EXITINTINFO_TYPE __BITS(10,8) 325 #define VMCB_CTRL_EXITINTINFO_EV __BIT(11) 326 #define VMCB_CTRL_EXITINTINFO_V __BIT(31) 327 #define VMCB_CTRL_EXITINTINFO_ERRORCODE __BITS(63,32) 328 329 uint64_t enable1; 330 #define VMCB_CTRL_ENABLE_NP __BIT(0) 331 #define VMCB_CTRL_ENABLE_SEV __BIT(1) 332 #define VMCB_CTRL_ENABLE_ES_SEV __BIT(2) 333 334 uint64_t avic; 335 #define VMCB_CTRL_AVIC_APIC_BAR __BITS(51,0) 336 337 uint64_t ghcb; 338 339 uint64_t eventinj; 340 #define VMCB_CTRL_EVENTINJ_VECTOR __BITS(7,0) 341 #define VMCB_CTRL_EVENTINJ_TYPE __BITS(10,8) 342 #define VMCB_CTRL_EVENTINJ_EV __BIT(11) 343 #define VMCB_CTRL_EVENTINJ_V __BIT(31) 344 #define VMCB_CTRL_EVENTINJ_ERRORCODE __BITS(63,32) 345 346 uint64_t n_cr3; 347 348 uint64_t enable2; 349 #define VMCB_CTRL_ENABLE_LBR __BIT(0) 350 #define VMCB_CTRL_ENABLE_VVMSAVE __BIT(1) 351 352 uint32_t vmcb_clean; 353 #define VMCB_CTRL_VMCB_CLEAN_I __BIT(0) 354 #define VMCB_CTRL_VMCB_CLEAN_IOPM __BIT(1) 355 #define VMCB_CTRL_VMCB_CLEAN_ASID __BIT(2) 356 #define VMCB_CTRL_VMCB_CLEAN_TPR __BIT(3) 357 #define VMCB_CTRL_VMCB_CLEAN_NP __BIT(4) 358 #define VMCB_CTRL_VMCB_CLEAN_CR __BIT(5) 359 #define VMCB_CTRL_VMCB_CLEAN_DR __BIT(6) 360 #define VMCB_CTRL_VMCB_CLEAN_DT __BIT(7) 361 #define VMCB_CTRL_VMCB_CLEAN_SEG __BIT(8) 362 #define VMCB_CTRL_VMCB_CLEAN_CR2 __BIT(9) 363 #define VMCB_CTRL_VMCB_CLEAN_LBR __BIT(10) 364 #define VMCB_CTRL_VMCB_CLEAN_AVIC __BIT(11) 365 366 uint32_t rsvd2; 367 uint64_t nrip; 368 uint8_t inst_len; 369 uint8_t inst_bytes[15]; 370 uint64_t avic_abpp; 371 uint64_t rsvd3; 372 uint64_t avic_ltp; 373 374 uint64_t avic_phys; 375 #define VMCB_CTRL_AVIC_PHYS_TABLE_PTR __BITS(51,12) 376 #define VMCB_CTRL_AVIC_PHYS_MAX_INDEX __BITS(7,0) 377 378 uint64_t rsvd4; 379 uint64_t vmcb_ptr; 380 381 uint8_t pad[752]; 382 } __packed; 383 384 CTASSERT(sizeof(struct vmcb_ctrl) == 1024); 385 386 struct vmcb_segment { 387 uint16_t selector; 388 uint16_t attrib; /* hidden */ 389 uint32_t limit; /* hidden */ 390 uint64_t base; /* hidden */ 391 } __packed; 392 393 CTASSERT(sizeof(struct vmcb_segment) == 16); 394 395 struct vmcb_state { 396 struct vmcb_segment es; 397 struct vmcb_segment cs; 398 struct vmcb_segment ss; 399 struct vmcb_segment ds; 400 struct vmcb_segment fs; 401 struct vmcb_segment gs; 402 struct vmcb_segment gdt; 403 struct vmcb_segment ldt; 404 struct vmcb_segment idt; 405 struct vmcb_segment tr; 406 uint8_t rsvd1[43]; 407 uint8_t cpl; 408 uint8_t rsvd2[4]; 409 uint64_t efer; 410 uint8_t rsvd3[112]; 411 uint64_t cr4; 412 uint64_t cr3; 413 uint64_t cr0; 414 uint64_t dr7; 415 uint64_t dr6; 416 uint64_t rflags; 417 uint64_t rip; 418 uint8_t rsvd4[88]; 419 uint64_t rsp; 420 uint8_t rsvd5[24]; 421 uint64_t rax; 422 uint64_t star; 423 uint64_t lstar; 424 uint64_t cstar; 425 uint64_t sfmask; 426 uint64_t kernelgsbase; 427 uint64_t sysenter_cs; 428 uint64_t sysenter_esp; 429 uint64_t sysenter_eip; 430 uint64_t cr2; 431 uint8_t rsvd6[32]; 432 uint64_t g_pat; 433 uint64_t dbgctl; 434 uint64_t br_from; 435 uint64_t br_to; 436 uint64_t int_from; 437 uint64_t int_to; 438 uint8_t pad[2408]; 439 } __packed; 440 441 CTASSERT(sizeof(struct vmcb_state) == 0xC00); 442 443 struct vmcb { 444 struct vmcb_ctrl ctrl; 445 struct vmcb_state state; 446 } __packed; 447 448 CTASSERT(sizeof(struct vmcb) == PAGE_SIZE); 449 CTASSERT(offsetof(struct vmcb, state) == 0x400); 450 451 /* -------------------------------------------------------------------------- */ 452 453 struct svm_hsave { 454 paddr_t pa; 455 }; 456 457 static struct svm_hsave hsave[MAXCPUS]; 458 459 static uint8_t *svm_asidmap __read_mostly; 460 static uint32_t svm_maxasid __read_mostly; 461 static kmutex_t svm_asidlock __cacheline_aligned; 462 463 static bool svm_decode_assist __read_mostly; 464 static uint32_t svm_ctrl_tlb_flush __read_mostly; 465 466 #define SVM_XCR0_MASK_DEFAULT (XCR0_X87|XCR0_SSE) 467 static uint64_t svm_xcr0_mask __read_mostly; 468 469 #define SVM_NCPUIDS 32 470 471 #define VMCB_NPAGES 1 472 473 #define MSRBM_NPAGES 2 474 #define MSRBM_SIZE (MSRBM_NPAGES * PAGE_SIZE) 475 476 #define IOBM_NPAGES 3 477 #define IOBM_SIZE (IOBM_NPAGES * PAGE_SIZE) 478 479 /* Does not include EFER_LMSLE. */ 480 #define EFER_VALID \ 481 (EFER_SCE|EFER_LME|EFER_LMA|EFER_NXE|EFER_SVME|EFER_FFXSR|EFER_TCE) 482 483 #define EFER_TLB_FLUSH \ 484 (EFER_NXE|EFER_LMA|EFER_LME) 485 #define CR0_TLB_FLUSH \ 486 (CR0_PG|CR0_WP|CR0_CD|CR0_NW) 487 #define CR4_TLB_FLUSH \ 488 (CR4_PGE|CR4_PAE|CR4_PSE) 489 490 /* -------------------------------------------------------------------------- */ 491 492 struct svm_machdata { 493 bool cpuidpresent[SVM_NCPUIDS]; 494 struct nvmm_x86_conf_cpuid cpuid[SVM_NCPUIDS]; 495 }; 496 497 static const size_t svm_conf_sizes[NVMM_X86_NCONF] = { 498 [NVMM_X86_CONF_CPUID] = sizeof(struct nvmm_x86_conf_cpuid) 499 }; 500 501 struct svm_cpudata { 502 /* General */ 503 bool shared_asid; 504 bool tlb_want_flush; 505 506 /* VMCB */ 507 struct vmcb *vmcb; 508 paddr_t vmcb_pa; 509 510 /* I/O bitmap */ 511 uint8_t *iobm; 512 paddr_t iobm_pa; 513 514 /* MSR bitmap */ 515 uint8_t *msrbm; 516 paddr_t msrbm_pa; 517 518 /* Host state */ 519 uint64_t hxcr0; 520 uint64_t star; 521 uint64_t lstar; 522 uint64_t cstar; 523 uint64_t sfmask; 524 uint64_t fsbase; 525 uint64_t kernelgsbase; 526 bool ts_set; 527 struct xsave_header hfpu __aligned(64); 528 529 /* Event state */ 530 bool int_window_exit; 531 bool nmi_window_exit; 532 533 /* Guest state */ 534 uint64_t gxcr0; 535 uint64_t gprs[NVMM_X64_NGPR]; 536 uint64_t drs[NVMM_X64_NDR]; 537 uint64_t tsc_offset; 538 struct xsave_header gfpu __aligned(64); 539 }; 540 541 static void 542 svm_vmcb_cache_default(struct vmcb *vmcb) 543 { 544 vmcb->ctrl.vmcb_clean = 545 VMCB_CTRL_VMCB_CLEAN_I | 546 VMCB_CTRL_VMCB_CLEAN_IOPM | 547 VMCB_CTRL_VMCB_CLEAN_ASID | 548 VMCB_CTRL_VMCB_CLEAN_TPR | 549 VMCB_CTRL_VMCB_CLEAN_NP | 550 VMCB_CTRL_VMCB_CLEAN_CR | 551 VMCB_CTRL_VMCB_CLEAN_DR | 552 VMCB_CTRL_VMCB_CLEAN_DT | 553 VMCB_CTRL_VMCB_CLEAN_SEG | 554 VMCB_CTRL_VMCB_CLEAN_CR2 | 555 VMCB_CTRL_VMCB_CLEAN_LBR | 556 VMCB_CTRL_VMCB_CLEAN_AVIC; 557 } 558 559 static void 560 svm_vmcb_cache_update(struct vmcb *vmcb, uint64_t flags) 561 { 562 if (flags & NVMM_X64_STATE_SEGS) { 563 vmcb->ctrl.vmcb_clean &= 564 ~(VMCB_CTRL_VMCB_CLEAN_SEG | VMCB_CTRL_VMCB_CLEAN_DT); 565 } 566 if (flags & NVMM_X64_STATE_CRS) { 567 vmcb->ctrl.vmcb_clean &= 568 ~(VMCB_CTRL_VMCB_CLEAN_CR | VMCB_CTRL_VMCB_CLEAN_CR2 | 569 VMCB_CTRL_VMCB_CLEAN_TPR); 570 } 571 if (flags & NVMM_X64_STATE_DRS) { 572 vmcb->ctrl.vmcb_clean &= ~VMCB_CTRL_VMCB_CLEAN_DR; 573 } 574 if (flags & NVMM_X64_STATE_MSRS) { 575 /* CR for EFER, NP for PAT. */ 576 vmcb->ctrl.vmcb_clean &= 577 ~(VMCB_CTRL_VMCB_CLEAN_CR | VMCB_CTRL_VMCB_CLEAN_NP); 578 } 579 if (flags & NVMM_X64_STATE_MISC) { 580 /* SEG for CPL. */ 581 vmcb->ctrl.vmcb_clean &= ~VMCB_CTRL_VMCB_CLEAN_SEG; 582 } 583 } 584 585 static inline void 586 svm_vmcb_cache_flush(struct vmcb *vmcb, uint64_t flags) 587 { 588 vmcb->ctrl.vmcb_clean &= ~flags; 589 } 590 591 static inline void 592 svm_vmcb_cache_flush_all(struct vmcb *vmcb) 593 { 594 vmcb->ctrl.vmcb_clean = 0; 595 } 596 597 #define SVM_EVENT_TYPE_HW_INT 0 598 #define SVM_EVENT_TYPE_NMI 2 599 #define SVM_EVENT_TYPE_EXC 3 600 #define SVM_EVENT_TYPE_SW_INT 4 601 602 static void 603 svm_event_waitexit_enable(struct nvmm_cpu *vcpu, bool nmi) 604 { 605 struct svm_cpudata *cpudata = vcpu->cpudata; 606 struct vmcb *vmcb = cpudata->vmcb; 607 608 if (nmi) { 609 vmcb->ctrl.intercept_misc1 |= VMCB_CTRL_INTERCEPT_IRET; 610 cpudata->nmi_window_exit = true; 611 } else { 612 vmcb->ctrl.intercept_misc1 |= VMCB_CTRL_INTERCEPT_VINTR; 613 vmcb->ctrl.v |= (VMCB_CTRL_V_IRQ | VMCB_CTRL_V_IGN_TPR); 614 svm_vmcb_cache_flush(vmcb, VMCB_CTRL_VMCB_CLEAN_TPR); 615 cpudata->int_window_exit = true; 616 } 617 618 svm_vmcb_cache_flush(vmcb, VMCB_CTRL_VMCB_CLEAN_I); 619 } 620 621 static void 622 svm_event_waitexit_disable(struct nvmm_cpu *vcpu, bool nmi) 623 { 624 struct svm_cpudata *cpudata = vcpu->cpudata; 625 struct vmcb *vmcb = cpudata->vmcb; 626 627 if (nmi) { 628 vmcb->ctrl.intercept_misc1 &= ~VMCB_CTRL_INTERCEPT_IRET; 629 cpudata->nmi_window_exit = false; 630 } else { 631 vmcb->ctrl.intercept_misc1 &= ~VMCB_CTRL_INTERCEPT_VINTR; 632 vmcb->ctrl.v &= ~(VMCB_CTRL_V_IRQ | VMCB_CTRL_V_IGN_TPR); 633 svm_vmcb_cache_flush(vmcb, VMCB_CTRL_VMCB_CLEAN_TPR); 634 cpudata->int_window_exit = false; 635 } 636 637 svm_vmcb_cache_flush(vmcb, VMCB_CTRL_VMCB_CLEAN_I); 638 } 639 640 static inline int 641 svm_event_has_error(uint64_t vector) 642 { 643 switch (vector) { 644 case 8: /* #DF */ 645 case 10: /* #TS */ 646 case 11: /* #NP */ 647 case 12: /* #SS */ 648 case 13: /* #GP */ 649 case 14: /* #PF */ 650 case 17: /* #AC */ 651 case 30: /* #SX */ 652 return 1; 653 default: 654 return 0; 655 } 656 } 657 658 static int 659 svm_vcpu_inject(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 660 struct nvmm_event *event) 661 { 662 struct svm_cpudata *cpudata = vcpu->cpudata; 663 struct vmcb *vmcb = cpudata->vmcb; 664 int type = 0, err = 0; 665 666 if (event->vector >= 256) { 667 return EINVAL; 668 } 669 670 switch (event->type) { 671 case NVMM_EVENT_INTERRUPT_HW: 672 type = SVM_EVENT_TYPE_HW_INT; 673 if (event->vector == 2) { 674 type = SVM_EVENT_TYPE_NMI; 675 } 676 if (type == SVM_EVENT_TYPE_NMI) { 677 if (cpudata->nmi_window_exit) { 678 return EAGAIN; 679 } 680 svm_event_waitexit_enable(vcpu, true); 681 } else { 682 if (((vmcb->state.rflags & PSL_I) == 0) || 683 ((vmcb->ctrl.intr & VMCB_CTRL_INTR_SHADOW) != 0)) { 684 svm_event_waitexit_enable(vcpu, false); 685 return EAGAIN; 686 } 687 } 688 err = 0; 689 break; 690 case NVMM_EVENT_INTERRUPT_SW: 691 type = SVM_EVENT_TYPE_SW_INT; 692 err = 0; 693 break; 694 case NVMM_EVENT_EXCEPTION: 695 type = SVM_EVENT_TYPE_EXC; 696 if (event->vector == 2 || event->vector >= 32) 697 return EINVAL; 698 err = svm_event_has_error(event->vector); 699 break; 700 default: 701 return EINVAL; 702 } 703 704 vmcb->ctrl.eventinj = 705 __SHIFTIN(event->vector, VMCB_CTRL_EVENTINJ_VECTOR) | 706 __SHIFTIN(type, VMCB_CTRL_EVENTINJ_TYPE) | 707 __SHIFTIN(err, VMCB_CTRL_EVENTINJ_EV) | 708 __SHIFTIN(1, VMCB_CTRL_EVENTINJ_V) | 709 __SHIFTIN(event->u.error, VMCB_CTRL_EVENTINJ_ERRORCODE); 710 711 return 0; 712 } 713 714 static void 715 svm_inject_ud(struct nvmm_machine *mach, struct nvmm_cpu *vcpu) 716 { 717 struct nvmm_event event; 718 int ret __diagused; 719 720 event.type = NVMM_EVENT_EXCEPTION; 721 event.vector = 6; 722 event.u.error = 0; 723 724 ret = svm_vcpu_inject(mach, vcpu, &event); 725 KASSERT(ret == 0); 726 } 727 728 static void 729 svm_inject_gp(struct nvmm_machine *mach, struct nvmm_cpu *vcpu) 730 { 731 struct nvmm_event event; 732 int ret __diagused; 733 734 event.type = NVMM_EVENT_EXCEPTION; 735 event.vector = 13; 736 event.u.error = 0; 737 738 ret = svm_vcpu_inject(mach, vcpu, &event); 739 KASSERT(ret == 0); 740 } 741 742 static inline void 743 svm_inkernel_advance(struct vmcb *vmcb) 744 { 745 /* 746 * Maybe we should also apply single-stepping and debug exceptions. 747 * Matters for guest-ring3, because it can execute 'cpuid' under a 748 * debugger. 749 */ 750 vmcb->state.rip = vmcb->ctrl.nrip; 751 vmcb->ctrl.intr &= ~VMCB_CTRL_INTR_SHADOW; 752 } 753 754 static void 755 svm_inkernel_handle_cpuid(struct nvmm_cpu *vcpu, uint64_t eax, uint64_t ecx) 756 { 757 struct svm_cpudata *cpudata = vcpu->cpudata; 758 759 switch (eax) { 760 case 0x00000001: /* APIC number in RBX. The rest is tunable. */ 761 cpudata->gprs[NVMM_X64_GPR_RBX] &= ~CPUID_LOCAL_APIC_ID; 762 cpudata->gprs[NVMM_X64_GPR_RBX] |= __SHIFTIN(vcpu->cpuid, 763 CPUID_LOCAL_APIC_ID); 764 break; 765 case 0x0000000D: /* FPU description. Not tunable. */ 766 if (ecx != 0 || svm_xcr0_mask == 0) { 767 break; 768 } 769 cpudata->vmcb->state.rax = svm_xcr0_mask & 0xFFFFFFFF; 770 if (cpudata->gxcr0 & XCR0_SSE) { 771 cpudata->gprs[NVMM_X64_GPR_RBX] = sizeof(struct fxsave); 772 } else { 773 cpudata->gprs[NVMM_X64_GPR_RBX] = sizeof(struct save87); 774 } 775 cpudata->gprs[NVMM_X64_GPR_RBX] += 64; /* XSAVE header */ 776 cpudata->gprs[NVMM_X64_GPR_RCX] = sizeof(struct fxsave); 777 cpudata->gprs[NVMM_X64_GPR_RDX] = svm_xcr0_mask >> 32; 778 break; 779 case 0x40000000: 780 cpudata->gprs[NVMM_X64_GPR_RBX] = 0; 781 cpudata->gprs[NVMM_X64_GPR_RCX] = 0; 782 cpudata->gprs[NVMM_X64_GPR_RDX] = 0; 783 memcpy(&cpudata->gprs[NVMM_X64_GPR_RBX], "___ ", 4); 784 memcpy(&cpudata->gprs[NVMM_X64_GPR_RCX], "NVMM", 4); 785 memcpy(&cpudata->gprs[NVMM_X64_GPR_RDX], " ___", 4); 786 break; 787 case 0x80000001: /* No SVM, no RDTSCP. The rest is tunable. */ 788 cpudata->gprs[NVMM_X64_GPR_RCX] &= ~CPUID_SVM; 789 cpudata->gprs[NVMM_X64_GPR_RDX] &= ~CPUID_RDTSCP; 790 break; 791 default: 792 break; 793 } 794 } 795 796 static void 797 svm_exit_cpuid(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 798 struct nvmm_exit *exit) 799 { 800 struct svm_machdata *machdata = mach->machdata; 801 struct svm_cpudata *cpudata = vcpu->cpudata; 802 struct nvmm_x86_conf_cpuid *cpuid; 803 uint64_t eax, ecx; 804 u_int descs[4]; 805 size_t i; 806 807 eax = cpudata->vmcb->state.rax; 808 ecx = cpudata->gprs[NVMM_X64_GPR_RCX]; 809 x86_cpuid2(eax, ecx, descs); 810 811 cpudata->vmcb->state.rax = descs[0]; 812 cpudata->gprs[NVMM_X64_GPR_RBX] = descs[1]; 813 cpudata->gprs[NVMM_X64_GPR_RCX] = descs[2]; 814 cpudata->gprs[NVMM_X64_GPR_RDX] = descs[3]; 815 816 for (i = 0; i < SVM_NCPUIDS; i++) { 817 cpuid = &machdata->cpuid[i]; 818 if (!machdata->cpuidpresent[i]) { 819 continue; 820 } 821 if (cpuid->leaf != eax) { 822 continue; 823 } 824 825 /* del */ 826 cpudata->vmcb->state.rax &= ~cpuid->del.eax; 827 cpudata->gprs[NVMM_X64_GPR_RBX] &= ~cpuid->del.ebx; 828 cpudata->gprs[NVMM_X64_GPR_RCX] &= ~cpuid->del.ecx; 829 cpudata->gprs[NVMM_X64_GPR_RDX] &= ~cpuid->del.edx; 830 831 /* set */ 832 cpudata->vmcb->state.rax |= cpuid->set.eax; 833 cpudata->gprs[NVMM_X64_GPR_RBX] |= cpuid->set.ebx; 834 cpudata->gprs[NVMM_X64_GPR_RCX] |= cpuid->set.ecx; 835 cpudata->gprs[NVMM_X64_GPR_RDX] |= cpuid->set.edx; 836 837 break; 838 } 839 840 /* Overwrite non-tunable leaves. */ 841 svm_inkernel_handle_cpuid(vcpu, eax, ecx); 842 843 svm_inkernel_advance(cpudata->vmcb); 844 exit->reason = NVMM_EXIT_NONE; 845 } 846 847 static void 848 svm_exit_hlt(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 849 struct nvmm_exit *exit) 850 { 851 struct svm_cpudata *cpudata = vcpu->cpudata; 852 struct vmcb *vmcb = cpudata->vmcb; 853 854 if (cpudata->int_window_exit && (vmcb->state.rflags & PSL_I)) { 855 svm_event_waitexit_disable(vcpu, false); 856 } 857 858 svm_inkernel_advance(cpudata->vmcb); 859 exit->reason = NVMM_EXIT_HALTED; 860 } 861 862 #define SVM_EXIT_IO_PORT __BITS(31,16) 863 #define SVM_EXIT_IO_SEG __BITS(12,10) 864 #define SVM_EXIT_IO_A64 __BIT(9) 865 #define SVM_EXIT_IO_A32 __BIT(8) 866 #define SVM_EXIT_IO_A16 __BIT(7) 867 #define SVM_EXIT_IO_SZ32 __BIT(6) 868 #define SVM_EXIT_IO_SZ16 __BIT(5) 869 #define SVM_EXIT_IO_SZ8 __BIT(4) 870 #define SVM_EXIT_IO_REP __BIT(3) 871 #define SVM_EXIT_IO_STR __BIT(2) 872 #define SVM_EXIT_IO_IN __BIT(0) 873 874 static const int seg_to_nvmm[] = { 875 [0] = NVMM_X64_SEG_ES, 876 [1] = NVMM_X64_SEG_CS, 877 [2] = NVMM_X64_SEG_SS, 878 [3] = NVMM_X64_SEG_DS, 879 [4] = NVMM_X64_SEG_FS, 880 [5] = NVMM_X64_SEG_GS 881 }; 882 883 static void 884 svm_exit_io(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 885 struct nvmm_exit *exit) 886 { 887 struct svm_cpudata *cpudata = vcpu->cpudata; 888 uint64_t info = cpudata->vmcb->ctrl.exitinfo1; 889 uint64_t nextpc = cpudata->vmcb->ctrl.exitinfo2; 890 891 exit->reason = NVMM_EXIT_IO; 892 893 if (info & SVM_EXIT_IO_IN) { 894 exit->u.io.type = NVMM_EXIT_IO_IN; 895 } else { 896 exit->u.io.type = NVMM_EXIT_IO_OUT; 897 } 898 899 exit->u.io.port = __SHIFTOUT(info, SVM_EXIT_IO_PORT); 900 901 if (svm_decode_assist) { 902 KASSERT(__SHIFTOUT(info, SVM_EXIT_IO_SEG) < 6); 903 exit->u.io.seg = seg_to_nvmm[__SHIFTOUT(info, SVM_EXIT_IO_SEG)]; 904 } else { 905 exit->u.io.seg = -1; 906 } 907 908 if (info & SVM_EXIT_IO_A64) { 909 exit->u.io.address_size = 8; 910 } else if (info & SVM_EXIT_IO_A32) { 911 exit->u.io.address_size = 4; 912 } else if (info & SVM_EXIT_IO_A16) { 913 exit->u.io.address_size = 2; 914 } 915 916 if (info & SVM_EXIT_IO_SZ32) { 917 exit->u.io.operand_size = 4; 918 } else if (info & SVM_EXIT_IO_SZ16) { 919 exit->u.io.operand_size = 2; 920 } else if (info & SVM_EXIT_IO_SZ8) { 921 exit->u.io.operand_size = 1; 922 } 923 924 exit->u.io.rep = (info & SVM_EXIT_IO_REP) != 0; 925 exit->u.io.str = (info & SVM_EXIT_IO_STR) != 0; 926 exit->u.io.npc = nextpc; 927 } 928 929 static const uint64_t msr_ignore_list[] = { 930 0xc0010055, /* MSR_CMPHALT */ 931 MSR_DE_CFG, 932 MSR_IC_CFG, 933 MSR_UCODE_AMD_PATCHLEVEL 934 }; 935 936 static bool 937 svm_inkernel_handle_msr(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 938 struct nvmm_exit *exit) 939 { 940 struct svm_cpudata *cpudata = vcpu->cpudata; 941 uint64_t val; 942 size_t i; 943 944 switch (exit->u.msr.type) { 945 case NVMM_EXIT_MSR_RDMSR: 946 if (exit->u.msr.msr == MSR_CR_PAT) { 947 val = cpudata->vmcb->state.g_pat; 948 cpudata->vmcb->state.rax = (val & 0xFFFFFFFF); 949 cpudata->gprs[NVMM_X64_GPR_RDX] = (val >> 32); 950 goto handled; 951 } 952 if (exit->u.msr.msr == MSR_NB_CFG) { 953 val = NB_CFG_INITAPICCPUIDLO; 954 cpudata->vmcb->state.rax = (val & 0xFFFFFFFF); 955 cpudata->gprs[NVMM_X64_GPR_RDX] = (val >> 32); 956 goto handled; 957 } 958 for (i = 0; i < __arraycount(msr_ignore_list); i++) { 959 if (msr_ignore_list[i] != exit->u.msr.msr) 960 continue; 961 val = 0; 962 cpudata->vmcb->state.rax = (val & 0xFFFFFFFF); 963 cpudata->gprs[NVMM_X64_GPR_RDX] = (val >> 32); 964 goto handled; 965 } 966 break; 967 case NVMM_EXIT_MSR_WRMSR: 968 if (exit->u.msr.msr == MSR_EFER) { 969 if (__predict_false(exit->u.msr.val & ~EFER_VALID)) { 970 svm_inject_gp(mach, vcpu); 971 goto handled; 972 } 973 if ((cpudata->vmcb->state.efer ^ exit->u.msr.val) & 974 EFER_TLB_FLUSH) { 975 cpudata->tlb_want_flush = true; 976 } 977 cpudata->vmcb->state.efer = exit->u.msr.val | EFER_SVME; 978 goto handled; 979 } 980 if (exit->u.msr.msr == MSR_CR_PAT) { 981 cpudata->vmcb->state.g_pat = exit->u.msr.val; 982 goto handled; 983 } 984 for (i = 0; i < __arraycount(msr_ignore_list); i++) { 985 if (msr_ignore_list[i] != exit->u.msr.msr) 986 continue; 987 goto handled; 988 } 989 break; 990 } 991 992 return false; 993 994 handled: 995 svm_inkernel_advance(cpudata->vmcb); 996 return true; 997 } 998 999 static void 1000 svm_exit_msr(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 1001 struct nvmm_exit *exit) 1002 { 1003 struct svm_cpudata *cpudata = vcpu->cpudata; 1004 uint64_t info = cpudata->vmcb->ctrl.exitinfo1; 1005 1006 if (info == 0) { 1007 exit->u.msr.type = NVMM_EXIT_MSR_RDMSR; 1008 } else { 1009 exit->u.msr.type = NVMM_EXIT_MSR_WRMSR; 1010 } 1011 1012 exit->u.msr.msr = (cpudata->gprs[NVMM_X64_GPR_RCX] & 0xFFFFFFFF); 1013 1014 if (info == 1) { 1015 uint64_t rdx, rax; 1016 rdx = cpudata->gprs[NVMM_X64_GPR_RDX]; 1017 rax = cpudata->vmcb->state.rax; 1018 exit->u.msr.val = (rdx << 32) | (rax & 0xFFFFFFFF); 1019 } else { 1020 exit->u.msr.val = 0; 1021 } 1022 1023 if (svm_inkernel_handle_msr(mach, vcpu, exit)) { 1024 exit->reason = NVMM_EXIT_NONE; 1025 return; 1026 } 1027 1028 exit->reason = NVMM_EXIT_MSR; 1029 exit->u.msr.npc = cpudata->vmcb->ctrl.nrip; 1030 } 1031 1032 static void 1033 svm_exit_npf(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 1034 struct nvmm_exit *exit) 1035 { 1036 struct svm_cpudata *cpudata = vcpu->cpudata; 1037 gpaddr_t gpa = cpudata->vmcb->ctrl.exitinfo2; 1038 int error; 1039 1040 error = uvm_fault(&mach->vm->vm_map, gpa, VM_PROT_ALL); 1041 1042 if (error) { 1043 exit->reason = NVMM_EXIT_MEMORY; 1044 if (cpudata->vmcb->ctrl.exitinfo1 & PGEX_W) 1045 exit->u.mem.perm = NVMM_EXIT_MEMORY_WRITE; 1046 else if (cpudata->vmcb->ctrl.exitinfo1 & PGEX_X) 1047 exit->u.mem.perm = NVMM_EXIT_MEMORY_EXEC; 1048 else 1049 exit->u.mem.perm = NVMM_EXIT_MEMORY_READ; 1050 exit->u.mem.gpa = gpa; 1051 exit->u.mem.inst_len = cpudata->vmcb->ctrl.inst_len; 1052 memcpy(exit->u.mem.inst_bytes, cpudata->vmcb->ctrl.inst_bytes, 1053 sizeof(exit->u.mem.inst_bytes)); 1054 } else { 1055 exit->reason = NVMM_EXIT_NONE; 1056 } 1057 } 1058 1059 static void 1060 svm_exit_insn(struct vmcb *vmcb, struct nvmm_exit *exit, uint64_t reason) 1061 { 1062 exit->u.insn.npc = vmcb->ctrl.nrip; 1063 exit->reason = reason; 1064 } 1065 1066 static void 1067 svm_exit_xsetbv(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 1068 struct nvmm_exit *exit) 1069 { 1070 struct svm_cpudata *cpudata = vcpu->cpudata; 1071 struct vmcb *vmcb = cpudata->vmcb; 1072 uint64_t val; 1073 1074 exit->reason = NVMM_EXIT_NONE; 1075 1076 val = (cpudata->gprs[NVMM_X64_GPR_RDX] << 32) | 1077 (vmcb->state.rax & 0xFFFFFFFF); 1078 1079 if (__predict_false(cpudata->gprs[NVMM_X64_GPR_RCX] != 0)) { 1080 goto error; 1081 } else if (__predict_false(vmcb->state.cpl != 0)) { 1082 goto error; 1083 } else if (__predict_false((val & ~svm_xcr0_mask) != 0)) { 1084 goto error; 1085 } else if (__predict_false((val & XCR0_X87) == 0)) { 1086 goto error; 1087 } 1088 1089 cpudata->gxcr0 = val; 1090 1091 svm_inkernel_advance(cpudata->vmcb); 1092 return; 1093 1094 error: 1095 svm_inject_gp(mach, vcpu); 1096 } 1097 1098 static void 1099 svm_vcpu_guest_fpu_enter(struct nvmm_cpu *vcpu) 1100 { 1101 struct svm_cpudata *cpudata = vcpu->cpudata; 1102 1103 cpudata->ts_set = (rcr0() & CR0_TS) != 0; 1104 1105 fpu_area_save(&cpudata->hfpu, svm_xcr0_mask); 1106 fpu_area_restore(&cpudata->gfpu, svm_xcr0_mask); 1107 1108 if (svm_xcr0_mask != 0) { 1109 cpudata->hxcr0 = rdxcr(0); 1110 wrxcr(0, cpudata->gxcr0); 1111 } 1112 } 1113 1114 static void 1115 svm_vcpu_guest_fpu_leave(struct nvmm_cpu *vcpu) 1116 { 1117 struct svm_cpudata *cpudata = vcpu->cpudata; 1118 1119 if (svm_xcr0_mask != 0) { 1120 cpudata->gxcr0 = rdxcr(0); 1121 wrxcr(0, cpudata->hxcr0); 1122 } 1123 1124 fpu_area_save(&cpudata->gfpu, svm_xcr0_mask); 1125 fpu_area_restore(&cpudata->hfpu, svm_xcr0_mask); 1126 1127 if (cpudata->ts_set) { 1128 stts(); 1129 } 1130 } 1131 1132 static void 1133 svm_vcpu_guest_dbregs_enter(struct nvmm_cpu *vcpu) 1134 { 1135 struct svm_cpudata *cpudata = vcpu->cpudata; 1136 1137 x86_dbregs_save(curlwp); 1138 1139 ldr7(0); 1140 1141 ldr0(cpudata->drs[NVMM_X64_DR_DR0]); 1142 ldr1(cpudata->drs[NVMM_X64_DR_DR1]); 1143 ldr2(cpudata->drs[NVMM_X64_DR_DR2]); 1144 ldr3(cpudata->drs[NVMM_X64_DR_DR3]); 1145 } 1146 1147 static void 1148 svm_vcpu_guest_dbregs_leave(struct nvmm_cpu *vcpu) 1149 { 1150 struct svm_cpudata *cpudata = vcpu->cpudata; 1151 1152 cpudata->drs[NVMM_X64_DR_DR0] = rdr0(); 1153 cpudata->drs[NVMM_X64_DR_DR1] = rdr1(); 1154 cpudata->drs[NVMM_X64_DR_DR2] = rdr2(); 1155 cpudata->drs[NVMM_X64_DR_DR3] = rdr3(); 1156 1157 x86_dbregs_restore(curlwp); 1158 } 1159 1160 static void 1161 svm_vcpu_guest_misc_enter(struct nvmm_cpu *vcpu) 1162 { 1163 struct svm_cpudata *cpudata = vcpu->cpudata; 1164 1165 cpudata->star = rdmsr(MSR_STAR); 1166 cpudata->lstar = rdmsr(MSR_LSTAR); 1167 cpudata->cstar = rdmsr(MSR_CSTAR); 1168 cpudata->sfmask = rdmsr(MSR_SFMASK); 1169 cpudata->fsbase = rdmsr(MSR_FSBASE); 1170 cpudata->kernelgsbase = rdmsr(MSR_KERNELGSBASE); 1171 } 1172 1173 static void 1174 svm_vcpu_guest_misc_leave(struct nvmm_cpu *vcpu) 1175 { 1176 struct svm_cpudata *cpudata = vcpu->cpudata; 1177 1178 wrmsr(MSR_STAR, cpudata->star); 1179 wrmsr(MSR_LSTAR, cpudata->lstar); 1180 wrmsr(MSR_CSTAR, cpudata->cstar); 1181 wrmsr(MSR_SFMASK, cpudata->sfmask); 1182 wrmsr(MSR_FSBASE, cpudata->fsbase); 1183 wrmsr(MSR_KERNELGSBASE, cpudata->kernelgsbase); 1184 } 1185 1186 static int 1187 svm_vcpu_run(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 1188 struct nvmm_exit *exit) 1189 { 1190 struct svm_cpudata *cpudata = vcpu->cpudata; 1191 struct vmcb *vmcb = cpudata->vmcb; 1192 bool tlb_need_flush = false; 1193 int hcpu, s; 1194 1195 kpreempt_disable(); 1196 hcpu = cpu_number(); 1197 1198 if (vcpu->hcpu_last != hcpu || cpudata->shared_asid) { 1199 tlb_need_flush = true; 1200 } 1201 1202 if (cpudata->tlb_want_flush || tlb_need_flush) { 1203 vmcb->ctrl.tlb_ctrl = svm_ctrl_tlb_flush; 1204 } else { 1205 vmcb->ctrl.tlb_ctrl = 0; 1206 } 1207 1208 if (vcpu->hcpu_last != hcpu) { 1209 vmcb->ctrl.tsc_offset = cpudata->tsc_offset + 1210 curcpu()->ci_data.cpu_cc_skew; 1211 svm_vmcb_cache_flush_all(vmcb); 1212 } 1213 1214 svm_vcpu_guest_dbregs_enter(vcpu); 1215 svm_vcpu_guest_misc_enter(vcpu); 1216 1217 while (1) { 1218 s = splhigh(); 1219 svm_vcpu_guest_fpu_enter(vcpu); 1220 svm_vmrun(cpudata->vmcb_pa, cpudata->gprs); 1221 svm_vcpu_guest_fpu_leave(vcpu); 1222 splx(s); 1223 1224 svm_vmcb_cache_default(vmcb); 1225 1226 if (vmcb->ctrl.exitcode != VMCB_EXITCODE_INVALID) { 1227 if (cpudata->tlb_want_flush) { 1228 cpudata->tlb_want_flush = false; 1229 } 1230 vcpu->hcpu_last = hcpu; 1231 } 1232 1233 switch (vmcb->ctrl.exitcode) { 1234 case VMCB_EXITCODE_INTR: 1235 case VMCB_EXITCODE_NMI: 1236 exit->reason = NVMM_EXIT_NONE; 1237 break; 1238 case VMCB_EXITCODE_VINTR: 1239 svm_event_waitexit_disable(vcpu, false); 1240 exit->reason = NVMM_EXIT_INT_READY; 1241 break; 1242 case VMCB_EXITCODE_IRET: 1243 svm_event_waitexit_disable(vcpu, true); 1244 exit->reason = NVMM_EXIT_NMI_READY; 1245 break; 1246 case VMCB_EXITCODE_CPUID: 1247 svm_exit_cpuid(mach, vcpu, exit); 1248 break; 1249 case VMCB_EXITCODE_HLT: 1250 svm_exit_hlt(mach, vcpu, exit); 1251 break; 1252 case VMCB_EXITCODE_IOIO: 1253 svm_exit_io(mach, vcpu, exit); 1254 break; 1255 case VMCB_EXITCODE_MSR: 1256 svm_exit_msr(mach, vcpu, exit); 1257 break; 1258 case VMCB_EXITCODE_SHUTDOWN: 1259 exit->reason = NVMM_EXIT_SHUTDOWN; 1260 break; 1261 case VMCB_EXITCODE_RDPMC: 1262 case VMCB_EXITCODE_RSM: 1263 case VMCB_EXITCODE_INVLPGA: 1264 case VMCB_EXITCODE_VMRUN: 1265 case VMCB_EXITCODE_VMMCALL: 1266 case VMCB_EXITCODE_VMLOAD: 1267 case VMCB_EXITCODE_VMSAVE: 1268 case VMCB_EXITCODE_STGI: 1269 case VMCB_EXITCODE_CLGI: 1270 case VMCB_EXITCODE_SKINIT: 1271 case VMCB_EXITCODE_RDTSCP: 1272 svm_inject_ud(mach, vcpu); 1273 exit->reason = NVMM_EXIT_NONE; 1274 break; 1275 case VMCB_EXITCODE_MONITOR: 1276 svm_exit_insn(vmcb, exit, NVMM_EXIT_MONITOR); 1277 break; 1278 case VMCB_EXITCODE_MWAIT: 1279 svm_exit_insn(vmcb, exit, NVMM_EXIT_MWAIT); 1280 break; 1281 case VMCB_EXITCODE_MWAIT_CONDITIONAL: 1282 svm_exit_insn(vmcb, exit, NVMM_EXIT_MWAIT_COND); 1283 break; 1284 case VMCB_EXITCODE_XSETBV: 1285 svm_exit_xsetbv(mach, vcpu, exit); 1286 break; 1287 case VMCB_EXITCODE_NPF: 1288 svm_exit_npf(mach, vcpu, exit); 1289 break; 1290 case VMCB_EXITCODE_FERR_FREEZE: /* ? */ 1291 default: 1292 exit->reason = NVMM_EXIT_INVALID; 1293 break; 1294 } 1295 1296 /* If no reason to return to userland, keep rolling. */ 1297 if (curcpu()->ci_schedstate.spc_flags & SPCF_SHOULDYIELD) { 1298 break; 1299 } 1300 if (curcpu()->ci_data.cpu_softints != 0) { 1301 break; 1302 } 1303 if (curlwp->l_flag & LW_USERRET) { 1304 break; 1305 } 1306 if (exit->reason != NVMM_EXIT_NONE) { 1307 break; 1308 } 1309 } 1310 1311 svm_vcpu_guest_misc_leave(vcpu); 1312 svm_vcpu_guest_dbregs_leave(vcpu); 1313 1314 kpreempt_enable(); 1315 1316 exit->exitstate[NVMM_X64_EXITSTATE_CR8] = __SHIFTOUT(vmcb->ctrl.v, 1317 VMCB_CTRL_V_TPR); 1318 exit->exitstate[NVMM_X64_EXITSTATE_RFLAGS] = vmcb->state.rflags; 1319 1320 exit->exitstate[NVMM_X64_EXITSTATE_INT_SHADOW] = 1321 ((vmcb->ctrl.intr & VMCB_CTRL_INTR_SHADOW) != 0); 1322 exit->exitstate[NVMM_X64_EXITSTATE_INT_WINDOW_EXIT] = 1323 cpudata->int_window_exit; 1324 exit->exitstate[NVMM_X64_EXITSTATE_NMI_WINDOW_EXIT] = 1325 cpudata->nmi_window_exit; 1326 1327 return 0; 1328 } 1329 1330 /* -------------------------------------------------------------------------- */ 1331 1332 static int 1333 svm_memalloc(paddr_t *pa, vaddr_t *va, size_t npages) 1334 { 1335 struct pglist pglist; 1336 paddr_t _pa; 1337 vaddr_t _va; 1338 size_t i; 1339 int ret; 1340 1341 ret = uvm_pglistalloc(npages * PAGE_SIZE, 0, ~0UL, PAGE_SIZE, 0, 1342 &pglist, 1, 0); 1343 if (ret != 0) 1344 return ENOMEM; 1345 _pa = TAILQ_FIRST(&pglist)->phys_addr; 1346 _va = uvm_km_alloc(kernel_map, npages * PAGE_SIZE, 0, 1347 UVM_KMF_VAONLY | UVM_KMF_NOWAIT); 1348 if (_va == 0) 1349 goto error; 1350 1351 for (i = 0; i < npages; i++) { 1352 pmap_kenter_pa(_va + i * PAGE_SIZE, _pa + i * PAGE_SIZE, 1353 VM_PROT_READ | VM_PROT_WRITE, PMAP_WRITE_BACK); 1354 } 1355 pmap_update(pmap_kernel()); 1356 1357 memset((void *)_va, 0, npages * PAGE_SIZE); 1358 1359 *pa = _pa; 1360 *va = _va; 1361 return 0; 1362 1363 error: 1364 for (i = 0; i < npages; i++) { 1365 uvm_pagefree(PHYS_TO_VM_PAGE(_pa + i * PAGE_SIZE)); 1366 } 1367 return ENOMEM; 1368 } 1369 1370 static void 1371 svm_memfree(paddr_t pa, vaddr_t va, size_t npages) 1372 { 1373 size_t i; 1374 1375 pmap_kremove(va, npages * PAGE_SIZE); 1376 pmap_update(pmap_kernel()); 1377 uvm_km_free(kernel_map, va, npages * PAGE_SIZE, UVM_KMF_VAONLY); 1378 for (i = 0; i < npages; i++) { 1379 uvm_pagefree(PHYS_TO_VM_PAGE(pa + i * PAGE_SIZE)); 1380 } 1381 } 1382 1383 /* -------------------------------------------------------------------------- */ 1384 1385 #define SVM_MSRBM_READ __BIT(0) 1386 #define SVM_MSRBM_WRITE __BIT(1) 1387 1388 static void 1389 svm_vcpu_msr_allow(uint8_t *bitmap, uint64_t msr, bool read, bool write) 1390 { 1391 uint64_t byte; 1392 uint8_t bitoff; 1393 1394 if (msr < 0x00002000) { 1395 /* Range 1 */ 1396 byte = ((msr - 0x00000000) >> 2UL) + 0x0000; 1397 } else if (msr >= 0xC0000000 && msr < 0xC0002000) { 1398 /* Range 2 */ 1399 byte = ((msr - 0xC0000000) >> 2UL) + 0x0800; 1400 } else if (msr >= 0xC0010000 && msr < 0xC0012000) { 1401 /* Range 3 */ 1402 byte = ((msr - 0xC0010000) >> 2UL) + 0x1000; 1403 } else { 1404 panic("%s: wrong range", __func__); 1405 } 1406 1407 bitoff = (msr & 0x3) << 1; 1408 1409 if (read) { 1410 bitmap[byte] &= ~(SVM_MSRBM_READ << bitoff); 1411 } 1412 if (write) { 1413 bitmap[byte] &= ~(SVM_MSRBM_WRITE << bitoff); 1414 } 1415 } 1416 1417 static void 1418 svm_asid_alloc(struct nvmm_cpu *vcpu) 1419 { 1420 struct svm_cpudata *cpudata = vcpu->cpudata; 1421 struct vmcb *vmcb = cpudata->vmcb; 1422 size_t i, oct, bit; 1423 1424 mutex_enter(&svm_asidlock); 1425 1426 for (i = 0; i < svm_maxasid; i++) { 1427 oct = i / 8; 1428 bit = i % 8; 1429 1430 if (svm_asidmap[oct] & __BIT(bit)) { 1431 continue; 1432 } 1433 1434 svm_asidmap[oct] |= __BIT(bit); 1435 vmcb->ctrl.guest_asid = i; 1436 mutex_exit(&svm_asidlock); 1437 return; 1438 } 1439 1440 /* 1441 * No free ASID. Use the last one, which is shared and requires 1442 * special TLB handling. 1443 */ 1444 cpudata->shared_asid = true; 1445 vmcb->ctrl.guest_asid = svm_maxasid - 1; 1446 mutex_exit(&svm_asidlock); 1447 } 1448 1449 static void 1450 svm_asid_free(struct nvmm_cpu *vcpu) 1451 { 1452 struct svm_cpudata *cpudata = vcpu->cpudata; 1453 struct vmcb *vmcb = cpudata->vmcb; 1454 size_t oct, bit; 1455 1456 if (cpudata->shared_asid) { 1457 return; 1458 } 1459 1460 oct = vmcb->ctrl.guest_asid / 8; 1461 bit = vmcb->ctrl.guest_asid % 8; 1462 1463 mutex_enter(&svm_asidlock); 1464 svm_asidmap[oct] &= ~__BIT(bit); 1465 mutex_exit(&svm_asidlock); 1466 } 1467 1468 static void 1469 svm_vcpu_init(struct nvmm_machine *mach, struct nvmm_cpu *vcpu) 1470 { 1471 struct svm_cpudata *cpudata = vcpu->cpudata; 1472 struct vmcb *vmcb = cpudata->vmcb; 1473 1474 /* Allow reads/writes of Control Registers. */ 1475 vmcb->ctrl.intercept_cr = 0; 1476 1477 /* Allow reads/writes of Debug Registers. */ 1478 vmcb->ctrl.intercept_dr = 0; 1479 1480 /* Allow exceptions 0 to 31. */ 1481 vmcb->ctrl.intercept_vec = 0; 1482 1483 /* 1484 * Allow: 1485 * - SMI [smm interrupts] 1486 * - VINTR [virtual interrupts] 1487 * - CR0_SPEC [CR0 writes changing other fields than CR0.TS or CR0.MP] 1488 * - RIDTR [reads of IDTR] 1489 * - RGDTR [reads of GDTR] 1490 * - RLDTR [reads of LDTR] 1491 * - RTR [reads of TR] 1492 * - WIDTR [writes of IDTR] 1493 * - WGDTR [writes of GDTR] 1494 * - WLDTR [writes of LDTR] 1495 * - WTR [writes of TR] 1496 * - RDTSC [rdtsc instruction] 1497 * - PUSHF [pushf instruction] 1498 * - POPF [popf instruction] 1499 * - IRET [iret instruction] 1500 * - INTN [int $n instructions] 1501 * - INVD [invd instruction] 1502 * - PAUSE [pause instruction] 1503 * - INVLPG [invplg instruction] 1504 * - TASKSW [task switches] 1505 * 1506 * Intercept the rest below. 1507 */ 1508 vmcb->ctrl.intercept_misc1 = 1509 VMCB_CTRL_INTERCEPT_INTR | 1510 VMCB_CTRL_INTERCEPT_NMI | 1511 VMCB_CTRL_INTERCEPT_INIT | 1512 VMCB_CTRL_INTERCEPT_RDPMC | 1513 VMCB_CTRL_INTERCEPT_CPUID | 1514 VMCB_CTRL_INTERCEPT_RSM | 1515 VMCB_CTRL_INTERCEPT_HLT | 1516 VMCB_CTRL_INTERCEPT_INVLPGA | 1517 VMCB_CTRL_INTERCEPT_IOIO_PROT | 1518 VMCB_CTRL_INTERCEPT_MSR_PROT | 1519 VMCB_CTRL_INTERCEPT_FERR_FREEZE | 1520 VMCB_CTRL_INTERCEPT_SHUTDOWN; 1521 1522 /* 1523 * Allow: 1524 * - ICEBP [icebp instruction] 1525 * - WBINVD [wbinvd instruction] 1526 * - WCR_SPEC(0..15) [writes of CR0-15, received after instruction] 1527 * 1528 * Intercept the rest below. 1529 */ 1530 vmcb->ctrl.intercept_misc2 = 1531 VMCB_CTRL_INTERCEPT_VMRUN | 1532 VMCB_CTRL_INTERCEPT_VMMCALL | 1533 VMCB_CTRL_INTERCEPT_VMLOAD | 1534 VMCB_CTRL_INTERCEPT_VMSAVE | 1535 VMCB_CTRL_INTERCEPT_STGI | 1536 VMCB_CTRL_INTERCEPT_CLGI | 1537 VMCB_CTRL_INTERCEPT_SKINIT | 1538 VMCB_CTRL_INTERCEPT_RDTSCP | 1539 VMCB_CTRL_INTERCEPT_MONITOR | 1540 VMCB_CTRL_INTERCEPT_MWAIT | 1541 VMCB_CTRL_INTERCEPT_XSETBV; 1542 1543 /* Intercept all I/O accesses. */ 1544 memset(cpudata->iobm, 0xFF, IOBM_SIZE); 1545 vmcb->ctrl.iopm_base_pa = cpudata->iobm_pa; 1546 1547 /* 1548 * Allow: 1549 * - EFER [read] 1550 * - STAR [read, write] 1551 * - LSTAR [read, write] 1552 * - CSTAR [read, write] 1553 * - SFMASK [read, write] 1554 * - KERNELGSBASE [read, write] 1555 * - SYSENTER_CS [read, write] 1556 * - SYSENTER_ESP [read, write] 1557 * - SYSENTER_EIP [read, write] 1558 * - FSBASE [read, write] 1559 * - GSBASE [read, write] 1560 * - TSC [read] 1561 * 1562 * Intercept the rest. 1563 */ 1564 memset(cpudata->msrbm, 0xFF, MSRBM_SIZE); 1565 svm_vcpu_msr_allow(cpudata->msrbm, MSR_EFER, true, false); 1566 svm_vcpu_msr_allow(cpudata->msrbm, MSR_STAR, true, true); 1567 svm_vcpu_msr_allow(cpudata->msrbm, MSR_LSTAR, true, true); 1568 svm_vcpu_msr_allow(cpudata->msrbm, MSR_CSTAR, true, true); 1569 svm_vcpu_msr_allow(cpudata->msrbm, MSR_SFMASK, true, true); 1570 svm_vcpu_msr_allow(cpudata->msrbm, MSR_KERNELGSBASE, true, true); 1571 svm_vcpu_msr_allow(cpudata->msrbm, MSR_SYSENTER_CS, true, true); 1572 svm_vcpu_msr_allow(cpudata->msrbm, MSR_SYSENTER_ESP, true, true); 1573 svm_vcpu_msr_allow(cpudata->msrbm, MSR_SYSENTER_EIP, true, true); 1574 svm_vcpu_msr_allow(cpudata->msrbm, MSR_FSBASE, true, true); 1575 svm_vcpu_msr_allow(cpudata->msrbm, MSR_GSBASE, true, true); 1576 svm_vcpu_msr_allow(cpudata->msrbm, MSR_TSC, true, false); 1577 vmcb->ctrl.msrpm_base_pa = cpudata->msrbm_pa; 1578 1579 /* Generate ASID. */ 1580 svm_asid_alloc(vcpu); 1581 1582 /* Virtual TPR. */ 1583 vmcb->ctrl.v = VMCB_CTRL_V_INTR_MASKING; 1584 1585 /* Enable Nested Paging. */ 1586 vmcb->ctrl.enable1 = VMCB_CTRL_ENABLE_NP; 1587 vmcb->ctrl.n_cr3 = mach->vm->vm_map.pmap->pm_pdirpa[0]; 1588 1589 /* Must always be set. */ 1590 vmcb->state.efer = EFER_SVME; 1591 cpudata->gxcr0 = XCR0_X87; 1592 1593 /* Init XSAVE header. */ 1594 cpudata->gfpu.xsh_xstate_bv = svm_xcr0_mask; 1595 cpudata->gfpu.xsh_xcomp_bv = 0; 1596 1597 /* Bluntly hide the host TSC. */ 1598 cpudata->tsc_offset = rdtsc(); 1599 } 1600 1601 static int 1602 svm_vcpu_create(struct nvmm_machine *mach, struct nvmm_cpu *vcpu) 1603 { 1604 struct svm_cpudata *cpudata; 1605 int error; 1606 1607 /* Allocate the SVM cpudata. */ 1608 cpudata = (struct svm_cpudata *)uvm_km_alloc(kernel_map, 1609 roundup(sizeof(*cpudata), PAGE_SIZE), 0, 1610 UVM_KMF_WIRED|UVM_KMF_ZERO); 1611 vcpu->cpudata = cpudata; 1612 1613 /* VMCB */ 1614 error = svm_memalloc(&cpudata->vmcb_pa, (vaddr_t *)&cpudata->vmcb, 1615 VMCB_NPAGES); 1616 if (error) 1617 goto error; 1618 1619 /* I/O Bitmap */ 1620 error = svm_memalloc(&cpudata->iobm_pa, (vaddr_t *)&cpudata->iobm, 1621 IOBM_NPAGES); 1622 if (error) 1623 goto error; 1624 1625 /* MSR Bitmap */ 1626 error = svm_memalloc(&cpudata->msrbm_pa, (vaddr_t *)&cpudata->msrbm, 1627 MSRBM_NPAGES); 1628 if (error) 1629 goto error; 1630 1631 /* Init the VCPU info. */ 1632 svm_vcpu_init(mach, vcpu); 1633 1634 return 0; 1635 1636 error: 1637 if (cpudata->vmcb_pa) { 1638 svm_memfree(cpudata->vmcb_pa, (vaddr_t)cpudata->vmcb, 1639 VMCB_NPAGES); 1640 } 1641 if (cpudata->iobm_pa) { 1642 svm_memfree(cpudata->iobm_pa, (vaddr_t)cpudata->iobm, 1643 IOBM_NPAGES); 1644 } 1645 if (cpudata->msrbm_pa) { 1646 svm_memfree(cpudata->msrbm_pa, (vaddr_t)cpudata->msrbm, 1647 MSRBM_NPAGES); 1648 } 1649 uvm_km_free(kernel_map, (vaddr_t)cpudata, 1650 roundup(sizeof(*cpudata), PAGE_SIZE), UVM_KMF_WIRED); 1651 return error; 1652 } 1653 1654 static void 1655 svm_vcpu_destroy(struct nvmm_machine *mach, struct nvmm_cpu *vcpu) 1656 { 1657 struct svm_cpudata *cpudata = vcpu->cpudata; 1658 1659 svm_asid_free(vcpu); 1660 1661 svm_memfree(cpudata->vmcb_pa, (vaddr_t)cpudata->vmcb, VMCB_NPAGES); 1662 svm_memfree(cpudata->iobm_pa, (vaddr_t)cpudata->iobm, IOBM_NPAGES); 1663 svm_memfree(cpudata->msrbm_pa, (vaddr_t)cpudata->msrbm, MSRBM_NPAGES); 1664 1665 uvm_km_free(kernel_map, (vaddr_t)cpudata, 1666 roundup(sizeof(*cpudata), PAGE_SIZE), UVM_KMF_WIRED); 1667 } 1668 1669 #define SVM_SEG_ATTRIB_TYPE __BITS(4,0) 1670 #define SVM_SEG_ATTRIB_DPL __BITS(6,5) 1671 #define SVM_SEG_ATTRIB_P __BIT(7) 1672 #define SVM_SEG_ATTRIB_AVL __BIT(8) 1673 #define SVM_SEG_ATTRIB_LONG __BIT(9) 1674 #define SVM_SEG_ATTRIB_DEF32 __BIT(10) 1675 #define SVM_SEG_ATTRIB_GRAN __BIT(11) 1676 1677 static void 1678 svm_vcpu_setstate_seg(struct nvmm_x64_state_seg *seg, struct vmcb_segment *vseg) 1679 { 1680 vseg->selector = seg->selector; 1681 vseg->attrib = 1682 __SHIFTIN(seg->attrib.type, SVM_SEG_ATTRIB_TYPE) | 1683 __SHIFTIN(seg->attrib.dpl, SVM_SEG_ATTRIB_DPL) | 1684 __SHIFTIN(seg->attrib.p, SVM_SEG_ATTRIB_P) | 1685 __SHIFTIN(seg->attrib.avl, SVM_SEG_ATTRIB_AVL) | 1686 __SHIFTIN(seg->attrib.lng, SVM_SEG_ATTRIB_LONG) | 1687 __SHIFTIN(seg->attrib.def32, SVM_SEG_ATTRIB_DEF32) | 1688 __SHIFTIN(seg->attrib.gran, SVM_SEG_ATTRIB_GRAN); 1689 vseg->limit = seg->limit; 1690 vseg->base = seg->base; 1691 } 1692 1693 static void 1694 svm_vcpu_getstate_seg(struct nvmm_x64_state_seg *seg, struct vmcb_segment *vseg) 1695 { 1696 seg->selector = vseg->selector; 1697 seg->attrib.type = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_TYPE); 1698 seg->attrib.dpl = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_DPL); 1699 seg->attrib.p = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_P); 1700 seg->attrib.avl = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_AVL); 1701 seg->attrib.lng = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_LONG); 1702 seg->attrib.def32 = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_DEF32); 1703 seg->attrib.gran = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_GRAN); 1704 seg->limit = vseg->limit; 1705 seg->base = vseg->base; 1706 } 1707 1708 static inline bool 1709 svm_state_tlb_flush(struct vmcb *vmcb, struct nvmm_x64_state *state, 1710 uint64_t flags) 1711 { 1712 if (flags & NVMM_X64_STATE_CRS) { 1713 if ((vmcb->state.cr0 ^ 1714 state->crs[NVMM_X64_CR_CR0]) & CR0_TLB_FLUSH) { 1715 return true; 1716 } 1717 if (vmcb->state.cr3 != state->crs[NVMM_X64_CR_CR3]) { 1718 return true; 1719 } 1720 if ((vmcb->state.cr4 ^ 1721 state->crs[NVMM_X64_CR_CR4]) & CR4_TLB_FLUSH) { 1722 return true; 1723 } 1724 } 1725 1726 if (flags & NVMM_X64_STATE_MSRS) { 1727 if ((vmcb->state.efer ^ 1728 state->msrs[NVMM_X64_MSR_EFER]) & EFER_TLB_FLUSH) { 1729 return true; 1730 } 1731 } 1732 1733 return false; 1734 } 1735 1736 static void 1737 svm_vcpu_setstate(struct nvmm_cpu *vcpu, void *data, uint64_t flags) 1738 { 1739 struct nvmm_x64_state *state = (struct nvmm_x64_state *)data; 1740 struct svm_cpudata *cpudata = vcpu->cpudata; 1741 struct vmcb *vmcb = cpudata->vmcb; 1742 struct fxsave *fpustate; 1743 1744 if (svm_state_tlb_flush(vmcb, state, flags)) { 1745 cpudata->tlb_want_flush = true; 1746 } 1747 1748 if (flags & NVMM_X64_STATE_SEGS) { 1749 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_CS], 1750 &vmcb->state.cs); 1751 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_DS], 1752 &vmcb->state.ds); 1753 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_ES], 1754 &vmcb->state.es); 1755 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_FS], 1756 &vmcb->state.fs); 1757 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_GS], 1758 &vmcb->state.gs); 1759 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_SS], 1760 &vmcb->state.ss); 1761 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_GDT], 1762 &vmcb->state.gdt); 1763 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_IDT], 1764 &vmcb->state.idt); 1765 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_LDT], 1766 &vmcb->state.ldt); 1767 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_TR], 1768 &vmcb->state.tr); 1769 } 1770 1771 CTASSERT(sizeof(cpudata->gprs) == sizeof(state->gprs)); 1772 if (flags & NVMM_X64_STATE_GPRS) { 1773 memcpy(cpudata->gprs, state->gprs, sizeof(state->gprs)); 1774 1775 vmcb->state.rip = state->gprs[NVMM_X64_GPR_RIP]; 1776 vmcb->state.rsp = state->gprs[NVMM_X64_GPR_RSP]; 1777 vmcb->state.rax = state->gprs[NVMM_X64_GPR_RAX]; 1778 vmcb->state.rflags = state->gprs[NVMM_X64_GPR_RFLAGS]; 1779 } 1780 1781 if (flags & NVMM_X64_STATE_CRS) { 1782 vmcb->state.cr0 = state->crs[NVMM_X64_CR_CR0]; 1783 vmcb->state.cr2 = state->crs[NVMM_X64_CR_CR2]; 1784 vmcb->state.cr3 = state->crs[NVMM_X64_CR_CR3]; 1785 vmcb->state.cr4 = state->crs[NVMM_X64_CR_CR4]; 1786 1787 vmcb->ctrl.v &= ~VMCB_CTRL_V_TPR; 1788 vmcb->ctrl.v |= __SHIFTIN(state->crs[NVMM_X64_CR_CR8], 1789 VMCB_CTRL_V_TPR); 1790 1791 if (svm_xcr0_mask != 0) { 1792 /* Clear illegal XCR0 bits, set mandatory X87 bit. */ 1793 cpudata->gxcr0 = state->crs[NVMM_X64_CR_XCR0]; 1794 cpudata->gxcr0 &= svm_xcr0_mask; 1795 cpudata->gxcr0 |= XCR0_X87; 1796 } 1797 } 1798 1799 CTASSERT(sizeof(cpudata->drs) == sizeof(state->drs)); 1800 if (flags & NVMM_X64_STATE_DRS) { 1801 memcpy(cpudata->drs, state->drs, sizeof(state->drs)); 1802 1803 vmcb->state.dr6 = state->drs[NVMM_X64_DR_DR6]; 1804 vmcb->state.dr7 = state->drs[NVMM_X64_DR_DR7]; 1805 } 1806 1807 if (flags & NVMM_X64_STATE_MSRS) { 1808 /* Bit EFER_SVME is mandatory. */ 1809 vmcb->state.efer = state->msrs[NVMM_X64_MSR_EFER] | EFER_SVME; 1810 1811 vmcb->state.star = state->msrs[NVMM_X64_MSR_STAR]; 1812 vmcb->state.lstar = state->msrs[NVMM_X64_MSR_LSTAR]; 1813 vmcb->state.cstar = state->msrs[NVMM_X64_MSR_CSTAR]; 1814 vmcb->state.sfmask = state->msrs[NVMM_X64_MSR_SFMASK]; 1815 vmcb->state.kernelgsbase = 1816 state->msrs[NVMM_X64_MSR_KERNELGSBASE]; 1817 vmcb->state.sysenter_cs = 1818 state->msrs[NVMM_X64_MSR_SYSENTER_CS]; 1819 vmcb->state.sysenter_esp = 1820 state->msrs[NVMM_X64_MSR_SYSENTER_ESP]; 1821 vmcb->state.sysenter_eip = 1822 state->msrs[NVMM_X64_MSR_SYSENTER_EIP]; 1823 vmcb->state.g_pat = state->msrs[NVMM_X64_MSR_PAT]; 1824 } 1825 1826 if (flags & NVMM_X64_STATE_MISC) { 1827 vmcb->state.cpl = state->misc[NVMM_X64_MISC_CPL]; 1828 1829 if (state->misc[NVMM_X64_MISC_INT_SHADOW]) { 1830 vmcb->ctrl.intr |= VMCB_CTRL_INTR_SHADOW; 1831 } else { 1832 vmcb->ctrl.intr &= ~VMCB_CTRL_INTR_SHADOW; 1833 } 1834 1835 if (state->misc[NVMM_X64_MISC_INT_WINDOW_EXIT]) { 1836 svm_event_waitexit_enable(vcpu, false); 1837 } else { 1838 svm_event_waitexit_disable(vcpu, false); 1839 } 1840 1841 if (state->misc[NVMM_X64_MISC_NMI_WINDOW_EXIT]) { 1842 svm_event_waitexit_enable(vcpu, true); 1843 } else { 1844 svm_event_waitexit_disable(vcpu, true); 1845 } 1846 } 1847 1848 CTASSERT(sizeof(cpudata->gfpu.xsh_fxsave) == sizeof(state->fpu)); 1849 if (flags & NVMM_X64_STATE_FPU) { 1850 memcpy(cpudata->gfpu.xsh_fxsave, &state->fpu, 1851 sizeof(state->fpu)); 1852 1853 fpustate = (struct fxsave *)cpudata->gfpu.xsh_fxsave; 1854 fpustate->fx_mxcsr_mask &= x86_fpu_mxcsr_mask; 1855 fpustate->fx_mxcsr &= fpustate->fx_mxcsr_mask; 1856 1857 if (svm_xcr0_mask != 0) { 1858 /* Reset XSTATE_BV, to force a reload. */ 1859 cpudata->gfpu.xsh_xstate_bv = svm_xcr0_mask; 1860 } 1861 } 1862 1863 svm_vmcb_cache_update(vmcb, flags); 1864 } 1865 1866 static void 1867 svm_vcpu_getstate(struct nvmm_cpu *vcpu, void *data, uint64_t flags) 1868 { 1869 struct nvmm_x64_state *state = (struct nvmm_x64_state *)data; 1870 struct svm_cpudata *cpudata = vcpu->cpudata; 1871 struct vmcb *vmcb = cpudata->vmcb; 1872 1873 if (flags & NVMM_X64_STATE_SEGS) { 1874 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_CS], 1875 &vmcb->state.cs); 1876 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_DS], 1877 &vmcb->state.ds); 1878 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_ES], 1879 &vmcb->state.es); 1880 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_FS], 1881 &vmcb->state.fs); 1882 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_GS], 1883 &vmcb->state.gs); 1884 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_SS], 1885 &vmcb->state.ss); 1886 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_GDT], 1887 &vmcb->state.gdt); 1888 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_IDT], 1889 &vmcb->state.idt); 1890 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_LDT], 1891 &vmcb->state.ldt); 1892 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_TR], 1893 &vmcb->state.tr); 1894 } 1895 1896 CTASSERT(sizeof(cpudata->gprs) == sizeof(state->gprs)); 1897 if (flags & NVMM_X64_STATE_GPRS) { 1898 memcpy(state->gprs, cpudata->gprs, sizeof(state->gprs)); 1899 1900 state->gprs[NVMM_X64_GPR_RIP] = vmcb->state.rip; 1901 state->gprs[NVMM_X64_GPR_RSP] = vmcb->state.rsp; 1902 state->gprs[NVMM_X64_GPR_RAX] = vmcb->state.rax; 1903 state->gprs[NVMM_X64_GPR_RFLAGS] = vmcb->state.rflags; 1904 } 1905 1906 if (flags & NVMM_X64_STATE_CRS) { 1907 state->crs[NVMM_X64_CR_CR0] = vmcb->state.cr0; 1908 state->crs[NVMM_X64_CR_CR2] = vmcb->state.cr2; 1909 state->crs[NVMM_X64_CR_CR3] = vmcb->state.cr3; 1910 state->crs[NVMM_X64_CR_CR4] = vmcb->state.cr4; 1911 state->crs[NVMM_X64_CR_CR8] = __SHIFTOUT(vmcb->ctrl.v, 1912 VMCB_CTRL_V_TPR); 1913 state->crs[NVMM_X64_CR_XCR0] = cpudata->gxcr0; 1914 } 1915 1916 CTASSERT(sizeof(cpudata->drs) == sizeof(state->drs)); 1917 if (flags & NVMM_X64_STATE_DRS) { 1918 memcpy(state->drs, cpudata->drs, sizeof(state->drs)); 1919 1920 state->drs[NVMM_X64_DR_DR6] = vmcb->state.dr6; 1921 state->drs[NVMM_X64_DR_DR7] = vmcb->state.dr7; 1922 } 1923 1924 if (flags & NVMM_X64_STATE_MSRS) { 1925 state->msrs[NVMM_X64_MSR_EFER] = vmcb->state.efer; 1926 state->msrs[NVMM_X64_MSR_STAR] = vmcb->state.star; 1927 state->msrs[NVMM_X64_MSR_LSTAR] = vmcb->state.lstar; 1928 state->msrs[NVMM_X64_MSR_CSTAR] = vmcb->state.cstar; 1929 state->msrs[NVMM_X64_MSR_SFMASK] = vmcb->state.sfmask; 1930 state->msrs[NVMM_X64_MSR_KERNELGSBASE] = 1931 vmcb->state.kernelgsbase; 1932 state->msrs[NVMM_X64_MSR_SYSENTER_CS] = 1933 vmcb->state.sysenter_cs; 1934 state->msrs[NVMM_X64_MSR_SYSENTER_ESP] = 1935 vmcb->state.sysenter_esp; 1936 state->msrs[NVMM_X64_MSR_SYSENTER_EIP] = 1937 vmcb->state.sysenter_eip; 1938 state->msrs[NVMM_X64_MSR_PAT] = vmcb->state.g_pat; 1939 1940 /* Hide SVME. */ 1941 state->msrs[NVMM_X64_MSR_EFER] &= ~EFER_SVME; 1942 } 1943 1944 if (flags & NVMM_X64_STATE_MISC) { 1945 state->misc[NVMM_X64_MISC_CPL] = vmcb->state.cpl; 1946 1947 state->misc[NVMM_X64_MISC_INT_SHADOW] = 1948 (vmcb->ctrl.intr & VMCB_CTRL_INTR_SHADOW) != 0; 1949 state->misc[NVMM_X64_MISC_INT_WINDOW_EXIT] = 1950 cpudata->int_window_exit; 1951 state->misc[NVMM_X64_MISC_NMI_WINDOW_EXIT] = 1952 cpudata->nmi_window_exit; 1953 } 1954 1955 CTASSERT(sizeof(cpudata->gfpu.xsh_fxsave) == sizeof(state->fpu)); 1956 if (flags & NVMM_X64_STATE_FPU) { 1957 memcpy(&state->fpu, cpudata->gfpu.xsh_fxsave, 1958 sizeof(state->fpu)); 1959 } 1960 } 1961 1962 /* -------------------------------------------------------------------------- */ 1963 1964 static void 1965 svm_tlb_flush(struct pmap *pm) 1966 { 1967 struct nvmm_machine *mach = pm->pm_data; 1968 struct svm_cpudata *cpudata; 1969 struct nvmm_cpu *vcpu; 1970 int error; 1971 size_t i; 1972 1973 /* Request TLB flushes. */ 1974 for (i = 0; i < NVMM_MAX_VCPUS; i++) { 1975 error = nvmm_vcpu_get(mach, i, &vcpu); 1976 if (error) 1977 continue; 1978 cpudata = vcpu->cpudata; 1979 cpudata->tlb_want_flush = true; 1980 nvmm_vcpu_put(vcpu); 1981 } 1982 } 1983 1984 static void 1985 svm_machine_create(struct nvmm_machine *mach) 1986 { 1987 /* Fill in pmap info. */ 1988 mach->vm->vm_map.pmap->pm_data = (void *)mach; 1989 mach->vm->vm_map.pmap->pm_tlb_flush = svm_tlb_flush; 1990 1991 mach->machdata = kmem_zalloc(sizeof(struct svm_machdata), KM_SLEEP); 1992 } 1993 1994 static void 1995 svm_machine_destroy(struct nvmm_machine *mach) 1996 { 1997 kmem_free(mach->machdata, sizeof(struct svm_machdata)); 1998 } 1999 2000 static int 2001 svm_machine_configure(struct nvmm_machine *mach, uint64_t op, void *data) 2002 { 2003 struct nvmm_x86_conf_cpuid *cpuid = data; 2004 struct svm_machdata *machdata = (struct svm_machdata *)mach->machdata; 2005 size_t i; 2006 2007 if (__predict_false(op != NVMM_X86_CONF_CPUID)) { 2008 return EINVAL; 2009 } 2010 2011 if (__predict_false((cpuid->set.eax & cpuid->del.eax) || 2012 (cpuid->set.ebx & cpuid->del.ebx) || 2013 (cpuid->set.ecx & cpuid->del.ecx) || 2014 (cpuid->set.edx & cpuid->del.edx))) { 2015 return EINVAL; 2016 } 2017 2018 /* If already here, replace. */ 2019 for (i = 0; i < SVM_NCPUIDS; i++) { 2020 if (!machdata->cpuidpresent[i]) { 2021 continue; 2022 } 2023 if (machdata->cpuid[i].leaf == cpuid->leaf) { 2024 memcpy(&machdata->cpuid[i], cpuid, 2025 sizeof(struct nvmm_x86_conf_cpuid)); 2026 return 0; 2027 } 2028 } 2029 2030 /* Not here, insert. */ 2031 for (i = 0; i < SVM_NCPUIDS; i++) { 2032 if (!machdata->cpuidpresent[i]) { 2033 machdata->cpuidpresent[i] = true; 2034 memcpy(&machdata->cpuid[i], cpuid, 2035 sizeof(struct nvmm_x86_conf_cpuid)); 2036 return 0; 2037 } 2038 } 2039 2040 return ENOBUFS; 2041 } 2042 2043 /* -------------------------------------------------------------------------- */ 2044 2045 static bool 2046 svm_ident(void) 2047 { 2048 u_int descs[4]; 2049 uint64_t msr; 2050 2051 if (cpu_vendor != CPUVENDOR_AMD) { 2052 return false; 2053 } 2054 if (!(cpu_feature[3] & CPUID_SVM)) { 2055 return false; 2056 } 2057 2058 if (curcpu()->ci_max_ext_cpuid < 0x8000000a) { 2059 return false; 2060 } 2061 x86_cpuid(0x8000000a, descs); 2062 2063 /* Want Nested Paging. */ 2064 if (!(descs[3] & CPUID_AMD_SVM_NP)) { 2065 return false; 2066 } 2067 2068 /* Want nRIP. */ 2069 if (!(descs[3] & CPUID_AMD_SVM_NRIPS)) { 2070 return false; 2071 } 2072 2073 svm_decode_assist = (descs[3] & CPUID_AMD_SVM_DecodeAssist) != 0; 2074 2075 msr = rdmsr(MSR_VMCR); 2076 if ((msr & VMCR_SVMED) && (msr & VMCR_LOCK)) { 2077 return false; 2078 } 2079 2080 return true; 2081 } 2082 2083 static void 2084 svm_init_asid(uint32_t maxasid) 2085 { 2086 size_t i, j, allocsz; 2087 2088 mutex_init(&svm_asidlock, MUTEX_DEFAULT, IPL_NONE); 2089 2090 /* Arbitrarily limit. */ 2091 maxasid = uimin(maxasid, 8192); 2092 2093 svm_maxasid = maxasid; 2094 allocsz = roundup(maxasid, 8) / 8; 2095 svm_asidmap = kmem_zalloc(allocsz, KM_SLEEP); 2096 2097 /* ASID 0 is reserved for the host. */ 2098 svm_asidmap[0] |= __BIT(0); 2099 2100 /* ASID n-1 is special, we share it. */ 2101 i = (maxasid - 1) / 8; 2102 j = (maxasid - 1) % 8; 2103 svm_asidmap[i] |= __BIT(j); 2104 } 2105 2106 static void 2107 svm_change_cpu(void *arg1, void *arg2) 2108 { 2109 bool enable = (bool)arg1; 2110 uint64_t msr; 2111 2112 msr = rdmsr(MSR_VMCR); 2113 if (msr & VMCR_SVMED) { 2114 wrmsr(MSR_VMCR, msr & ~VMCR_SVMED); 2115 } 2116 2117 if (!enable) { 2118 wrmsr(MSR_VM_HSAVE_PA, 0); 2119 } 2120 2121 msr = rdmsr(MSR_EFER); 2122 if (enable) { 2123 msr |= EFER_SVME; 2124 } else { 2125 msr &= ~EFER_SVME; 2126 } 2127 wrmsr(MSR_EFER, msr); 2128 2129 if (enable) { 2130 wrmsr(MSR_VM_HSAVE_PA, hsave[cpu_index(curcpu())].pa); 2131 } 2132 } 2133 2134 static void 2135 svm_init(void) 2136 { 2137 CPU_INFO_ITERATOR cii; 2138 struct cpu_info *ci; 2139 struct vm_page *pg; 2140 u_int descs[4]; 2141 uint64_t xc; 2142 2143 x86_cpuid(0x8000000a, descs); 2144 2145 /* The guest TLB flush command. */ 2146 if (descs[3] & CPUID_AMD_SVM_FlushByASID) { 2147 svm_ctrl_tlb_flush = VMCB_CTRL_TLB_CTRL_FLUSH_GUEST; 2148 } else { 2149 svm_ctrl_tlb_flush = VMCB_CTRL_TLB_CTRL_FLUSH_ALL; 2150 } 2151 2152 /* Init the ASID. */ 2153 svm_init_asid(descs[1]); 2154 2155 /* Init the XCR0 mask. */ 2156 svm_xcr0_mask = SVM_XCR0_MASK_DEFAULT & x86_xsave_features; 2157 2158 memset(hsave, 0, sizeof(hsave)); 2159 for (CPU_INFO_FOREACH(cii, ci)) { 2160 pg = uvm_pagealloc(NULL, 0, NULL, UVM_PGA_ZERO); 2161 hsave[cpu_index(ci)].pa = VM_PAGE_TO_PHYS(pg); 2162 } 2163 2164 xc = xc_broadcast(0, svm_change_cpu, (void *)true, NULL); 2165 xc_wait(xc); 2166 } 2167 2168 static void 2169 svm_fini_asid(void) 2170 { 2171 size_t allocsz; 2172 2173 allocsz = roundup(svm_maxasid, 8) / 8; 2174 kmem_free(svm_asidmap, allocsz); 2175 2176 mutex_destroy(&svm_asidlock); 2177 } 2178 2179 static void 2180 svm_fini(void) 2181 { 2182 uint64_t xc; 2183 size_t i; 2184 2185 xc = xc_broadcast(0, svm_change_cpu, (void *)false, NULL); 2186 xc_wait(xc); 2187 2188 for (i = 0; i < MAXCPUS; i++) { 2189 if (hsave[i].pa != 0) 2190 uvm_pagefree(PHYS_TO_VM_PAGE(hsave[i].pa)); 2191 } 2192 2193 svm_fini_asid(); 2194 } 2195 2196 static void 2197 svm_capability(struct nvmm_capability *cap) 2198 { 2199 cap->u.x86.xcr0_mask = svm_xcr0_mask; 2200 cap->u.x86.mxcsr_mask = x86_fpu_mxcsr_mask; 2201 cap->u.x86.conf_cpuid_maxops = SVM_NCPUIDS; 2202 } 2203 2204 const struct nvmm_impl nvmm_x86_svm = { 2205 .ident = svm_ident, 2206 .init = svm_init, 2207 .fini = svm_fini, 2208 .capability = svm_capability, 2209 .conf_max = NVMM_X86_NCONF, 2210 .conf_sizes = svm_conf_sizes, 2211 .state_size = sizeof(struct nvmm_x64_state), 2212 .machine_create = svm_machine_create, 2213 .machine_destroy = svm_machine_destroy, 2214 .machine_configure = svm_machine_configure, 2215 .vcpu_create = svm_vcpu_create, 2216 .vcpu_destroy = svm_vcpu_destroy, 2217 .vcpu_setstate = svm_vcpu_setstate, 2218 .vcpu_getstate = svm_vcpu_getstate, 2219 .vcpu_inject = svm_vcpu_inject, 2220 .vcpu_run = svm_vcpu_run 2221 }; 2222
Indexes created Sat Oct 25 16:10:12 GMT 2025