nvmm_x86_svm.c revision 1.24
1 /* $NetBSD: nvmm_x86_svm.c,v 1.24 2019/02/15 13:17:05 maxv Exp $ */ 2 3 /* 4 * Copyright (c) 2018 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Maxime Villard. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: nvmm_x86_svm.c,v 1.24 2019/02/15 13:17:05 maxv Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/kmem.h> 39 #include <sys/cpu.h> 40 #include <sys/xcall.h> 41 42 #include <uvm/uvm.h> 43 #include <uvm/uvm_page.h> 44 45 #include <x86/cputypes.h> 46 #include <x86/specialreg.h> 47 #include <x86/pmap.h> 48 #include <x86/dbregs.h> 49 #include <x86/cpu_counter.h> 50 #include <machine/cpuvar.h> 51 52 #include <dev/nvmm/nvmm.h> 53 #include <dev/nvmm/nvmm_internal.h> 54 #include <dev/nvmm/x86/nvmm_x86.h> 55 56 int svm_vmrun(paddr_t, uint64_t *); 57 58 #define MSR_VM_HSAVE_PA 0xC0010117 59 60 /* -------------------------------------------------------------------------- */ 61 62 #define VMCB_EXITCODE_CR0_READ 0x0000 63 #define VMCB_EXITCODE_CR1_READ 0x0001 64 #define VMCB_EXITCODE_CR2_READ 0x0002 65 #define VMCB_EXITCODE_CR3_READ 0x0003 66 #define VMCB_EXITCODE_CR4_READ 0x0004 67 #define VMCB_EXITCODE_CR5_READ 0x0005 68 #define VMCB_EXITCODE_CR6_READ 0x0006 69 #define VMCB_EXITCODE_CR7_READ 0x0007 70 #define VMCB_EXITCODE_CR8_READ 0x0008 71 #define VMCB_EXITCODE_CR9_READ 0x0009 72 #define VMCB_EXITCODE_CR10_READ 0x000A 73 #define VMCB_EXITCODE_CR11_READ 0x000B 74 #define VMCB_EXITCODE_CR12_READ 0x000C 75 #define VMCB_EXITCODE_CR13_READ 0x000D 76 #define VMCB_EXITCODE_CR14_READ 0x000E 77 #define VMCB_EXITCODE_CR15_READ 0x000F 78 #define VMCB_EXITCODE_CR0_WRITE 0x0010 79 #define VMCB_EXITCODE_CR1_WRITE 0x0011 80 #define VMCB_EXITCODE_CR2_WRITE 0x0012 81 #define VMCB_EXITCODE_CR3_WRITE 0x0013 82 #define VMCB_EXITCODE_CR4_WRITE 0x0014 83 #define VMCB_EXITCODE_CR5_WRITE 0x0015 84 #define VMCB_EXITCODE_CR6_WRITE 0x0016 85 #define VMCB_EXITCODE_CR7_WRITE 0x0017 86 #define VMCB_EXITCODE_CR8_WRITE 0x0018 87 #define VMCB_EXITCODE_CR9_WRITE 0x0019 88 #define VMCB_EXITCODE_CR10_WRITE 0x001A 89 #define VMCB_EXITCODE_CR11_WRITE 0x001B 90 #define VMCB_EXITCODE_CR12_WRITE 0x001C 91 #define VMCB_EXITCODE_CR13_WRITE 0x001D 92 #define VMCB_EXITCODE_CR14_WRITE 0x001E 93 #define VMCB_EXITCODE_CR15_WRITE 0x001F 94 #define VMCB_EXITCODE_DR0_READ 0x0020 95 #define VMCB_EXITCODE_DR1_READ 0x0021 96 #define VMCB_EXITCODE_DR2_READ 0x0022 97 #define VMCB_EXITCODE_DR3_READ 0x0023 98 #define VMCB_EXITCODE_DR4_READ 0x0024 99 #define VMCB_EXITCODE_DR5_READ 0x0025 100 #define VMCB_EXITCODE_DR6_READ 0x0026 101 #define VMCB_EXITCODE_DR7_READ 0x0027 102 #define VMCB_EXITCODE_DR8_READ 0x0028 103 #define VMCB_EXITCODE_DR9_READ 0x0029 104 #define VMCB_EXITCODE_DR10_READ 0x002A 105 #define VMCB_EXITCODE_DR11_READ 0x002B 106 #define VMCB_EXITCODE_DR12_READ 0x002C 107 #define VMCB_EXITCODE_DR13_READ 0x002D 108 #define VMCB_EXITCODE_DR14_READ 0x002E 109 #define VMCB_EXITCODE_DR15_READ 0x002F 110 #define VMCB_EXITCODE_DR0_WRITE 0x0030 111 #define VMCB_EXITCODE_DR1_WRITE 0x0031 112 #define VMCB_EXITCODE_DR2_WRITE 0x0032 113 #define VMCB_EXITCODE_DR3_WRITE 0x0033 114 #define VMCB_EXITCODE_DR4_WRITE 0x0034 115 #define VMCB_EXITCODE_DR5_WRITE 0x0035 116 #define VMCB_EXITCODE_DR6_WRITE 0x0036 117 #define VMCB_EXITCODE_DR7_WRITE 0x0037 118 #define VMCB_EXITCODE_DR8_WRITE 0x0038 119 #define VMCB_EXITCODE_DR9_WRITE 0x0039 120 #define VMCB_EXITCODE_DR10_WRITE 0x003A 121 #define VMCB_EXITCODE_DR11_WRITE 0x003B 122 #define VMCB_EXITCODE_DR12_WRITE 0x003C 123 #define VMCB_EXITCODE_DR13_WRITE 0x003D 124 #define VMCB_EXITCODE_DR14_WRITE 0x003E 125 #define VMCB_EXITCODE_DR15_WRITE 0x003F 126 #define VMCB_EXITCODE_EXCP0 0x0040 127 #define VMCB_EXITCODE_EXCP1 0x0041 128 #define VMCB_EXITCODE_EXCP2 0x0042 129 #define VMCB_EXITCODE_EXCP3 0x0043 130 #define VMCB_EXITCODE_EXCP4 0x0044 131 #define VMCB_EXITCODE_EXCP5 0x0045 132 #define VMCB_EXITCODE_EXCP6 0x0046 133 #define VMCB_EXITCODE_EXCP7 0x0047 134 #define VMCB_EXITCODE_EXCP8 0x0048 135 #define VMCB_EXITCODE_EXCP9 0x0049 136 #define VMCB_EXITCODE_EXCP10 0x004A 137 #define VMCB_EXITCODE_EXCP11 0x004B 138 #define VMCB_EXITCODE_EXCP12 0x004C 139 #define VMCB_EXITCODE_EXCP13 0x004D 140 #define VMCB_EXITCODE_EXCP14 0x004E 141 #define VMCB_EXITCODE_EXCP15 0x004F 142 #define VMCB_EXITCODE_EXCP16 0x0050 143 #define VMCB_EXITCODE_EXCP17 0x0051 144 #define VMCB_EXITCODE_EXCP18 0x0052 145 #define VMCB_EXITCODE_EXCP19 0x0053 146 #define VMCB_EXITCODE_EXCP20 0x0054 147 #define VMCB_EXITCODE_EXCP21 0x0055 148 #define VMCB_EXITCODE_EXCP22 0x0056 149 #define VMCB_EXITCODE_EXCP23 0x0057 150 #define VMCB_EXITCODE_EXCP24 0x0058 151 #define VMCB_EXITCODE_EXCP25 0x0059 152 #define VMCB_EXITCODE_EXCP26 0x005A 153 #define VMCB_EXITCODE_EXCP27 0x005B 154 #define VMCB_EXITCODE_EXCP28 0x005C 155 #define VMCB_EXITCODE_EXCP29 0x005D 156 #define VMCB_EXITCODE_EXCP30 0x005E 157 #define VMCB_EXITCODE_EXCP31 0x005F 158 #define VMCB_EXITCODE_INTR 0x0060 159 #define VMCB_EXITCODE_NMI 0x0061 160 #define VMCB_EXITCODE_SMI 0x0062 161 #define VMCB_EXITCODE_INIT 0x0063 162 #define VMCB_EXITCODE_VINTR 0x0064 163 #define VMCB_EXITCODE_CR0_SEL_WRITE 0x0065 164 #define VMCB_EXITCODE_IDTR_READ 0x0066 165 #define VMCB_EXITCODE_GDTR_READ 0x0067 166 #define VMCB_EXITCODE_LDTR_READ 0x0068 167 #define VMCB_EXITCODE_TR_READ 0x0069 168 #define VMCB_EXITCODE_IDTR_WRITE 0x006A 169 #define VMCB_EXITCODE_GDTR_WRITE 0x006B 170 #define VMCB_EXITCODE_LDTR_WRITE 0x006C 171 #define VMCB_EXITCODE_TR_WRITE 0x006D 172 #define VMCB_EXITCODE_RDTSC 0x006E 173 #define VMCB_EXITCODE_RDPMC 0x006F 174 #define VMCB_EXITCODE_PUSHF 0x0070 175 #define VMCB_EXITCODE_POPF 0x0071 176 #define VMCB_EXITCODE_CPUID 0x0072 177 #define VMCB_EXITCODE_RSM 0x0073 178 #define VMCB_EXITCODE_IRET 0x0074 179 #define VMCB_EXITCODE_SWINT 0x0075 180 #define VMCB_EXITCODE_INVD 0x0076 181 #define VMCB_EXITCODE_PAUSE 0x0077 182 #define VMCB_EXITCODE_HLT 0x0078 183 #define VMCB_EXITCODE_INVLPG 0x0079 184 #define VMCB_EXITCODE_INVLPGA 0x007A 185 #define VMCB_EXITCODE_IOIO 0x007B 186 #define VMCB_EXITCODE_MSR 0x007C 187 #define VMCB_EXITCODE_TASK_SWITCH 0x007D 188 #define VMCB_EXITCODE_FERR_FREEZE 0x007E 189 #define VMCB_EXITCODE_SHUTDOWN 0x007F 190 #define VMCB_EXITCODE_VMRUN 0x0080 191 #define VMCB_EXITCODE_VMMCALL 0x0081 192 #define VMCB_EXITCODE_VMLOAD 0x0082 193 #define VMCB_EXITCODE_VMSAVE 0x0083 194 #define VMCB_EXITCODE_STGI 0x0084 195 #define VMCB_EXITCODE_CLGI 0x0085 196 #define VMCB_EXITCODE_SKINIT 0x0086 197 #define VMCB_EXITCODE_RDTSCP 0x0087 198 #define VMCB_EXITCODE_ICEBP 0x0088 199 #define VMCB_EXITCODE_WBINVD 0x0089 200 #define VMCB_EXITCODE_MONITOR 0x008A 201 #define VMCB_EXITCODE_MWAIT 0x008B 202 #define VMCB_EXITCODE_MWAIT_CONDITIONAL 0x008C 203 #define VMCB_EXITCODE_XSETBV 0x008D 204 #define VMCB_EXITCODE_EFER_WRITE_TRAP 0x008F 205 #define VMCB_EXITCODE_CR0_WRITE_TRAP 0x0090 206 #define VMCB_EXITCODE_CR1_WRITE_TRAP 0x0091 207 #define VMCB_EXITCODE_CR2_WRITE_TRAP 0x0092 208 #define VMCB_EXITCODE_CR3_WRITE_TRAP 0x0093 209 #define VMCB_EXITCODE_CR4_WRITE_TRAP 0x0094 210 #define VMCB_EXITCODE_CR5_WRITE_TRAP 0x0095 211 #define VMCB_EXITCODE_CR6_WRITE_TRAP 0x0096 212 #define VMCB_EXITCODE_CR7_WRITE_TRAP 0x0097 213 #define VMCB_EXITCODE_CR8_WRITE_TRAP 0x0098 214 #define VMCB_EXITCODE_CR9_WRITE_TRAP 0x0099 215 #define VMCB_EXITCODE_CR10_WRITE_TRAP 0x009A 216 #define VMCB_EXITCODE_CR11_WRITE_TRAP 0x009B 217 #define VMCB_EXITCODE_CR12_WRITE_TRAP 0x009C 218 #define VMCB_EXITCODE_CR13_WRITE_TRAP 0x009D 219 #define VMCB_EXITCODE_CR14_WRITE_TRAP 0x009E 220 #define VMCB_EXITCODE_CR15_WRITE_TRAP 0x009F 221 #define VMCB_EXITCODE_NPF 0x0400 222 #define VMCB_EXITCODE_AVIC_INCOMP_IPI 0x0401 223 #define VMCB_EXITCODE_AVIC_NOACCEL 0x0402 224 #define VMCB_EXITCODE_VMGEXIT 0x0403 225 #define VMCB_EXITCODE_INVALID -1 226 227 /* -------------------------------------------------------------------------- */ 228 229 struct vmcb_ctrl { 230 uint32_t intercept_cr; 231 #define VMCB_CTRL_INTERCEPT_RCR(x) __BIT( 0 + x) 232 #define VMCB_CTRL_INTERCEPT_WCR(x) __BIT(16 + x) 233 234 uint32_t intercept_dr; 235 #define VMCB_CTRL_INTERCEPT_RDR(x) __BIT( 0 + x) 236 #define VMCB_CTRL_INTERCEPT_WDR(x) __BIT(16 + x) 237 238 uint32_t intercept_vec; 239 #define VMCB_CTRL_INTERCEPT_VEC(x) __BIT(x) 240 241 uint32_t intercept_misc1; 242 #define VMCB_CTRL_INTERCEPT_INTR __BIT(0) 243 #define VMCB_CTRL_INTERCEPT_NMI __BIT(1) 244 #define VMCB_CTRL_INTERCEPT_SMI __BIT(2) 245 #define VMCB_CTRL_INTERCEPT_INIT __BIT(3) 246 #define VMCB_CTRL_INTERCEPT_VINTR __BIT(4) 247 #define VMCB_CTRL_INTERCEPT_CR0_SPEC __BIT(5) 248 #define VMCB_CTRL_INTERCEPT_RIDTR __BIT(6) 249 #define VMCB_CTRL_INTERCEPT_RGDTR __BIT(7) 250 #define VMCB_CTRL_INTERCEPT_RLDTR __BIT(8) 251 #define VMCB_CTRL_INTERCEPT_RTR __BIT(9) 252 #define VMCB_CTRL_INTERCEPT_WIDTR __BIT(10) 253 #define VMCB_CTRL_INTERCEPT_WGDTR __BIT(11) 254 #define VMCB_CTRL_INTERCEPT_WLDTR __BIT(12) 255 #define VMCB_CTRL_INTERCEPT_WTR __BIT(13) 256 #define VMCB_CTRL_INTERCEPT_RDTSC __BIT(14) 257 #define VMCB_CTRL_INTERCEPT_RDPMC __BIT(15) 258 #define VMCB_CTRL_INTERCEPT_PUSHF __BIT(16) 259 #define VMCB_CTRL_INTERCEPT_POPF __BIT(17) 260 #define VMCB_CTRL_INTERCEPT_CPUID __BIT(18) 261 #define VMCB_CTRL_INTERCEPT_RSM __BIT(19) 262 #define VMCB_CTRL_INTERCEPT_IRET __BIT(20) 263 #define VMCB_CTRL_INTERCEPT_INTN __BIT(21) 264 #define VMCB_CTRL_INTERCEPT_INVD __BIT(22) 265 #define VMCB_CTRL_INTERCEPT_PAUSE __BIT(23) 266 #define VMCB_CTRL_INTERCEPT_HLT __BIT(24) 267 #define VMCB_CTRL_INTERCEPT_INVLPG __BIT(25) 268 #define VMCB_CTRL_INTERCEPT_INVLPGA __BIT(26) 269 #define VMCB_CTRL_INTERCEPT_IOIO_PROT __BIT(27) 270 #define VMCB_CTRL_INTERCEPT_MSR_PROT __BIT(28) 271 #define VMCB_CTRL_INTERCEPT_TASKSW __BIT(29) 272 #define VMCB_CTRL_INTERCEPT_FERR_FREEZE __BIT(30) 273 #define VMCB_CTRL_INTERCEPT_SHUTDOWN __BIT(31) 274 275 uint32_t intercept_misc2; 276 #define VMCB_CTRL_INTERCEPT_VMRUN __BIT(0) 277 #define VMCB_CTRL_INTERCEPT_VMMCALL __BIT(1) 278 #define VMCB_CTRL_INTERCEPT_VMLOAD __BIT(2) 279 #define VMCB_CTRL_INTERCEPT_VMSAVE __BIT(3) 280 #define VMCB_CTRL_INTERCEPT_STGI __BIT(4) 281 #define VMCB_CTRL_INTERCEPT_CLGI __BIT(5) 282 #define VMCB_CTRL_INTERCEPT_SKINIT __BIT(6) 283 #define VMCB_CTRL_INTERCEPT_RDTSCP __BIT(7) 284 #define VMCB_CTRL_INTERCEPT_ICEBP __BIT(8) 285 #define VMCB_CTRL_INTERCEPT_WBINVD __BIT(9) 286 #define VMCB_CTRL_INTERCEPT_MONITOR __BIT(10) 287 #define VMCB_CTRL_INTERCEPT_MWAIT __BIT(12) 288 #define VMCB_CTRL_INTERCEPT_XSETBV __BIT(13) 289 #define VMCB_CTRL_INTERCEPT_EFER_SPEC __BIT(15) 290 #define VMCB_CTRL_INTERCEPT_WCR_SPEC(x) __BIT(16 + x) 291 292 uint8_t rsvd1[40]; 293 uint16_t pause_filt_thresh; 294 uint16_t pause_filt_cnt; 295 uint64_t iopm_base_pa; 296 uint64_t msrpm_base_pa; 297 uint64_t tsc_offset; 298 uint32_t guest_asid; 299 300 uint32_t tlb_ctrl; 301 #define VMCB_CTRL_TLB_CTRL_FLUSH_ALL 0x01 302 #define VMCB_CTRL_TLB_CTRL_FLUSH_GUEST 0x03 303 #define VMCB_CTRL_TLB_CTRL_FLUSH_GUEST_NONGLOBAL 0x07 304 305 uint64_t v; 306 #define VMCB_CTRL_V_TPR __BITS(7,0) 307 #define VMCB_CTRL_V_IRQ __BIT(8) 308 #define VMCB_CTRL_V_VGIF __BIT(9) 309 #define VMCB_CTRL_V_INTR_PRIO __BITS(19,16) 310 #define VMCB_CTRL_V_IGN_TPR __BIT(20) 311 #define VMCB_CTRL_V_INTR_MASKING __BIT(24) 312 #define VMCB_CTRL_V_GUEST_VGIF __BIT(25) 313 #define VMCB_CTRL_V_AVIC_EN __BIT(31) 314 #define VMCB_CTRL_V_INTR_VECTOR __BITS(39,32) 315 316 uint64_t intr; 317 #define VMCB_CTRL_INTR_SHADOW __BIT(0) 318 319 uint64_t exitcode; 320 uint64_t exitinfo1; 321 uint64_t exitinfo2; 322 323 uint64_t exitintinfo; 324 #define VMCB_CTRL_EXITINTINFO_VECTOR __BITS(7,0) 325 #define VMCB_CTRL_EXITINTINFO_TYPE __BITS(10,8) 326 #define VMCB_CTRL_EXITINTINFO_EV __BIT(11) 327 #define VMCB_CTRL_EXITINTINFO_V __BIT(31) 328 #define VMCB_CTRL_EXITINTINFO_ERRORCODE __BITS(63,32) 329 330 uint64_t enable1; 331 #define VMCB_CTRL_ENABLE_NP __BIT(0) 332 #define VMCB_CTRL_ENABLE_SEV __BIT(1) 333 #define VMCB_CTRL_ENABLE_ES_SEV __BIT(2) 334 335 uint64_t avic; 336 #define VMCB_CTRL_AVIC_APIC_BAR __BITS(51,0) 337 338 uint64_t ghcb; 339 340 uint64_t eventinj; 341 #define VMCB_CTRL_EVENTINJ_VECTOR __BITS(7,0) 342 #define VMCB_CTRL_EVENTINJ_TYPE __BITS(10,8) 343 #define VMCB_CTRL_EVENTINJ_EV __BIT(11) 344 #define VMCB_CTRL_EVENTINJ_V __BIT(31) 345 #define VMCB_CTRL_EVENTINJ_ERRORCODE __BITS(63,32) 346 347 uint64_t n_cr3; 348 349 uint64_t enable2; 350 #define VMCB_CTRL_ENABLE_LBR __BIT(0) 351 #define VMCB_CTRL_ENABLE_VVMSAVE __BIT(1) 352 353 uint32_t vmcb_clean; 354 #define VMCB_CTRL_VMCB_CLEAN_I __BIT(0) 355 #define VMCB_CTRL_VMCB_CLEAN_IOPM __BIT(1) 356 #define VMCB_CTRL_VMCB_CLEAN_ASID __BIT(2) 357 #define VMCB_CTRL_VMCB_CLEAN_TPR __BIT(3) 358 #define VMCB_CTRL_VMCB_CLEAN_NP __BIT(4) 359 #define VMCB_CTRL_VMCB_CLEAN_CR __BIT(5) 360 #define VMCB_CTRL_VMCB_CLEAN_DR __BIT(6) 361 #define VMCB_CTRL_VMCB_CLEAN_DT __BIT(7) 362 #define VMCB_CTRL_VMCB_CLEAN_SEG __BIT(8) 363 #define VMCB_CTRL_VMCB_CLEAN_CR2 __BIT(9) 364 #define VMCB_CTRL_VMCB_CLEAN_LBR __BIT(10) 365 #define VMCB_CTRL_VMCB_CLEAN_AVIC __BIT(11) 366 367 uint32_t rsvd2; 368 uint64_t nrip; 369 uint8_t inst_len; 370 uint8_t inst_bytes[15]; 371 uint64_t avic_abpp; 372 uint64_t rsvd3; 373 uint64_t avic_ltp; 374 375 uint64_t avic_phys; 376 #define VMCB_CTRL_AVIC_PHYS_TABLE_PTR __BITS(51,12) 377 #define VMCB_CTRL_AVIC_PHYS_MAX_INDEX __BITS(7,0) 378 379 uint64_t rsvd4; 380 uint64_t vmcb_ptr; 381 382 uint8_t pad[752]; 383 } __packed; 384 385 CTASSERT(sizeof(struct vmcb_ctrl) == 1024); 386 387 struct vmcb_segment { 388 uint16_t selector; 389 uint16_t attrib; /* hidden */ 390 uint32_t limit; /* hidden */ 391 uint64_t base; /* hidden */ 392 } __packed; 393 394 CTASSERT(sizeof(struct vmcb_segment) == 16); 395 396 struct vmcb_state { 397 struct vmcb_segment es; 398 struct vmcb_segment cs; 399 struct vmcb_segment ss; 400 struct vmcb_segment ds; 401 struct vmcb_segment fs; 402 struct vmcb_segment gs; 403 struct vmcb_segment gdt; 404 struct vmcb_segment ldt; 405 struct vmcb_segment idt; 406 struct vmcb_segment tr; 407 uint8_t rsvd1[43]; 408 uint8_t cpl; 409 uint8_t rsvd2[4]; 410 uint64_t efer; 411 uint8_t rsvd3[112]; 412 uint64_t cr4; 413 uint64_t cr3; 414 uint64_t cr0; 415 uint64_t dr7; 416 uint64_t dr6; 417 uint64_t rflags; 418 uint64_t rip; 419 uint8_t rsvd4[88]; 420 uint64_t rsp; 421 uint8_t rsvd5[24]; 422 uint64_t rax; 423 uint64_t star; 424 uint64_t lstar; 425 uint64_t cstar; 426 uint64_t sfmask; 427 uint64_t kernelgsbase; 428 uint64_t sysenter_cs; 429 uint64_t sysenter_esp; 430 uint64_t sysenter_eip; 431 uint64_t cr2; 432 uint8_t rsvd6[32]; 433 uint64_t g_pat; 434 uint64_t dbgctl; 435 uint64_t br_from; 436 uint64_t br_to; 437 uint64_t int_from; 438 uint64_t int_to; 439 uint8_t pad[2408]; 440 } __packed; 441 442 CTASSERT(sizeof(struct vmcb_state) == 0xC00); 443 444 struct vmcb { 445 struct vmcb_ctrl ctrl; 446 struct vmcb_state state; 447 } __packed; 448 449 CTASSERT(sizeof(struct vmcb) == PAGE_SIZE); 450 CTASSERT(offsetof(struct vmcb, state) == 0x400); 451 452 /* -------------------------------------------------------------------------- */ 453 454 struct svm_hsave { 455 paddr_t pa; 456 }; 457 458 static struct svm_hsave hsave[MAXCPUS]; 459 460 static uint8_t *svm_asidmap __read_mostly; 461 static uint32_t svm_maxasid __read_mostly; 462 static kmutex_t svm_asidlock __cacheline_aligned; 463 464 static bool svm_decode_assist __read_mostly; 465 static uint32_t svm_ctrl_tlb_flush __read_mostly; 466 467 #define SVM_XCR0_MASK_DEFAULT (XCR0_X87|XCR0_SSE) 468 static uint64_t svm_xcr0_mask __read_mostly; 469 470 #define SVM_NCPUIDS 32 471 472 #define VMCB_NPAGES 1 473 474 #define MSRBM_NPAGES 2 475 #define MSRBM_SIZE (MSRBM_NPAGES * PAGE_SIZE) 476 477 #define IOBM_NPAGES 3 478 #define IOBM_SIZE (IOBM_NPAGES * PAGE_SIZE) 479 480 /* Does not include EFER_LMSLE. */ 481 #define EFER_VALID \ 482 (EFER_SCE|EFER_LME|EFER_LMA|EFER_NXE|EFER_SVME|EFER_FFXSR|EFER_TCE) 483 484 #define EFER_TLB_FLUSH \ 485 (EFER_NXE|EFER_LMA|EFER_LME) 486 #define CR0_TLB_FLUSH \ 487 (CR0_PG|CR0_WP|CR0_CD|CR0_NW) 488 #define CR4_TLB_FLUSH \ 489 (CR4_PGE|CR4_PAE|CR4_PSE) 490 491 /* -------------------------------------------------------------------------- */ 492 493 struct svm_machdata { 494 bool cpuidpresent[SVM_NCPUIDS]; 495 struct nvmm_x86_conf_cpuid cpuid[SVM_NCPUIDS]; 496 }; 497 498 static const size_t svm_conf_sizes[NVMM_X86_NCONF] = { 499 [NVMM_X86_CONF_CPUID] = sizeof(struct nvmm_x86_conf_cpuid) 500 }; 501 502 struct svm_cpudata { 503 /* General */ 504 bool shared_asid; 505 bool tlb_want_flush; 506 507 /* VMCB */ 508 struct vmcb *vmcb; 509 paddr_t vmcb_pa; 510 511 /* I/O bitmap */ 512 uint8_t *iobm; 513 paddr_t iobm_pa; 514 515 /* MSR bitmap */ 516 uint8_t *msrbm; 517 paddr_t msrbm_pa; 518 519 /* Host state */ 520 uint64_t hxcr0; 521 uint64_t star; 522 uint64_t lstar; 523 uint64_t cstar; 524 uint64_t sfmask; 525 uint64_t fsbase; 526 uint64_t kernelgsbase; 527 bool ts_set; 528 struct xsave_header hfpu __aligned(64); 529 530 /* Event state */ 531 bool int_window_exit; 532 bool nmi_window_exit; 533 534 /* Guest state */ 535 uint64_t gxcr0; 536 uint64_t gprs[NVMM_X64_NGPR]; 537 uint64_t drs[NVMM_X64_NDR]; 538 uint64_t tsc_offset; 539 struct xsave_header gfpu __aligned(64); 540 }; 541 542 static void 543 svm_vmcb_cache_default(struct vmcb *vmcb) 544 { 545 vmcb->ctrl.vmcb_clean = 546 VMCB_CTRL_VMCB_CLEAN_I | 547 VMCB_CTRL_VMCB_CLEAN_IOPM | 548 VMCB_CTRL_VMCB_CLEAN_ASID | 549 VMCB_CTRL_VMCB_CLEAN_TPR | 550 VMCB_CTRL_VMCB_CLEAN_NP | 551 VMCB_CTRL_VMCB_CLEAN_CR | 552 VMCB_CTRL_VMCB_CLEAN_DR | 553 VMCB_CTRL_VMCB_CLEAN_DT | 554 VMCB_CTRL_VMCB_CLEAN_SEG | 555 VMCB_CTRL_VMCB_CLEAN_CR2 | 556 VMCB_CTRL_VMCB_CLEAN_LBR | 557 VMCB_CTRL_VMCB_CLEAN_AVIC; 558 } 559 560 static void 561 svm_vmcb_cache_update(struct vmcb *vmcb, uint64_t flags) 562 { 563 if (flags & NVMM_X64_STATE_SEGS) { 564 vmcb->ctrl.vmcb_clean &= 565 ~(VMCB_CTRL_VMCB_CLEAN_SEG | VMCB_CTRL_VMCB_CLEAN_DT); 566 } 567 if (flags & NVMM_X64_STATE_CRS) { 568 vmcb->ctrl.vmcb_clean &= 569 ~(VMCB_CTRL_VMCB_CLEAN_CR | VMCB_CTRL_VMCB_CLEAN_CR2 | 570 VMCB_CTRL_VMCB_CLEAN_TPR); 571 } 572 if (flags & NVMM_X64_STATE_DRS) { 573 vmcb->ctrl.vmcb_clean &= ~VMCB_CTRL_VMCB_CLEAN_DR; 574 } 575 if (flags & NVMM_X64_STATE_MSRS) { 576 /* CR for EFER, NP for PAT. */ 577 vmcb->ctrl.vmcb_clean &= 578 ~(VMCB_CTRL_VMCB_CLEAN_CR | VMCB_CTRL_VMCB_CLEAN_NP); 579 } 580 } 581 582 static inline void 583 svm_vmcb_cache_flush(struct vmcb *vmcb, uint64_t flags) 584 { 585 vmcb->ctrl.vmcb_clean &= ~flags; 586 } 587 588 static inline void 589 svm_vmcb_cache_flush_all(struct vmcb *vmcb) 590 { 591 vmcb->ctrl.vmcb_clean = 0; 592 } 593 594 #define SVM_EVENT_TYPE_HW_INT 0 595 #define SVM_EVENT_TYPE_NMI 2 596 #define SVM_EVENT_TYPE_EXC 3 597 #define SVM_EVENT_TYPE_SW_INT 4 598 599 static void 600 svm_event_waitexit_enable(struct nvmm_cpu *vcpu, bool nmi) 601 { 602 struct svm_cpudata *cpudata = vcpu->cpudata; 603 struct vmcb *vmcb = cpudata->vmcb; 604 605 if (nmi) { 606 vmcb->ctrl.intercept_misc1 |= VMCB_CTRL_INTERCEPT_IRET; 607 cpudata->nmi_window_exit = true; 608 } else { 609 vmcb->ctrl.intercept_misc1 |= VMCB_CTRL_INTERCEPT_VINTR; 610 vmcb->ctrl.v |= (VMCB_CTRL_V_IRQ | VMCB_CTRL_V_IGN_TPR); 611 svm_vmcb_cache_flush(vmcb, VMCB_CTRL_VMCB_CLEAN_TPR); 612 cpudata->int_window_exit = true; 613 } 614 615 svm_vmcb_cache_flush(vmcb, VMCB_CTRL_VMCB_CLEAN_I); 616 } 617 618 static void 619 svm_event_waitexit_disable(struct nvmm_cpu *vcpu, bool nmi) 620 { 621 struct svm_cpudata *cpudata = vcpu->cpudata; 622 struct vmcb *vmcb = cpudata->vmcb; 623 624 if (nmi) { 625 vmcb->ctrl.intercept_misc1 &= ~VMCB_CTRL_INTERCEPT_IRET; 626 cpudata->nmi_window_exit = false; 627 } else { 628 vmcb->ctrl.intercept_misc1 &= ~VMCB_CTRL_INTERCEPT_VINTR; 629 vmcb->ctrl.v &= ~(VMCB_CTRL_V_IRQ | VMCB_CTRL_V_IGN_TPR); 630 svm_vmcb_cache_flush(vmcb, VMCB_CTRL_VMCB_CLEAN_TPR); 631 cpudata->int_window_exit = false; 632 } 633 634 svm_vmcb_cache_flush(vmcb, VMCB_CTRL_VMCB_CLEAN_I); 635 } 636 637 static inline int 638 svm_event_has_error(uint64_t vector) 639 { 640 switch (vector) { 641 case 8: /* #DF */ 642 case 10: /* #TS */ 643 case 11: /* #NP */ 644 case 12: /* #SS */ 645 case 13: /* #GP */ 646 case 14: /* #PF */ 647 case 17: /* #AC */ 648 case 30: /* #SX */ 649 return 1; 650 default: 651 return 0; 652 } 653 } 654 655 static int 656 svm_vcpu_inject(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 657 struct nvmm_event *event) 658 { 659 struct svm_cpudata *cpudata = vcpu->cpudata; 660 struct vmcb *vmcb = cpudata->vmcb; 661 int type = 0, err = 0; 662 663 if (event->vector >= 256) { 664 return EINVAL; 665 } 666 667 switch (event->type) { 668 case NVMM_EVENT_INTERRUPT_HW: 669 type = SVM_EVENT_TYPE_HW_INT; 670 if (event->vector == 2) { 671 type = SVM_EVENT_TYPE_NMI; 672 } 673 if (type == SVM_EVENT_TYPE_NMI) { 674 if (cpudata->nmi_window_exit) { 675 return EAGAIN; 676 } 677 svm_event_waitexit_enable(vcpu, true); 678 } else { 679 if (((vmcb->state.rflags & PSL_I) == 0) || 680 ((vmcb->ctrl.intr & VMCB_CTRL_INTR_SHADOW) != 0)) { 681 svm_event_waitexit_enable(vcpu, false); 682 return EAGAIN; 683 } 684 } 685 err = 0; 686 break; 687 case NVMM_EVENT_INTERRUPT_SW: 688 return EINVAL; 689 case NVMM_EVENT_EXCEPTION: 690 type = SVM_EVENT_TYPE_EXC; 691 if (event->vector == 2 || event->vector >= 32) 692 return EINVAL; 693 if (event->vector == 3 || event->vector == 0) 694 return EINVAL; 695 err = svm_event_has_error(event->vector); 696 break; 697 default: 698 return EINVAL; 699 } 700 701 vmcb->ctrl.eventinj = 702 __SHIFTIN(event->vector, VMCB_CTRL_EVENTINJ_VECTOR) | 703 __SHIFTIN(type, VMCB_CTRL_EVENTINJ_TYPE) | 704 __SHIFTIN(err, VMCB_CTRL_EVENTINJ_EV) | 705 __SHIFTIN(1, VMCB_CTRL_EVENTINJ_V) | 706 __SHIFTIN(event->u.error, VMCB_CTRL_EVENTINJ_ERRORCODE); 707 708 return 0; 709 } 710 711 static void 712 svm_inject_ud(struct nvmm_machine *mach, struct nvmm_cpu *vcpu) 713 { 714 struct nvmm_event event; 715 int ret __diagused; 716 717 event.type = NVMM_EVENT_EXCEPTION; 718 event.vector = 6; 719 event.u.error = 0; 720 721 ret = svm_vcpu_inject(mach, vcpu, &event); 722 KASSERT(ret == 0); 723 } 724 725 static void 726 svm_inject_gp(struct nvmm_machine *mach, struct nvmm_cpu *vcpu) 727 { 728 struct nvmm_event event; 729 int ret __diagused; 730 731 event.type = NVMM_EVENT_EXCEPTION; 732 event.vector = 13; 733 event.u.error = 0; 734 735 ret = svm_vcpu_inject(mach, vcpu, &event); 736 KASSERT(ret == 0); 737 } 738 739 static inline void 740 svm_inkernel_advance(struct vmcb *vmcb) 741 { 742 /* 743 * Maybe we should also apply single-stepping and debug exceptions. 744 * Matters for guest-ring3, because it can execute 'cpuid' under a 745 * debugger. 746 */ 747 vmcb->state.rip = vmcb->ctrl.nrip; 748 vmcb->ctrl.intr &= ~VMCB_CTRL_INTR_SHADOW; 749 } 750 751 static void 752 svm_inkernel_handle_cpuid(struct nvmm_cpu *vcpu, uint64_t eax, uint64_t ecx) 753 { 754 struct svm_cpudata *cpudata = vcpu->cpudata; 755 756 switch (eax) { 757 case 0x00000001: /* APIC number in RBX. The rest is tunable. */ 758 cpudata->gprs[NVMM_X64_GPR_RBX] &= ~CPUID_LOCAL_APIC_ID; 759 cpudata->gprs[NVMM_X64_GPR_RBX] |= __SHIFTIN(vcpu->cpuid, 760 CPUID_LOCAL_APIC_ID); 761 break; 762 case 0x0000000D: /* FPU description. Not tunable. */ 763 if (ecx != 0 || svm_xcr0_mask == 0) { 764 break; 765 } 766 cpudata->vmcb->state.rax = svm_xcr0_mask & 0xFFFFFFFF; 767 if (cpudata->gxcr0 & XCR0_SSE) { 768 cpudata->gprs[NVMM_X64_GPR_RBX] = sizeof(struct fxsave); 769 } else { 770 cpudata->gprs[NVMM_X64_GPR_RBX] = sizeof(struct save87); 771 } 772 cpudata->gprs[NVMM_X64_GPR_RBX] += 64; /* XSAVE header */ 773 cpudata->gprs[NVMM_X64_GPR_RCX] = sizeof(struct fxsave); 774 cpudata->gprs[NVMM_X64_GPR_RDX] = svm_xcr0_mask >> 32; 775 break; 776 case 0x40000000: 777 cpudata->gprs[NVMM_X64_GPR_RBX] = 0; 778 cpudata->gprs[NVMM_X64_GPR_RCX] = 0; 779 cpudata->gprs[NVMM_X64_GPR_RDX] = 0; 780 memcpy(&cpudata->gprs[NVMM_X64_GPR_RBX], "___ ", 4); 781 memcpy(&cpudata->gprs[NVMM_X64_GPR_RCX], "NVMM", 4); 782 memcpy(&cpudata->gprs[NVMM_X64_GPR_RDX], " ___", 4); 783 break; 784 case 0x80000001: /* No SVM, no RDTSCP. The rest is tunable. */ 785 cpudata->gprs[NVMM_X64_GPR_RCX] &= ~CPUID_SVM; 786 cpudata->gprs[NVMM_X64_GPR_RDX] &= ~CPUID_RDTSCP; 787 break; 788 default: 789 break; 790 } 791 } 792 793 static void 794 svm_exit_cpuid(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 795 struct nvmm_exit *exit) 796 { 797 struct svm_machdata *machdata = mach->machdata; 798 struct svm_cpudata *cpudata = vcpu->cpudata; 799 struct nvmm_x86_conf_cpuid *cpuid; 800 uint64_t eax, ecx; 801 u_int descs[4]; 802 size_t i; 803 804 eax = cpudata->vmcb->state.rax; 805 ecx = cpudata->gprs[NVMM_X64_GPR_RCX]; 806 x86_cpuid2(eax, ecx, descs); 807 808 cpudata->vmcb->state.rax = descs[0]; 809 cpudata->gprs[NVMM_X64_GPR_RBX] = descs[1]; 810 cpudata->gprs[NVMM_X64_GPR_RCX] = descs[2]; 811 cpudata->gprs[NVMM_X64_GPR_RDX] = descs[3]; 812 813 for (i = 0; i < SVM_NCPUIDS; i++) { 814 cpuid = &machdata->cpuid[i]; 815 if (!machdata->cpuidpresent[i]) { 816 continue; 817 } 818 if (cpuid->leaf != eax) { 819 continue; 820 } 821 822 /* del */ 823 cpudata->vmcb->state.rax &= ~cpuid->del.eax; 824 cpudata->gprs[NVMM_X64_GPR_RBX] &= ~cpuid->del.ebx; 825 cpudata->gprs[NVMM_X64_GPR_RCX] &= ~cpuid->del.ecx; 826 cpudata->gprs[NVMM_X64_GPR_RDX] &= ~cpuid->del.edx; 827 828 /* set */ 829 cpudata->vmcb->state.rax |= cpuid->set.eax; 830 cpudata->gprs[NVMM_X64_GPR_RBX] |= cpuid->set.ebx; 831 cpudata->gprs[NVMM_X64_GPR_RCX] |= cpuid->set.ecx; 832 cpudata->gprs[NVMM_X64_GPR_RDX] |= cpuid->set.edx; 833 834 break; 835 } 836 837 /* Overwrite non-tunable leaves. */ 838 svm_inkernel_handle_cpuid(vcpu, eax, ecx); 839 840 svm_inkernel_advance(cpudata->vmcb); 841 exit->reason = NVMM_EXIT_NONE; 842 } 843 844 static void 845 svm_exit_hlt(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 846 struct nvmm_exit *exit) 847 { 848 struct svm_cpudata *cpudata = vcpu->cpudata; 849 struct vmcb *vmcb = cpudata->vmcb; 850 851 if (cpudata->int_window_exit && (vmcb->state.rflags & PSL_I)) { 852 svm_event_waitexit_disable(vcpu, false); 853 } 854 855 svm_inkernel_advance(cpudata->vmcb); 856 exit->reason = NVMM_EXIT_HALTED; 857 } 858 859 #define SVM_EXIT_IO_PORT __BITS(31,16) 860 #define SVM_EXIT_IO_SEG __BITS(12,10) 861 #define SVM_EXIT_IO_A64 __BIT(9) 862 #define SVM_EXIT_IO_A32 __BIT(8) 863 #define SVM_EXIT_IO_A16 __BIT(7) 864 #define SVM_EXIT_IO_SZ32 __BIT(6) 865 #define SVM_EXIT_IO_SZ16 __BIT(5) 866 #define SVM_EXIT_IO_SZ8 __BIT(4) 867 #define SVM_EXIT_IO_REP __BIT(3) 868 #define SVM_EXIT_IO_STR __BIT(2) 869 #define SVM_EXIT_IO_IN __BIT(0) 870 871 static const int seg_to_nvmm[] = { 872 [0] = NVMM_X64_SEG_ES, 873 [1] = NVMM_X64_SEG_CS, 874 [2] = NVMM_X64_SEG_SS, 875 [3] = NVMM_X64_SEG_DS, 876 [4] = NVMM_X64_SEG_FS, 877 [5] = NVMM_X64_SEG_GS 878 }; 879 880 static void 881 svm_exit_io(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 882 struct nvmm_exit *exit) 883 { 884 struct svm_cpudata *cpudata = vcpu->cpudata; 885 uint64_t info = cpudata->vmcb->ctrl.exitinfo1; 886 uint64_t nextpc = cpudata->vmcb->ctrl.exitinfo2; 887 888 exit->reason = NVMM_EXIT_IO; 889 890 if (info & SVM_EXIT_IO_IN) { 891 exit->u.io.type = NVMM_EXIT_IO_IN; 892 } else { 893 exit->u.io.type = NVMM_EXIT_IO_OUT; 894 } 895 896 exit->u.io.port = __SHIFTOUT(info, SVM_EXIT_IO_PORT); 897 898 if (svm_decode_assist) { 899 KASSERT(__SHIFTOUT(info, SVM_EXIT_IO_SEG) < 6); 900 exit->u.io.seg = seg_to_nvmm[__SHIFTOUT(info, SVM_EXIT_IO_SEG)]; 901 } else { 902 exit->u.io.seg = -1; 903 } 904 905 if (info & SVM_EXIT_IO_A64) { 906 exit->u.io.address_size = 8; 907 } else if (info & SVM_EXIT_IO_A32) { 908 exit->u.io.address_size = 4; 909 } else if (info & SVM_EXIT_IO_A16) { 910 exit->u.io.address_size = 2; 911 } 912 913 if (info & SVM_EXIT_IO_SZ32) { 914 exit->u.io.operand_size = 4; 915 } else if (info & SVM_EXIT_IO_SZ16) { 916 exit->u.io.operand_size = 2; 917 } else if (info & SVM_EXIT_IO_SZ8) { 918 exit->u.io.operand_size = 1; 919 } 920 921 exit->u.io.rep = (info & SVM_EXIT_IO_REP) != 0; 922 exit->u.io.str = (info & SVM_EXIT_IO_STR) != 0; 923 exit->u.io.npc = nextpc; 924 } 925 926 static const uint64_t msr_ignore_list[] = { 927 0xc0010055, /* MSR_CMPHALT */ 928 MSR_DE_CFG, 929 MSR_IC_CFG, 930 MSR_UCODE_AMD_PATCHLEVEL 931 }; 932 933 static bool 934 svm_inkernel_handle_msr(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 935 struct nvmm_exit *exit) 936 { 937 struct svm_cpudata *cpudata = vcpu->cpudata; 938 struct vmcb *vmcb = cpudata->vmcb; 939 uint64_t val; 940 size_t i; 941 942 switch (exit->u.msr.type) { 943 case NVMM_EXIT_MSR_RDMSR: 944 if (exit->u.msr.msr == MSR_NB_CFG) { 945 val = NB_CFG_INITAPICCPUIDLO; 946 vmcb->state.rax = (val & 0xFFFFFFFF); 947 cpudata->gprs[NVMM_X64_GPR_RDX] = (val >> 32); 948 goto handled; 949 } 950 for (i = 0; i < __arraycount(msr_ignore_list); i++) { 951 if (msr_ignore_list[i] != exit->u.msr.msr) 952 continue; 953 val = 0; 954 vmcb->state.rax = (val & 0xFFFFFFFF); 955 cpudata->gprs[NVMM_X64_GPR_RDX] = (val >> 32); 956 goto handled; 957 } 958 break; 959 case NVMM_EXIT_MSR_WRMSR: 960 if (exit->u.msr.msr == MSR_EFER) { 961 if (__predict_false(exit->u.msr.val & ~EFER_VALID)) { 962 goto error; 963 } 964 if ((vmcb->state.efer ^ exit->u.msr.val) & 965 EFER_TLB_FLUSH) { 966 cpudata->tlb_want_flush = true; 967 } 968 vmcb->state.efer = exit->u.msr.val | EFER_SVME; 969 svm_vmcb_cache_flush(vmcb, VMCB_CTRL_VMCB_CLEAN_CR); 970 goto handled; 971 } 972 if (exit->u.msr.msr == MSR_TSC) { 973 cpudata->tsc_offset = exit->u.msr.val - cpu_counter(); 974 vmcb->ctrl.tsc_offset = cpudata->tsc_offset + 975 curcpu()->ci_data.cpu_cc_skew; 976 svm_vmcb_cache_flush(vmcb, VMCB_CTRL_VMCB_CLEAN_I); 977 goto handled; 978 } 979 for (i = 0; i < __arraycount(msr_ignore_list); i++) { 980 if (msr_ignore_list[i] != exit->u.msr.msr) 981 continue; 982 goto handled; 983 } 984 break; 985 } 986 987 return false; 988 989 handled: 990 svm_inkernel_advance(cpudata->vmcb); 991 return true; 992 993 error: 994 svm_inject_gp(mach, vcpu); 995 return true; 996 } 997 998 static void 999 svm_exit_msr(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 1000 struct nvmm_exit *exit) 1001 { 1002 struct svm_cpudata *cpudata = vcpu->cpudata; 1003 uint64_t info = cpudata->vmcb->ctrl.exitinfo1; 1004 1005 if (info == 0) { 1006 exit->u.msr.type = NVMM_EXIT_MSR_RDMSR; 1007 } else { 1008 exit->u.msr.type = NVMM_EXIT_MSR_WRMSR; 1009 } 1010 1011 exit->u.msr.msr = (cpudata->gprs[NVMM_X64_GPR_RCX] & 0xFFFFFFFF); 1012 1013 if (info == 1) { 1014 uint64_t rdx, rax; 1015 rdx = cpudata->gprs[NVMM_X64_GPR_RDX]; 1016 rax = cpudata->vmcb->state.rax; 1017 exit->u.msr.val = (rdx << 32) | (rax & 0xFFFFFFFF); 1018 } else { 1019 exit->u.msr.val = 0; 1020 } 1021 1022 if (svm_inkernel_handle_msr(mach, vcpu, exit)) { 1023 exit->reason = NVMM_EXIT_NONE; 1024 return; 1025 } 1026 1027 exit->reason = NVMM_EXIT_MSR; 1028 exit->u.msr.npc = cpudata->vmcb->ctrl.nrip; 1029 } 1030 1031 static void 1032 svm_exit_npf(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 1033 struct nvmm_exit *exit) 1034 { 1035 struct svm_cpudata *cpudata = vcpu->cpudata; 1036 gpaddr_t gpa = cpudata->vmcb->ctrl.exitinfo2; 1037 int error; 1038 1039 error = uvm_fault(&mach->vm->vm_map, gpa, VM_PROT_ALL); 1040 1041 if (error) { 1042 exit->reason = NVMM_EXIT_MEMORY; 1043 if (cpudata->vmcb->ctrl.exitinfo1 & PGEX_W) 1044 exit->u.mem.perm = NVMM_EXIT_MEMORY_WRITE; 1045 else if (cpudata->vmcb->ctrl.exitinfo1 & PGEX_X) 1046 exit->u.mem.perm = NVMM_EXIT_MEMORY_EXEC; 1047 else 1048 exit->u.mem.perm = NVMM_EXIT_MEMORY_READ; 1049 exit->u.mem.gpa = gpa; 1050 exit->u.mem.inst_len = cpudata->vmcb->ctrl.inst_len; 1051 memcpy(exit->u.mem.inst_bytes, cpudata->vmcb->ctrl.inst_bytes, 1052 sizeof(exit->u.mem.inst_bytes)); 1053 } else { 1054 exit->reason = NVMM_EXIT_NONE; 1055 } 1056 } 1057 1058 static void 1059 svm_exit_insn(struct vmcb *vmcb, struct nvmm_exit *exit, uint64_t reason) 1060 { 1061 exit->u.insn.npc = vmcb->ctrl.nrip; 1062 exit->reason = reason; 1063 } 1064 1065 static void 1066 svm_exit_xsetbv(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 1067 struct nvmm_exit *exit) 1068 { 1069 struct svm_cpudata *cpudata = vcpu->cpudata; 1070 struct vmcb *vmcb = cpudata->vmcb; 1071 uint64_t val; 1072 1073 exit->reason = NVMM_EXIT_NONE; 1074 1075 val = (cpudata->gprs[NVMM_X64_GPR_RDX] << 32) | 1076 (vmcb->state.rax & 0xFFFFFFFF); 1077 1078 if (__predict_false(cpudata->gprs[NVMM_X64_GPR_RCX] != 0)) { 1079 goto error; 1080 } else if (__predict_false(vmcb->state.cpl != 0)) { 1081 goto error; 1082 } else if (__predict_false((val & ~svm_xcr0_mask) != 0)) { 1083 goto error; 1084 } else if (__predict_false((val & XCR0_X87) == 0)) { 1085 goto error; 1086 } 1087 1088 cpudata->gxcr0 = val; 1089 1090 svm_inkernel_advance(cpudata->vmcb); 1091 return; 1092 1093 error: 1094 svm_inject_gp(mach, vcpu); 1095 } 1096 1097 static void 1098 svm_vcpu_guest_fpu_enter(struct nvmm_cpu *vcpu) 1099 { 1100 struct svm_cpudata *cpudata = vcpu->cpudata; 1101 1102 cpudata->ts_set = (rcr0() & CR0_TS) != 0; 1103 1104 fpu_area_save(&cpudata->hfpu, svm_xcr0_mask); 1105 fpu_area_restore(&cpudata->gfpu, svm_xcr0_mask); 1106 1107 if (svm_xcr0_mask != 0) { 1108 cpudata->hxcr0 = rdxcr(0); 1109 wrxcr(0, cpudata->gxcr0); 1110 } 1111 } 1112 1113 static void 1114 svm_vcpu_guest_fpu_leave(struct nvmm_cpu *vcpu) 1115 { 1116 struct svm_cpudata *cpudata = vcpu->cpudata; 1117 1118 if (svm_xcr0_mask != 0) { 1119 cpudata->gxcr0 = rdxcr(0); 1120 wrxcr(0, cpudata->hxcr0); 1121 } 1122 1123 fpu_area_save(&cpudata->gfpu, svm_xcr0_mask); 1124 fpu_area_restore(&cpudata->hfpu, svm_xcr0_mask); 1125 1126 if (cpudata->ts_set) { 1127 stts(); 1128 } 1129 } 1130 1131 static void 1132 svm_vcpu_guest_dbregs_enter(struct nvmm_cpu *vcpu) 1133 { 1134 struct svm_cpudata *cpudata = vcpu->cpudata; 1135 1136 x86_dbregs_save(curlwp); 1137 1138 ldr7(0); 1139 1140 ldr0(cpudata->drs[NVMM_X64_DR_DR0]); 1141 ldr1(cpudata->drs[NVMM_X64_DR_DR1]); 1142 ldr2(cpudata->drs[NVMM_X64_DR_DR2]); 1143 ldr3(cpudata->drs[NVMM_X64_DR_DR3]); 1144 } 1145 1146 static void 1147 svm_vcpu_guest_dbregs_leave(struct nvmm_cpu *vcpu) 1148 { 1149 struct svm_cpudata *cpudata = vcpu->cpudata; 1150 1151 cpudata->drs[NVMM_X64_DR_DR0] = rdr0(); 1152 cpudata->drs[NVMM_X64_DR_DR1] = rdr1(); 1153 cpudata->drs[NVMM_X64_DR_DR2] = rdr2(); 1154 cpudata->drs[NVMM_X64_DR_DR3] = rdr3(); 1155 1156 x86_dbregs_restore(curlwp); 1157 } 1158 1159 static void 1160 svm_vcpu_guest_misc_enter(struct nvmm_cpu *vcpu) 1161 { 1162 struct svm_cpudata *cpudata = vcpu->cpudata; 1163 1164 cpudata->fsbase = rdmsr(MSR_FSBASE); 1165 cpudata->kernelgsbase = rdmsr(MSR_KERNELGSBASE); 1166 } 1167 1168 static void 1169 svm_vcpu_guest_misc_leave(struct nvmm_cpu *vcpu) 1170 { 1171 struct svm_cpudata *cpudata = vcpu->cpudata; 1172 1173 wrmsr(MSR_STAR, cpudata->star); 1174 wrmsr(MSR_LSTAR, cpudata->lstar); 1175 wrmsr(MSR_CSTAR, cpudata->cstar); 1176 wrmsr(MSR_SFMASK, cpudata->sfmask); 1177 wrmsr(MSR_FSBASE, cpudata->fsbase); 1178 wrmsr(MSR_KERNELGSBASE, cpudata->kernelgsbase); 1179 } 1180 1181 static int 1182 svm_vcpu_run(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 1183 struct nvmm_exit *exit) 1184 { 1185 struct svm_cpudata *cpudata = vcpu->cpudata; 1186 struct vmcb *vmcb = cpudata->vmcb; 1187 bool tlb_need_flush = false; 1188 int hcpu, s; 1189 1190 kpreempt_disable(); 1191 hcpu = cpu_number(); 1192 1193 if (vcpu->hcpu_last != hcpu || cpudata->shared_asid) { 1194 tlb_need_flush = true; 1195 } 1196 1197 if (vcpu->hcpu_last != hcpu) { 1198 vmcb->ctrl.tsc_offset = cpudata->tsc_offset + 1199 curcpu()->ci_data.cpu_cc_skew; 1200 svm_vmcb_cache_flush_all(vmcb); 1201 } 1202 1203 svm_vcpu_guest_dbregs_enter(vcpu); 1204 svm_vcpu_guest_misc_enter(vcpu); 1205 1206 while (1) { 1207 if (cpudata->tlb_want_flush || tlb_need_flush) { 1208 vmcb->ctrl.tlb_ctrl = svm_ctrl_tlb_flush; 1209 } else { 1210 vmcb->ctrl.tlb_ctrl = 0; 1211 } 1212 1213 s = splhigh(); 1214 svm_vcpu_guest_fpu_enter(vcpu); 1215 svm_vmrun(cpudata->vmcb_pa, cpudata->gprs); 1216 svm_vcpu_guest_fpu_leave(vcpu); 1217 splx(s); 1218 1219 svm_vmcb_cache_default(vmcb); 1220 1221 if (vmcb->ctrl.exitcode != VMCB_EXITCODE_INVALID) { 1222 cpudata->tlb_want_flush = false; 1223 tlb_need_flush = false; 1224 vcpu->hcpu_last = hcpu; 1225 } 1226 1227 switch (vmcb->ctrl.exitcode) { 1228 case VMCB_EXITCODE_INTR: 1229 case VMCB_EXITCODE_NMI: 1230 exit->reason = NVMM_EXIT_NONE; 1231 break; 1232 case VMCB_EXITCODE_VINTR: 1233 svm_event_waitexit_disable(vcpu, false); 1234 exit->reason = NVMM_EXIT_INT_READY; 1235 break; 1236 case VMCB_EXITCODE_IRET: 1237 svm_event_waitexit_disable(vcpu, true); 1238 exit->reason = NVMM_EXIT_NMI_READY; 1239 break; 1240 case VMCB_EXITCODE_CPUID: 1241 svm_exit_cpuid(mach, vcpu, exit); 1242 break; 1243 case VMCB_EXITCODE_HLT: 1244 svm_exit_hlt(mach, vcpu, exit); 1245 break; 1246 case VMCB_EXITCODE_IOIO: 1247 svm_exit_io(mach, vcpu, exit); 1248 break; 1249 case VMCB_EXITCODE_MSR: 1250 svm_exit_msr(mach, vcpu, exit); 1251 break; 1252 case VMCB_EXITCODE_SHUTDOWN: 1253 exit->reason = NVMM_EXIT_SHUTDOWN; 1254 break; 1255 case VMCB_EXITCODE_RDPMC: 1256 case VMCB_EXITCODE_RSM: 1257 case VMCB_EXITCODE_INVLPGA: 1258 case VMCB_EXITCODE_VMRUN: 1259 case VMCB_EXITCODE_VMMCALL: 1260 case VMCB_EXITCODE_VMLOAD: 1261 case VMCB_EXITCODE_VMSAVE: 1262 case VMCB_EXITCODE_STGI: 1263 case VMCB_EXITCODE_CLGI: 1264 case VMCB_EXITCODE_SKINIT: 1265 case VMCB_EXITCODE_RDTSCP: 1266 svm_inject_ud(mach, vcpu); 1267 exit->reason = NVMM_EXIT_NONE; 1268 break; 1269 case VMCB_EXITCODE_MONITOR: 1270 svm_exit_insn(vmcb, exit, NVMM_EXIT_MONITOR); 1271 break; 1272 case VMCB_EXITCODE_MWAIT: 1273 svm_exit_insn(vmcb, exit, NVMM_EXIT_MWAIT); 1274 break; 1275 case VMCB_EXITCODE_MWAIT_CONDITIONAL: 1276 svm_exit_insn(vmcb, exit, NVMM_EXIT_MWAIT_COND); 1277 break; 1278 case VMCB_EXITCODE_XSETBV: 1279 svm_exit_xsetbv(mach, vcpu, exit); 1280 break; 1281 case VMCB_EXITCODE_NPF: 1282 svm_exit_npf(mach, vcpu, exit); 1283 break; 1284 case VMCB_EXITCODE_FERR_FREEZE: /* ? */ 1285 default: 1286 exit->reason = NVMM_EXIT_INVALID; 1287 break; 1288 } 1289 1290 /* If no reason to return to userland, keep rolling. */ 1291 if (curcpu()->ci_schedstate.spc_flags & SPCF_SHOULDYIELD) { 1292 break; 1293 } 1294 if (curcpu()->ci_data.cpu_softints != 0) { 1295 break; 1296 } 1297 if (curlwp->l_flag & LW_USERRET) { 1298 break; 1299 } 1300 if (exit->reason != NVMM_EXIT_NONE) { 1301 break; 1302 } 1303 } 1304 1305 svm_vcpu_guest_misc_leave(vcpu); 1306 svm_vcpu_guest_dbregs_leave(vcpu); 1307 1308 kpreempt_enable(); 1309 1310 exit->exitstate[NVMM_X64_EXITSTATE_CR8] = __SHIFTOUT(vmcb->ctrl.v, 1311 VMCB_CTRL_V_TPR); 1312 exit->exitstate[NVMM_X64_EXITSTATE_RFLAGS] = vmcb->state.rflags; 1313 1314 exit->exitstate[NVMM_X64_EXITSTATE_INT_SHADOW] = 1315 ((vmcb->ctrl.intr & VMCB_CTRL_INTR_SHADOW) != 0); 1316 exit->exitstate[NVMM_X64_EXITSTATE_INT_WINDOW_EXIT] = 1317 cpudata->int_window_exit; 1318 exit->exitstate[NVMM_X64_EXITSTATE_NMI_WINDOW_EXIT] = 1319 cpudata->nmi_window_exit; 1320 1321 return 0; 1322 } 1323 1324 /* -------------------------------------------------------------------------- */ 1325 1326 static int 1327 svm_memalloc(paddr_t *pa, vaddr_t *va, size_t npages) 1328 { 1329 struct pglist pglist; 1330 paddr_t _pa; 1331 vaddr_t _va; 1332 size_t i; 1333 int ret; 1334 1335 ret = uvm_pglistalloc(npages * PAGE_SIZE, 0, ~0UL, PAGE_SIZE, 0, 1336 &pglist, 1, 0); 1337 if (ret != 0) 1338 return ENOMEM; 1339 _pa = TAILQ_FIRST(&pglist)->phys_addr; 1340 _va = uvm_km_alloc(kernel_map, npages * PAGE_SIZE, 0, 1341 UVM_KMF_VAONLY | UVM_KMF_NOWAIT); 1342 if (_va == 0) 1343 goto error; 1344 1345 for (i = 0; i < npages; i++) { 1346 pmap_kenter_pa(_va + i * PAGE_SIZE, _pa + i * PAGE_SIZE, 1347 VM_PROT_READ | VM_PROT_WRITE, PMAP_WRITE_BACK); 1348 } 1349 pmap_update(pmap_kernel()); 1350 1351 memset((void *)_va, 0, npages * PAGE_SIZE); 1352 1353 *pa = _pa; 1354 *va = _va; 1355 return 0; 1356 1357 error: 1358 for (i = 0; i < npages; i++) { 1359 uvm_pagefree(PHYS_TO_VM_PAGE(_pa + i * PAGE_SIZE)); 1360 } 1361 return ENOMEM; 1362 } 1363 1364 static void 1365 svm_memfree(paddr_t pa, vaddr_t va, size_t npages) 1366 { 1367 size_t i; 1368 1369 pmap_kremove(va, npages * PAGE_SIZE); 1370 pmap_update(pmap_kernel()); 1371 uvm_km_free(kernel_map, va, npages * PAGE_SIZE, UVM_KMF_VAONLY); 1372 for (i = 0; i < npages; i++) { 1373 uvm_pagefree(PHYS_TO_VM_PAGE(pa + i * PAGE_SIZE)); 1374 } 1375 } 1376 1377 /* -------------------------------------------------------------------------- */ 1378 1379 #define SVM_MSRBM_READ __BIT(0) 1380 #define SVM_MSRBM_WRITE __BIT(1) 1381 1382 static void 1383 svm_vcpu_msr_allow(uint8_t *bitmap, uint64_t msr, bool read, bool write) 1384 { 1385 uint64_t byte; 1386 uint8_t bitoff; 1387 1388 if (msr < 0x00002000) { 1389 /* Range 1 */ 1390 byte = ((msr - 0x00000000) >> 2UL) + 0x0000; 1391 } else if (msr >= 0xC0000000 && msr < 0xC0002000) { 1392 /* Range 2 */ 1393 byte = ((msr - 0xC0000000) >> 2UL) + 0x0800; 1394 } else if (msr >= 0xC0010000 && msr < 0xC0012000) { 1395 /* Range 3 */ 1396 byte = ((msr - 0xC0010000) >> 2UL) + 0x1000; 1397 } else { 1398 panic("%s: wrong range", __func__); 1399 } 1400 1401 bitoff = (msr & 0x3) << 1; 1402 1403 if (read) { 1404 bitmap[byte] &= ~(SVM_MSRBM_READ << bitoff); 1405 } 1406 if (write) { 1407 bitmap[byte] &= ~(SVM_MSRBM_WRITE << bitoff); 1408 } 1409 } 1410 1411 static void 1412 svm_asid_alloc(struct nvmm_cpu *vcpu) 1413 { 1414 struct svm_cpudata *cpudata = vcpu->cpudata; 1415 struct vmcb *vmcb = cpudata->vmcb; 1416 size_t i, oct, bit; 1417 1418 mutex_enter(&svm_asidlock); 1419 1420 for (i = 0; i < svm_maxasid; i++) { 1421 oct = i / 8; 1422 bit = i % 8; 1423 1424 if (svm_asidmap[oct] & __BIT(bit)) { 1425 continue; 1426 } 1427 1428 svm_asidmap[oct] |= __BIT(bit); 1429 vmcb->ctrl.guest_asid = i; 1430 mutex_exit(&svm_asidlock); 1431 return; 1432 } 1433 1434 /* 1435 * No free ASID. Use the last one, which is shared and requires 1436 * special TLB handling. 1437 */ 1438 cpudata->shared_asid = true; 1439 vmcb->ctrl.guest_asid = svm_maxasid - 1; 1440 mutex_exit(&svm_asidlock); 1441 } 1442 1443 static void 1444 svm_asid_free(struct nvmm_cpu *vcpu) 1445 { 1446 struct svm_cpudata *cpudata = vcpu->cpudata; 1447 struct vmcb *vmcb = cpudata->vmcb; 1448 size_t oct, bit; 1449 1450 if (cpudata->shared_asid) { 1451 return; 1452 } 1453 1454 oct = vmcb->ctrl.guest_asid / 8; 1455 bit = vmcb->ctrl.guest_asid % 8; 1456 1457 mutex_enter(&svm_asidlock); 1458 svm_asidmap[oct] &= ~__BIT(bit); 1459 mutex_exit(&svm_asidlock); 1460 } 1461 1462 static void 1463 svm_vcpu_init(struct nvmm_machine *mach, struct nvmm_cpu *vcpu) 1464 { 1465 struct svm_cpudata *cpudata = vcpu->cpudata; 1466 struct vmcb *vmcb = cpudata->vmcb; 1467 1468 /* Allow reads/writes of Control Registers. */ 1469 vmcb->ctrl.intercept_cr = 0; 1470 1471 /* Allow reads/writes of Debug Registers. */ 1472 vmcb->ctrl.intercept_dr = 0; 1473 1474 /* Allow exceptions 0 to 31. */ 1475 vmcb->ctrl.intercept_vec = 0; 1476 1477 /* 1478 * Allow: 1479 * - SMI [smm interrupts] 1480 * - VINTR [virtual interrupts] 1481 * - CR0_SPEC [CR0 writes changing other fields than CR0.TS or CR0.MP] 1482 * - RIDTR [reads of IDTR] 1483 * - RGDTR [reads of GDTR] 1484 * - RLDTR [reads of LDTR] 1485 * - RTR [reads of TR] 1486 * - WIDTR [writes of IDTR] 1487 * - WGDTR [writes of GDTR] 1488 * - WLDTR [writes of LDTR] 1489 * - WTR [writes of TR] 1490 * - RDTSC [rdtsc instruction] 1491 * - PUSHF [pushf instruction] 1492 * - POPF [popf instruction] 1493 * - IRET [iret instruction] 1494 * - INTN [int $n instructions] 1495 * - INVD [invd instruction] 1496 * - PAUSE [pause instruction] 1497 * - INVLPG [invplg instruction] 1498 * - TASKSW [task switches] 1499 * 1500 * Intercept the rest below. 1501 */ 1502 vmcb->ctrl.intercept_misc1 = 1503 VMCB_CTRL_INTERCEPT_INTR | 1504 VMCB_CTRL_INTERCEPT_NMI | 1505 VMCB_CTRL_INTERCEPT_INIT | 1506 VMCB_CTRL_INTERCEPT_RDPMC | 1507 VMCB_CTRL_INTERCEPT_CPUID | 1508 VMCB_CTRL_INTERCEPT_RSM | 1509 VMCB_CTRL_INTERCEPT_HLT | 1510 VMCB_CTRL_INTERCEPT_INVLPGA | 1511 VMCB_CTRL_INTERCEPT_IOIO_PROT | 1512 VMCB_CTRL_INTERCEPT_MSR_PROT | 1513 VMCB_CTRL_INTERCEPT_FERR_FREEZE | 1514 VMCB_CTRL_INTERCEPT_SHUTDOWN; 1515 1516 /* 1517 * Allow: 1518 * - ICEBP [icebp instruction] 1519 * - WBINVD [wbinvd instruction] 1520 * - WCR_SPEC(0..15) [writes of CR0-15, received after instruction] 1521 * 1522 * Intercept the rest below. 1523 */ 1524 vmcb->ctrl.intercept_misc2 = 1525 VMCB_CTRL_INTERCEPT_VMRUN | 1526 VMCB_CTRL_INTERCEPT_VMMCALL | 1527 VMCB_CTRL_INTERCEPT_VMLOAD | 1528 VMCB_CTRL_INTERCEPT_VMSAVE | 1529 VMCB_CTRL_INTERCEPT_STGI | 1530 VMCB_CTRL_INTERCEPT_CLGI | 1531 VMCB_CTRL_INTERCEPT_SKINIT | 1532 VMCB_CTRL_INTERCEPT_RDTSCP | 1533 VMCB_CTRL_INTERCEPT_MONITOR | 1534 VMCB_CTRL_INTERCEPT_MWAIT | 1535 VMCB_CTRL_INTERCEPT_XSETBV; 1536 1537 /* Intercept all I/O accesses. */ 1538 memset(cpudata->iobm, 0xFF, IOBM_SIZE); 1539 vmcb->ctrl.iopm_base_pa = cpudata->iobm_pa; 1540 1541 /* 1542 * Allow: 1543 * - EFER [read] 1544 * - STAR [read, write] 1545 * - LSTAR [read, write] 1546 * - CSTAR [read, write] 1547 * - SFMASK [read, write] 1548 * - KERNELGSBASE [read, write] 1549 * - SYSENTER_CS [read, write] 1550 * - SYSENTER_ESP [read, write] 1551 * - SYSENTER_EIP [read, write] 1552 * - FSBASE [read, write] 1553 * - GSBASE [read, write] 1554 * - PAT [read, write] 1555 * - TSC [read] 1556 * 1557 * Intercept the rest. 1558 */ 1559 memset(cpudata->msrbm, 0xFF, MSRBM_SIZE); 1560 svm_vcpu_msr_allow(cpudata->msrbm, MSR_EFER, true, false); 1561 svm_vcpu_msr_allow(cpudata->msrbm, MSR_STAR, true, true); 1562 svm_vcpu_msr_allow(cpudata->msrbm, MSR_LSTAR, true, true); 1563 svm_vcpu_msr_allow(cpudata->msrbm, MSR_CSTAR, true, true); 1564 svm_vcpu_msr_allow(cpudata->msrbm, MSR_SFMASK, true, true); 1565 svm_vcpu_msr_allow(cpudata->msrbm, MSR_KERNELGSBASE, true, true); 1566 svm_vcpu_msr_allow(cpudata->msrbm, MSR_SYSENTER_CS, true, true); 1567 svm_vcpu_msr_allow(cpudata->msrbm, MSR_SYSENTER_ESP, true, true); 1568 svm_vcpu_msr_allow(cpudata->msrbm, MSR_SYSENTER_EIP, true, true); 1569 svm_vcpu_msr_allow(cpudata->msrbm, MSR_FSBASE, true, true); 1570 svm_vcpu_msr_allow(cpudata->msrbm, MSR_GSBASE, true, true); 1571 svm_vcpu_msr_allow(cpudata->msrbm, MSR_CR_PAT, true, true); 1572 svm_vcpu_msr_allow(cpudata->msrbm, MSR_TSC, true, false); 1573 vmcb->ctrl.msrpm_base_pa = cpudata->msrbm_pa; 1574 1575 /* Generate ASID. */ 1576 svm_asid_alloc(vcpu); 1577 1578 /* Virtual TPR. */ 1579 vmcb->ctrl.v = VMCB_CTRL_V_INTR_MASKING; 1580 1581 /* Enable Nested Paging. */ 1582 vmcb->ctrl.enable1 = VMCB_CTRL_ENABLE_NP; 1583 vmcb->ctrl.n_cr3 = mach->vm->vm_map.pmap->pm_pdirpa[0]; 1584 1585 /* Must always be set. */ 1586 vmcb->state.efer = EFER_SVME; 1587 cpudata->gxcr0 = XCR0_X87; 1588 1589 /* Init XSAVE header. */ 1590 cpudata->gfpu.xsh_xstate_bv = svm_xcr0_mask; 1591 cpudata->gfpu.xsh_xcomp_bv = 0; 1592 1593 /* Set guest TSC to zero, more or less. */ 1594 cpudata->tsc_offset = -cpu_counter(); 1595 1596 /* These MSRs are static. */ 1597 cpudata->star = rdmsr(MSR_STAR); 1598 cpudata->lstar = rdmsr(MSR_LSTAR); 1599 cpudata->cstar = rdmsr(MSR_CSTAR); 1600 cpudata->sfmask = rdmsr(MSR_SFMASK); 1601 } 1602 1603 static int 1604 svm_vcpu_create(struct nvmm_machine *mach, struct nvmm_cpu *vcpu) 1605 { 1606 struct svm_cpudata *cpudata; 1607 int error; 1608 1609 /* Allocate the SVM cpudata. */ 1610 cpudata = (struct svm_cpudata *)uvm_km_alloc(kernel_map, 1611 roundup(sizeof(*cpudata), PAGE_SIZE), 0, 1612 UVM_KMF_WIRED|UVM_KMF_ZERO); 1613 vcpu->cpudata = cpudata; 1614 1615 /* VMCB */ 1616 error = svm_memalloc(&cpudata->vmcb_pa, (vaddr_t *)&cpudata->vmcb, 1617 VMCB_NPAGES); 1618 if (error) 1619 goto error; 1620 1621 /* I/O Bitmap */ 1622 error = svm_memalloc(&cpudata->iobm_pa, (vaddr_t *)&cpudata->iobm, 1623 IOBM_NPAGES); 1624 if (error) 1625 goto error; 1626 1627 /* MSR Bitmap */ 1628 error = svm_memalloc(&cpudata->msrbm_pa, (vaddr_t *)&cpudata->msrbm, 1629 MSRBM_NPAGES); 1630 if (error) 1631 goto error; 1632 1633 /* Init the VCPU info. */ 1634 svm_vcpu_init(mach, vcpu); 1635 1636 return 0; 1637 1638 error: 1639 if (cpudata->vmcb_pa) { 1640 svm_memfree(cpudata->vmcb_pa, (vaddr_t)cpudata->vmcb, 1641 VMCB_NPAGES); 1642 } 1643 if (cpudata->iobm_pa) { 1644 svm_memfree(cpudata->iobm_pa, (vaddr_t)cpudata->iobm, 1645 IOBM_NPAGES); 1646 } 1647 if (cpudata->msrbm_pa) { 1648 svm_memfree(cpudata->msrbm_pa, (vaddr_t)cpudata->msrbm, 1649 MSRBM_NPAGES); 1650 } 1651 uvm_km_free(kernel_map, (vaddr_t)cpudata, 1652 roundup(sizeof(*cpudata), PAGE_SIZE), UVM_KMF_WIRED); 1653 return error; 1654 } 1655 1656 static void 1657 svm_vcpu_destroy(struct nvmm_machine *mach, struct nvmm_cpu *vcpu) 1658 { 1659 struct svm_cpudata *cpudata = vcpu->cpudata; 1660 1661 svm_asid_free(vcpu); 1662 1663 svm_memfree(cpudata->vmcb_pa, (vaddr_t)cpudata->vmcb, VMCB_NPAGES); 1664 svm_memfree(cpudata->iobm_pa, (vaddr_t)cpudata->iobm, IOBM_NPAGES); 1665 svm_memfree(cpudata->msrbm_pa, (vaddr_t)cpudata->msrbm, MSRBM_NPAGES); 1666 1667 uvm_km_free(kernel_map, (vaddr_t)cpudata, 1668 roundup(sizeof(*cpudata), PAGE_SIZE), UVM_KMF_WIRED); 1669 } 1670 1671 #define SVM_SEG_ATTRIB_TYPE __BITS(4,0) 1672 #define SVM_SEG_ATTRIB_DPL __BITS(6,5) 1673 #define SVM_SEG_ATTRIB_P __BIT(7) 1674 #define SVM_SEG_ATTRIB_AVL __BIT(8) 1675 #define SVM_SEG_ATTRIB_LONG __BIT(9) 1676 #define SVM_SEG_ATTRIB_DEF32 __BIT(10) 1677 #define SVM_SEG_ATTRIB_GRAN __BIT(11) 1678 1679 static void 1680 svm_vcpu_setstate_seg(struct nvmm_x64_state_seg *seg, struct vmcb_segment *vseg) 1681 { 1682 vseg->selector = seg->selector; 1683 vseg->attrib = 1684 __SHIFTIN(seg->attrib.type, SVM_SEG_ATTRIB_TYPE) | 1685 __SHIFTIN(seg->attrib.dpl, SVM_SEG_ATTRIB_DPL) | 1686 __SHIFTIN(seg->attrib.p, SVM_SEG_ATTRIB_P) | 1687 __SHIFTIN(seg->attrib.avl, SVM_SEG_ATTRIB_AVL) | 1688 __SHIFTIN(seg->attrib.lng, SVM_SEG_ATTRIB_LONG) | 1689 __SHIFTIN(seg->attrib.def32, SVM_SEG_ATTRIB_DEF32) | 1690 __SHIFTIN(seg->attrib.gran, SVM_SEG_ATTRIB_GRAN); 1691 vseg->limit = seg->limit; 1692 vseg->base = seg->base; 1693 } 1694 1695 static void 1696 svm_vcpu_getstate_seg(struct nvmm_x64_state_seg *seg, struct vmcb_segment *vseg) 1697 { 1698 seg->selector = vseg->selector; 1699 seg->attrib.type = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_TYPE); 1700 seg->attrib.dpl = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_DPL); 1701 seg->attrib.p = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_P); 1702 seg->attrib.avl = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_AVL); 1703 seg->attrib.lng = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_LONG); 1704 seg->attrib.def32 = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_DEF32); 1705 seg->attrib.gran = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_GRAN); 1706 seg->limit = vseg->limit; 1707 seg->base = vseg->base; 1708 } 1709 1710 static inline bool 1711 svm_state_tlb_flush(struct vmcb *vmcb, struct nvmm_x64_state *state, 1712 uint64_t flags) 1713 { 1714 if (flags & NVMM_X64_STATE_CRS) { 1715 if ((vmcb->state.cr0 ^ 1716 state->crs[NVMM_X64_CR_CR0]) & CR0_TLB_FLUSH) { 1717 return true; 1718 } 1719 if (vmcb->state.cr3 != state->crs[NVMM_X64_CR_CR3]) { 1720 return true; 1721 } 1722 if ((vmcb->state.cr4 ^ 1723 state->crs[NVMM_X64_CR_CR4]) & CR4_TLB_FLUSH) { 1724 return true; 1725 } 1726 } 1727 1728 if (flags & NVMM_X64_STATE_MSRS) { 1729 if ((vmcb->state.efer ^ 1730 state->msrs[NVMM_X64_MSR_EFER]) & EFER_TLB_FLUSH) { 1731 return true; 1732 } 1733 } 1734 1735 return false; 1736 } 1737 1738 static void 1739 svm_vcpu_setstate(struct nvmm_cpu *vcpu, void *data, uint64_t flags) 1740 { 1741 struct nvmm_x64_state *state = (struct nvmm_x64_state *)data; 1742 struct svm_cpudata *cpudata = vcpu->cpudata; 1743 struct vmcb *vmcb = cpudata->vmcb; 1744 struct fxsave *fpustate; 1745 1746 if (svm_state_tlb_flush(vmcb, state, flags)) { 1747 cpudata->tlb_want_flush = true; 1748 } 1749 1750 if (flags & NVMM_X64_STATE_SEGS) { 1751 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_CS], 1752 &vmcb->state.cs); 1753 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_DS], 1754 &vmcb->state.ds); 1755 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_ES], 1756 &vmcb->state.es); 1757 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_FS], 1758 &vmcb->state.fs); 1759 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_GS], 1760 &vmcb->state.gs); 1761 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_SS], 1762 &vmcb->state.ss); 1763 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_GDT], 1764 &vmcb->state.gdt); 1765 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_IDT], 1766 &vmcb->state.idt); 1767 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_LDT], 1768 &vmcb->state.ldt); 1769 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_TR], 1770 &vmcb->state.tr); 1771 1772 vmcb->state.cpl = state->segs[NVMM_X64_SEG_SS].attrib.dpl; 1773 } 1774 1775 CTASSERT(sizeof(cpudata->gprs) == sizeof(state->gprs)); 1776 if (flags & NVMM_X64_STATE_GPRS) { 1777 memcpy(cpudata->gprs, state->gprs, sizeof(state->gprs)); 1778 1779 vmcb->state.rip = state->gprs[NVMM_X64_GPR_RIP]; 1780 vmcb->state.rsp = state->gprs[NVMM_X64_GPR_RSP]; 1781 vmcb->state.rax = state->gprs[NVMM_X64_GPR_RAX]; 1782 vmcb->state.rflags = state->gprs[NVMM_X64_GPR_RFLAGS]; 1783 } 1784 1785 if (flags & NVMM_X64_STATE_CRS) { 1786 vmcb->state.cr0 = state->crs[NVMM_X64_CR_CR0]; 1787 vmcb->state.cr2 = state->crs[NVMM_X64_CR_CR2]; 1788 vmcb->state.cr3 = state->crs[NVMM_X64_CR_CR3]; 1789 vmcb->state.cr4 = state->crs[NVMM_X64_CR_CR4]; 1790 1791 vmcb->ctrl.v &= ~VMCB_CTRL_V_TPR; 1792 vmcb->ctrl.v |= __SHIFTIN(state->crs[NVMM_X64_CR_CR8], 1793 VMCB_CTRL_V_TPR); 1794 1795 if (svm_xcr0_mask != 0) { 1796 /* Clear illegal XCR0 bits, set mandatory X87 bit. */ 1797 cpudata->gxcr0 = state->crs[NVMM_X64_CR_XCR0]; 1798 cpudata->gxcr0 &= svm_xcr0_mask; 1799 cpudata->gxcr0 |= XCR0_X87; 1800 } 1801 } 1802 1803 CTASSERT(sizeof(cpudata->drs) == sizeof(state->drs)); 1804 if (flags & NVMM_X64_STATE_DRS) { 1805 memcpy(cpudata->drs, state->drs, sizeof(state->drs)); 1806 1807 vmcb->state.dr6 = state->drs[NVMM_X64_DR_DR6]; 1808 vmcb->state.dr7 = state->drs[NVMM_X64_DR_DR7]; 1809 } 1810 1811 if (flags & NVMM_X64_STATE_MSRS) { 1812 /* Bit EFER_SVME is mandatory. */ 1813 vmcb->state.efer = state->msrs[NVMM_X64_MSR_EFER] | EFER_SVME; 1814 1815 vmcb->state.star = state->msrs[NVMM_X64_MSR_STAR]; 1816 vmcb->state.lstar = state->msrs[NVMM_X64_MSR_LSTAR]; 1817 vmcb->state.cstar = state->msrs[NVMM_X64_MSR_CSTAR]; 1818 vmcb->state.sfmask = state->msrs[NVMM_X64_MSR_SFMASK]; 1819 vmcb->state.kernelgsbase = 1820 state->msrs[NVMM_X64_MSR_KERNELGSBASE]; 1821 vmcb->state.sysenter_cs = 1822 state->msrs[NVMM_X64_MSR_SYSENTER_CS]; 1823 vmcb->state.sysenter_esp = 1824 state->msrs[NVMM_X64_MSR_SYSENTER_ESP]; 1825 vmcb->state.sysenter_eip = 1826 state->msrs[NVMM_X64_MSR_SYSENTER_EIP]; 1827 vmcb->state.g_pat = state->msrs[NVMM_X64_MSR_PAT]; 1828 } 1829 1830 if (flags & NVMM_X64_STATE_MISC) { 1831 if (state->misc[NVMM_X64_MISC_INT_SHADOW]) { 1832 vmcb->ctrl.intr |= VMCB_CTRL_INTR_SHADOW; 1833 } else { 1834 vmcb->ctrl.intr &= ~VMCB_CTRL_INTR_SHADOW; 1835 } 1836 1837 if (state->misc[NVMM_X64_MISC_INT_WINDOW_EXIT]) { 1838 svm_event_waitexit_enable(vcpu, false); 1839 } else { 1840 svm_event_waitexit_disable(vcpu, false); 1841 } 1842 1843 if (state->misc[NVMM_X64_MISC_NMI_WINDOW_EXIT]) { 1844 svm_event_waitexit_enable(vcpu, true); 1845 } else { 1846 svm_event_waitexit_disable(vcpu, true); 1847 } 1848 } 1849 1850 CTASSERT(sizeof(cpudata->gfpu.xsh_fxsave) == sizeof(state->fpu)); 1851 if (flags & NVMM_X64_STATE_FPU) { 1852 memcpy(cpudata->gfpu.xsh_fxsave, &state->fpu, 1853 sizeof(state->fpu)); 1854 1855 fpustate = (struct fxsave *)cpudata->gfpu.xsh_fxsave; 1856 fpustate->fx_mxcsr_mask &= x86_fpu_mxcsr_mask; 1857 fpustate->fx_mxcsr &= fpustate->fx_mxcsr_mask; 1858 1859 if (svm_xcr0_mask != 0) { 1860 /* Reset XSTATE_BV, to force a reload. */ 1861 cpudata->gfpu.xsh_xstate_bv = svm_xcr0_mask; 1862 } 1863 } 1864 1865 svm_vmcb_cache_update(vmcb, flags); 1866 } 1867 1868 static void 1869 svm_vcpu_getstate(struct nvmm_cpu *vcpu, void *data, uint64_t flags) 1870 { 1871 struct nvmm_x64_state *state = (struct nvmm_x64_state *)data; 1872 struct svm_cpudata *cpudata = vcpu->cpudata; 1873 struct vmcb *vmcb = cpudata->vmcb; 1874 1875 if (flags & NVMM_X64_STATE_SEGS) { 1876 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_CS], 1877 &vmcb->state.cs); 1878 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_DS], 1879 &vmcb->state.ds); 1880 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_ES], 1881 &vmcb->state.es); 1882 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_FS], 1883 &vmcb->state.fs); 1884 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_GS], 1885 &vmcb->state.gs); 1886 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_SS], 1887 &vmcb->state.ss); 1888 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_GDT], 1889 &vmcb->state.gdt); 1890 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_IDT], 1891 &vmcb->state.idt); 1892 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_LDT], 1893 &vmcb->state.ldt); 1894 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_TR], 1895 &vmcb->state.tr); 1896 1897 state->segs[NVMM_X64_SEG_SS].attrib.dpl = vmcb->state.cpl; 1898 } 1899 1900 CTASSERT(sizeof(cpudata->gprs) == sizeof(state->gprs)); 1901 if (flags & NVMM_X64_STATE_GPRS) { 1902 memcpy(state->gprs, cpudata->gprs, sizeof(state->gprs)); 1903 1904 state->gprs[NVMM_X64_GPR_RIP] = vmcb->state.rip; 1905 state->gprs[NVMM_X64_GPR_RSP] = vmcb->state.rsp; 1906 state->gprs[NVMM_X64_GPR_RAX] = vmcb->state.rax; 1907 state->gprs[NVMM_X64_GPR_RFLAGS] = vmcb->state.rflags; 1908 } 1909 1910 if (flags & NVMM_X64_STATE_CRS) { 1911 state->crs[NVMM_X64_CR_CR0] = vmcb->state.cr0; 1912 state->crs[NVMM_X64_CR_CR2] = vmcb->state.cr2; 1913 state->crs[NVMM_X64_CR_CR3] = vmcb->state.cr3; 1914 state->crs[NVMM_X64_CR_CR4] = vmcb->state.cr4; 1915 state->crs[NVMM_X64_CR_CR8] = __SHIFTOUT(vmcb->ctrl.v, 1916 VMCB_CTRL_V_TPR); 1917 state->crs[NVMM_X64_CR_XCR0] = cpudata->gxcr0; 1918 } 1919 1920 CTASSERT(sizeof(cpudata->drs) == sizeof(state->drs)); 1921 if (flags & NVMM_X64_STATE_DRS) { 1922 memcpy(state->drs, cpudata->drs, sizeof(state->drs)); 1923 1924 state->drs[NVMM_X64_DR_DR6] = vmcb->state.dr6; 1925 state->drs[NVMM_X64_DR_DR7] = vmcb->state.dr7; 1926 } 1927 1928 if (flags & NVMM_X64_STATE_MSRS) { 1929 state->msrs[NVMM_X64_MSR_EFER] = vmcb->state.efer; 1930 state->msrs[NVMM_X64_MSR_STAR] = vmcb->state.star; 1931 state->msrs[NVMM_X64_MSR_LSTAR] = vmcb->state.lstar; 1932 state->msrs[NVMM_X64_MSR_CSTAR] = vmcb->state.cstar; 1933 state->msrs[NVMM_X64_MSR_SFMASK] = vmcb->state.sfmask; 1934 state->msrs[NVMM_X64_MSR_KERNELGSBASE] = 1935 vmcb->state.kernelgsbase; 1936 state->msrs[NVMM_X64_MSR_SYSENTER_CS] = 1937 vmcb->state.sysenter_cs; 1938 state->msrs[NVMM_X64_MSR_SYSENTER_ESP] = 1939 vmcb->state.sysenter_esp; 1940 state->msrs[NVMM_X64_MSR_SYSENTER_EIP] = 1941 vmcb->state.sysenter_eip; 1942 state->msrs[NVMM_X64_MSR_PAT] = vmcb->state.g_pat; 1943 1944 /* Hide SVME. */ 1945 state->msrs[NVMM_X64_MSR_EFER] &= ~EFER_SVME; 1946 } 1947 1948 if (flags & NVMM_X64_STATE_MISC) { 1949 state->misc[NVMM_X64_MISC_INT_SHADOW] = 1950 (vmcb->ctrl.intr & VMCB_CTRL_INTR_SHADOW) != 0; 1951 state->misc[NVMM_X64_MISC_INT_WINDOW_EXIT] = 1952 cpudata->int_window_exit; 1953 state->misc[NVMM_X64_MISC_NMI_WINDOW_EXIT] = 1954 cpudata->nmi_window_exit; 1955 } 1956 1957 CTASSERT(sizeof(cpudata->gfpu.xsh_fxsave) == sizeof(state->fpu)); 1958 if (flags & NVMM_X64_STATE_FPU) { 1959 memcpy(&state->fpu, cpudata->gfpu.xsh_fxsave, 1960 sizeof(state->fpu)); 1961 } 1962 } 1963 1964 /* -------------------------------------------------------------------------- */ 1965 1966 static void 1967 svm_tlb_flush(struct pmap *pm) 1968 { 1969 struct nvmm_machine *mach = pm->pm_data; 1970 struct svm_cpudata *cpudata; 1971 struct nvmm_cpu *vcpu; 1972 int error; 1973 size_t i; 1974 1975 /* Request TLB flushes. */ 1976 for (i = 0; i < NVMM_MAX_VCPUS; i++) { 1977 error = nvmm_vcpu_get(mach, i, &vcpu); 1978 if (error) 1979 continue; 1980 cpudata = vcpu->cpudata; 1981 cpudata->tlb_want_flush = true; 1982 nvmm_vcpu_put(vcpu); 1983 } 1984 } 1985 1986 static void 1987 svm_machine_create(struct nvmm_machine *mach) 1988 { 1989 /* Fill in pmap info. */ 1990 mach->vm->vm_map.pmap->pm_data = (void *)mach; 1991 mach->vm->vm_map.pmap->pm_tlb_flush = svm_tlb_flush; 1992 1993 mach->machdata = kmem_zalloc(sizeof(struct svm_machdata), KM_SLEEP); 1994 } 1995 1996 static void 1997 svm_machine_destroy(struct nvmm_machine *mach) 1998 { 1999 kmem_free(mach->machdata, sizeof(struct svm_machdata)); 2000 } 2001 2002 static int 2003 svm_machine_configure(struct nvmm_machine *mach, uint64_t op, void *data) 2004 { 2005 struct nvmm_x86_conf_cpuid *cpuid = data; 2006 struct svm_machdata *machdata = (struct svm_machdata *)mach->machdata; 2007 size_t i; 2008 2009 if (__predict_false(op != NVMM_X86_CONF_CPUID)) { 2010 return EINVAL; 2011 } 2012 2013 if (__predict_false((cpuid->set.eax & cpuid->del.eax) || 2014 (cpuid->set.ebx & cpuid->del.ebx) || 2015 (cpuid->set.ecx & cpuid->del.ecx) || 2016 (cpuid->set.edx & cpuid->del.edx))) { 2017 return EINVAL; 2018 } 2019 2020 /* If already here, replace. */ 2021 for (i = 0; i < SVM_NCPUIDS; i++) { 2022 if (!machdata->cpuidpresent[i]) { 2023 continue; 2024 } 2025 if (machdata->cpuid[i].leaf == cpuid->leaf) { 2026 memcpy(&machdata->cpuid[i], cpuid, 2027 sizeof(struct nvmm_x86_conf_cpuid)); 2028 return 0; 2029 } 2030 } 2031 2032 /* Not here, insert. */ 2033 for (i = 0; i < SVM_NCPUIDS; i++) { 2034 if (!machdata->cpuidpresent[i]) { 2035 machdata->cpuidpresent[i] = true; 2036 memcpy(&machdata->cpuid[i], cpuid, 2037 sizeof(struct nvmm_x86_conf_cpuid)); 2038 return 0; 2039 } 2040 } 2041 2042 return ENOBUFS; 2043 } 2044 2045 /* -------------------------------------------------------------------------- */ 2046 2047 static bool 2048 svm_ident(void) 2049 { 2050 u_int descs[4]; 2051 uint64_t msr; 2052 2053 if (cpu_vendor != CPUVENDOR_AMD) { 2054 return false; 2055 } 2056 if (!(cpu_feature[3] & CPUID_SVM)) { 2057 return false; 2058 } 2059 2060 if (curcpu()->ci_max_ext_cpuid < 0x8000000a) { 2061 return false; 2062 } 2063 x86_cpuid(0x8000000a, descs); 2064 2065 /* Want Nested Paging. */ 2066 if (!(descs[3] & CPUID_AMD_SVM_NP)) { 2067 return false; 2068 } 2069 2070 /* Want nRIP. */ 2071 if (!(descs[3] & CPUID_AMD_SVM_NRIPS)) { 2072 return false; 2073 } 2074 2075 svm_decode_assist = (descs[3] & CPUID_AMD_SVM_DecodeAssist) != 0; 2076 2077 msr = rdmsr(MSR_VMCR); 2078 if ((msr & VMCR_SVMED) && (msr & VMCR_LOCK)) { 2079 return false; 2080 } 2081 2082 return true; 2083 } 2084 2085 static void 2086 svm_init_asid(uint32_t maxasid) 2087 { 2088 size_t i, j, allocsz; 2089 2090 mutex_init(&svm_asidlock, MUTEX_DEFAULT, IPL_NONE); 2091 2092 /* Arbitrarily limit. */ 2093 maxasid = uimin(maxasid, 8192); 2094 2095 svm_maxasid = maxasid; 2096 allocsz = roundup(maxasid, 8) / 8; 2097 svm_asidmap = kmem_zalloc(allocsz, KM_SLEEP); 2098 2099 /* ASID 0 is reserved for the host. */ 2100 svm_asidmap[0] |= __BIT(0); 2101 2102 /* ASID n-1 is special, we share it. */ 2103 i = (maxasid - 1) / 8; 2104 j = (maxasid - 1) % 8; 2105 svm_asidmap[i] |= __BIT(j); 2106 } 2107 2108 static void 2109 svm_change_cpu(void *arg1, void *arg2) 2110 { 2111 bool enable = (bool)arg1; 2112 uint64_t msr; 2113 2114 msr = rdmsr(MSR_VMCR); 2115 if (msr & VMCR_SVMED) { 2116 wrmsr(MSR_VMCR, msr & ~VMCR_SVMED); 2117 } 2118 2119 if (!enable) { 2120 wrmsr(MSR_VM_HSAVE_PA, 0); 2121 } 2122 2123 msr = rdmsr(MSR_EFER); 2124 if (enable) { 2125 msr |= EFER_SVME; 2126 } else { 2127 msr &= ~EFER_SVME; 2128 } 2129 wrmsr(MSR_EFER, msr); 2130 2131 if (enable) { 2132 wrmsr(MSR_VM_HSAVE_PA, hsave[cpu_index(curcpu())].pa); 2133 } 2134 } 2135 2136 static void 2137 svm_init(void) 2138 { 2139 CPU_INFO_ITERATOR cii; 2140 struct cpu_info *ci; 2141 struct vm_page *pg; 2142 u_int descs[4]; 2143 uint64_t xc; 2144 2145 x86_cpuid(0x8000000a, descs); 2146 2147 /* The guest TLB flush command. */ 2148 if (descs[3] & CPUID_AMD_SVM_FlushByASID) { 2149 svm_ctrl_tlb_flush = VMCB_CTRL_TLB_CTRL_FLUSH_GUEST; 2150 } else { 2151 svm_ctrl_tlb_flush = VMCB_CTRL_TLB_CTRL_FLUSH_ALL; 2152 } 2153 2154 /* Init the ASID. */ 2155 svm_init_asid(descs[1]); 2156 2157 /* Init the XCR0 mask. */ 2158 svm_xcr0_mask = SVM_XCR0_MASK_DEFAULT & x86_xsave_features; 2159 2160 memset(hsave, 0, sizeof(hsave)); 2161 for (CPU_INFO_FOREACH(cii, ci)) { 2162 pg = uvm_pagealloc(NULL, 0, NULL, UVM_PGA_ZERO); 2163 hsave[cpu_index(ci)].pa = VM_PAGE_TO_PHYS(pg); 2164 } 2165 2166 xc = xc_broadcast(0, svm_change_cpu, (void *)true, NULL); 2167 xc_wait(xc); 2168 } 2169 2170 static void 2171 svm_fini_asid(void) 2172 { 2173 size_t allocsz; 2174 2175 allocsz = roundup(svm_maxasid, 8) / 8; 2176 kmem_free(svm_asidmap, allocsz); 2177 2178 mutex_destroy(&svm_asidlock); 2179 } 2180 2181 static void 2182 svm_fini(void) 2183 { 2184 uint64_t xc; 2185 size_t i; 2186 2187 xc = xc_broadcast(0, svm_change_cpu, (void *)false, NULL); 2188 xc_wait(xc); 2189 2190 for (i = 0; i < MAXCPUS; i++) { 2191 if (hsave[i].pa != 0) 2192 uvm_pagefree(PHYS_TO_VM_PAGE(hsave[i].pa)); 2193 } 2194 2195 svm_fini_asid(); 2196 } 2197 2198 static void 2199 svm_capability(struct nvmm_capability *cap) 2200 { 2201 cap->u.x86.xcr0_mask = svm_xcr0_mask; 2202 cap->u.x86.mxcsr_mask = x86_fpu_mxcsr_mask; 2203 cap->u.x86.conf_cpuid_maxops = SVM_NCPUIDS; 2204 } 2205 2206 const struct nvmm_impl nvmm_x86_svm = { 2207 .ident = svm_ident, 2208 .init = svm_init, 2209 .fini = svm_fini, 2210 .capability = svm_capability, 2211 .conf_max = NVMM_X86_NCONF, 2212 .conf_sizes = svm_conf_sizes, 2213 .state_size = sizeof(struct nvmm_x64_state), 2214 .machine_create = svm_machine_create, 2215 .machine_destroy = svm_machine_destroy, 2216 .machine_configure = svm_machine_configure, 2217 .vcpu_create = svm_vcpu_create, 2218 .vcpu_destroy = svm_vcpu_destroy, 2219 .vcpu_setstate = svm_vcpu_setstate, 2220 .vcpu_getstate = svm_vcpu_getstate, 2221 .vcpu_inject = svm_vcpu_inject, 2222 .vcpu_run = svm_vcpu_run 2223 }; 2224
Indexes created Wed Oct 01 07:09:59 GMT 2025