nvmm_x86_svm.c revision 1.26
1 /* $NetBSD: nvmm_x86_svm.c,v 1.26 2019/02/16 12:58:13 maxv Exp $ */ 2 3 /* 4 * Copyright (c) 2018 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Maxime Villard. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: nvmm_x86_svm.c,v 1.26 2019/02/16 12:58:13 maxv Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/kmem.h> 39 #include <sys/cpu.h> 40 #include <sys/xcall.h> 41 42 #include <uvm/uvm.h> 43 #include <uvm/uvm_page.h> 44 45 #include <x86/cputypes.h> 46 #include <x86/specialreg.h> 47 #include <x86/pmap.h> 48 #include <x86/dbregs.h> 49 #include <x86/cpu_counter.h> 50 #include <machine/cpuvar.h> 51 52 #include <dev/nvmm/nvmm.h> 53 #include <dev/nvmm/nvmm_internal.h> 54 #include <dev/nvmm/x86/nvmm_x86.h> 55 56 int svm_vmrun(paddr_t, uint64_t *); 57 58 #define MSR_VM_HSAVE_PA 0xC0010117 59 60 /* -------------------------------------------------------------------------- */ 61 62 #define VMCB_EXITCODE_CR0_READ 0x0000 63 #define VMCB_EXITCODE_CR1_READ 0x0001 64 #define VMCB_EXITCODE_CR2_READ 0x0002 65 #define VMCB_EXITCODE_CR3_READ 0x0003 66 #define VMCB_EXITCODE_CR4_READ 0x0004 67 #define VMCB_EXITCODE_CR5_READ 0x0005 68 #define VMCB_EXITCODE_CR6_READ 0x0006 69 #define VMCB_EXITCODE_CR7_READ 0x0007 70 #define VMCB_EXITCODE_CR8_READ 0x0008 71 #define VMCB_EXITCODE_CR9_READ 0x0009 72 #define VMCB_EXITCODE_CR10_READ 0x000A 73 #define VMCB_EXITCODE_CR11_READ 0x000B 74 #define VMCB_EXITCODE_CR12_READ 0x000C 75 #define VMCB_EXITCODE_CR13_READ 0x000D 76 #define VMCB_EXITCODE_CR14_READ 0x000E 77 #define VMCB_EXITCODE_CR15_READ 0x000F 78 #define VMCB_EXITCODE_CR0_WRITE 0x0010 79 #define VMCB_EXITCODE_CR1_WRITE 0x0011 80 #define VMCB_EXITCODE_CR2_WRITE 0x0012 81 #define VMCB_EXITCODE_CR3_WRITE 0x0013 82 #define VMCB_EXITCODE_CR4_WRITE 0x0014 83 #define VMCB_EXITCODE_CR5_WRITE 0x0015 84 #define VMCB_EXITCODE_CR6_WRITE 0x0016 85 #define VMCB_EXITCODE_CR7_WRITE 0x0017 86 #define VMCB_EXITCODE_CR8_WRITE 0x0018 87 #define VMCB_EXITCODE_CR9_WRITE 0x0019 88 #define VMCB_EXITCODE_CR10_WRITE 0x001A 89 #define VMCB_EXITCODE_CR11_WRITE 0x001B 90 #define VMCB_EXITCODE_CR12_WRITE 0x001C 91 #define VMCB_EXITCODE_CR13_WRITE 0x001D 92 #define VMCB_EXITCODE_CR14_WRITE 0x001E 93 #define VMCB_EXITCODE_CR15_WRITE 0x001F 94 #define VMCB_EXITCODE_DR0_READ 0x0020 95 #define VMCB_EXITCODE_DR1_READ 0x0021 96 #define VMCB_EXITCODE_DR2_READ 0x0022 97 #define VMCB_EXITCODE_DR3_READ 0x0023 98 #define VMCB_EXITCODE_DR4_READ 0x0024 99 #define VMCB_EXITCODE_DR5_READ 0x0025 100 #define VMCB_EXITCODE_DR6_READ 0x0026 101 #define VMCB_EXITCODE_DR7_READ 0x0027 102 #define VMCB_EXITCODE_DR8_READ 0x0028 103 #define VMCB_EXITCODE_DR9_READ 0x0029 104 #define VMCB_EXITCODE_DR10_READ 0x002A 105 #define VMCB_EXITCODE_DR11_READ 0x002B 106 #define VMCB_EXITCODE_DR12_READ 0x002C 107 #define VMCB_EXITCODE_DR13_READ 0x002D 108 #define VMCB_EXITCODE_DR14_READ 0x002E 109 #define VMCB_EXITCODE_DR15_READ 0x002F 110 #define VMCB_EXITCODE_DR0_WRITE 0x0030 111 #define VMCB_EXITCODE_DR1_WRITE 0x0031 112 #define VMCB_EXITCODE_DR2_WRITE 0x0032 113 #define VMCB_EXITCODE_DR3_WRITE 0x0033 114 #define VMCB_EXITCODE_DR4_WRITE 0x0034 115 #define VMCB_EXITCODE_DR5_WRITE 0x0035 116 #define VMCB_EXITCODE_DR6_WRITE 0x0036 117 #define VMCB_EXITCODE_DR7_WRITE 0x0037 118 #define VMCB_EXITCODE_DR8_WRITE 0x0038 119 #define VMCB_EXITCODE_DR9_WRITE 0x0039 120 #define VMCB_EXITCODE_DR10_WRITE 0x003A 121 #define VMCB_EXITCODE_DR11_WRITE 0x003B 122 #define VMCB_EXITCODE_DR12_WRITE 0x003C 123 #define VMCB_EXITCODE_DR13_WRITE 0x003D 124 #define VMCB_EXITCODE_DR14_WRITE 0x003E 125 #define VMCB_EXITCODE_DR15_WRITE 0x003F 126 #define VMCB_EXITCODE_EXCP0 0x0040 127 #define VMCB_EXITCODE_EXCP1 0x0041 128 #define VMCB_EXITCODE_EXCP2 0x0042 129 #define VMCB_EXITCODE_EXCP3 0x0043 130 #define VMCB_EXITCODE_EXCP4 0x0044 131 #define VMCB_EXITCODE_EXCP5 0x0045 132 #define VMCB_EXITCODE_EXCP6 0x0046 133 #define VMCB_EXITCODE_EXCP7 0x0047 134 #define VMCB_EXITCODE_EXCP8 0x0048 135 #define VMCB_EXITCODE_EXCP9 0x0049 136 #define VMCB_EXITCODE_EXCP10 0x004A 137 #define VMCB_EXITCODE_EXCP11 0x004B 138 #define VMCB_EXITCODE_EXCP12 0x004C 139 #define VMCB_EXITCODE_EXCP13 0x004D 140 #define VMCB_EXITCODE_EXCP14 0x004E 141 #define VMCB_EXITCODE_EXCP15 0x004F 142 #define VMCB_EXITCODE_EXCP16 0x0050 143 #define VMCB_EXITCODE_EXCP17 0x0051 144 #define VMCB_EXITCODE_EXCP18 0x0052 145 #define VMCB_EXITCODE_EXCP19 0x0053 146 #define VMCB_EXITCODE_EXCP20 0x0054 147 #define VMCB_EXITCODE_EXCP21 0x0055 148 #define VMCB_EXITCODE_EXCP22 0x0056 149 #define VMCB_EXITCODE_EXCP23 0x0057 150 #define VMCB_EXITCODE_EXCP24 0x0058 151 #define VMCB_EXITCODE_EXCP25 0x0059 152 #define VMCB_EXITCODE_EXCP26 0x005A 153 #define VMCB_EXITCODE_EXCP27 0x005B 154 #define VMCB_EXITCODE_EXCP28 0x005C 155 #define VMCB_EXITCODE_EXCP29 0x005D 156 #define VMCB_EXITCODE_EXCP30 0x005E 157 #define VMCB_EXITCODE_EXCP31 0x005F 158 #define VMCB_EXITCODE_INTR 0x0060 159 #define VMCB_EXITCODE_NMI 0x0061 160 #define VMCB_EXITCODE_SMI 0x0062 161 #define VMCB_EXITCODE_INIT 0x0063 162 #define VMCB_EXITCODE_VINTR 0x0064 163 #define VMCB_EXITCODE_CR0_SEL_WRITE 0x0065 164 #define VMCB_EXITCODE_IDTR_READ 0x0066 165 #define VMCB_EXITCODE_GDTR_READ 0x0067 166 #define VMCB_EXITCODE_LDTR_READ 0x0068 167 #define VMCB_EXITCODE_TR_READ 0x0069 168 #define VMCB_EXITCODE_IDTR_WRITE 0x006A 169 #define VMCB_EXITCODE_GDTR_WRITE 0x006B 170 #define VMCB_EXITCODE_LDTR_WRITE 0x006C 171 #define VMCB_EXITCODE_TR_WRITE 0x006D 172 #define VMCB_EXITCODE_RDTSC 0x006E 173 #define VMCB_EXITCODE_RDPMC 0x006F 174 #define VMCB_EXITCODE_PUSHF 0x0070 175 #define VMCB_EXITCODE_POPF 0x0071 176 #define VMCB_EXITCODE_CPUID 0x0072 177 #define VMCB_EXITCODE_RSM 0x0073 178 #define VMCB_EXITCODE_IRET 0x0074 179 #define VMCB_EXITCODE_SWINT 0x0075 180 #define VMCB_EXITCODE_INVD 0x0076 181 #define VMCB_EXITCODE_PAUSE 0x0077 182 #define VMCB_EXITCODE_HLT 0x0078 183 #define VMCB_EXITCODE_INVLPG 0x0079 184 #define VMCB_EXITCODE_INVLPGA 0x007A 185 #define VMCB_EXITCODE_IOIO 0x007B 186 #define VMCB_EXITCODE_MSR 0x007C 187 #define VMCB_EXITCODE_TASK_SWITCH 0x007D 188 #define VMCB_EXITCODE_FERR_FREEZE 0x007E 189 #define VMCB_EXITCODE_SHUTDOWN 0x007F 190 #define VMCB_EXITCODE_VMRUN 0x0080 191 #define VMCB_EXITCODE_VMMCALL 0x0081 192 #define VMCB_EXITCODE_VMLOAD 0x0082 193 #define VMCB_EXITCODE_VMSAVE 0x0083 194 #define VMCB_EXITCODE_STGI 0x0084 195 #define VMCB_EXITCODE_CLGI 0x0085 196 #define VMCB_EXITCODE_SKINIT 0x0086 197 #define VMCB_EXITCODE_RDTSCP 0x0087 198 #define VMCB_EXITCODE_ICEBP 0x0088 199 #define VMCB_EXITCODE_WBINVD 0x0089 200 #define VMCB_EXITCODE_MONITOR 0x008A 201 #define VMCB_EXITCODE_MWAIT 0x008B 202 #define VMCB_EXITCODE_MWAIT_CONDITIONAL 0x008C 203 #define VMCB_EXITCODE_XSETBV 0x008D 204 #define VMCB_EXITCODE_EFER_WRITE_TRAP 0x008F 205 #define VMCB_EXITCODE_CR0_WRITE_TRAP 0x0090 206 #define VMCB_EXITCODE_CR1_WRITE_TRAP 0x0091 207 #define VMCB_EXITCODE_CR2_WRITE_TRAP 0x0092 208 #define VMCB_EXITCODE_CR3_WRITE_TRAP 0x0093 209 #define VMCB_EXITCODE_CR4_WRITE_TRAP 0x0094 210 #define VMCB_EXITCODE_CR5_WRITE_TRAP 0x0095 211 #define VMCB_EXITCODE_CR6_WRITE_TRAP 0x0096 212 #define VMCB_EXITCODE_CR7_WRITE_TRAP 0x0097 213 #define VMCB_EXITCODE_CR8_WRITE_TRAP 0x0098 214 #define VMCB_EXITCODE_CR9_WRITE_TRAP 0x0099 215 #define VMCB_EXITCODE_CR10_WRITE_TRAP 0x009A 216 #define VMCB_EXITCODE_CR11_WRITE_TRAP 0x009B 217 #define VMCB_EXITCODE_CR12_WRITE_TRAP 0x009C 218 #define VMCB_EXITCODE_CR13_WRITE_TRAP 0x009D 219 #define VMCB_EXITCODE_CR14_WRITE_TRAP 0x009E 220 #define VMCB_EXITCODE_CR15_WRITE_TRAP 0x009F 221 #define VMCB_EXITCODE_NPF 0x0400 222 #define VMCB_EXITCODE_AVIC_INCOMP_IPI 0x0401 223 #define VMCB_EXITCODE_AVIC_NOACCEL 0x0402 224 #define VMCB_EXITCODE_VMGEXIT 0x0403 225 #define VMCB_EXITCODE_INVALID -1 226 227 /* -------------------------------------------------------------------------- */ 228 229 struct vmcb_ctrl { 230 uint32_t intercept_cr; 231 #define VMCB_CTRL_INTERCEPT_RCR(x) __BIT( 0 + x) 232 #define VMCB_CTRL_INTERCEPT_WCR(x) __BIT(16 + x) 233 234 uint32_t intercept_dr; 235 #define VMCB_CTRL_INTERCEPT_RDR(x) __BIT( 0 + x) 236 #define VMCB_CTRL_INTERCEPT_WDR(x) __BIT(16 + x) 237 238 uint32_t intercept_vec; 239 #define VMCB_CTRL_INTERCEPT_VEC(x) __BIT(x) 240 241 uint32_t intercept_misc1; 242 #define VMCB_CTRL_INTERCEPT_INTR __BIT(0) 243 #define VMCB_CTRL_INTERCEPT_NMI __BIT(1) 244 #define VMCB_CTRL_INTERCEPT_SMI __BIT(2) 245 #define VMCB_CTRL_INTERCEPT_INIT __BIT(3) 246 #define VMCB_CTRL_INTERCEPT_VINTR __BIT(4) 247 #define VMCB_CTRL_INTERCEPT_CR0_SPEC __BIT(5) 248 #define VMCB_CTRL_INTERCEPT_RIDTR __BIT(6) 249 #define VMCB_CTRL_INTERCEPT_RGDTR __BIT(7) 250 #define VMCB_CTRL_INTERCEPT_RLDTR __BIT(8) 251 #define VMCB_CTRL_INTERCEPT_RTR __BIT(9) 252 #define VMCB_CTRL_INTERCEPT_WIDTR __BIT(10) 253 #define VMCB_CTRL_INTERCEPT_WGDTR __BIT(11) 254 #define VMCB_CTRL_INTERCEPT_WLDTR __BIT(12) 255 #define VMCB_CTRL_INTERCEPT_WTR __BIT(13) 256 #define VMCB_CTRL_INTERCEPT_RDTSC __BIT(14) 257 #define VMCB_CTRL_INTERCEPT_RDPMC __BIT(15) 258 #define VMCB_CTRL_INTERCEPT_PUSHF __BIT(16) 259 #define VMCB_CTRL_INTERCEPT_POPF __BIT(17) 260 #define VMCB_CTRL_INTERCEPT_CPUID __BIT(18) 261 #define VMCB_CTRL_INTERCEPT_RSM __BIT(19) 262 #define VMCB_CTRL_INTERCEPT_IRET __BIT(20) 263 #define VMCB_CTRL_INTERCEPT_INTN __BIT(21) 264 #define VMCB_CTRL_INTERCEPT_INVD __BIT(22) 265 #define VMCB_CTRL_INTERCEPT_PAUSE __BIT(23) 266 #define VMCB_CTRL_INTERCEPT_HLT __BIT(24) 267 #define VMCB_CTRL_INTERCEPT_INVLPG __BIT(25) 268 #define VMCB_CTRL_INTERCEPT_INVLPGA __BIT(26) 269 #define VMCB_CTRL_INTERCEPT_IOIO_PROT __BIT(27) 270 #define VMCB_CTRL_INTERCEPT_MSR_PROT __BIT(28) 271 #define VMCB_CTRL_INTERCEPT_TASKSW __BIT(29) 272 #define VMCB_CTRL_INTERCEPT_FERR_FREEZE __BIT(30) 273 #define VMCB_CTRL_INTERCEPT_SHUTDOWN __BIT(31) 274 275 uint32_t intercept_misc2; 276 #define VMCB_CTRL_INTERCEPT_VMRUN __BIT(0) 277 #define VMCB_CTRL_INTERCEPT_VMMCALL __BIT(1) 278 #define VMCB_CTRL_INTERCEPT_VMLOAD __BIT(2) 279 #define VMCB_CTRL_INTERCEPT_VMSAVE __BIT(3) 280 #define VMCB_CTRL_INTERCEPT_STGI __BIT(4) 281 #define VMCB_CTRL_INTERCEPT_CLGI __BIT(5) 282 #define VMCB_CTRL_INTERCEPT_SKINIT __BIT(6) 283 #define VMCB_CTRL_INTERCEPT_RDTSCP __BIT(7) 284 #define VMCB_CTRL_INTERCEPT_ICEBP __BIT(8) 285 #define VMCB_CTRL_INTERCEPT_WBINVD __BIT(9) 286 #define VMCB_CTRL_INTERCEPT_MONITOR __BIT(10) 287 #define VMCB_CTRL_INTERCEPT_MWAIT __BIT(12) 288 #define VMCB_CTRL_INTERCEPT_XSETBV __BIT(13) 289 #define VMCB_CTRL_INTERCEPT_EFER_SPEC __BIT(15) 290 #define VMCB_CTRL_INTERCEPT_WCR_SPEC(x) __BIT(16 + x) 291 292 uint8_t rsvd1[40]; 293 uint16_t pause_filt_thresh; 294 uint16_t pause_filt_cnt; 295 uint64_t iopm_base_pa; 296 uint64_t msrpm_base_pa; 297 uint64_t tsc_offset; 298 uint32_t guest_asid; 299 300 uint32_t tlb_ctrl; 301 #define VMCB_CTRL_TLB_CTRL_FLUSH_ALL 0x01 302 #define VMCB_CTRL_TLB_CTRL_FLUSH_GUEST 0x03 303 #define VMCB_CTRL_TLB_CTRL_FLUSH_GUEST_NONGLOBAL 0x07 304 305 uint64_t v; 306 #define VMCB_CTRL_V_TPR __BITS(7,0) 307 #define VMCB_CTRL_V_IRQ __BIT(8) 308 #define VMCB_CTRL_V_VGIF __BIT(9) 309 #define VMCB_CTRL_V_INTR_PRIO __BITS(19,16) 310 #define VMCB_CTRL_V_IGN_TPR __BIT(20) 311 #define VMCB_CTRL_V_INTR_MASKING __BIT(24) 312 #define VMCB_CTRL_V_GUEST_VGIF __BIT(25) 313 #define VMCB_CTRL_V_AVIC_EN __BIT(31) 314 #define VMCB_CTRL_V_INTR_VECTOR __BITS(39,32) 315 316 uint64_t intr; 317 #define VMCB_CTRL_INTR_SHADOW __BIT(0) 318 319 uint64_t exitcode; 320 uint64_t exitinfo1; 321 uint64_t exitinfo2; 322 323 uint64_t exitintinfo; 324 #define VMCB_CTRL_EXITINTINFO_VECTOR __BITS(7,0) 325 #define VMCB_CTRL_EXITINTINFO_TYPE __BITS(10,8) 326 #define VMCB_CTRL_EXITINTINFO_EV __BIT(11) 327 #define VMCB_CTRL_EXITINTINFO_V __BIT(31) 328 #define VMCB_CTRL_EXITINTINFO_ERRORCODE __BITS(63,32) 329 330 uint64_t enable1; 331 #define VMCB_CTRL_ENABLE_NP __BIT(0) 332 #define VMCB_CTRL_ENABLE_SEV __BIT(1) 333 #define VMCB_CTRL_ENABLE_ES_SEV __BIT(2) 334 335 uint64_t avic; 336 #define VMCB_CTRL_AVIC_APIC_BAR __BITS(51,0) 337 338 uint64_t ghcb; 339 340 uint64_t eventinj; 341 #define VMCB_CTRL_EVENTINJ_VECTOR __BITS(7,0) 342 #define VMCB_CTRL_EVENTINJ_TYPE __BITS(10,8) 343 #define VMCB_CTRL_EVENTINJ_EV __BIT(11) 344 #define VMCB_CTRL_EVENTINJ_V __BIT(31) 345 #define VMCB_CTRL_EVENTINJ_ERRORCODE __BITS(63,32) 346 347 uint64_t n_cr3; 348 349 uint64_t enable2; 350 #define VMCB_CTRL_ENABLE_LBR __BIT(0) 351 #define VMCB_CTRL_ENABLE_VVMSAVE __BIT(1) 352 353 uint32_t vmcb_clean; 354 #define VMCB_CTRL_VMCB_CLEAN_I __BIT(0) 355 #define VMCB_CTRL_VMCB_CLEAN_IOPM __BIT(1) 356 #define VMCB_CTRL_VMCB_CLEAN_ASID __BIT(2) 357 #define VMCB_CTRL_VMCB_CLEAN_TPR __BIT(3) 358 #define VMCB_CTRL_VMCB_CLEAN_NP __BIT(4) 359 #define VMCB_CTRL_VMCB_CLEAN_CR __BIT(5) 360 #define VMCB_CTRL_VMCB_CLEAN_DR __BIT(6) 361 #define VMCB_CTRL_VMCB_CLEAN_DT __BIT(7) 362 #define VMCB_CTRL_VMCB_CLEAN_SEG __BIT(8) 363 #define VMCB_CTRL_VMCB_CLEAN_CR2 __BIT(9) 364 #define VMCB_CTRL_VMCB_CLEAN_LBR __BIT(10) 365 #define VMCB_CTRL_VMCB_CLEAN_AVIC __BIT(11) 366 367 uint32_t rsvd2; 368 uint64_t nrip; 369 uint8_t inst_len; 370 uint8_t inst_bytes[15]; 371 uint64_t avic_abpp; 372 uint64_t rsvd3; 373 uint64_t avic_ltp; 374 375 uint64_t avic_phys; 376 #define VMCB_CTRL_AVIC_PHYS_TABLE_PTR __BITS(51,12) 377 #define VMCB_CTRL_AVIC_PHYS_MAX_INDEX __BITS(7,0) 378 379 uint64_t rsvd4; 380 uint64_t vmcb_ptr; 381 382 uint8_t pad[752]; 383 } __packed; 384 385 CTASSERT(sizeof(struct vmcb_ctrl) == 1024); 386 387 struct vmcb_segment { 388 uint16_t selector; 389 uint16_t attrib; /* hidden */ 390 uint32_t limit; /* hidden */ 391 uint64_t base; /* hidden */ 392 } __packed; 393 394 CTASSERT(sizeof(struct vmcb_segment) == 16); 395 396 struct vmcb_state { 397 struct vmcb_segment es; 398 struct vmcb_segment cs; 399 struct vmcb_segment ss; 400 struct vmcb_segment ds; 401 struct vmcb_segment fs; 402 struct vmcb_segment gs; 403 struct vmcb_segment gdt; 404 struct vmcb_segment ldt; 405 struct vmcb_segment idt; 406 struct vmcb_segment tr; 407 uint8_t rsvd1[43]; 408 uint8_t cpl; 409 uint8_t rsvd2[4]; 410 uint64_t efer; 411 uint8_t rsvd3[112]; 412 uint64_t cr4; 413 uint64_t cr3; 414 uint64_t cr0; 415 uint64_t dr7; 416 uint64_t dr6; 417 uint64_t rflags; 418 uint64_t rip; 419 uint8_t rsvd4[88]; 420 uint64_t rsp; 421 uint8_t rsvd5[24]; 422 uint64_t rax; 423 uint64_t star; 424 uint64_t lstar; 425 uint64_t cstar; 426 uint64_t sfmask; 427 uint64_t kernelgsbase; 428 uint64_t sysenter_cs; 429 uint64_t sysenter_esp; 430 uint64_t sysenter_eip; 431 uint64_t cr2; 432 uint8_t rsvd6[32]; 433 uint64_t g_pat; 434 uint64_t dbgctl; 435 uint64_t br_from; 436 uint64_t br_to; 437 uint64_t int_from; 438 uint64_t int_to; 439 uint8_t pad[2408]; 440 } __packed; 441 442 CTASSERT(sizeof(struct vmcb_state) == 0xC00); 443 444 struct vmcb { 445 struct vmcb_ctrl ctrl; 446 struct vmcb_state state; 447 } __packed; 448 449 CTASSERT(sizeof(struct vmcb) == PAGE_SIZE); 450 CTASSERT(offsetof(struct vmcb, state) == 0x400); 451 452 /* -------------------------------------------------------------------------- */ 453 454 struct svm_hsave { 455 paddr_t pa; 456 }; 457 458 static struct svm_hsave hsave[MAXCPUS]; 459 460 static uint8_t *svm_asidmap __read_mostly; 461 static uint32_t svm_maxasid __read_mostly; 462 static kmutex_t svm_asidlock __cacheline_aligned; 463 464 static bool svm_decode_assist __read_mostly; 465 static uint32_t svm_ctrl_tlb_flush __read_mostly; 466 467 #define SVM_XCR0_MASK_DEFAULT (XCR0_X87|XCR0_SSE) 468 static uint64_t svm_xcr0_mask __read_mostly; 469 470 #define SVM_NCPUIDS 32 471 472 #define VMCB_NPAGES 1 473 474 #define MSRBM_NPAGES 2 475 #define MSRBM_SIZE (MSRBM_NPAGES * PAGE_SIZE) 476 477 #define IOBM_NPAGES 3 478 #define IOBM_SIZE (IOBM_NPAGES * PAGE_SIZE) 479 480 /* Does not include EFER_LMSLE. */ 481 #define EFER_VALID \ 482 (EFER_SCE|EFER_LME|EFER_LMA|EFER_NXE|EFER_SVME|EFER_FFXSR|EFER_TCE) 483 484 #define EFER_TLB_FLUSH \ 485 (EFER_NXE|EFER_LMA|EFER_LME) 486 #define CR0_TLB_FLUSH \ 487 (CR0_PG|CR0_WP|CR0_CD|CR0_NW) 488 #define CR4_TLB_FLUSH \ 489 (CR4_PGE|CR4_PAE|CR4_PSE) 490 491 /* -------------------------------------------------------------------------- */ 492 493 struct svm_machdata { 494 bool cpuidpresent[SVM_NCPUIDS]; 495 struct nvmm_x86_conf_cpuid cpuid[SVM_NCPUIDS]; 496 }; 497 498 static const size_t svm_conf_sizes[NVMM_X86_NCONF] = { 499 [NVMM_X86_CONF_CPUID] = sizeof(struct nvmm_x86_conf_cpuid) 500 }; 501 502 struct svm_cpudata { 503 /* General */ 504 bool shared_asid; 505 bool tlb_want_flush; 506 507 /* VMCB */ 508 struct vmcb *vmcb; 509 paddr_t vmcb_pa; 510 511 /* I/O bitmap */ 512 uint8_t *iobm; 513 paddr_t iobm_pa; 514 515 /* MSR bitmap */ 516 uint8_t *msrbm; 517 paddr_t msrbm_pa; 518 519 /* Host state */ 520 uint64_t hxcr0; 521 uint64_t star; 522 uint64_t lstar; 523 uint64_t cstar; 524 uint64_t sfmask; 525 uint64_t fsbase; 526 uint64_t kernelgsbase; 527 bool ts_set; 528 struct xsave_header hfpu __aligned(64); 529 530 /* Event state */ 531 bool int_window_exit; 532 bool nmi_window_exit; 533 534 /* Guest state */ 535 uint64_t gxcr0; 536 uint64_t gprs[NVMM_X64_NGPR]; 537 uint64_t drs[NVMM_X64_NDR]; 538 uint64_t tsc_offset; 539 struct xsave_header gfpu __aligned(64); 540 }; 541 542 static void 543 svm_vmcb_cache_default(struct vmcb *vmcb) 544 { 545 vmcb->ctrl.vmcb_clean = 546 VMCB_CTRL_VMCB_CLEAN_I | 547 VMCB_CTRL_VMCB_CLEAN_IOPM | 548 VMCB_CTRL_VMCB_CLEAN_ASID | 549 VMCB_CTRL_VMCB_CLEAN_TPR | 550 VMCB_CTRL_VMCB_CLEAN_NP | 551 VMCB_CTRL_VMCB_CLEAN_CR | 552 VMCB_CTRL_VMCB_CLEAN_DR | 553 VMCB_CTRL_VMCB_CLEAN_DT | 554 VMCB_CTRL_VMCB_CLEAN_SEG | 555 VMCB_CTRL_VMCB_CLEAN_CR2 | 556 VMCB_CTRL_VMCB_CLEAN_LBR | 557 VMCB_CTRL_VMCB_CLEAN_AVIC; 558 } 559 560 static void 561 svm_vmcb_cache_update(struct vmcb *vmcb, uint64_t flags) 562 { 563 if (flags & NVMM_X64_STATE_SEGS) { 564 vmcb->ctrl.vmcb_clean &= 565 ~(VMCB_CTRL_VMCB_CLEAN_SEG | VMCB_CTRL_VMCB_CLEAN_DT); 566 } 567 if (flags & NVMM_X64_STATE_CRS) { 568 vmcb->ctrl.vmcb_clean &= 569 ~(VMCB_CTRL_VMCB_CLEAN_CR | VMCB_CTRL_VMCB_CLEAN_CR2 | 570 VMCB_CTRL_VMCB_CLEAN_TPR); 571 } 572 if (flags & NVMM_X64_STATE_DRS) { 573 vmcb->ctrl.vmcb_clean &= ~VMCB_CTRL_VMCB_CLEAN_DR; 574 } 575 if (flags & NVMM_X64_STATE_MSRS) { 576 /* CR for EFER, NP for PAT. */ 577 vmcb->ctrl.vmcb_clean &= 578 ~(VMCB_CTRL_VMCB_CLEAN_CR | VMCB_CTRL_VMCB_CLEAN_NP); 579 } 580 } 581 582 static inline void 583 svm_vmcb_cache_flush(struct vmcb *vmcb, uint64_t flags) 584 { 585 vmcb->ctrl.vmcb_clean &= ~flags; 586 } 587 588 static inline void 589 svm_vmcb_cache_flush_all(struct vmcb *vmcb) 590 { 591 vmcb->ctrl.vmcb_clean = 0; 592 } 593 594 #define SVM_EVENT_TYPE_HW_INT 0 595 #define SVM_EVENT_TYPE_NMI 2 596 #define SVM_EVENT_TYPE_EXC 3 597 #define SVM_EVENT_TYPE_SW_INT 4 598 599 static void 600 svm_event_waitexit_enable(struct nvmm_cpu *vcpu, bool nmi) 601 { 602 struct svm_cpudata *cpudata = vcpu->cpudata; 603 struct vmcb *vmcb = cpudata->vmcb; 604 605 if (nmi) { 606 vmcb->ctrl.intercept_misc1 |= VMCB_CTRL_INTERCEPT_IRET; 607 cpudata->nmi_window_exit = true; 608 } else { 609 vmcb->ctrl.intercept_misc1 |= VMCB_CTRL_INTERCEPT_VINTR; 610 vmcb->ctrl.v |= (VMCB_CTRL_V_IRQ | VMCB_CTRL_V_IGN_TPR); 611 svm_vmcb_cache_flush(vmcb, VMCB_CTRL_VMCB_CLEAN_TPR); 612 cpudata->int_window_exit = true; 613 } 614 615 svm_vmcb_cache_flush(vmcb, VMCB_CTRL_VMCB_CLEAN_I); 616 } 617 618 static void 619 svm_event_waitexit_disable(struct nvmm_cpu *vcpu, bool nmi) 620 { 621 struct svm_cpudata *cpudata = vcpu->cpudata; 622 struct vmcb *vmcb = cpudata->vmcb; 623 624 if (nmi) { 625 vmcb->ctrl.intercept_misc1 &= ~VMCB_CTRL_INTERCEPT_IRET; 626 cpudata->nmi_window_exit = false; 627 } else { 628 vmcb->ctrl.intercept_misc1 &= ~VMCB_CTRL_INTERCEPT_VINTR; 629 vmcb->ctrl.v &= ~(VMCB_CTRL_V_IRQ | VMCB_CTRL_V_IGN_TPR); 630 svm_vmcb_cache_flush(vmcb, VMCB_CTRL_VMCB_CLEAN_TPR); 631 cpudata->int_window_exit = false; 632 } 633 634 svm_vmcb_cache_flush(vmcb, VMCB_CTRL_VMCB_CLEAN_I); 635 } 636 637 static inline int 638 svm_event_has_error(uint64_t vector) 639 { 640 switch (vector) { 641 case 8: /* #DF */ 642 case 10: /* #TS */ 643 case 11: /* #NP */ 644 case 12: /* #SS */ 645 case 13: /* #GP */ 646 case 14: /* #PF */ 647 case 17: /* #AC */ 648 case 30: /* #SX */ 649 return 1; 650 default: 651 return 0; 652 } 653 } 654 655 static int 656 svm_vcpu_inject(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 657 struct nvmm_event *event) 658 { 659 struct svm_cpudata *cpudata = vcpu->cpudata; 660 struct vmcb *vmcb = cpudata->vmcb; 661 int type = 0, err = 0; 662 663 if (event->vector >= 256) { 664 return EINVAL; 665 } 666 667 switch (event->type) { 668 case NVMM_EVENT_INTERRUPT_HW: 669 type = SVM_EVENT_TYPE_HW_INT; 670 if (event->vector == 2) { 671 type = SVM_EVENT_TYPE_NMI; 672 } 673 if (type == SVM_EVENT_TYPE_NMI) { 674 if (cpudata->nmi_window_exit) { 675 return EAGAIN; 676 } 677 svm_event_waitexit_enable(vcpu, true); 678 } else { 679 if (((vmcb->state.rflags & PSL_I) == 0) || 680 ((vmcb->ctrl.intr & VMCB_CTRL_INTR_SHADOW) != 0)) { 681 svm_event_waitexit_enable(vcpu, false); 682 return EAGAIN; 683 } 684 } 685 err = 0; 686 break; 687 case NVMM_EVENT_INTERRUPT_SW: 688 return EINVAL; 689 case NVMM_EVENT_EXCEPTION: 690 type = SVM_EVENT_TYPE_EXC; 691 if (event->vector == 2 || event->vector >= 32) 692 return EINVAL; 693 if (event->vector == 3 || event->vector == 0) 694 return EINVAL; 695 err = svm_event_has_error(event->vector); 696 break; 697 default: 698 return EINVAL; 699 } 700 701 vmcb->ctrl.eventinj = 702 __SHIFTIN(event->vector, VMCB_CTRL_EVENTINJ_VECTOR) | 703 __SHIFTIN(type, VMCB_CTRL_EVENTINJ_TYPE) | 704 __SHIFTIN(err, VMCB_CTRL_EVENTINJ_EV) | 705 __SHIFTIN(1, VMCB_CTRL_EVENTINJ_V) | 706 __SHIFTIN(event->u.error, VMCB_CTRL_EVENTINJ_ERRORCODE); 707 708 return 0; 709 } 710 711 static void 712 svm_inject_ud(struct nvmm_machine *mach, struct nvmm_cpu *vcpu) 713 { 714 struct nvmm_event event; 715 int ret __diagused; 716 717 event.type = NVMM_EVENT_EXCEPTION; 718 event.vector = 6; 719 event.u.error = 0; 720 721 ret = svm_vcpu_inject(mach, vcpu, &event); 722 KASSERT(ret == 0); 723 } 724 725 static void 726 svm_inject_gp(struct nvmm_machine *mach, struct nvmm_cpu *vcpu) 727 { 728 struct nvmm_event event; 729 int ret __diagused; 730 731 event.type = NVMM_EVENT_EXCEPTION; 732 event.vector = 13; 733 event.u.error = 0; 734 735 ret = svm_vcpu_inject(mach, vcpu, &event); 736 KASSERT(ret == 0); 737 } 738 739 static inline void 740 svm_inkernel_advance(struct vmcb *vmcb) 741 { 742 /* 743 * Maybe we should also apply single-stepping and debug exceptions. 744 * Matters for guest-ring3, because it can execute 'cpuid' under a 745 * debugger. 746 */ 747 vmcb->state.rip = vmcb->ctrl.nrip; 748 vmcb->ctrl.intr &= ~VMCB_CTRL_INTR_SHADOW; 749 } 750 751 static void 752 svm_inkernel_handle_cpuid(struct nvmm_cpu *vcpu, uint64_t eax, uint64_t ecx) 753 { 754 struct svm_cpudata *cpudata = vcpu->cpudata; 755 uint64_t cr4; 756 757 switch (eax) { 758 case 0x00000001: 759 cpudata->gprs[NVMM_X64_GPR_RBX] &= ~CPUID_LOCAL_APIC_ID; 760 cpudata->gprs[NVMM_X64_GPR_RBX] |= __SHIFTIN(vcpu->cpuid, 761 CPUID_LOCAL_APIC_ID); 762 763 /* CPUID2_OSXSAVE depends on CR4. */ 764 cr4 = cpudata->vmcb->state.cr4; 765 if (!(cr4 & CR4_OSXSAVE)) { 766 cpudata->gprs[NVMM_X64_GPR_RCX] &= ~CPUID2_OSXSAVE; 767 } 768 break; 769 case 0x0000000D: 770 if (svm_xcr0_mask == 0) { 771 break; 772 } 773 switch (ecx) { 774 case 0: 775 cpudata->vmcb->state.rax = svm_xcr0_mask & 0xFFFFFFFF; 776 if (cpudata->gxcr0 & XCR0_SSE) { 777 cpudata->gprs[NVMM_X64_GPR_RBX] = sizeof(struct fxsave); 778 } else { 779 cpudata->gprs[NVMM_X64_GPR_RBX] = sizeof(struct save87); 780 } 781 cpudata->gprs[NVMM_X64_GPR_RBX] += 64; /* XSAVE header */ 782 cpudata->gprs[NVMM_X64_GPR_RCX] = sizeof(struct fxsave); 783 cpudata->gprs[NVMM_X64_GPR_RDX] = svm_xcr0_mask >> 32; 784 break; 785 case 1: 786 cpudata->vmcb->state.rax &= ~CPUID_PES1_XSAVES; 787 break; 788 } 789 break; 790 case 0x40000000: 791 cpudata->gprs[NVMM_X64_GPR_RBX] = 0; 792 cpudata->gprs[NVMM_X64_GPR_RCX] = 0; 793 cpudata->gprs[NVMM_X64_GPR_RDX] = 0; 794 memcpy(&cpudata->gprs[NVMM_X64_GPR_RBX], "___ ", 4); 795 memcpy(&cpudata->gprs[NVMM_X64_GPR_RCX], "NVMM", 4); 796 memcpy(&cpudata->gprs[NVMM_X64_GPR_RDX], " ___", 4); 797 break; 798 case 0x80000001: 799 cpudata->gprs[NVMM_X64_GPR_RCX] &= ~CPUID_SVM; 800 cpudata->gprs[NVMM_X64_GPR_RDX] &= ~CPUID_RDTSCP; 801 break; 802 default: 803 break; 804 } 805 } 806 807 static void 808 svm_exit_cpuid(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 809 struct nvmm_exit *exit) 810 { 811 struct svm_machdata *machdata = mach->machdata; 812 struct svm_cpudata *cpudata = vcpu->cpudata; 813 struct nvmm_x86_conf_cpuid *cpuid; 814 uint64_t eax, ecx; 815 u_int descs[4]; 816 size_t i; 817 818 eax = cpudata->vmcb->state.rax; 819 ecx = cpudata->gprs[NVMM_X64_GPR_RCX]; 820 x86_cpuid2(eax, ecx, descs); 821 822 cpudata->vmcb->state.rax = descs[0]; 823 cpudata->gprs[NVMM_X64_GPR_RBX] = descs[1]; 824 cpudata->gprs[NVMM_X64_GPR_RCX] = descs[2]; 825 cpudata->gprs[NVMM_X64_GPR_RDX] = descs[3]; 826 827 for (i = 0; i < SVM_NCPUIDS; i++) { 828 cpuid = &machdata->cpuid[i]; 829 if (!machdata->cpuidpresent[i]) { 830 continue; 831 } 832 if (cpuid->leaf != eax) { 833 continue; 834 } 835 836 /* del */ 837 cpudata->vmcb->state.rax &= ~cpuid->del.eax; 838 cpudata->gprs[NVMM_X64_GPR_RBX] &= ~cpuid->del.ebx; 839 cpudata->gprs[NVMM_X64_GPR_RCX] &= ~cpuid->del.ecx; 840 cpudata->gprs[NVMM_X64_GPR_RDX] &= ~cpuid->del.edx; 841 842 /* set */ 843 cpudata->vmcb->state.rax |= cpuid->set.eax; 844 cpudata->gprs[NVMM_X64_GPR_RBX] |= cpuid->set.ebx; 845 cpudata->gprs[NVMM_X64_GPR_RCX] |= cpuid->set.ecx; 846 cpudata->gprs[NVMM_X64_GPR_RDX] |= cpuid->set.edx; 847 848 break; 849 } 850 851 /* Overwrite non-tunable leaves. */ 852 svm_inkernel_handle_cpuid(vcpu, eax, ecx); 853 854 svm_inkernel_advance(cpudata->vmcb); 855 exit->reason = NVMM_EXIT_NONE; 856 } 857 858 static void 859 svm_exit_hlt(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 860 struct nvmm_exit *exit) 861 { 862 struct svm_cpudata *cpudata = vcpu->cpudata; 863 struct vmcb *vmcb = cpudata->vmcb; 864 865 if (cpudata->int_window_exit && (vmcb->state.rflags & PSL_I)) { 866 svm_event_waitexit_disable(vcpu, false); 867 } 868 869 svm_inkernel_advance(cpudata->vmcb); 870 exit->reason = NVMM_EXIT_HALTED; 871 } 872 873 #define SVM_EXIT_IO_PORT __BITS(31,16) 874 #define SVM_EXIT_IO_SEG __BITS(12,10) 875 #define SVM_EXIT_IO_A64 __BIT(9) 876 #define SVM_EXIT_IO_A32 __BIT(8) 877 #define SVM_EXIT_IO_A16 __BIT(7) 878 #define SVM_EXIT_IO_SZ32 __BIT(6) 879 #define SVM_EXIT_IO_SZ16 __BIT(5) 880 #define SVM_EXIT_IO_SZ8 __BIT(4) 881 #define SVM_EXIT_IO_REP __BIT(3) 882 #define SVM_EXIT_IO_STR __BIT(2) 883 #define SVM_EXIT_IO_IN __BIT(0) 884 885 static const int seg_to_nvmm[] = { 886 [0] = NVMM_X64_SEG_ES, 887 [1] = NVMM_X64_SEG_CS, 888 [2] = NVMM_X64_SEG_SS, 889 [3] = NVMM_X64_SEG_DS, 890 [4] = NVMM_X64_SEG_FS, 891 [5] = NVMM_X64_SEG_GS 892 }; 893 894 static void 895 svm_exit_io(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 896 struct nvmm_exit *exit) 897 { 898 struct svm_cpudata *cpudata = vcpu->cpudata; 899 uint64_t info = cpudata->vmcb->ctrl.exitinfo1; 900 uint64_t nextpc = cpudata->vmcb->ctrl.exitinfo2; 901 902 exit->reason = NVMM_EXIT_IO; 903 904 if (info & SVM_EXIT_IO_IN) { 905 exit->u.io.type = NVMM_EXIT_IO_IN; 906 } else { 907 exit->u.io.type = NVMM_EXIT_IO_OUT; 908 } 909 910 exit->u.io.port = __SHIFTOUT(info, SVM_EXIT_IO_PORT); 911 912 if (svm_decode_assist) { 913 KASSERT(__SHIFTOUT(info, SVM_EXIT_IO_SEG) < 6); 914 exit->u.io.seg = seg_to_nvmm[__SHIFTOUT(info, SVM_EXIT_IO_SEG)]; 915 } else { 916 exit->u.io.seg = -1; 917 } 918 919 if (info & SVM_EXIT_IO_A64) { 920 exit->u.io.address_size = 8; 921 } else if (info & SVM_EXIT_IO_A32) { 922 exit->u.io.address_size = 4; 923 } else if (info & SVM_EXIT_IO_A16) { 924 exit->u.io.address_size = 2; 925 } 926 927 if (info & SVM_EXIT_IO_SZ32) { 928 exit->u.io.operand_size = 4; 929 } else if (info & SVM_EXIT_IO_SZ16) { 930 exit->u.io.operand_size = 2; 931 } else if (info & SVM_EXIT_IO_SZ8) { 932 exit->u.io.operand_size = 1; 933 } 934 935 exit->u.io.rep = (info & SVM_EXIT_IO_REP) != 0; 936 exit->u.io.str = (info & SVM_EXIT_IO_STR) != 0; 937 exit->u.io.npc = nextpc; 938 } 939 940 static const uint64_t msr_ignore_list[] = { 941 0xc0010055, /* MSR_CMPHALT */ 942 MSR_DE_CFG, 943 MSR_IC_CFG, 944 MSR_UCODE_AMD_PATCHLEVEL 945 }; 946 947 static bool 948 svm_inkernel_handle_msr(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 949 struct nvmm_exit *exit) 950 { 951 struct svm_cpudata *cpudata = vcpu->cpudata; 952 struct vmcb *vmcb = cpudata->vmcb; 953 uint64_t val; 954 size_t i; 955 956 switch (exit->u.msr.type) { 957 case NVMM_EXIT_MSR_RDMSR: 958 if (exit->u.msr.msr == MSR_NB_CFG) { 959 val = NB_CFG_INITAPICCPUIDLO; 960 vmcb->state.rax = (val & 0xFFFFFFFF); 961 cpudata->gprs[NVMM_X64_GPR_RDX] = (val >> 32); 962 goto handled; 963 } 964 for (i = 0; i < __arraycount(msr_ignore_list); i++) { 965 if (msr_ignore_list[i] != exit->u.msr.msr) 966 continue; 967 val = 0; 968 vmcb->state.rax = (val & 0xFFFFFFFF); 969 cpudata->gprs[NVMM_X64_GPR_RDX] = (val >> 32); 970 goto handled; 971 } 972 break; 973 case NVMM_EXIT_MSR_WRMSR: 974 if (exit->u.msr.msr == MSR_EFER) { 975 if (__predict_false(exit->u.msr.val & ~EFER_VALID)) { 976 goto error; 977 } 978 if ((vmcb->state.efer ^ exit->u.msr.val) & 979 EFER_TLB_FLUSH) { 980 cpudata->tlb_want_flush = true; 981 } 982 vmcb->state.efer = exit->u.msr.val | EFER_SVME; 983 svm_vmcb_cache_flush(vmcb, VMCB_CTRL_VMCB_CLEAN_CR); 984 goto handled; 985 } 986 if (exit->u.msr.msr == MSR_TSC) { 987 cpudata->tsc_offset = exit->u.msr.val - cpu_counter(); 988 vmcb->ctrl.tsc_offset = cpudata->tsc_offset + 989 curcpu()->ci_data.cpu_cc_skew; 990 svm_vmcb_cache_flush(vmcb, VMCB_CTRL_VMCB_CLEAN_I); 991 goto handled; 992 } 993 for (i = 0; i < __arraycount(msr_ignore_list); i++) { 994 if (msr_ignore_list[i] != exit->u.msr.msr) 995 continue; 996 goto handled; 997 } 998 break; 999 } 1000 1001 return false; 1002 1003 handled: 1004 svm_inkernel_advance(cpudata->vmcb); 1005 return true; 1006 1007 error: 1008 svm_inject_gp(mach, vcpu); 1009 return true; 1010 } 1011 1012 static void 1013 svm_exit_msr(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 1014 struct nvmm_exit *exit) 1015 { 1016 struct svm_cpudata *cpudata = vcpu->cpudata; 1017 uint64_t info = cpudata->vmcb->ctrl.exitinfo1; 1018 1019 if (info == 0) { 1020 exit->u.msr.type = NVMM_EXIT_MSR_RDMSR; 1021 } else { 1022 exit->u.msr.type = NVMM_EXIT_MSR_WRMSR; 1023 } 1024 1025 exit->u.msr.msr = (cpudata->gprs[NVMM_X64_GPR_RCX] & 0xFFFFFFFF); 1026 1027 if (info == 1) { 1028 uint64_t rdx, rax; 1029 rdx = cpudata->gprs[NVMM_X64_GPR_RDX]; 1030 rax = cpudata->vmcb->state.rax; 1031 exit->u.msr.val = (rdx << 32) | (rax & 0xFFFFFFFF); 1032 } else { 1033 exit->u.msr.val = 0; 1034 } 1035 1036 if (svm_inkernel_handle_msr(mach, vcpu, exit)) { 1037 exit->reason = NVMM_EXIT_NONE; 1038 return; 1039 } 1040 1041 exit->reason = NVMM_EXIT_MSR; 1042 exit->u.msr.npc = cpudata->vmcb->ctrl.nrip; 1043 } 1044 1045 static void 1046 svm_exit_npf(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 1047 struct nvmm_exit *exit) 1048 { 1049 struct svm_cpudata *cpudata = vcpu->cpudata; 1050 gpaddr_t gpa = cpudata->vmcb->ctrl.exitinfo2; 1051 int error; 1052 1053 error = uvm_fault(&mach->vm->vm_map, gpa, VM_PROT_ALL); 1054 1055 if (error) { 1056 exit->reason = NVMM_EXIT_MEMORY; 1057 if (cpudata->vmcb->ctrl.exitinfo1 & PGEX_W) 1058 exit->u.mem.perm = NVMM_EXIT_MEMORY_WRITE; 1059 else if (cpudata->vmcb->ctrl.exitinfo1 & PGEX_X) 1060 exit->u.mem.perm = NVMM_EXIT_MEMORY_EXEC; 1061 else 1062 exit->u.mem.perm = NVMM_EXIT_MEMORY_READ; 1063 exit->u.mem.gpa = gpa; 1064 exit->u.mem.inst_len = cpudata->vmcb->ctrl.inst_len; 1065 memcpy(exit->u.mem.inst_bytes, cpudata->vmcb->ctrl.inst_bytes, 1066 sizeof(exit->u.mem.inst_bytes)); 1067 } else { 1068 exit->reason = NVMM_EXIT_NONE; 1069 } 1070 } 1071 1072 static void 1073 svm_exit_insn(struct vmcb *vmcb, struct nvmm_exit *exit, uint64_t reason) 1074 { 1075 exit->u.insn.npc = vmcb->ctrl.nrip; 1076 exit->reason = reason; 1077 } 1078 1079 static void 1080 svm_exit_xsetbv(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 1081 struct nvmm_exit *exit) 1082 { 1083 struct svm_cpudata *cpudata = vcpu->cpudata; 1084 struct vmcb *vmcb = cpudata->vmcb; 1085 uint64_t val; 1086 1087 exit->reason = NVMM_EXIT_NONE; 1088 1089 val = (cpudata->gprs[NVMM_X64_GPR_RDX] << 32) | 1090 (vmcb->state.rax & 0xFFFFFFFF); 1091 1092 if (__predict_false(cpudata->gprs[NVMM_X64_GPR_RCX] != 0)) { 1093 goto error; 1094 } else if (__predict_false(vmcb->state.cpl != 0)) { 1095 goto error; 1096 } else if (__predict_false((val & ~svm_xcr0_mask) != 0)) { 1097 goto error; 1098 } else if (__predict_false((val & XCR0_X87) == 0)) { 1099 goto error; 1100 } 1101 1102 cpudata->gxcr0 = val; 1103 1104 svm_inkernel_advance(cpudata->vmcb); 1105 return; 1106 1107 error: 1108 svm_inject_gp(mach, vcpu); 1109 } 1110 1111 static void 1112 svm_vcpu_guest_fpu_enter(struct nvmm_cpu *vcpu) 1113 { 1114 struct svm_cpudata *cpudata = vcpu->cpudata; 1115 1116 cpudata->ts_set = (rcr0() & CR0_TS) != 0; 1117 1118 fpu_area_save(&cpudata->hfpu, svm_xcr0_mask); 1119 fpu_area_restore(&cpudata->gfpu, svm_xcr0_mask); 1120 1121 if (svm_xcr0_mask != 0) { 1122 cpudata->hxcr0 = rdxcr(0); 1123 wrxcr(0, cpudata->gxcr0); 1124 } 1125 } 1126 1127 static void 1128 svm_vcpu_guest_fpu_leave(struct nvmm_cpu *vcpu) 1129 { 1130 struct svm_cpudata *cpudata = vcpu->cpudata; 1131 1132 if (svm_xcr0_mask != 0) { 1133 cpudata->gxcr0 = rdxcr(0); 1134 wrxcr(0, cpudata->hxcr0); 1135 } 1136 1137 fpu_area_save(&cpudata->gfpu, svm_xcr0_mask); 1138 fpu_area_restore(&cpudata->hfpu, svm_xcr0_mask); 1139 1140 if (cpudata->ts_set) { 1141 stts(); 1142 } 1143 } 1144 1145 static void 1146 svm_vcpu_guest_dbregs_enter(struct nvmm_cpu *vcpu) 1147 { 1148 struct svm_cpudata *cpudata = vcpu->cpudata; 1149 1150 x86_dbregs_save(curlwp); 1151 1152 ldr7(0); 1153 1154 ldr0(cpudata->drs[NVMM_X64_DR_DR0]); 1155 ldr1(cpudata->drs[NVMM_X64_DR_DR1]); 1156 ldr2(cpudata->drs[NVMM_X64_DR_DR2]); 1157 ldr3(cpudata->drs[NVMM_X64_DR_DR3]); 1158 } 1159 1160 static void 1161 svm_vcpu_guest_dbregs_leave(struct nvmm_cpu *vcpu) 1162 { 1163 struct svm_cpudata *cpudata = vcpu->cpudata; 1164 1165 cpudata->drs[NVMM_X64_DR_DR0] = rdr0(); 1166 cpudata->drs[NVMM_X64_DR_DR1] = rdr1(); 1167 cpudata->drs[NVMM_X64_DR_DR2] = rdr2(); 1168 cpudata->drs[NVMM_X64_DR_DR3] = rdr3(); 1169 1170 x86_dbregs_restore(curlwp); 1171 } 1172 1173 static void 1174 svm_vcpu_guest_misc_enter(struct nvmm_cpu *vcpu) 1175 { 1176 struct svm_cpudata *cpudata = vcpu->cpudata; 1177 1178 cpudata->fsbase = rdmsr(MSR_FSBASE); 1179 cpudata->kernelgsbase = rdmsr(MSR_KERNELGSBASE); 1180 } 1181 1182 static void 1183 svm_vcpu_guest_misc_leave(struct nvmm_cpu *vcpu) 1184 { 1185 struct svm_cpudata *cpudata = vcpu->cpudata; 1186 1187 wrmsr(MSR_STAR, cpudata->star); 1188 wrmsr(MSR_LSTAR, cpudata->lstar); 1189 wrmsr(MSR_CSTAR, cpudata->cstar); 1190 wrmsr(MSR_SFMASK, cpudata->sfmask); 1191 wrmsr(MSR_FSBASE, cpudata->fsbase); 1192 wrmsr(MSR_KERNELGSBASE, cpudata->kernelgsbase); 1193 } 1194 1195 static int 1196 svm_vcpu_run(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 1197 struct nvmm_exit *exit) 1198 { 1199 struct svm_cpudata *cpudata = vcpu->cpudata; 1200 struct vmcb *vmcb = cpudata->vmcb; 1201 bool tlb_need_flush = false; 1202 int hcpu, s; 1203 1204 kpreempt_disable(); 1205 hcpu = cpu_number(); 1206 1207 if (vcpu->hcpu_last != hcpu || cpudata->shared_asid) { 1208 tlb_need_flush = true; 1209 } 1210 1211 if (vcpu->hcpu_last != hcpu) { 1212 vmcb->ctrl.tsc_offset = cpudata->tsc_offset + 1213 curcpu()->ci_data.cpu_cc_skew; 1214 svm_vmcb_cache_flush_all(vmcb); 1215 } 1216 1217 svm_vcpu_guest_dbregs_enter(vcpu); 1218 svm_vcpu_guest_misc_enter(vcpu); 1219 1220 while (1) { 1221 if (cpudata->tlb_want_flush || tlb_need_flush) { 1222 vmcb->ctrl.tlb_ctrl = svm_ctrl_tlb_flush; 1223 } else { 1224 vmcb->ctrl.tlb_ctrl = 0; 1225 } 1226 1227 s = splhigh(); 1228 svm_vcpu_guest_fpu_enter(vcpu); 1229 svm_vmrun(cpudata->vmcb_pa, cpudata->gprs); 1230 svm_vcpu_guest_fpu_leave(vcpu); 1231 splx(s); 1232 1233 svm_vmcb_cache_default(vmcb); 1234 1235 if (vmcb->ctrl.exitcode != VMCB_EXITCODE_INVALID) { 1236 cpudata->tlb_want_flush = false; 1237 tlb_need_flush = false; 1238 vcpu->hcpu_last = hcpu; 1239 } 1240 1241 switch (vmcb->ctrl.exitcode) { 1242 case VMCB_EXITCODE_INTR: 1243 case VMCB_EXITCODE_NMI: 1244 exit->reason = NVMM_EXIT_NONE; 1245 break; 1246 case VMCB_EXITCODE_VINTR: 1247 svm_event_waitexit_disable(vcpu, false); 1248 exit->reason = NVMM_EXIT_INT_READY; 1249 break; 1250 case VMCB_EXITCODE_IRET: 1251 svm_event_waitexit_disable(vcpu, true); 1252 exit->reason = NVMM_EXIT_NMI_READY; 1253 break; 1254 case VMCB_EXITCODE_CPUID: 1255 svm_exit_cpuid(mach, vcpu, exit); 1256 break; 1257 case VMCB_EXITCODE_HLT: 1258 svm_exit_hlt(mach, vcpu, exit); 1259 break; 1260 case VMCB_EXITCODE_IOIO: 1261 svm_exit_io(mach, vcpu, exit); 1262 break; 1263 case VMCB_EXITCODE_MSR: 1264 svm_exit_msr(mach, vcpu, exit); 1265 break; 1266 case VMCB_EXITCODE_SHUTDOWN: 1267 exit->reason = NVMM_EXIT_SHUTDOWN; 1268 break; 1269 case VMCB_EXITCODE_RDPMC: 1270 case VMCB_EXITCODE_RSM: 1271 case VMCB_EXITCODE_INVLPGA: 1272 case VMCB_EXITCODE_VMRUN: 1273 case VMCB_EXITCODE_VMMCALL: 1274 case VMCB_EXITCODE_VMLOAD: 1275 case VMCB_EXITCODE_VMSAVE: 1276 case VMCB_EXITCODE_STGI: 1277 case VMCB_EXITCODE_CLGI: 1278 case VMCB_EXITCODE_SKINIT: 1279 case VMCB_EXITCODE_RDTSCP: 1280 svm_inject_ud(mach, vcpu); 1281 exit->reason = NVMM_EXIT_NONE; 1282 break; 1283 case VMCB_EXITCODE_MONITOR: 1284 svm_exit_insn(vmcb, exit, NVMM_EXIT_MONITOR); 1285 break; 1286 case VMCB_EXITCODE_MWAIT: 1287 svm_exit_insn(vmcb, exit, NVMM_EXIT_MWAIT); 1288 break; 1289 case VMCB_EXITCODE_MWAIT_CONDITIONAL: 1290 svm_exit_insn(vmcb, exit, NVMM_EXIT_MWAIT_COND); 1291 break; 1292 case VMCB_EXITCODE_XSETBV: 1293 svm_exit_xsetbv(mach, vcpu, exit); 1294 break; 1295 case VMCB_EXITCODE_NPF: 1296 svm_exit_npf(mach, vcpu, exit); 1297 break; 1298 case VMCB_EXITCODE_FERR_FREEZE: /* ? */ 1299 default: 1300 exit->reason = NVMM_EXIT_INVALID; 1301 break; 1302 } 1303 1304 /* If no reason to return to userland, keep rolling. */ 1305 if (curcpu()->ci_schedstate.spc_flags & SPCF_SHOULDYIELD) { 1306 break; 1307 } 1308 if (curcpu()->ci_data.cpu_softints != 0) { 1309 break; 1310 } 1311 if (curlwp->l_flag & LW_USERRET) { 1312 break; 1313 } 1314 if (exit->reason != NVMM_EXIT_NONE) { 1315 break; 1316 } 1317 } 1318 1319 svm_vcpu_guest_misc_leave(vcpu); 1320 svm_vcpu_guest_dbregs_leave(vcpu); 1321 1322 kpreempt_enable(); 1323 1324 exit->exitstate[NVMM_X64_EXITSTATE_CR8] = __SHIFTOUT(vmcb->ctrl.v, 1325 VMCB_CTRL_V_TPR); 1326 exit->exitstate[NVMM_X64_EXITSTATE_RFLAGS] = vmcb->state.rflags; 1327 1328 exit->exitstate[NVMM_X64_EXITSTATE_INT_SHADOW] = 1329 ((vmcb->ctrl.intr & VMCB_CTRL_INTR_SHADOW) != 0); 1330 exit->exitstate[NVMM_X64_EXITSTATE_INT_WINDOW_EXIT] = 1331 cpudata->int_window_exit; 1332 exit->exitstate[NVMM_X64_EXITSTATE_NMI_WINDOW_EXIT] = 1333 cpudata->nmi_window_exit; 1334 1335 return 0; 1336 } 1337 1338 /* -------------------------------------------------------------------------- */ 1339 1340 static int 1341 svm_memalloc(paddr_t *pa, vaddr_t *va, size_t npages) 1342 { 1343 struct pglist pglist; 1344 paddr_t _pa; 1345 vaddr_t _va; 1346 size_t i; 1347 int ret; 1348 1349 ret = uvm_pglistalloc(npages * PAGE_SIZE, 0, ~0UL, PAGE_SIZE, 0, 1350 &pglist, 1, 0); 1351 if (ret != 0) 1352 return ENOMEM; 1353 _pa = TAILQ_FIRST(&pglist)->phys_addr; 1354 _va = uvm_km_alloc(kernel_map, npages * PAGE_SIZE, 0, 1355 UVM_KMF_VAONLY | UVM_KMF_NOWAIT); 1356 if (_va == 0) 1357 goto error; 1358 1359 for (i = 0; i < npages; i++) { 1360 pmap_kenter_pa(_va + i * PAGE_SIZE, _pa + i * PAGE_SIZE, 1361 VM_PROT_READ | VM_PROT_WRITE, PMAP_WRITE_BACK); 1362 } 1363 pmap_update(pmap_kernel()); 1364 1365 memset((void *)_va, 0, npages * PAGE_SIZE); 1366 1367 *pa = _pa; 1368 *va = _va; 1369 return 0; 1370 1371 error: 1372 for (i = 0; i < npages; i++) { 1373 uvm_pagefree(PHYS_TO_VM_PAGE(_pa + i * PAGE_SIZE)); 1374 } 1375 return ENOMEM; 1376 } 1377 1378 static void 1379 svm_memfree(paddr_t pa, vaddr_t va, size_t npages) 1380 { 1381 size_t i; 1382 1383 pmap_kremove(va, npages * PAGE_SIZE); 1384 pmap_update(pmap_kernel()); 1385 uvm_km_free(kernel_map, va, npages * PAGE_SIZE, UVM_KMF_VAONLY); 1386 for (i = 0; i < npages; i++) { 1387 uvm_pagefree(PHYS_TO_VM_PAGE(pa + i * PAGE_SIZE)); 1388 } 1389 } 1390 1391 /* -------------------------------------------------------------------------- */ 1392 1393 #define SVM_MSRBM_READ __BIT(0) 1394 #define SVM_MSRBM_WRITE __BIT(1) 1395 1396 static void 1397 svm_vcpu_msr_allow(uint8_t *bitmap, uint64_t msr, bool read, bool write) 1398 { 1399 uint64_t byte; 1400 uint8_t bitoff; 1401 1402 if (msr < 0x00002000) { 1403 /* Range 1 */ 1404 byte = ((msr - 0x00000000) >> 2UL) + 0x0000; 1405 } else if (msr >= 0xC0000000 && msr < 0xC0002000) { 1406 /* Range 2 */ 1407 byte = ((msr - 0xC0000000) >> 2UL) + 0x0800; 1408 } else if (msr >= 0xC0010000 && msr < 0xC0012000) { 1409 /* Range 3 */ 1410 byte = ((msr - 0xC0010000) >> 2UL) + 0x1000; 1411 } else { 1412 panic("%s: wrong range", __func__); 1413 } 1414 1415 bitoff = (msr & 0x3) << 1; 1416 1417 if (read) { 1418 bitmap[byte] &= ~(SVM_MSRBM_READ << bitoff); 1419 } 1420 if (write) { 1421 bitmap[byte] &= ~(SVM_MSRBM_WRITE << bitoff); 1422 } 1423 } 1424 1425 static void 1426 svm_asid_alloc(struct nvmm_cpu *vcpu) 1427 { 1428 struct svm_cpudata *cpudata = vcpu->cpudata; 1429 struct vmcb *vmcb = cpudata->vmcb; 1430 size_t i, oct, bit; 1431 1432 mutex_enter(&svm_asidlock); 1433 1434 for (i = 0; i < svm_maxasid; i++) { 1435 oct = i / 8; 1436 bit = i % 8; 1437 1438 if (svm_asidmap[oct] & __BIT(bit)) { 1439 continue; 1440 } 1441 1442 svm_asidmap[oct] |= __BIT(bit); 1443 vmcb->ctrl.guest_asid = i; 1444 mutex_exit(&svm_asidlock); 1445 return; 1446 } 1447 1448 /* 1449 * No free ASID. Use the last one, which is shared and requires 1450 * special TLB handling. 1451 */ 1452 cpudata->shared_asid = true; 1453 vmcb->ctrl.guest_asid = svm_maxasid - 1; 1454 mutex_exit(&svm_asidlock); 1455 } 1456 1457 static void 1458 svm_asid_free(struct nvmm_cpu *vcpu) 1459 { 1460 struct svm_cpudata *cpudata = vcpu->cpudata; 1461 struct vmcb *vmcb = cpudata->vmcb; 1462 size_t oct, bit; 1463 1464 if (cpudata->shared_asid) { 1465 return; 1466 } 1467 1468 oct = vmcb->ctrl.guest_asid / 8; 1469 bit = vmcb->ctrl.guest_asid % 8; 1470 1471 mutex_enter(&svm_asidlock); 1472 svm_asidmap[oct] &= ~__BIT(bit); 1473 mutex_exit(&svm_asidlock); 1474 } 1475 1476 static void 1477 svm_vcpu_init(struct nvmm_machine *mach, struct nvmm_cpu *vcpu) 1478 { 1479 struct svm_cpudata *cpudata = vcpu->cpudata; 1480 struct vmcb *vmcb = cpudata->vmcb; 1481 1482 /* Allow reads/writes of Control Registers. */ 1483 vmcb->ctrl.intercept_cr = 0; 1484 1485 /* Allow reads/writes of Debug Registers. */ 1486 vmcb->ctrl.intercept_dr = 0; 1487 1488 /* Allow exceptions 0 to 31. */ 1489 vmcb->ctrl.intercept_vec = 0; 1490 1491 /* 1492 * Allow: 1493 * - SMI [smm interrupts] 1494 * - VINTR [virtual interrupts] 1495 * - CR0_SPEC [CR0 writes changing other fields than CR0.TS or CR0.MP] 1496 * - RIDTR [reads of IDTR] 1497 * - RGDTR [reads of GDTR] 1498 * - RLDTR [reads of LDTR] 1499 * - RTR [reads of TR] 1500 * - WIDTR [writes of IDTR] 1501 * - WGDTR [writes of GDTR] 1502 * - WLDTR [writes of LDTR] 1503 * - WTR [writes of TR] 1504 * - RDTSC [rdtsc instruction] 1505 * - PUSHF [pushf instruction] 1506 * - POPF [popf instruction] 1507 * - IRET [iret instruction] 1508 * - INTN [int $n instructions] 1509 * - INVD [invd instruction] 1510 * - PAUSE [pause instruction] 1511 * - INVLPG [invplg instruction] 1512 * - TASKSW [task switches] 1513 * 1514 * Intercept the rest below. 1515 */ 1516 vmcb->ctrl.intercept_misc1 = 1517 VMCB_CTRL_INTERCEPT_INTR | 1518 VMCB_CTRL_INTERCEPT_NMI | 1519 VMCB_CTRL_INTERCEPT_INIT | 1520 VMCB_CTRL_INTERCEPT_RDPMC | 1521 VMCB_CTRL_INTERCEPT_CPUID | 1522 VMCB_CTRL_INTERCEPT_RSM | 1523 VMCB_CTRL_INTERCEPT_HLT | 1524 VMCB_CTRL_INTERCEPT_INVLPGA | 1525 VMCB_CTRL_INTERCEPT_IOIO_PROT | 1526 VMCB_CTRL_INTERCEPT_MSR_PROT | 1527 VMCB_CTRL_INTERCEPT_FERR_FREEZE | 1528 VMCB_CTRL_INTERCEPT_SHUTDOWN; 1529 1530 /* 1531 * Allow: 1532 * - ICEBP [icebp instruction] 1533 * - WBINVD [wbinvd instruction] 1534 * - WCR_SPEC(0..15) [writes of CR0-15, received after instruction] 1535 * 1536 * Intercept the rest below. 1537 */ 1538 vmcb->ctrl.intercept_misc2 = 1539 VMCB_CTRL_INTERCEPT_VMRUN | 1540 VMCB_CTRL_INTERCEPT_VMMCALL | 1541 VMCB_CTRL_INTERCEPT_VMLOAD | 1542 VMCB_CTRL_INTERCEPT_VMSAVE | 1543 VMCB_CTRL_INTERCEPT_STGI | 1544 VMCB_CTRL_INTERCEPT_CLGI | 1545 VMCB_CTRL_INTERCEPT_SKINIT | 1546 VMCB_CTRL_INTERCEPT_RDTSCP | 1547 VMCB_CTRL_INTERCEPT_MONITOR | 1548 VMCB_CTRL_INTERCEPT_MWAIT | 1549 VMCB_CTRL_INTERCEPT_XSETBV; 1550 1551 /* Intercept all I/O accesses. */ 1552 memset(cpudata->iobm, 0xFF, IOBM_SIZE); 1553 vmcb->ctrl.iopm_base_pa = cpudata->iobm_pa; 1554 1555 /* 1556 * Allow: 1557 * - EFER [read] 1558 * - STAR [read, write] 1559 * - LSTAR [read, write] 1560 * - CSTAR [read, write] 1561 * - SFMASK [read, write] 1562 * - KERNELGSBASE [read, write] 1563 * - SYSENTER_CS [read, write] 1564 * - SYSENTER_ESP [read, write] 1565 * - SYSENTER_EIP [read, write] 1566 * - FSBASE [read, write] 1567 * - GSBASE [read, write] 1568 * - PAT [read, write] 1569 * - TSC [read] 1570 * 1571 * Intercept the rest. 1572 */ 1573 memset(cpudata->msrbm, 0xFF, MSRBM_SIZE); 1574 svm_vcpu_msr_allow(cpudata->msrbm, MSR_EFER, true, false); 1575 svm_vcpu_msr_allow(cpudata->msrbm, MSR_STAR, true, true); 1576 svm_vcpu_msr_allow(cpudata->msrbm, MSR_LSTAR, true, true); 1577 svm_vcpu_msr_allow(cpudata->msrbm, MSR_CSTAR, true, true); 1578 svm_vcpu_msr_allow(cpudata->msrbm, MSR_SFMASK, true, true); 1579 svm_vcpu_msr_allow(cpudata->msrbm, MSR_KERNELGSBASE, true, true); 1580 svm_vcpu_msr_allow(cpudata->msrbm, MSR_SYSENTER_CS, true, true); 1581 svm_vcpu_msr_allow(cpudata->msrbm, MSR_SYSENTER_ESP, true, true); 1582 svm_vcpu_msr_allow(cpudata->msrbm, MSR_SYSENTER_EIP, true, true); 1583 svm_vcpu_msr_allow(cpudata->msrbm, MSR_FSBASE, true, true); 1584 svm_vcpu_msr_allow(cpudata->msrbm, MSR_GSBASE, true, true); 1585 svm_vcpu_msr_allow(cpudata->msrbm, MSR_CR_PAT, true, true); 1586 svm_vcpu_msr_allow(cpudata->msrbm, MSR_TSC, true, false); 1587 vmcb->ctrl.msrpm_base_pa = cpudata->msrbm_pa; 1588 1589 /* Generate ASID. */ 1590 svm_asid_alloc(vcpu); 1591 1592 /* Virtual TPR. */ 1593 vmcb->ctrl.v = VMCB_CTRL_V_INTR_MASKING; 1594 1595 /* Enable Nested Paging. */ 1596 vmcb->ctrl.enable1 = VMCB_CTRL_ENABLE_NP; 1597 vmcb->ctrl.n_cr3 = mach->vm->vm_map.pmap->pm_pdirpa[0]; 1598 1599 /* Must always be set. */ 1600 vmcb->state.efer = EFER_SVME; 1601 cpudata->gxcr0 = XCR0_X87; 1602 1603 /* Init XSAVE header. */ 1604 cpudata->gfpu.xsh_xstate_bv = svm_xcr0_mask; 1605 cpudata->gfpu.xsh_xcomp_bv = 0; 1606 1607 /* Set guest TSC to zero, more or less. */ 1608 cpudata->tsc_offset = -cpu_counter(); 1609 1610 /* These MSRs are static. */ 1611 cpudata->star = rdmsr(MSR_STAR); 1612 cpudata->lstar = rdmsr(MSR_LSTAR); 1613 cpudata->cstar = rdmsr(MSR_CSTAR); 1614 cpudata->sfmask = rdmsr(MSR_SFMASK); 1615 } 1616 1617 static int 1618 svm_vcpu_create(struct nvmm_machine *mach, struct nvmm_cpu *vcpu) 1619 { 1620 struct svm_cpudata *cpudata; 1621 int error; 1622 1623 /* Allocate the SVM cpudata. */ 1624 cpudata = (struct svm_cpudata *)uvm_km_alloc(kernel_map, 1625 roundup(sizeof(*cpudata), PAGE_SIZE), 0, 1626 UVM_KMF_WIRED|UVM_KMF_ZERO); 1627 vcpu->cpudata = cpudata; 1628 1629 /* VMCB */ 1630 error = svm_memalloc(&cpudata->vmcb_pa, (vaddr_t *)&cpudata->vmcb, 1631 VMCB_NPAGES); 1632 if (error) 1633 goto error; 1634 1635 /* I/O Bitmap */ 1636 error = svm_memalloc(&cpudata->iobm_pa, (vaddr_t *)&cpudata->iobm, 1637 IOBM_NPAGES); 1638 if (error) 1639 goto error; 1640 1641 /* MSR Bitmap */ 1642 error = svm_memalloc(&cpudata->msrbm_pa, (vaddr_t *)&cpudata->msrbm, 1643 MSRBM_NPAGES); 1644 if (error) 1645 goto error; 1646 1647 /* Init the VCPU info. */ 1648 svm_vcpu_init(mach, vcpu); 1649 1650 return 0; 1651 1652 error: 1653 if (cpudata->vmcb_pa) { 1654 svm_memfree(cpudata->vmcb_pa, (vaddr_t)cpudata->vmcb, 1655 VMCB_NPAGES); 1656 } 1657 if (cpudata->iobm_pa) { 1658 svm_memfree(cpudata->iobm_pa, (vaddr_t)cpudata->iobm, 1659 IOBM_NPAGES); 1660 } 1661 if (cpudata->msrbm_pa) { 1662 svm_memfree(cpudata->msrbm_pa, (vaddr_t)cpudata->msrbm, 1663 MSRBM_NPAGES); 1664 } 1665 uvm_km_free(kernel_map, (vaddr_t)cpudata, 1666 roundup(sizeof(*cpudata), PAGE_SIZE), UVM_KMF_WIRED); 1667 return error; 1668 } 1669 1670 static void 1671 svm_vcpu_destroy(struct nvmm_machine *mach, struct nvmm_cpu *vcpu) 1672 { 1673 struct svm_cpudata *cpudata = vcpu->cpudata; 1674 1675 svm_asid_free(vcpu); 1676 1677 svm_memfree(cpudata->vmcb_pa, (vaddr_t)cpudata->vmcb, VMCB_NPAGES); 1678 svm_memfree(cpudata->iobm_pa, (vaddr_t)cpudata->iobm, IOBM_NPAGES); 1679 svm_memfree(cpudata->msrbm_pa, (vaddr_t)cpudata->msrbm, MSRBM_NPAGES); 1680 1681 uvm_km_free(kernel_map, (vaddr_t)cpudata, 1682 roundup(sizeof(*cpudata), PAGE_SIZE), UVM_KMF_WIRED); 1683 } 1684 1685 #define SVM_SEG_ATTRIB_TYPE __BITS(4,0) 1686 #define SVM_SEG_ATTRIB_DPL __BITS(6,5) 1687 #define SVM_SEG_ATTRIB_P __BIT(7) 1688 #define SVM_SEG_ATTRIB_AVL __BIT(8) 1689 #define SVM_SEG_ATTRIB_LONG __BIT(9) 1690 #define SVM_SEG_ATTRIB_DEF32 __BIT(10) 1691 #define SVM_SEG_ATTRIB_GRAN __BIT(11) 1692 1693 static void 1694 svm_vcpu_setstate_seg(struct nvmm_x64_state_seg *seg, struct vmcb_segment *vseg) 1695 { 1696 vseg->selector = seg->selector; 1697 vseg->attrib = 1698 __SHIFTIN(seg->attrib.type, SVM_SEG_ATTRIB_TYPE) | 1699 __SHIFTIN(seg->attrib.dpl, SVM_SEG_ATTRIB_DPL) | 1700 __SHIFTIN(seg->attrib.p, SVM_SEG_ATTRIB_P) | 1701 __SHIFTIN(seg->attrib.avl, SVM_SEG_ATTRIB_AVL) | 1702 __SHIFTIN(seg->attrib.lng, SVM_SEG_ATTRIB_LONG) | 1703 __SHIFTIN(seg->attrib.def32, SVM_SEG_ATTRIB_DEF32) | 1704 __SHIFTIN(seg->attrib.gran, SVM_SEG_ATTRIB_GRAN); 1705 vseg->limit = seg->limit; 1706 vseg->base = seg->base; 1707 } 1708 1709 static void 1710 svm_vcpu_getstate_seg(struct nvmm_x64_state_seg *seg, struct vmcb_segment *vseg) 1711 { 1712 seg->selector = vseg->selector; 1713 seg->attrib.type = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_TYPE); 1714 seg->attrib.dpl = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_DPL); 1715 seg->attrib.p = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_P); 1716 seg->attrib.avl = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_AVL); 1717 seg->attrib.lng = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_LONG); 1718 seg->attrib.def32 = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_DEF32); 1719 seg->attrib.gran = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_GRAN); 1720 seg->limit = vseg->limit; 1721 seg->base = vseg->base; 1722 } 1723 1724 static inline bool 1725 svm_state_tlb_flush(struct vmcb *vmcb, struct nvmm_x64_state *state, 1726 uint64_t flags) 1727 { 1728 if (flags & NVMM_X64_STATE_CRS) { 1729 if ((vmcb->state.cr0 ^ 1730 state->crs[NVMM_X64_CR_CR0]) & CR0_TLB_FLUSH) { 1731 return true; 1732 } 1733 if (vmcb->state.cr3 != state->crs[NVMM_X64_CR_CR3]) { 1734 return true; 1735 } 1736 if ((vmcb->state.cr4 ^ 1737 state->crs[NVMM_X64_CR_CR4]) & CR4_TLB_FLUSH) { 1738 return true; 1739 } 1740 } 1741 1742 if (flags & NVMM_X64_STATE_MSRS) { 1743 if ((vmcb->state.efer ^ 1744 state->msrs[NVMM_X64_MSR_EFER]) & EFER_TLB_FLUSH) { 1745 return true; 1746 } 1747 } 1748 1749 return false; 1750 } 1751 1752 static void 1753 svm_vcpu_setstate(struct nvmm_cpu *vcpu, void *data, uint64_t flags) 1754 { 1755 struct nvmm_x64_state *state = (struct nvmm_x64_state *)data; 1756 struct svm_cpudata *cpudata = vcpu->cpudata; 1757 struct vmcb *vmcb = cpudata->vmcb; 1758 struct fxsave *fpustate; 1759 1760 if (svm_state_tlb_flush(vmcb, state, flags)) { 1761 cpudata->tlb_want_flush = true; 1762 } 1763 1764 if (flags & NVMM_X64_STATE_SEGS) { 1765 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_CS], 1766 &vmcb->state.cs); 1767 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_DS], 1768 &vmcb->state.ds); 1769 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_ES], 1770 &vmcb->state.es); 1771 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_FS], 1772 &vmcb->state.fs); 1773 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_GS], 1774 &vmcb->state.gs); 1775 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_SS], 1776 &vmcb->state.ss); 1777 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_GDT], 1778 &vmcb->state.gdt); 1779 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_IDT], 1780 &vmcb->state.idt); 1781 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_LDT], 1782 &vmcb->state.ldt); 1783 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_TR], 1784 &vmcb->state.tr); 1785 1786 vmcb->state.cpl = state->segs[NVMM_X64_SEG_SS].attrib.dpl; 1787 } 1788 1789 CTASSERT(sizeof(cpudata->gprs) == sizeof(state->gprs)); 1790 if (flags & NVMM_X64_STATE_GPRS) { 1791 memcpy(cpudata->gprs, state->gprs, sizeof(state->gprs)); 1792 1793 vmcb->state.rip = state->gprs[NVMM_X64_GPR_RIP]; 1794 vmcb->state.rsp = state->gprs[NVMM_X64_GPR_RSP]; 1795 vmcb->state.rax = state->gprs[NVMM_X64_GPR_RAX]; 1796 vmcb->state.rflags = state->gprs[NVMM_X64_GPR_RFLAGS]; 1797 } 1798 1799 if (flags & NVMM_X64_STATE_CRS) { 1800 vmcb->state.cr0 = state->crs[NVMM_X64_CR_CR0]; 1801 vmcb->state.cr2 = state->crs[NVMM_X64_CR_CR2]; 1802 vmcb->state.cr3 = state->crs[NVMM_X64_CR_CR3]; 1803 vmcb->state.cr4 = state->crs[NVMM_X64_CR_CR4]; 1804 1805 vmcb->ctrl.v &= ~VMCB_CTRL_V_TPR; 1806 vmcb->ctrl.v |= __SHIFTIN(state->crs[NVMM_X64_CR_CR8], 1807 VMCB_CTRL_V_TPR); 1808 1809 if (svm_xcr0_mask != 0) { 1810 /* Clear illegal XCR0 bits, set mandatory X87 bit. */ 1811 cpudata->gxcr0 = state->crs[NVMM_X64_CR_XCR0]; 1812 cpudata->gxcr0 &= svm_xcr0_mask; 1813 cpudata->gxcr0 |= XCR0_X87; 1814 } 1815 } 1816 1817 CTASSERT(sizeof(cpudata->drs) == sizeof(state->drs)); 1818 if (flags & NVMM_X64_STATE_DRS) { 1819 memcpy(cpudata->drs, state->drs, sizeof(state->drs)); 1820 1821 vmcb->state.dr6 = state->drs[NVMM_X64_DR_DR6]; 1822 vmcb->state.dr7 = state->drs[NVMM_X64_DR_DR7]; 1823 } 1824 1825 if (flags & NVMM_X64_STATE_MSRS) { 1826 /* Bit EFER_SVME is mandatory. */ 1827 vmcb->state.efer = state->msrs[NVMM_X64_MSR_EFER] | EFER_SVME; 1828 1829 vmcb->state.star = state->msrs[NVMM_X64_MSR_STAR]; 1830 vmcb->state.lstar = state->msrs[NVMM_X64_MSR_LSTAR]; 1831 vmcb->state.cstar = state->msrs[NVMM_X64_MSR_CSTAR]; 1832 vmcb->state.sfmask = state->msrs[NVMM_X64_MSR_SFMASK]; 1833 vmcb->state.kernelgsbase = 1834 state->msrs[NVMM_X64_MSR_KERNELGSBASE]; 1835 vmcb->state.sysenter_cs = 1836 state->msrs[NVMM_X64_MSR_SYSENTER_CS]; 1837 vmcb->state.sysenter_esp = 1838 state->msrs[NVMM_X64_MSR_SYSENTER_ESP]; 1839 vmcb->state.sysenter_eip = 1840 state->msrs[NVMM_X64_MSR_SYSENTER_EIP]; 1841 vmcb->state.g_pat = state->msrs[NVMM_X64_MSR_PAT]; 1842 } 1843 1844 if (flags & NVMM_X64_STATE_MISC) { 1845 if (state->misc[NVMM_X64_MISC_INT_SHADOW]) { 1846 vmcb->ctrl.intr |= VMCB_CTRL_INTR_SHADOW; 1847 } else { 1848 vmcb->ctrl.intr &= ~VMCB_CTRL_INTR_SHADOW; 1849 } 1850 1851 if (state->misc[NVMM_X64_MISC_INT_WINDOW_EXIT]) { 1852 svm_event_waitexit_enable(vcpu, false); 1853 } else { 1854 svm_event_waitexit_disable(vcpu, false); 1855 } 1856 1857 if (state->misc[NVMM_X64_MISC_NMI_WINDOW_EXIT]) { 1858 svm_event_waitexit_enable(vcpu, true); 1859 } else { 1860 svm_event_waitexit_disable(vcpu, true); 1861 } 1862 } 1863 1864 CTASSERT(sizeof(cpudata->gfpu.xsh_fxsave) == sizeof(state->fpu)); 1865 if (flags & NVMM_X64_STATE_FPU) { 1866 memcpy(cpudata->gfpu.xsh_fxsave, &state->fpu, 1867 sizeof(state->fpu)); 1868 1869 fpustate = (struct fxsave *)cpudata->gfpu.xsh_fxsave; 1870 fpustate->fx_mxcsr_mask &= x86_fpu_mxcsr_mask; 1871 fpustate->fx_mxcsr &= fpustate->fx_mxcsr_mask; 1872 1873 if (svm_xcr0_mask != 0) { 1874 /* Reset XSTATE_BV, to force a reload. */ 1875 cpudata->gfpu.xsh_xstate_bv = svm_xcr0_mask; 1876 } 1877 } 1878 1879 svm_vmcb_cache_update(vmcb, flags); 1880 } 1881 1882 static void 1883 svm_vcpu_getstate(struct nvmm_cpu *vcpu, void *data, uint64_t flags) 1884 { 1885 struct nvmm_x64_state *state = (struct nvmm_x64_state *)data; 1886 struct svm_cpudata *cpudata = vcpu->cpudata; 1887 struct vmcb *vmcb = cpudata->vmcb; 1888 1889 if (flags & NVMM_X64_STATE_SEGS) { 1890 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_CS], 1891 &vmcb->state.cs); 1892 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_DS], 1893 &vmcb->state.ds); 1894 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_ES], 1895 &vmcb->state.es); 1896 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_FS], 1897 &vmcb->state.fs); 1898 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_GS], 1899 &vmcb->state.gs); 1900 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_SS], 1901 &vmcb->state.ss); 1902 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_GDT], 1903 &vmcb->state.gdt); 1904 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_IDT], 1905 &vmcb->state.idt); 1906 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_LDT], 1907 &vmcb->state.ldt); 1908 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_TR], 1909 &vmcb->state.tr); 1910 1911 state->segs[NVMM_X64_SEG_SS].attrib.dpl = vmcb->state.cpl; 1912 } 1913 1914 CTASSERT(sizeof(cpudata->gprs) == sizeof(state->gprs)); 1915 if (flags & NVMM_X64_STATE_GPRS) { 1916 memcpy(state->gprs, cpudata->gprs, sizeof(state->gprs)); 1917 1918 state->gprs[NVMM_X64_GPR_RIP] = vmcb->state.rip; 1919 state->gprs[NVMM_X64_GPR_RSP] = vmcb->state.rsp; 1920 state->gprs[NVMM_X64_GPR_RAX] = vmcb->state.rax; 1921 state->gprs[NVMM_X64_GPR_RFLAGS] = vmcb->state.rflags; 1922 } 1923 1924 if (flags & NVMM_X64_STATE_CRS) { 1925 state->crs[NVMM_X64_CR_CR0] = vmcb->state.cr0; 1926 state->crs[NVMM_X64_CR_CR2] = vmcb->state.cr2; 1927 state->crs[NVMM_X64_CR_CR3] = vmcb->state.cr3; 1928 state->crs[NVMM_X64_CR_CR4] = vmcb->state.cr4; 1929 state->crs[NVMM_X64_CR_CR8] = __SHIFTOUT(vmcb->ctrl.v, 1930 VMCB_CTRL_V_TPR); 1931 state->crs[NVMM_X64_CR_XCR0] = cpudata->gxcr0; 1932 } 1933 1934 CTASSERT(sizeof(cpudata->drs) == sizeof(state->drs)); 1935 if (flags & NVMM_X64_STATE_DRS) { 1936 memcpy(state->drs, cpudata->drs, sizeof(state->drs)); 1937 1938 state->drs[NVMM_X64_DR_DR6] = vmcb->state.dr6; 1939 state->drs[NVMM_X64_DR_DR7] = vmcb->state.dr7; 1940 } 1941 1942 if (flags & NVMM_X64_STATE_MSRS) { 1943 state->msrs[NVMM_X64_MSR_EFER] = vmcb->state.efer; 1944 state->msrs[NVMM_X64_MSR_STAR] = vmcb->state.star; 1945 state->msrs[NVMM_X64_MSR_LSTAR] = vmcb->state.lstar; 1946 state->msrs[NVMM_X64_MSR_CSTAR] = vmcb->state.cstar; 1947 state->msrs[NVMM_X64_MSR_SFMASK] = vmcb->state.sfmask; 1948 state->msrs[NVMM_X64_MSR_KERNELGSBASE] = 1949 vmcb->state.kernelgsbase; 1950 state->msrs[NVMM_X64_MSR_SYSENTER_CS] = 1951 vmcb->state.sysenter_cs; 1952 state->msrs[NVMM_X64_MSR_SYSENTER_ESP] = 1953 vmcb->state.sysenter_esp; 1954 state->msrs[NVMM_X64_MSR_SYSENTER_EIP] = 1955 vmcb->state.sysenter_eip; 1956 state->msrs[NVMM_X64_MSR_PAT] = vmcb->state.g_pat; 1957 1958 /* Hide SVME. */ 1959 state->msrs[NVMM_X64_MSR_EFER] &= ~EFER_SVME; 1960 } 1961 1962 if (flags & NVMM_X64_STATE_MISC) { 1963 state->misc[NVMM_X64_MISC_INT_SHADOW] = 1964 (vmcb->ctrl.intr & VMCB_CTRL_INTR_SHADOW) != 0; 1965 state->misc[NVMM_X64_MISC_INT_WINDOW_EXIT] = 1966 cpudata->int_window_exit; 1967 state->misc[NVMM_X64_MISC_NMI_WINDOW_EXIT] = 1968 cpudata->nmi_window_exit; 1969 } 1970 1971 CTASSERT(sizeof(cpudata->gfpu.xsh_fxsave) == sizeof(state->fpu)); 1972 if (flags & NVMM_X64_STATE_FPU) { 1973 memcpy(&state->fpu, cpudata->gfpu.xsh_fxsave, 1974 sizeof(state->fpu)); 1975 } 1976 } 1977 1978 /* -------------------------------------------------------------------------- */ 1979 1980 static void 1981 svm_tlb_flush(struct pmap *pm) 1982 { 1983 struct nvmm_machine *mach = pm->pm_data; 1984 struct svm_cpudata *cpudata; 1985 struct nvmm_cpu *vcpu; 1986 int error; 1987 size_t i; 1988 1989 /* Request TLB flushes. */ 1990 for (i = 0; i < NVMM_MAX_VCPUS; i++) { 1991 error = nvmm_vcpu_get(mach, i, &vcpu); 1992 if (error) 1993 continue; 1994 cpudata = vcpu->cpudata; 1995 cpudata->tlb_want_flush = true; 1996 nvmm_vcpu_put(vcpu); 1997 } 1998 } 1999 2000 static void 2001 svm_machine_create(struct nvmm_machine *mach) 2002 { 2003 /* Fill in pmap info. */ 2004 mach->vm->vm_map.pmap->pm_data = (void *)mach; 2005 mach->vm->vm_map.pmap->pm_tlb_flush = svm_tlb_flush; 2006 2007 mach->machdata = kmem_zalloc(sizeof(struct svm_machdata), KM_SLEEP); 2008 } 2009 2010 static void 2011 svm_machine_destroy(struct nvmm_machine *mach) 2012 { 2013 kmem_free(mach->machdata, sizeof(struct svm_machdata)); 2014 } 2015 2016 static int 2017 svm_machine_configure(struct nvmm_machine *mach, uint64_t op, void *data) 2018 { 2019 struct nvmm_x86_conf_cpuid *cpuid = data; 2020 struct svm_machdata *machdata = (struct svm_machdata *)mach->machdata; 2021 size_t i; 2022 2023 if (__predict_false(op != NVMM_X86_CONF_CPUID)) { 2024 return EINVAL; 2025 } 2026 2027 if (__predict_false((cpuid->set.eax & cpuid->del.eax) || 2028 (cpuid->set.ebx & cpuid->del.ebx) || 2029 (cpuid->set.ecx & cpuid->del.ecx) || 2030 (cpuid->set.edx & cpuid->del.edx))) { 2031 return EINVAL; 2032 } 2033 2034 /* If already here, replace. */ 2035 for (i = 0; i < SVM_NCPUIDS; i++) { 2036 if (!machdata->cpuidpresent[i]) { 2037 continue; 2038 } 2039 if (machdata->cpuid[i].leaf == cpuid->leaf) { 2040 memcpy(&machdata->cpuid[i], cpuid, 2041 sizeof(struct nvmm_x86_conf_cpuid)); 2042 return 0; 2043 } 2044 } 2045 2046 /* Not here, insert. */ 2047 for (i = 0; i < SVM_NCPUIDS; i++) { 2048 if (!machdata->cpuidpresent[i]) { 2049 machdata->cpuidpresent[i] = true; 2050 memcpy(&machdata->cpuid[i], cpuid, 2051 sizeof(struct nvmm_x86_conf_cpuid)); 2052 return 0; 2053 } 2054 } 2055 2056 return ENOBUFS; 2057 } 2058 2059 /* -------------------------------------------------------------------------- */ 2060 2061 static bool 2062 svm_ident(void) 2063 { 2064 u_int descs[4]; 2065 uint64_t msr; 2066 2067 if (cpu_vendor != CPUVENDOR_AMD) { 2068 return false; 2069 } 2070 if (!(cpu_feature[3] & CPUID_SVM)) { 2071 return false; 2072 } 2073 2074 if (curcpu()->ci_max_ext_cpuid < 0x8000000a) { 2075 return false; 2076 } 2077 x86_cpuid(0x8000000a, descs); 2078 2079 /* Want Nested Paging. */ 2080 if (!(descs[3] & CPUID_AMD_SVM_NP)) { 2081 return false; 2082 } 2083 2084 /* Want nRIP. */ 2085 if (!(descs[3] & CPUID_AMD_SVM_NRIPS)) { 2086 return false; 2087 } 2088 2089 svm_decode_assist = (descs[3] & CPUID_AMD_SVM_DecodeAssist) != 0; 2090 2091 msr = rdmsr(MSR_VMCR); 2092 if ((msr & VMCR_SVMED) && (msr & VMCR_LOCK)) { 2093 return false; 2094 } 2095 2096 return true; 2097 } 2098 2099 static void 2100 svm_init_asid(uint32_t maxasid) 2101 { 2102 size_t i, j, allocsz; 2103 2104 mutex_init(&svm_asidlock, MUTEX_DEFAULT, IPL_NONE); 2105 2106 /* Arbitrarily limit. */ 2107 maxasid = uimin(maxasid, 8192); 2108 2109 svm_maxasid = maxasid; 2110 allocsz = roundup(maxasid, 8) / 8; 2111 svm_asidmap = kmem_zalloc(allocsz, KM_SLEEP); 2112 2113 /* ASID 0 is reserved for the host. */ 2114 svm_asidmap[0] |= __BIT(0); 2115 2116 /* ASID n-1 is special, we share it. */ 2117 i = (maxasid - 1) / 8; 2118 j = (maxasid - 1) % 8; 2119 svm_asidmap[i] |= __BIT(j); 2120 } 2121 2122 static void 2123 svm_change_cpu(void *arg1, void *arg2) 2124 { 2125 bool enable = (bool)arg1; 2126 uint64_t msr; 2127 2128 msr = rdmsr(MSR_VMCR); 2129 if (msr & VMCR_SVMED) { 2130 wrmsr(MSR_VMCR, msr & ~VMCR_SVMED); 2131 } 2132 2133 if (!enable) { 2134 wrmsr(MSR_VM_HSAVE_PA, 0); 2135 } 2136 2137 msr = rdmsr(MSR_EFER); 2138 if (enable) { 2139 msr |= EFER_SVME; 2140 } else { 2141 msr &= ~EFER_SVME; 2142 } 2143 wrmsr(MSR_EFER, msr); 2144 2145 if (enable) { 2146 wrmsr(MSR_VM_HSAVE_PA, hsave[cpu_index(curcpu())].pa); 2147 } 2148 } 2149 2150 static void 2151 svm_init(void) 2152 { 2153 CPU_INFO_ITERATOR cii; 2154 struct cpu_info *ci; 2155 struct vm_page *pg; 2156 u_int descs[4]; 2157 uint64_t xc; 2158 2159 x86_cpuid(0x8000000a, descs); 2160 2161 /* The guest TLB flush command. */ 2162 if (descs[3] & CPUID_AMD_SVM_FlushByASID) { 2163 svm_ctrl_tlb_flush = VMCB_CTRL_TLB_CTRL_FLUSH_GUEST; 2164 } else { 2165 svm_ctrl_tlb_flush = VMCB_CTRL_TLB_CTRL_FLUSH_ALL; 2166 } 2167 2168 /* Init the ASID. */ 2169 svm_init_asid(descs[1]); 2170 2171 /* Init the XCR0 mask. */ 2172 svm_xcr0_mask = SVM_XCR0_MASK_DEFAULT & x86_xsave_features; 2173 2174 memset(hsave, 0, sizeof(hsave)); 2175 for (CPU_INFO_FOREACH(cii, ci)) { 2176 pg = uvm_pagealloc(NULL, 0, NULL, UVM_PGA_ZERO); 2177 hsave[cpu_index(ci)].pa = VM_PAGE_TO_PHYS(pg); 2178 } 2179 2180 xc = xc_broadcast(0, svm_change_cpu, (void *)true, NULL); 2181 xc_wait(xc); 2182 } 2183 2184 static void 2185 svm_fini_asid(void) 2186 { 2187 size_t allocsz; 2188 2189 allocsz = roundup(svm_maxasid, 8) / 8; 2190 kmem_free(svm_asidmap, allocsz); 2191 2192 mutex_destroy(&svm_asidlock); 2193 } 2194 2195 static void 2196 svm_fini(void) 2197 { 2198 uint64_t xc; 2199 size_t i; 2200 2201 xc = xc_broadcast(0, svm_change_cpu, (void *)false, NULL); 2202 xc_wait(xc); 2203 2204 for (i = 0; i < MAXCPUS; i++) { 2205 if (hsave[i].pa != 0) 2206 uvm_pagefree(PHYS_TO_VM_PAGE(hsave[i].pa)); 2207 } 2208 2209 svm_fini_asid(); 2210 } 2211 2212 static void 2213 svm_capability(struct nvmm_capability *cap) 2214 { 2215 cap->u.x86.xcr0_mask = svm_xcr0_mask; 2216 cap->u.x86.mxcsr_mask = x86_fpu_mxcsr_mask; 2217 cap->u.x86.conf_cpuid_maxops = SVM_NCPUIDS; 2218 } 2219 2220 const struct nvmm_impl nvmm_x86_svm = { 2221 .ident = svm_ident, 2222 .init = svm_init, 2223 .fini = svm_fini, 2224 .capability = svm_capability, 2225 .conf_max = NVMM_X86_NCONF, 2226 .conf_sizes = svm_conf_sizes, 2227 .state_size = sizeof(struct nvmm_x64_state), 2228 .machine_create = svm_machine_create, 2229 .machine_destroy = svm_machine_destroy, 2230 .machine_configure = svm_machine_configure, 2231 .vcpu_create = svm_vcpu_create, 2232 .vcpu_destroy = svm_vcpu_destroy, 2233 .vcpu_setstate = svm_vcpu_setstate, 2234 .vcpu_getstate = svm_vcpu_getstate, 2235 .vcpu_inject = svm_vcpu_inject, 2236 .vcpu_run = svm_vcpu_run 2237 }; 2238
Indexes created Tue Sep 30 17:09:57 GMT 2025