nvmm_x86_svm.c revision 1.35
1 /* $NetBSD: nvmm_x86_svm.c,v 1.35 2019/03/21 20:21:41 maxv Exp $ */ 2 3 /* 4 * Copyright (c) 2018 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Maxime Villard. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: nvmm_x86_svm.c,v 1.35 2019/03/21 20:21:41 maxv Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/kmem.h> 39 #include <sys/cpu.h> 40 #include <sys/xcall.h> 41 #include <sys/mman.h> 42 43 #include <uvm/uvm.h> 44 #include <uvm/uvm_page.h> 45 46 #include <x86/cputypes.h> 47 #include <x86/specialreg.h> 48 #include <x86/pmap.h> 49 #include <x86/dbregs.h> 50 #include <x86/cpu_counter.h> 51 #include <machine/cpuvar.h> 52 53 #include <dev/nvmm/nvmm.h> 54 #include <dev/nvmm/nvmm_internal.h> 55 #include <dev/nvmm/x86/nvmm_x86.h> 56 57 int svm_vmrun(paddr_t, uint64_t *); 58 59 #define MSR_VM_HSAVE_PA 0xC0010117 60 61 /* -------------------------------------------------------------------------- */ 62 63 #define VMCB_EXITCODE_CR0_READ 0x0000 64 #define VMCB_EXITCODE_CR1_READ 0x0001 65 #define VMCB_EXITCODE_CR2_READ 0x0002 66 #define VMCB_EXITCODE_CR3_READ 0x0003 67 #define VMCB_EXITCODE_CR4_READ 0x0004 68 #define VMCB_EXITCODE_CR5_READ 0x0005 69 #define VMCB_EXITCODE_CR6_READ 0x0006 70 #define VMCB_EXITCODE_CR7_READ 0x0007 71 #define VMCB_EXITCODE_CR8_READ 0x0008 72 #define VMCB_EXITCODE_CR9_READ 0x0009 73 #define VMCB_EXITCODE_CR10_READ 0x000A 74 #define VMCB_EXITCODE_CR11_READ 0x000B 75 #define VMCB_EXITCODE_CR12_READ 0x000C 76 #define VMCB_EXITCODE_CR13_READ 0x000D 77 #define VMCB_EXITCODE_CR14_READ 0x000E 78 #define VMCB_EXITCODE_CR15_READ 0x000F 79 #define VMCB_EXITCODE_CR0_WRITE 0x0010 80 #define VMCB_EXITCODE_CR1_WRITE 0x0011 81 #define VMCB_EXITCODE_CR2_WRITE 0x0012 82 #define VMCB_EXITCODE_CR3_WRITE 0x0013 83 #define VMCB_EXITCODE_CR4_WRITE 0x0014 84 #define VMCB_EXITCODE_CR5_WRITE 0x0015 85 #define VMCB_EXITCODE_CR6_WRITE 0x0016 86 #define VMCB_EXITCODE_CR7_WRITE 0x0017 87 #define VMCB_EXITCODE_CR8_WRITE 0x0018 88 #define VMCB_EXITCODE_CR9_WRITE 0x0019 89 #define VMCB_EXITCODE_CR10_WRITE 0x001A 90 #define VMCB_EXITCODE_CR11_WRITE 0x001B 91 #define VMCB_EXITCODE_CR12_WRITE 0x001C 92 #define VMCB_EXITCODE_CR13_WRITE 0x001D 93 #define VMCB_EXITCODE_CR14_WRITE 0x001E 94 #define VMCB_EXITCODE_CR15_WRITE 0x001F 95 #define VMCB_EXITCODE_DR0_READ 0x0020 96 #define VMCB_EXITCODE_DR1_READ 0x0021 97 #define VMCB_EXITCODE_DR2_READ 0x0022 98 #define VMCB_EXITCODE_DR3_READ 0x0023 99 #define VMCB_EXITCODE_DR4_READ 0x0024 100 #define VMCB_EXITCODE_DR5_READ 0x0025 101 #define VMCB_EXITCODE_DR6_READ 0x0026 102 #define VMCB_EXITCODE_DR7_READ 0x0027 103 #define VMCB_EXITCODE_DR8_READ 0x0028 104 #define VMCB_EXITCODE_DR9_READ 0x0029 105 #define VMCB_EXITCODE_DR10_READ 0x002A 106 #define VMCB_EXITCODE_DR11_READ 0x002B 107 #define VMCB_EXITCODE_DR12_READ 0x002C 108 #define VMCB_EXITCODE_DR13_READ 0x002D 109 #define VMCB_EXITCODE_DR14_READ 0x002E 110 #define VMCB_EXITCODE_DR15_READ 0x002F 111 #define VMCB_EXITCODE_DR0_WRITE 0x0030 112 #define VMCB_EXITCODE_DR1_WRITE 0x0031 113 #define VMCB_EXITCODE_DR2_WRITE 0x0032 114 #define VMCB_EXITCODE_DR3_WRITE 0x0033 115 #define VMCB_EXITCODE_DR4_WRITE 0x0034 116 #define VMCB_EXITCODE_DR5_WRITE 0x0035 117 #define VMCB_EXITCODE_DR6_WRITE 0x0036 118 #define VMCB_EXITCODE_DR7_WRITE 0x0037 119 #define VMCB_EXITCODE_DR8_WRITE 0x0038 120 #define VMCB_EXITCODE_DR9_WRITE 0x0039 121 #define VMCB_EXITCODE_DR10_WRITE 0x003A 122 #define VMCB_EXITCODE_DR11_WRITE 0x003B 123 #define VMCB_EXITCODE_DR12_WRITE 0x003C 124 #define VMCB_EXITCODE_DR13_WRITE 0x003D 125 #define VMCB_EXITCODE_DR14_WRITE 0x003E 126 #define VMCB_EXITCODE_DR15_WRITE 0x003F 127 #define VMCB_EXITCODE_EXCP0 0x0040 128 #define VMCB_EXITCODE_EXCP1 0x0041 129 #define VMCB_EXITCODE_EXCP2 0x0042 130 #define VMCB_EXITCODE_EXCP3 0x0043 131 #define VMCB_EXITCODE_EXCP4 0x0044 132 #define VMCB_EXITCODE_EXCP5 0x0045 133 #define VMCB_EXITCODE_EXCP6 0x0046 134 #define VMCB_EXITCODE_EXCP7 0x0047 135 #define VMCB_EXITCODE_EXCP8 0x0048 136 #define VMCB_EXITCODE_EXCP9 0x0049 137 #define VMCB_EXITCODE_EXCP10 0x004A 138 #define VMCB_EXITCODE_EXCP11 0x004B 139 #define VMCB_EXITCODE_EXCP12 0x004C 140 #define VMCB_EXITCODE_EXCP13 0x004D 141 #define VMCB_EXITCODE_EXCP14 0x004E 142 #define VMCB_EXITCODE_EXCP15 0x004F 143 #define VMCB_EXITCODE_EXCP16 0x0050 144 #define VMCB_EXITCODE_EXCP17 0x0051 145 #define VMCB_EXITCODE_EXCP18 0x0052 146 #define VMCB_EXITCODE_EXCP19 0x0053 147 #define VMCB_EXITCODE_EXCP20 0x0054 148 #define VMCB_EXITCODE_EXCP21 0x0055 149 #define VMCB_EXITCODE_EXCP22 0x0056 150 #define VMCB_EXITCODE_EXCP23 0x0057 151 #define VMCB_EXITCODE_EXCP24 0x0058 152 #define VMCB_EXITCODE_EXCP25 0x0059 153 #define VMCB_EXITCODE_EXCP26 0x005A 154 #define VMCB_EXITCODE_EXCP27 0x005B 155 #define VMCB_EXITCODE_EXCP28 0x005C 156 #define VMCB_EXITCODE_EXCP29 0x005D 157 #define VMCB_EXITCODE_EXCP30 0x005E 158 #define VMCB_EXITCODE_EXCP31 0x005F 159 #define VMCB_EXITCODE_INTR 0x0060 160 #define VMCB_EXITCODE_NMI 0x0061 161 #define VMCB_EXITCODE_SMI 0x0062 162 #define VMCB_EXITCODE_INIT 0x0063 163 #define VMCB_EXITCODE_VINTR 0x0064 164 #define VMCB_EXITCODE_CR0_SEL_WRITE 0x0065 165 #define VMCB_EXITCODE_IDTR_READ 0x0066 166 #define VMCB_EXITCODE_GDTR_READ 0x0067 167 #define VMCB_EXITCODE_LDTR_READ 0x0068 168 #define VMCB_EXITCODE_TR_READ 0x0069 169 #define VMCB_EXITCODE_IDTR_WRITE 0x006A 170 #define VMCB_EXITCODE_GDTR_WRITE 0x006B 171 #define VMCB_EXITCODE_LDTR_WRITE 0x006C 172 #define VMCB_EXITCODE_TR_WRITE 0x006D 173 #define VMCB_EXITCODE_RDTSC 0x006E 174 #define VMCB_EXITCODE_RDPMC 0x006F 175 #define VMCB_EXITCODE_PUSHF 0x0070 176 #define VMCB_EXITCODE_POPF 0x0071 177 #define VMCB_EXITCODE_CPUID 0x0072 178 #define VMCB_EXITCODE_RSM 0x0073 179 #define VMCB_EXITCODE_IRET 0x0074 180 #define VMCB_EXITCODE_SWINT 0x0075 181 #define VMCB_EXITCODE_INVD 0x0076 182 #define VMCB_EXITCODE_PAUSE 0x0077 183 #define VMCB_EXITCODE_HLT 0x0078 184 #define VMCB_EXITCODE_INVLPG 0x0079 185 #define VMCB_EXITCODE_INVLPGA 0x007A 186 #define VMCB_EXITCODE_IOIO 0x007B 187 #define VMCB_EXITCODE_MSR 0x007C 188 #define VMCB_EXITCODE_TASK_SWITCH 0x007D 189 #define VMCB_EXITCODE_FERR_FREEZE 0x007E 190 #define VMCB_EXITCODE_SHUTDOWN 0x007F 191 #define VMCB_EXITCODE_VMRUN 0x0080 192 #define VMCB_EXITCODE_VMMCALL 0x0081 193 #define VMCB_EXITCODE_VMLOAD 0x0082 194 #define VMCB_EXITCODE_VMSAVE 0x0083 195 #define VMCB_EXITCODE_STGI 0x0084 196 #define VMCB_EXITCODE_CLGI 0x0085 197 #define VMCB_EXITCODE_SKINIT 0x0086 198 #define VMCB_EXITCODE_RDTSCP 0x0087 199 #define VMCB_EXITCODE_ICEBP 0x0088 200 #define VMCB_EXITCODE_WBINVD 0x0089 201 #define VMCB_EXITCODE_MONITOR 0x008A 202 #define VMCB_EXITCODE_MWAIT 0x008B 203 #define VMCB_EXITCODE_MWAIT_CONDITIONAL 0x008C 204 #define VMCB_EXITCODE_XSETBV 0x008D 205 #define VMCB_EXITCODE_EFER_WRITE_TRAP 0x008F 206 #define VMCB_EXITCODE_CR0_WRITE_TRAP 0x0090 207 #define VMCB_EXITCODE_CR1_WRITE_TRAP 0x0091 208 #define VMCB_EXITCODE_CR2_WRITE_TRAP 0x0092 209 #define VMCB_EXITCODE_CR3_WRITE_TRAP 0x0093 210 #define VMCB_EXITCODE_CR4_WRITE_TRAP 0x0094 211 #define VMCB_EXITCODE_CR5_WRITE_TRAP 0x0095 212 #define VMCB_EXITCODE_CR6_WRITE_TRAP 0x0096 213 #define VMCB_EXITCODE_CR7_WRITE_TRAP 0x0097 214 #define VMCB_EXITCODE_CR8_WRITE_TRAP 0x0098 215 #define VMCB_EXITCODE_CR9_WRITE_TRAP 0x0099 216 #define VMCB_EXITCODE_CR10_WRITE_TRAP 0x009A 217 #define VMCB_EXITCODE_CR11_WRITE_TRAP 0x009B 218 #define VMCB_EXITCODE_CR12_WRITE_TRAP 0x009C 219 #define VMCB_EXITCODE_CR13_WRITE_TRAP 0x009D 220 #define VMCB_EXITCODE_CR14_WRITE_TRAP 0x009E 221 #define VMCB_EXITCODE_CR15_WRITE_TRAP 0x009F 222 #define VMCB_EXITCODE_NPF 0x0400 223 #define VMCB_EXITCODE_AVIC_INCOMP_IPI 0x0401 224 #define VMCB_EXITCODE_AVIC_NOACCEL 0x0402 225 #define VMCB_EXITCODE_VMGEXIT 0x0403 226 #define VMCB_EXITCODE_INVALID -1 227 228 /* -------------------------------------------------------------------------- */ 229 230 struct vmcb_ctrl { 231 uint32_t intercept_cr; 232 #define VMCB_CTRL_INTERCEPT_RCR(x) __BIT( 0 + x) 233 #define VMCB_CTRL_INTERCEPT_WCR(x) __BIT(16 + x) 234 235 uint32_t intercept_dr; 236 #define VMCB_CTRL_INTERCEPT_RDR(x) __BIT( 0 + x) 237 #define VMCB_CTRL_INTERCEPT_WDR(x) __BIT(16 + x) 238 239 uint32_t intercept_vec; 240 #define VMCB_CTRL_INTERCEPT_VEC(x) __BIT(x) 241 242 uint32_t intercept_misc1; 243 #define VMCB_CTRL_INTERCEPT_INTR __BIT(0) 244 #define VMCB_CTRL_INTERCEPT_NMI __BIT(1) 245 #define VMCB_CTRL_INTERCEPT_SMI __BIT(2) 246 #define VMCB_CTRL_INTERCEPT_INIT __BIT(3) 247 #define VMCB_CTRL_INTERCEPT_VINTR __BIT(4) 248 #define VMCB_CTRL_INTERCEPT_CR0_SPEC __BIT(5) 249 #define VMCB_CTRL_INTERCEPT_RIDTR __BIT(6) 250 #define VMCB_CTRL_INTERCEPT_RGDTR __BIT(7) 251 #define VMCB_CTRL_INTERCEPT_RLDTR __BIT(8) 252 #define VMCB_CTRL_INTERCEPT_RTR __BIT(9) 253 #define VMCB_CTRL_INTERCEPT_WIDTR __BIT(10) 254 #define VMCB_CTRL_INTERCEPT_WGDTR __BIT(11) 255 #define VMCB_CTRL_INTERCEPT_WLDTR __BIT(12) 256 #define VMCB_CTRL_INTERCEPT_WTR __BIT(13) 257 #define VMCB_CTRL_INTERCEPT_RDTSC __BIT(14) 258 #define VMCB_CTRL_INTERCEPT_RDPMC __BIT(15) 259 #define VMCB_CTRL_INTERCEPT_PUSHF __BIT(16) 260 #define VMCB_CTRL_INTERCEPT_POPF __BIT(17) 261 #define VMCB_CTRL_INTERCEPT_CPUID __BIT(18) 262 #define VMCB_CTRL_INTERCEPT_RSM __BIT(19) 263 #define VMCB_CTRL_INTERCEPT_IRET __BIT(20) 264 #define VMCB_CTRL_INTERCEPT_INTN __BIT(21) 265 #define VMCB_CTRL_INTERCEPT_INVD __BIT(22) 266 #define VMCB_CTRL_INTERCEPT_PAUSE __BIT(23) 267 #define VMCB_CTRL_INTERCEPT_HLT __BIT(24) 268 #define VMCB_CTRL_INTERCEPT_INVLPG __BIT(25) 269 #define VMCB_CTRL_INTERCEPT_INVLPGA __BIT(26) 270 #define VMCB_CTRL_INTERCEPT_IOIO_PROT __BIT(27) 271 #define VMCB_CTRL_INTERCEPT_MSR_PROT __BIT(28) 272 #define VMCB_CTRL_INTERCEPT_TASKSW __BIT(29) 273 #define VMCB_CTRL_INTERCEPT_FERR_FREEZE __BIT(30) 274 #define VMCB_CTRL_INTERCEPT_SHUTDOWN __BIT(31) 275 276 uint32_t intercept_misc2; 277 #define VMCB_CTRL_INTERCEPT_VMRUN __BIT(0) 278 #define VMCB_CTRL_INTERCEPT_VMMCALL __BIT(1) 279 #define VMCB_CTRL_INTERCEPT_VMLOAD __BIT(2) 280 #define VMCB_CTRL_INTERCEPT_VMSAVE __BIT(3) 281 #define VMCB_CTRL_INTERCEPT_STGI __BIT(4) 282 #define VMCB_CTRL_INTERCEPT_CLGI __BIT(5) 283 #define VMCB_CTRL_INTERCEPT_SKINIT __BIT(6) 284 #define VMCB_CTRL_INTERCEPT_RDTSCP __BIT(7) 285 #define VMCB_CTRL_INTERCEPT_ICEBP __BIT(8) 286 #define VMCB_CTRL_INTERCEPT_WBINVD __BIT(9) 287 #define VMCB_CTRL_INTERCEPT_MONITOR __BIT(10) 288 #define VMCB_CTRL_INTERCEPT_MWAIT __BIT(12) 289 #define VMCB_CTRL_INTERCEPT_XSETBV __BIT(13) 290 #define VMCB_CTRL_INTERCEPT_EFER_SPEC __BIT(15) 291 #define VMCB_CTRL_INTERCEPT_WCR_SPEC(x) __BIT(16 + x) 292 293 uint8_t rsvd1[40]; 294 uint16_t pause_filt_thresh; 295 uint16_t pause_filt_cnt; 296 uint64_t iopm_base_pa; 297 uint64_t msrpm_base_pa; 298 uint64_t tsc_offset; 299 uint32_t guest_asid; 300 301 uint32_t tlb_ctrl; 302 #define VMCB_CTRL_TLB_CTRL_FLUSH_ALL 0x01 303 #define VMCB_CTRL_TLB_CTRL_FLUSH_GUEST 0x03 304 #define VMCB_CTRL_TLB_CTRL_FLUSH_GUEST_NONGLOBAL 0x07 305 306 uint64_t v; 307 #define VMCB_CTRL_V_TPR __BITS(3,0) 308 #define VMCB_CTRL_V_IRQ __BIT(8) 309 #define VMCB_CTRL_V_VGIF __BIT(9) 310 #define VMCB_CTRL_V_INTR_PRIO __BITS(19,16) 311 #define VMCB_CTRL_V_IGN_TPR __BIT(20) 312 #define VMCB_CTRL_V_INTR_MASKING __BIT(24) 313 #define VMCB_CTRL_V_GUEST_VGIF __BIT(25) 314 #define VMCB_CTRL_V_AVIC_EN __BIT(31) 315 #define VMCB_CTRL_V_INTR_VECTOR __BITS(39,32) 316 317 uint64_t intr; 318 #define VMCB_CTRL_INTR_SHADOW __BIT(0) 319 320 uint64_t exitcode; 321 uint64_t exitinfo1; 322 uint64_t exitinfo2; 323 324 uint64_t exitintinfo; 325 #define VMCB_CTRL_EXITINTINFO_VECTOR __BITS(7,0) 326 #define VMCB_CTRL_EXITINTINFO_TYPE __BITS(10,8) 327 #define VMCB_CTRL_EXITINTINFO_EV __BIT(11) 328 #define VMCB_CTRL_EXITINTINFO_V __BIT(31) 329 #define VMCB_CTRL_EXITINTINFO_ERRORCODE __BITS(63,32) 330 331 uint64_t enable1; 332 #define VMCB_CTRL_ENABLE_NP __BIT(0) 333 #define VMCB_CTRL_ENABLE_SEV __BIT(1) 334 #define VMCB_CTRL_ENABLE_ES_SEV __BIT(2) 335 336 uint64_t avic; 337 #define VMCB_CTRL_AVIC_APIC_BAR __BITS(51,0) 338 339 uint64_t ghcb; 340 341 uint64_t eventinj; 342 #define VMCB_CTRL_EVENTINJ_VECTOR __BITS(7,0) 343 #define VMCB_CTRL_EVENTINJ_TYPE __BITS(10,8) 344 #define VMCB_CTRL_EVENTINJ_EV __BIT(11) 345 #define VMCB_CTRL_EVENTINJ_V __BIT(31) 346 #define VMCB_CTRL_EVENTINJ_ERRORCODE __BITS(63,32) 347 348 uint64_t n_cr3; 349 350 uint64_t enable2; 351 #define VMCB_CTRL_ENABLE_LBR __BIT(0) 352 #define VMCB_CTRL_ENABLE_VVMSAVE __BIT(1) 353 354 uint32_t vmcb_clean; 355 #define VMCB_CTRL_VMCB_CLEAN_I __BIT(0) 356 #define VMCB_CTRL_VMCB_CLEAN_IOPM __BIT(1) 357 #define VMCB_CTRL_VMCB_CLEAN_ASID __BIT(2) 358 #define VMCB_CTRL_VMCB_CLEAN_TPR __BIT(3) 359 #define VMCB_CTRL_VMCB_CLEAN_NP __BIT(4) 360 #define VMCB_CTRL_VMCB_CLEAN_CR __BIT(5) 361 #define VMCB_CTRL_VMCB_CLEAN_DR __BIT(6) 362 #define VMCB_CTRL_VMCB_CLEAN_DT __BIT(7) 363 #define VMCB_CTRL_VMCB_CLEAN_SEG __BIT(8) 364 #define VMCB_CTRL_VMCB_CLEAN_CR2 __BIT(9) 365 #define VMCB_CTRL_VMCB_CLEAN_LBR __BIT(10) 366 #define VMCB_CTRL_VMCB_CLEAN_AVIC __BIT(11) 367 368 uint32_t rsvd2; 369 uint64_t nrip; 370 uint8_t inst_len; 371 uint8_t inst_bytes[15]; 372 uint64_t avic_abpp; 373 uint64_t rsvd3; 374 uint64_t avic_ltp; 375 376 uint64_t avic_phys; 377 #define VMCB_CTRL_AVIC_PHYS_TABLE_PTR __BITS(51,12) 378 #define VMCB_CTRL_AVIC_PHYS_MAX_INDEX __BITS(7,0) 379 380 uint64_t rsvd4; 381 uint64_t vmcb_ptr; 382 383 uint8_t pad[752]; 384 } __packed; 385 386 CTASSERT(sizeof(struct vmcb_ctrl) == 1024); 387 388 struct vmcb_segment { 389 uint16_t selector; 390 uint16_t attrib; /* hidden */ 391 uint32_t limit; /* hidden */ 392 uint64_t base; /* hidden */ 393 } __packed; 394 395 CTASSERT(sizeof(struct vmcb_segment) == 16); 396 397 struct vmcb_state { 398 struct vmcb_segment es; 399 struct vmcb_segment cs; 400 struct vmcb_segment ss; 401 struct vmcb_segment ds; 402 struct vmcb_segment fs; 403 struct vmcb_segment gs; 404 struct vmcb_segment gdt; 405 struct vmcb_segment ldt; 406 struct vmcb_segment idt; 407 struct vmcb_segment tr; 408 uint8_t rsvd1[43]; 409 uint8_t cpl; 410 uint8_t rsvd2[4]; 411 uint64_t efer; 412 uint8_t rsvd3[112]; 413 uint64_t cr4; 414 uint64_t cr3; 415 uint64_t cr0; 416 uint64_t dr7; 417 uint64_t dr6; 418 uint64_t rflags; 419 uint64_t rip; 420 uint8_t rsvd4[88]; 421 uint64_t rsp; 422 uint8_t rsvd5[24]; 423 uint64_t rax; 424 uint64_t star; 425 uint64_t lstar; 426 uint64_t cstar; 427 uint64_t sfmask; 428 uint64_t kernelgsbase; 429 uint64_t sysenter_cs; 430 uint64_t sysenter_esp; 431 uint64_t sysenter_eip; 432 uint64_t cr2; 433 uint8_t rsvd6[32]; 434 uint64_t g_pat; 435 uint64_t dbgctl; 436 uint64_t br_from; 437 uint64_t br_to; 438 uint64_t int_from; 439 uint64_t int_to; 440 uint8_t pad[2408]; 441 } __packed; 442 443 CTASSERT(sizeof(struct vmcb_state) == 0xC00); 444 445 struct vmcb { 446 struct vmcb_ctrl ctrl; 447 struct vmcb_state state; 448 } __packed; 449 450 CTASSERT(sizeof(struct vmcb) == PAGE_SIZE); 451 CTASSERT(offsetof(struct vmcb, state) == 0x400); 452 453 /* -------------------------------------------------------------------------- */ 454 455 struct svm_hsave { 456 paddr_t pa; 457 }; 458 459 static struct svm_hsave hsave[MAXCPUS]; 460 461 static uint8_t *svm_asidmap __read_mostly; 462 static uint32_t svm_maxasid __read_mostly; 463 static kmutex_t svm_asidlock __cacheline_aligned; 464 465 static bool svm_decode_assist __read_mostly; 466 static uint32_t svm_ctrl_tlb_flush __read_mostly; 467 468 #define SVM_XCR0_MASK_DEFAULT (XCR0_X87|XCR0_SSE) 469 static uint64_t svm_xcr0_mask __read_mostly; 470 471 #define SVM_NCPUIDS 32 472 473 #define VMCB_NPAGES 1 474 475 #define MSRBM_NPAGES 2 476 #define MSRBM_SIZE (MSRBM_NPAGES * PAGE_SIZE) 477 478 #define IOBM_NPAGES 3 479 #define IOBM_SIZE (IOBM_NPAGES * PAGE_SIZE) 480 481 /* Does not include EFER_LMSLE. */ 482 #define EFER_VALID \ 483 (EFER_SCE|EFER_LME|EFER_LMA|EFER_NXE|EFER_SVME|EFER_FFXSR|EFER_TCE) 484 485 #define EFER_TLB_FLUSH \ 486 (EFER_NXE|EFER_LMA|EFER_LME) 487 #define CR0_TLB_FLUSH \ 488 (CR0_PG|CR0_WP|CR0_CD|CR0_NW) 489 #define CR4_TLB_FLUSH \ 490 (CR4_PGE|CR4_PAE|CR4_PSE) 491 492 /* -------------------------------------------------------------------------- */ 493 494 struct svm_machdata { 495 bool cpuidpresent[SVM_NCPUIDS]; 496 struct nvmm_x86_conf_cpuid cpuid[SVM_NCPUIDS]; 497 volatile uint64_t mach_htlb_gen; 498 }; 499 500 static const size_t svm_conf_sizes[NVMM_X86_NCONF] = { 501 [NVMM_X86_CONF_CPUID] = sizeof(struct nvmm_x86_conf_cpuid) 502 }; 503 504 struct svm_cpudata { 505 /* General */ 506 bool shared_asid; 507 bool gtlb_want_flush; 508 uint64_t vcpu_htlb_gen; 509 510 /* VMCB */ 511 struct vmcb *vmcb; 512 paddr_t vmcb_pa; 513 514 /* I/O bitmap */ 515 uint8_t *iobm; 516 paddr_t iobm_pa; 517 518 /* MSR bitmap */ 519 uint8_t *msrbm; 520 paddr_t msrbm_pa; 521 522 /* Host state */ 523 uint64_t hxcr0; 524 uint64_t star; 525 uint64_t lstar; 526 uint64_t cstar; 527 uint64_t sfmask; 528 uint64_t fsbase; 529 uint64_t kernelgsbase; 530 bool ts_set; 531 struct xsave_header hfpu __aligned(64); 532 533 /* Event state */ 534 bool int_window_exit; 535 bool nmi_window_exit; 536 537 /* Guest state */ 538 uint64_t gxcr0; 539 uint64_t gprs[NVMM_X64_NGPR]; 540 uint64_t drs[NVMM_X64_NDR]; 541 uint64_t tsc_offset; 542 struct xsave_header gfpu __aligned(64); 543 }; 544 545 static void 546 svm_vmcb_cache_default(struct vmcb *vmcb) 547 { 548 vmcb->ctrl.vmcb_clean = 549 VMCB_CTRL_VMCB_CLEAN_I | 550 VMCB_CTRL_VMCB_CLEAN_IOPM | 551 VMCB_CTRL_VMCB_CLEAN_ASID | 552 VMCB_CTRL_VMCB_CLEAN_TPR | 553 VMCB_CTRL_VMCB_CLEAN_NP | 554 VMCB_CTRL_VMCB_CLEAN_CR | 555 VMCB_CTRL_VMCB_CLEAN_DR | 556 VMCB_CTRL_VMCB_CLEAN_DT | 557 VMCB_CTRL_VMCB_CLEAN_SEG | 558 VMCB_CTRL_VMCB_CLEAN_CR2 | 559 VMCB_CTRL_VMCB_CLEAN_LBR | 560 VMCB_CTRL_VMCB_CLEAN_AVIC; 561 } 562 563 static void 564 svm_vmcb_cache_update(struct vmcb *vmcb, uint64_t flags) 565 { 566 if (flags & NVMM_X64_STATE_SEGS) { 567 vmcb->ctrl.vmcb_clean &= 568 ~(VMCB_CTRL_VMCB_CLEAN_SEG | VMCB_CTRL_VMCB_CLEAN_DT); 569 } 570 if (flags & NVMM_X64_STATE_CRS) { 571 vmcb->ctrl.vmcb_clean &= 572 ~(VMCB_CTRL_VMCB_CLEAN_CR | VMCB_CTRL_VMCB_CLEAN_CR2 | 573 VMCB_CTRL_VMCB_CLEAN_TPR); 574 } 575 if (flags & NVMM_X64_STATE_DRS) { 576 vmcb->ctrl.vmcb_clean &= ~VMCB_CTRL_VMCB_CLEAN_DR; 577 } 578 if (flags & NVMM_X64_STATE_MSRS) { 579 /* CR for EFER, NP for PAT. */ 580 vmcb->ctrl.vmcb_clean &= 581 ~(VMCB_CTRL_VMCB_CLEAN_CR | VMCB_CTRL_VMCB_CLEAN_NP); 582 } 583 } 584 585 static inline void 586 svm_vmcb_cache_flush(struct vmcb *vmcb, uint64_t flags) 587 { 588 vmcb->ctrl.vmcb_clean &= ~flags; 589 } 590 591 static inline void 592 svm_vmcb_cache_flush_all(struct vmcb *vmcb) 593 { 594 vmcb->ctrl.vmcb_clean = 0; 595 } 596 597 #define SVM_EVENT_TYPE_HW_INT 0 598 #define SVM_EVENT_TYPE_NMI 2 599 #define SVM_EVENT_TYPE_EXC 3 600 #define SVM_EVENT_TYPE_SW_INT 4 601 602 static void 603 svm_event_waitexit_enable(struct nvmm_cpu *vcpu, bool nmi) 604 { 605 struct svm_cpudata *cpudata = vcpu->cpudata; 606 struct vmcb *vmcb = cpudata->vmcb; 607 608 if (nmi) { 609 vmcb->ctrl.intercept_misc1 |= VMCB_CTRL_INTERCEPT_IRET; 610 cpudata->nmi_window_exit = true; 611 } else { 612 vmcb->ctrl.intercept_misc1 |= VMCB_CTRL_INTERCEPT_VINTR; 613 vmcb->ctrl.v |= (VMCB_CTRL_V_IRQ | VMCB_CTRL_V_IGN_TPR); 614 svm_vmcb_cache_flush(vmcb, VMCB_CTRL_VMCB_CLEAN_TPR); 615 cpudata->int_window_exit = true; 616 } 617 618 svm_vmcb_cache_flush(vmcb, VMCB_CTRL_VMCB_CLEAN_I); 619 } 620 621 static void 622 svm_event_waitexit_disable(struct nvmm_cpu *vcpu, bool nmi) 623 { 624 struct svm_cpudata *cpudata = vcpu->cpudata; 625 struct vmcb *vmcb = cpudata->vmcb; 626 627 if (nmi) { 628 vmcb->ctrl.intercept_misc1 &= ~VMCB_CTRL_INTERCEPT_IRET; 629 cpudata->nmi_window_exit = false; 630 } else { 631 vmcb->ctrl.intercept_misc1 &= ~VMCB_CTRL_INTERCEPT_VINTR; 632 vmcb->ctrl.v &= ~(VMCB_CTRL_V_IRQ | VMCB_CTRL_V_IGN_TPR); 633 svm_vmcb_cache_flush(vmcb, VMCB_CTRL_VMCB_CLEAN_TPR); 634 cpudata->int_window_exit = false; 635 } 636 637 svm_vmcb_cache_flush(vmcb, VMCB_CTRL_VMCB_CLEAN_I); 638 } 639 640 static inline int 641 svm_event_has_error(uint64_t vector) 642 { 643 switch (vector) { 644 case 8: /* #DF */ 645 case 10: /* #TS */ 646 case 11: /* #NP */ 647 case 12: /* #SS */ 648 case 13: /* #GP */ 649 case 14: /* #PF */ 650 case 17: /* #AC */ 651 case 30: /* #SX */ 652 return 1; 653 default: 654 return 0; 655 } 656 } 657 658 static int 659 svm_vcpu_inject(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 660 struct nvmm_event *event) 661 { 662 struct svm_cpudata *cpudata = vcpu->cpudata; 663 struct vmcb *vmcb = cpudata->vmcb; 664 int type = 0, err = 0; 665 666 if (event->vector >= 256) { 667 return EINVAL; 668 } 669 670 switch (event->type) { 671 case NVMM_EVENT_INTERRUPT_HW: 672 type = SVM_EVENT_TYPE_HW_INT; 673 if (event->vector == 2) { 674 type = SVM_EVENT_TYPE_NMI; 675 } 676 if (type == SVM_EVENT_TYPE_NMI) { 677 if (cpudata->nmi_window_exit) { 678 return EAGAIN; 679 } 680 svm_event_waitexit_enable(vcpu, true); 681 } else { 682 if (((vmcb->state.rflags & PSL_I) == 0) || 683 ((vmcb->ctrl.intr & VMCB_CTRL_INTR_SHADOW) != 0)) { 684 svm_event_waitexit_enable(vcpu, false); 685 return EAGAIN; 686 } 687 } 688 err = 0; 689 break; 690 case NVMM_EVENT_INTERRUPT_SW: 691 return EINVAL; 692 case NVMM_EVENT_EXCEPTION: 693 type = SVM_EVENT_TYPE_EXC; 694 if (event->vector == 2 || event->vector >= 32) 695 return EINVAL; 696 if (event->vector == 3 || event->vector == 0) 697 return EINVAL; 698 err = svm_event_has_error(event->vector); 699 break; 700 default: 701 return EINVAL; 702 } 703 704 vmcb->ctrl.eventinj = 705 __SHIFTIN(event->vector, VMCB_CTRL_EVENTINJ_VECTOR) | 706 __SHIFTIN(type, VMCB_CTRL_EVENTINJ_TYPE) | 707 __SHIFTIN(err, VMCB_CTRL_EVENTINJ_EV) | 708 __SHIFTIN(1, VMCB_CTRL_EVENTINJ_V) | 709 __SHIFTIN(event->u.error, VMCB_CTRL_EVENTINJ_ERRORCODE); 710 711 return 0; 712 } 713 714 static void 715 svm_inject_ud(struct nvmm_machine *mach, struct nvmm_cpu *vcpu) 716 { 717 struct nvmm_event event; 718 int ret __diagused; 719 720 event.type = NVMM_EVENT_EXCEPTION; 721 event.vector = 6; 722 event.u.error = 0; 723 724 ret = svm_vcpu_inject(mach, vcpu, &event); 725 KASSERT(ret == 0); 726 } 727 728 static void 729 svm_inject_gp(struct nvmm_machine *mach, struct nvmm_cpu *vcpu) 730 { 731 struct nvmm_event event; 732 int ret __diagused; 733 734 event.type = NVMM_EVENT_EXCEPTION; 735 event.vector = 13; 736 event.u.error = 0; 737 738 ret = svm_vcpu_inject(mach, vcpu, &event); 739 KASSERT(ret == 0); 740 } 741 742 static inline void 743 svm_inkernel_advance(struct vmcb *vmcb) 744 { 745 /* 746 * Maybe we should also apply single-stepping and debug exceptions. 747 * Matters for guest-ring3, because it can execute 'cpuid' under a 748 * debugger. 749 */ 750 vmcb->state.rip = vmcb->ctrl.nrip; 751 vmcb->ctrl.intr &= ~VMCB_CTRL_INTR_SHADOW; 752 } 753 754 static void 755 svm_inkernel_handle_cpuid(struct nvmm_cpu *vcpu, uint64_t eax, uint64_t ecx) 756 { 757 struct svm_cpudata *cpudata = vcpu->cpudata; 758 uint64_t cr4; 759 760 switch (eax) { 761 case 0x00000001: 762 cpudata->vmcb->state.rax &= nvmm_cpuid_00000001.eax; 763 764 cpudata->gprs[NVMM_X64_GPR_RBX] &= ~CPUID_LOCAL_APIC_ID; 765 cpudata->gprs[NVMM_X64_GPR_RBX] |= __SHIFTIN(vcpu->cpuid, 766 CPUID_LOCAL_APIC_ID); 767 768 cpudata->gprs[NVMM_X64_GPR_RCX] &= nvmm_cpuid_00000001.ecx; 769 cpudata->gprs[NVMM_X64_GPR_RCX] |= CPUID2_RAZ; 770 771 cpudata->gprs[NVMM_X64_GPR_RDX] &= nvmm_cpuid_00000001.edx; 772 773 /* CPUID2_OSXSAVE depends on CR4. */ 774 cr4 = cpudata->vmcb->state.cr4; 775 if (!(cr4 & CR4_OSXSAVE)) { 776 cpudata->gprs[NVMM_X64_GPR_RCX] &= ~CPUID2_OSXSAVE; 777 } 778 break; 779 case 0x00000005: 780 case 0x00000006: 781 cpudata->vmcb->state.rax = 0; 782 cpudata->gprs[NVMM_X64_GPR_RBX] = 0; 783 cpudata->gprs[NVMM_X64_GPR_RCX] = 0; 784 cpudata->gprs[NVMM_X64_GPR_RDX] = 0; 785 break; 786 case 0x00000007: 787 cpudata->vmcb->state.rax &= nvmm_cpuid_00000007.eax; 788 cpudata->gprs[NVMM_X64_GPR_RBX] &= nvmm_cpuid_00000007.ebx; 789 cpudata->gprs[NVMM_X64_GPR_RCX] &= nvmm_cpuid_00000007.ecx; 790 cpudata->gprs[NVMM_X64_GPR_RDX] &= nvmm_cpuid_00000007.edx; 791 break; 792 case 0x0000000D: 793 if (svm_xcr0_mask == 0) { 794 break; 795 } 796 switch (ecx) { 797 case 0: 798 cpudata->vmcb->state.rax = svm_xcr0_mask & 0xFFFFFFFF; 799 if (cpudata->gxcr0 & XCR0_SSE) { 800 cpudata->gprs[NVMM_X64_GPR_RBX] = sizeof(struct fxsave); 801 } else { 802 cpudata->gprs[NVMM_X64_GPR_RBX] = sizeof(struct save87); 803 } 804 cpudata->gprs[NVMM_X64_GPR_RBX] += 64; /* XSAVE header */ 805 cpudata->gprs[NVMM_X64_GPR_RCX] = sizeof(struct fxsave); 806 cpudata->gprs[NVMM_X64_GPR_RDX] = svm_xcr0_mask >> 32; 807 break; 808 case 1: 809 cpudata->vmcb->state.rax &= ~CPUID_PES1_XSAVES; 810 break; 811 } 812 break; 813 case 0x40000000: 814 cpudata->gprs[NVMM_X64_GPR_RBX] = 0; 815 cpudata->gprs[NVMM_X64_GPR_RCX] = 0; 816 cpudata->gprs[NVMM_X64_GPR_RDX] = 0; 817 memcpy(&cpudata->gprs[NVMM_X64_GPR_RBX], "___ ", 4); 818 memcpy(&cpudata->gprs[NVMM_X64_GPR_RCX], "NVMM", 4); 819 memcpy(&cpudata->gprs[NVMM_X64_GPR_RDX], " ___", 4); 820 break; 821 case 0x80000001: 822 cpudata->vmcb->state.rax &= nvmm_cpuid_80000001.eax; 823 cpudata->gprs[NVMM_X64_GPR_RBX] &= nvmm_cpuid_80000001.ebx; 824 cpudata->gprs[NVMM_X64_GPR_RCX] &= nvmm_cpuid_80000001.ecx; 825 cpudata->gprs[NVMM_X64_GPR_RDX] &= nvmm_cpuid_80000001.edx; 826 break; 827 default: 828 break; 829 } 830 } 831 832 static void 833 svm_exit_cpuid(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 834 struct nvmm_exit *exit) 835 { 836 struct svm_machdata *machdata = mach->machdata; 837 struct svm_cpudata *cpudata = vcpu->cpudata; 838 struct nvmm_x86_conf_cpuid *cpuid; 839 uint64_t eax, ecx; 840 u_int descs[4]; 841 size_t i; 842 843 eax = cpudata->vmcb->state.rax; 844 ecx = cpudata->gprs[NVMM_X64_GPR_RCX]; 845 x86_cpuid2(eax, ecx, descs); 846 847 cpudata->vmcb->state.rax = descs[0]; 848 cpudata->gprs[NVMM_X64_GPR_RBX] = descs[1]; 849 cpudata->gprs[NVMM_X64_GPR_RCX] = descs[2]; 850 cpudata->gprs[NVMM_X64_GPR_RDX] = descs[3]; 851 852 for (i = 0; i < SVM_NCPUIDS; i++) { 853 cpuid = &machdata->cpuid[i]; 854 if (!machdata->cpuidpresent[i]) { 855 continue; 856 } 857 if (cpuid->leaf != eax) { 858 continue; 859 } 860 861 /* del */ 862 cpudata->vmcb->state.rax &= ~cpuid->del.eax; 863 cpudata->gprs[NVMM_X64_GPR_RBX] &= ~cpuid->del.ebx; 864 cpudata->gprs[NVMM_X64_GPR_RCX] &= ~cpuid->del.ecx; 865 cpudata->gprs[NVMM_X64_GPR_RDX] &= ~cpuid->del.edx; 866 867 /* set */ 868 cpudata->vmcb->state.rax |= cpuid->set.eax; 869 cpudata->gprs[NVMM_X64_GPR_RBX] |= cpuid->set.ebx; 870 cpudata->gprs[NVMM_X64_GPR_RCX] |= cpuid->set.ecx; 871 cpudata->gprs[NVMM_X64_GPR_RDX] |= cpuid->set.edx; 872 873 break; 874 } 875 876 /* Overwrite non-tunable leaves. */ 877 svm_inkernel_handle_cpuid(vcpu, eax, ecx); 878 879 svm_inkernel_advance(cpudata->vmcb); 880 exit->reason = NVMM_EXIT_NONE; 881 } 882 883 static void 884 svm_exit_hlt(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 885 struct nvmm_exit *exit) 886 { 887 struct svm_cpudata *cpudata = vcpu->cpudata; 888 struct vmcb *vmcb = cpudata->vmcb; 889 890 if (cpudata->int_window_exit && (vmcb->state.rflags & PSL_I)) { 891 svm_event_waitexit_disable(vcpu, false); 892 } 893 894 svm_inkernel_advance(cpudata->vmcb); 895 exit->reason = NVMM_EXIT_HALTED; 896 } 897 898 #define SVM_EXIT_IO_PORT __BITS(31,16) 899 #define SVM_EXIT_IO_SEG __BITS(12,10) 900 #define SVM_EXIT_IO_A64 __BIT(9) 901 #define SVM_EXIT_IO_A32 __BIT(8) 902 #define SVM_EXIT_IO_A16 __BIT(7) 903 #define SVM_EXIT_IO_SZ32 __BIT(6) 904 #define SVM_EXIT_IO_SZ16 __BIT(5) 905 #define SVM_EXIT_IO_SZ8 __BIT(4) 906 #define SVM_EXIT_IO_REP __BIT(3) 907 #define SVM_EXIT_IO_STR __BIT(2) 908 #define SVM_EXIT_IO_IN __BIT(0) 909 910 static void 911 svm_exit_io(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 912 struct nvmm_exit *exit) 913 { 914 struct svm_cpudata *cpudata = vcpu->cpudata; 915 uint64_t info = cpudata->vmcb->ctrl.exitinfo1; 916 uint64_t nextpc = cpudata->vmcb->ctrl.exitinfo2; 917 918 exit->reason = NVMM_EXIT_IO; 919 920 if (info & SVM_EXIT_IO_IN) { 921 exit->u.io.type = NVMM_EXIT_IO_IN; 922 } else { 923 exit->u.io.type = NVMM_EXIT_IO_OUT; 924 } 925 926 exit->u.io.port = __SHIFTOUT(info, SVM_EXIT_IO_PORT); 927 928 if (svm_decode_assist) { 929 KASSERT(__SHIFTOUT(info, SVM_EXIT_IO_SEG) < 6); 930 exit->u.io.seg = __SHIFTOUT(info, SVM_EXIT_IO_SEG); 931 } else { 932 exit->u.io.seg = -1; 933 } 934 935 if (info & SVM_EXIT_IO_A64) { 936 exit->u.io.address_size = 8; 937 } else if (info & SVM_EXIT_IO_A32) { 938 exit->u.io.address_size = 4; 939 } else if (info & SVM_EXIT_IO_A16) { 940 exit->u.io.address_size = 2; 941 } 942 943 if (info & SVM_EXIT_IO_SZ32) { 944 exit->u.io.operand_size = 4; 945 } else if (info & SVM_EXIT_IO_SZ16) { 946 exit->u.io.operand_size = 2; 947 } else if (info & SVM_EXIT_IO_SZ8) { 948 exit->u.io.operand_size = 1; 949 } 950 951 exit->u.io.rep = (info & SVM_EXIT_IO_REP) != 0; 952 exit->u.io.str = (info & SVM_EXIT_IO_STR) != 0; 953 exit->u.io.npc = nextpc; 954 } 955 956 static const uint64_t msr_ignore_list[] = { 957 0xc0010055, /* MSR_CMPHALT */ 958 MSR_DE_CFG, 959 MSR_IC_CFG, 960 MSR_UCODE_AMD_PATCHLEVEL 961 }; 962 963 static bool 964 svm_inkernel_handle_msr(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 965 struct nvmm_exit *exit) 966 { 967 struct svm_cpudata *cpudata = vcpu->cpudata; 968 struct vmcb *vmcb = cpudata->vmcb; 969 uint64_t val; 970 size_t i; 971 972 switch (exit->u.msr.type) { 973 case NVMM_EXIT_MSR_RDMSR: 974 if (exit->u.msr.msr == MSR_NB_CFG) { 975 val = NB_CFG_INITAPICCPUIDLO; 976 vmcb->state.rax = (val & 0xFFFFFFFF); 977 cpudata->gprs[NVMM_X64_GPR_RDX] = (val >> 32); 978 goto handled; 979 } 980 for (i = 0; i < __arraycount(msr_ignore_list); i++) { 981 if (msr_ignore_list[i] != exit->u.msr.msr) 982 continue; 983 val = 0; 984 vmcb->state.rax = (val & 0xFFFFFFFF); 985 cpudata->gprs[NVMM_X64_GPR_RDX] = (val >> 32); 986 goto handled; 987 } 988 break; 989 case NVMM_EXIT_MSR_WRMSR: 990 if (exit->u.msr.msr == MSR_EFER) { 991 if (__predict_false(exit->u.msr.val & ~EFER_VALID)) { 992 goto error; 993 } 994 if ((vmcb->state.efer ^ exit->u.msr.val) & 995 EFER_TLB_FLUSH) { 996 cpudata->gtlb_want_flush = true; 997 } 998 vmcb->state.efer = exit->u.msr.val | EFER_SVME; 999 svm_vmcb_cache_flush(vmcb, VMCB_CTRL_VMCB_CLEAN_CR); 1000 goto handled; 1001 } 1002 if (exit->u.msr.msr == MSR_TSC) { 1003 cpudata->tsc_offset = exit->u.msr.val - cpu_counter(); 1004 vmcb->ctrl.tsc_offset = cpudata->tsc_offset + 1005 curcpu()->ci_data.cpu_cc_skew; 1006 svm_vmcb_cache_flush(vmcb, VMCB_CTRL_VMCB_CLEAN_I); 1007 goto handled; 1008 } 1009 for (i = 0; i < __arraycount(msr_ignore_list); i++) { 1010 if (msr_ignore_list[i] != exit->u.msr.msr) 1011 continue; 1012 goto handled; 1013 } 1014 break; 1015 } 1016 1017 return false; 1018 1019 handled: 1020 svm_inkernel_advance(cpudata->vmcb); 1021 return true; 1022 1023 error: 1024 svm_inject_gp(mach, vcpu); 1025 return true; 1026 } 1027 1028 static void 1029 svm_exit_msr(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 1030 struct nvmm_exit *exit) 1031 { 1032 struct svm_cpudata *cpudata = vcpu->cpudata; 1033 uint64_t info = cpudata->vmcb->ctrl.exitinfo1; 1034 1035 if (info == 0) { 1036 exit->u.msr.type = NVMM_EXIT_MSR_RDMSR; 1037 } else { 1038 exit->u.msr.type = NVMM_EXIT_MSR_WRMSR; 1039 } 1040 1041 exit->u.msr.msr = (cpudata->gprs[NVMM_X64_GPR_RCX] & 0xFFFFFFFF); 1042 1043 if (info == 1) { 1044 uint64_t rdx, rax; 1045 rdx = cpudata->gprs[NVMM_X64_GPR_RDX]; 1046 rax = cpudata->vmcb->state.rax; 1047 exit->u.msr.val = (rdx << 32) | (rax & 0xFFFFFFFF); 1048 } else { 1049 exit->u.msr.val = 0; 1050 } 1051 1052 if (svm_inkernel_handle_msr(mach, vcpu, exit)) { 1053 exit->reason = NVMM_EXIT_NONE; 1054 return; 1055 } 1056 1057 exit->reason = NVMM_EXIT_MSR; 1058 exit->u.msr.npc = cpudata->vmcb->ctrl.nrip; 1059 } 1060 1061 static void 1062 svm_exit_npf(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 1063 struct nvmm_exit *exit) 1064 { 1065 struct svm_cpudata *cpudata = vcpu->cpudata; 1066 gpaddr_t gpa = cpudata->vmcb->ctrl.exitinfo2; 1067 1068 exit->reason = NVMM_EXIT_MEMORY; 1069 if (cpudata->vmcb->ctrl.exitinfo1 & PGEX_W) 1070 exit->u.mem.prot = PROT_WRITE; 1071 else if (cpudata->vmcb->ctrl.exitinfo1 & PGEX_X) 1072 exit->u.mem.prot = PROT_EXEC; 1073 else 1074 exit->u.mem.prot = PROT_READ; 1075 exit->u.mem.gpa = gpa; 1076 exit->u.mem.inst_len = cpudata->vmcb->ctrl.inst_len; 1077 memcpy(exit->u.mem.inst_bytes, cpudata->vmcb->ctrl.inst_bytes, 1078 sizeof(exit->u.mem.inst_bytes)); 1079 } 1080 1081 static void 1082 svm_exit_insn(struct vmcb *vmcb, struct nvmm_exit *exit, uint64_t reason) 1083 { 1084 exit->u.insn.npc = vmcb->ctrl.nrip; 1085 exit->reason = reason; 1086 } 1087 1088 static void 1089 svm_exit_xsetbv(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 1090 struct nvmm_exit *exit) 1091 { 1092 struct svm_cpudata *cpudata = vcpu->cpudata; 1093 struct vmcb *vmcb = cpudata->vmcb; 1094 uint64_t val; 1095 1096 exit->reason = NVMM_EXIT_NONE; 1097 1098 val = (cpudata->gprs[NVMM_X64_GPR_RDX] << 32) | 1099 (vmcb->state.rax & 0xFFFFFFFF); 1100 1101 if (__predict_false(cpudata->gprs[NVMM_X64_GPR_RCX] != 0)) { 1102 goto error; 1103 } else if (__predict_false(vmcb->state.cpl != 0)) { 1104 goto error; 1105 } else if (__predict_false((val & ~svm_xcr0_mask) != 0)) { 1106 goto error; 1107 } else if (__predict_false((val & XCR0_X87) == 0)) { 1108 goto error; 1109 } 1110 1111 cpudata->gxcr0 = val; 1112 1113 svm_inkernel_advance(cpudata->vmcb); 1114 return; 1115 1116 error: 1117 svm_inject_gp(mach, vcpu); 1118 } 1119 1120 /* -------------------------------------------------------------------------- */ 1121 1122 static void 1123 svm_vcpu_guest_fpu_enter(struct nvmm_cpu *vcpu) 1124 { 1125 struct svm_cpudata *cpudata = vcpu->cpudata; 1126 1127 cpudata->ts_set = (rcr0() & CR0_TS) != 0; 1128 1129 fpu_area_save(&cpudata->hfpu, svm_xcr0_mask); 1130 fpu_area_restore(&cpudata->gfpu, svm_xcr0_mask); 1131 1132 if (svm_xcr0_mask != 0) { 1133 cpudata->hxcr0 = rdxcr(0); 1134 wrxcr(0, cpudata->gxcr0); 1135 } 1136 } 1137 1138 static void 1139 svm_vcpu_guest_fpu_leave(struct nvmm_cpu *vcpu) 1140 { 1141 struct svm_cpudata *cpudata = vcpu->cpudata; 1142 1143 if (svm_xcr0_mask != 0) { 1144 cpudata->gxcr0 = rdxcr(0); 1145 wrxcr(0, cpudata->hxcr0); 1146 } 1147 1148 fpu_area_save(&cpudata->gfpu, svm_xcr0_mask); 1149 fpu_area_restore(&cpudata->hfpu, svm_xcr0_mask); 1150 1151 if (cpudata->ts_set) { 1152 stts(); 1153 } 1154 } 1155 1156 static void 1157 svm_vcpu_guest_dbregs_enter(struct nvmm_cpu *vcpu) 1158 { 1159 struct svm_cpudata *cpudata = vcpu->cpudata; 1160 1161 x86_dbregs_save(curlwp); 1162 1163 ldr7(0); 1164 1165 ldr0(cpudata->drs[NVMM_X64_DR_DR0]); 1166 ldr1(cpudata->drs[NVMM_X64_DR_DR1]); 1167 ldr2(cpudata->drs[NVMM_X64_DR_DR2]); 1168 ldr3(cpudata->drs[NVMM_X64_DR_DR3]); 1169 } 1170 1171 static void 1172 svm_vcpu_guest_dbregs_leave(struct nvmm_cpu *vcpu) 1173 { 1174 struct svm_cpudata *cpudata = vcpu->cpudata; 1175 1176 cpudata->drs[NVMM_X64_DR_DR0] = rdr0(); 1177 cpudata->drs[NVMM_X64_DR_DR1] = rdr1(); 1178 cpudata->drs[NVMM_X64_DR_DR2] = rdr2(); 1179 cpudata->drs[NVMM_X64_DR_DR3] = rdr3(); 1180 1181 x86_dbregs_restore(curlwp); 1182 } 1183 1184 static void 1185 svm_vcpu_guest_misc_enter(struct nvmm_cpu *vcpu) 1186 { 1187 struct svm_cpudata *cpudata = vcpu->cpudata; 1188 1189 cpudata->fsbase = rdmsr(MSR_FSBASE); 1190 cpudata->kernelgsbase = rdmsr(MSR_KERNELGSBASE); 1191 } 1192 1193 static void 1194 svm_vcpu_guest_misc_leave(struct nvmm_cpu *vcpu) 1195 { 1196 struct svm_cpudata *cpudata = vcpu->cpudata; 1197 1198 wrmsr(MSR_STAR, cpudata->star); 1199 wrmsr(MSR_LSTAR, cpudata->lstar); 1200 wrmsr(MSR_CSTAR, cpudata->cstar); 1201 wrmsr(MSR_SFMASK, cpudata->sfmask); 1202 wrmsr(MSR_FSBASE, cpudata->fsbase); 1203 wrmsr(MSR_KERNELGSBASE, cpudata->kernelgsbase); 1204 } 1205 1206 /* -------------------------------------------------------------------------- */ 1207 1208 static inline void 1209 svm_gtlb_catchup(struct nvmm_cpu *vcpu, int hcpu) 1210 { 1211 struct svm_cpudata *cpudata = vcpu->cpudata; 1212 1213 if (vcpu->hcpu_last != hcpu || cpudata->shared_asid) { 1214 cpudata->gtlb_want_flush = true; 1215 } 1216 } 1217 1218 static inline void 1219 svm_htlb_catchup(struct nvmm_cpu *vcpu, int hcpu) 1220 { 1221 /* 1222 * Nothing to do. If an hTLB flush was needed, either the VCPU was 1223 * executing on this hCPU and the hTLB already got flushed, or it 1224 * was executing on another hCPU in which case the catchup is done 1225 * in svm_gtlb_catchup(). 1226 */ 1227 } 1228 1229 static inline uint64_t 1230 svm_htlb_flush(struct svm_machdata *machdata, struct svm_cpudata *cpudata) 1231 { 1232 struct vmcb *vmcb = cpudata->vmcb; 1233 uint64_t machgen; 1234 1235 machgen = machdata->mach_htlb_gen; 1236 if (__predict_true(machgen == cpudata->vcpu_htlb_gen)) { 1237 return machgen; 1238 } 1239 1240 vmcb->ctrl.tlb_ctrl = svm_ctrl_tlb_flush; 1241 return machgen; 1242 } 1243 1244 static inline void 1245 svm_htlb_flush_ack(struct svm_cpudata *cpudata, uint64_t machgen) 1246 { 1247 struct vmcb *vmcb = cpudata->vmcb; 1248 1249 if (__predict_true(vmcb->ctrl.exitcode != VMCB_EXITCODE_INVALID)) { 1250 cpudata->vcpu_htlb_gen = machgen; 1251 } 1252 } 1253 1254 static int 1255 svm_vcpu_run(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 1256 struct nvmm_exit *exit) 1257 { 1258 struct svm_machdata *machdata = mach->machdata; 1259 struct svm_cpudata *cpudata = vcpu->cpudata; 1260 struct vmcb *vmcb = cpudata->vmcb; 1261 uint64_t machgen; 1262 int hcpu, s; 1263 1264 kpreempt_disable(); 1265 hcpu = cpu_number(); 1266 1267 svm_gtlb_catchup(vcpu, hcpu); 1268 svm_htlb_catchup(vcpu, hcpu); 1269 1270 if (vcpu->hcpu_last != hcpu) { 1271 vmcb->ctrl.tsc_offset = cpudata->tsc_offset + 1272 curcpu()->ci_data.cpu_cc_skew; 1273 svm_vmcb_cache_flush_all(vmcb); 1274 } 1275 1276 svm_vcpu_guest_dbregs_enter(vcpu); 1277 svm_vcpu_guest_misc_enter(vcpu); 1278 1279 while (1) { 1280 if (cpudata->gtlb_want_flush) { 1281 vmcb->ctrl.tlb_ctrl = svm_ctrl_tlb_flush; 1282 } else { 1283 vmcb->ctrl.tlb_ctrl = 0; 1284 } 1285 1286 s = splhigh(); 1287 machgen = svm_htlb_flush(machdata, cpudata); 1288 svm_vcpu_guest_fpu_enter(vcpu); 1289 svm_vmrun(cpudata->vmcb_pa, cpudata->gprs); 1290 svm_vcpu_guest_fpu_leave(vcpu); 1291 svm_htlb_flush_ack(cpudata, machgen); 1292 splx(s); 1293 1294 svm_vmcb_cache_default(vmcb); 1295 1296 if (vmcb->ctrl.exitcode != VMCB_EXITCODE_INVALID) { 1297 cpudata->gtlb_want_flush = false; 1298 vcpu->hcpu_last = hcpu; 1299 } 1300 1301 switch (vmcb->ctrl.exitcode) { 1302 case VMCB_EXITCODE_INTR: 1303 case VMCB_EXITCODE_NMI: 1304 exit->reason = NVMM_EXIT_NONE; 1305 break; 1306 case VMCB_EXITCODE_VINTR: 1307 svm_event_waitexit_disable(vcpu, false); 1308 exit->reason = NVMM_EXIT_INT_READY; 1309 break; 1310 case VMCB_EXITCODE_IRET: 1311 svm_event_waitexit_disable(vcpu, true); 1312 exit->reason = NVMM_EXIT_NMI_READY; 1313 break; 1314 case VMCB_EXITCODE_CPUID: 1315 svm_exit_cpuid(mach, vcpu, exit); 1316 break; 1317 case VMCB_EXITCODE_HLT: 1318 svm_exit_hlt(mach, vcpu, exit); 1319 break; 1320 case VMCB_EXITCODE_IOIO: 1321 svm_exit_io(mach, vcpu, exit); 1322 break; 1323 case VMCB_EXITCODE_MSR: 1324 svm_exit_msr(mach, vcpu, exit); 1325 break; 1326 case VMCB_EXITCODE_SHUTDOWN: 1327 exit->reason = NVMM_EXIT_SHUTDOWN; 1328 break; 1329 case VMCB_EXITCODE_RDPMC: 1330 case VMCB_EXITCODE_RSM: 1331 case VMCB_EXITCODE_INVLPGA: 1332 case VMCB_EXITCODE_VMRUN: 1333 case VMCB_EXITCODE_VMMCALL: 1334 case VMCB_EXITCODE_VMLOAD: 1335 case VMCB_EXITCODE_VMSAVE: 1336 case VMCB_EXITCODE_STGI: 1337 case VMCB_EXITCODE_CLGI: 1338 case VMCB_EXITCODE_SKINIT: 1339 case VMCB_EXITCODE_RDTSCP: 1340 svm_inject_ud(mach, vcpu); 1341 exit->reason = NVMM_EXIT_NONE; 1342 break; 1343 case VMCB_EXITCODE_MONITOR: 1344 svm_exit_insn(vmcb, exit, NVMM_EXIT_MONITOR); 1345 break; 1346 case VMCB_EXITCODE_MWAIT: 1347 svm_exit_insn(vmcb, exit, NVMM_EXIT_MWAIT); 1348 break; 1349 case VMCB_EXITCODE_MWAIT_CONDITIONAL: 1350 svm_exit_insn(vmcb, exit, NVMM_EXIT_MWAIT_COND); 1351 break; 1352 case VMCB_EXITCODE_XSETBV: 1353 svm_exit_xsetbv(mach, vcpu, exit); 1354 break; 1355 case VMCB_EXITCODE_NPF: 1356 svm_exit_npf(mach, vcpu, exit); 1357 break; 1358 case VMCB_EXITCODE_FERR_FREEZE: /* ? */ 1359 default: 1360 exit->reason = NVMM_EXIT_INVALID; 1361 break; 1362 } 1363 1364 /* If no reason to return to userland, keep rolling. */ 1365 if (curcpu()->ci_schedstate.spc_flags & SPCF_SHOULDYIELD) { 1366 break; 1367 } 1368 if (curcpu()->ci_data.cpu_softints != 0) { 1369 break; 1370 } 1371 if (curlwp->l_flag & LW_USERRET) { 1372 break; 1373 } 1374 if (exit->reason != NVMM_EXIT_NONE) { 1375 break; 1376 } 1377 } 1378 1379 svm_vcpu_guest_misc_leave(vcpu); 1380 svm_vcpu_guest_dbregs_leave(vcpu); 1381 1382 kpreempt_enable(); 1383 1384 exit->exitstate[NVMM_X64_EXITSTATE_CR8] = __SHIFTOUT(vmcb->ctrl.v, 1385 VMCB_CTRL_V_TPR); 1386 exit->exitstate[NVMM_X64_EXITSTATE_RFLAGS] = vmcb->state.rflags; 1387 1388 exit->exitstate[NVMM_X64_EXITSTATE_INT_SHADOW] = 1389 ((vmcb->ctrl.intr & VMCB_CTRL_INTR_SHADOW) != 0); 1390 exit->exitstate[NVMM_X64_EXITSTATE_INT_WINDOW_EXIT] = 1391 cpudata->int_window_exit; 1392 exit->exitstate[NVMM_X64_EXITSTATE_NMI_WINDOW_EXIT] = 1393 cpudata->nmi_window_exit; 1394 1395 return 0; 1396 } 1397 1398 /* -------------------------------------------------------------------------- */ 1399 1400 static int 1401 svm_memalloc(paddr_t *pa, vaddr_t *va, size_t npages) 1402 { 1403 struct pglist pglist; 1404 paddr_t _pa; 1405 vaddr_t _va; 1406 size_t i; 1407 int ret; 1408 1409 ret = uvm_pglistalloc(npages * PAGE_SIZE, 0, ~0UL, PAGE_SIZE, 0, 1410 &pglist, 1, 0); 1411 if (ret != 0) 1412 return ENOMEM; 1413 _pa = TAILQ_FIRST(&pglist)->phys_addr; 1414 _va = uvm_km_alloc(kernel_map, npages * PAGE_SIZE, 0, 1415 UVM_KMF_VAONLY | UVM_KMF_NOWAIT); 1416 if (_va == 0) 1417 goto error; 1418 1419 for (i = 0; i < npages; i++) { 1420 pmap_kenter_pa(_va + i * PAGE_SIZE, _pa + i * PAGE_SIZE, 1421 VM_PROT_READ | VM_PROT_WRITE, PMAP_WRITE_BACK); 1422 } 1423 pmap_update(pmap_kernel()); 1424 1425 memset((void *)_va, 0, npages * PAGE_SIZE); 1426 1427 *pa = _pa; 1428 *va = _va; 1429 return 0; 1430 1431 error: 1432 for (i = 0; i < npages; i++) { 1433 uvm_pagefree(PHYS_TO_VM_PAGE(_pa + i * PAGE_SIZE)); 1434 } 1435 return ENOMEM; 1436 } 1437 1438 static void 1439 svm_memfree(paddr_t pa, vaddr_t va, size_t npages) 1440 { 1441 size_t i; 1442 1443 pmap_kremove(va, npages * PAGE_SIZE); 1444 pmap_update(pmap_kernel()); 1445 uvm_km_free(kernel_map, va, npages * PAGE_SIZE, UVM_KMF_VAONLY); 1446 for (i = 0; i < npages; i++) { 1447 uvm_pagefree(PHYS_TO_VM_PAGE(pa + i * PAGE_SIZE)); 1448 } 1449 } 1450 1451 /* -------------------------------------------------------------------------- */ 1452 1453 #define SVM_MSRBM_READ __BIT(0) 1454 #define SVM_MSRBM_WRITE __BIT(1) 1455 1456 static void 1457 svm_vcpu_msr_allow(uint8_t *bitmap, uint64_t msr, bool read, bool write) 1458 { 1459 uint64_t byte; 1460 uint8_t bitoff; 1461 1462 if (msr < 0x00002000) { 1463 /* Range 1 */ 1464 byte = ((msr - 0x00000000) >> 2UL) + 0x0000; 1465 } else if (msr >= 0xC0000000 && msr < 0xC0002000) { 1466 /* Range 2 */ 1467 byte = ((msr - 0xC0000000) >> 2UL) + 0x0800; 1468 } else if (msr >= 0xC0010000 && msr < 0xC0012000) { 1469 /* Range 3 */ 1470 byte = ((msr - 0xC0010000) >> 2UL) + 0x1000; 1471 } else { 1472 panic("%s: wrong range", __func__); 1473 } 1474 1475 bitoff = (msr & 0x3) << 1; 1476 1477 if (read) { 1478 bitmap[byte] &= ~(SVM_MSRBM_READ << bitoff); 1479 } 1480 if (write) { 1481 bitmap[byte] &= ~(SVM_MSRBM_WRITE << bitoff); 1482 } 1483 } 1484 1485 #define SVM_SEG_ATTRIB_TYPE __BITS(3,0) 1486 #define SVM_SEG_ATTRIB_S __BIT(4) 1487 #define SVM_SEG_ATTRIB_DPL __BITS(6,5) 1488 #define SVM_SEG_ATTRIB_P __BIT(7) 1489 #define SVM_SEG_ATTRIB_AVL __BIT(8) 1490 #define SVM_SEG_ATTRIB_L __BIT(9) 1491 #define SVM_SEG_ATTRIB_DEF __BIT(10) 1492 #define SVM_SEG_ATTRIB_G __BIT(11) 1493 1494 static void 1495 svm_vcpu_setstate_seg(const struct nvmm_x64_state_seg *seg, 1496 struct vmcb_segment *vseg) 1497 { 1498 vseg->selector = seg->selector; 1499 vseg->attrib = 1500 __SHIFTIN(seg->attrib.type, SVM_SEG_ATTRIB_TYPE) | 1501 __SHIFTIN(seg->attrib.s, SVM_SEG_ATTRIB_S) | 1502 __SHIFTIN(seg->attrib.dpl, SVM_SEG_ATTRIB_DPL) | 1503 __SHIFTIN(seg->attrib.p, SVM_SEG_ATTRIB_P) | 1504 __SHIFTIN(seg->attrib.avl, SVM_SEG_ATTRIB_AVL) | 1505 __SHIFTIN(seg->attrib.l, SVM_SEG_ATTRIB_L) | 1506 __SHIFTIN(seg->attrib.def, SVM_SEG_ATTRIB_DEF) | 1507 __SHIFTIN(seg->attrib.g, SVM_SEG_ATTRIB_G); 1508 vseg->limit = seg->limit; 1509 vseg->base = seg->base; 1510 } 1511 1512 static void 1513 svm_vcpu_getstate_seg(struct nvmm_x64_state_seg *seg, struct vmcb_segment *vseg) 1514 { 1515 seg->selector = vseg->selector; 1516 seg->attrib.type = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_TYPE); 1517 seg->attrib.s = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_S); 1518 seg->attrib.dpl = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_DPL); 1519 seg->attrib.p = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_P); 1520 seg->attrib.avl = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_AVL); 1521 seg->attrib.l = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_L); 1522 seg->attrib.def = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_DEF); 1523 seg->attrib.g = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_G); 1524 seg->limit = vseg->limit; 1525 seg->base = vseg->base; 1526 } 1527 1528 static inline bool 1529 svm_state_tlb_flush(const struct vmcb *vmcb, const struct nvmm_x64_state *state, 1530 uint64_t flags) 1531 { 1532 if (flags & NVMM_X64_STATE_CRS) { 1533 if ((vmcb->state.cr0 ^ 1534 state->crs[NVMM_X64_CR_CR0]) & CR0_TLB_FLUSH) { 1535 return true; 1536 } 1537 if (vmcb->state.cr3 != state->crs[NVMM_X64_CR_CR3]) { 1538 return true; 1539 } 1540 if ((vmcb->state.cr4 ^ 1541 state->crs[NVMM_X64_CR_CR4]) & CR4_TLB_FLUSH) { 1542 return true; 1543 } 1544 } 1545 1546 if (flags & NVMM_X64_STATE_MSRS) { 1547 if ((vmcb->state.efer ^ 1548 state->msrs[NVMM_X64_MSR_EFER]) & EFER_TLB_FLUSH) { 1549 return true; 1550 } 1551 } 1552 1553 return false; 1554 } 1555 1556 static void 1557 svm_vcpu_setstate(struct nvmm_cpu *vcpu, const void *data, uint64_t flags) 1558 { 1559 const struct nvmm_x64_state *state = data; 1560 struct svm_cpudata *cpudata = vcpu->cpudata; 1561 struct vmcb *vmcb = cpudata->vmcb; 1562 struct fxsave *fpustate; 1563 1564 if (svm_state_tlb_flush(vmcb, state, flags)) { 1565 cpudata->gtlb_want_flush = true; 1566 } 1567 1568 if (flags & NVMM_X64_STATE_SEGS) { 1569 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_CS], 1570 &vmcb->state.cs); 1571 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_DS], 1572 &vmcb->state.ds); 1573 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_ES], 1574 &vmcb->state.es); 1575 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_FS], 1576 &vmcb->state.fs); 1577 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_GS], 1578 &vmcb->state.gs); 1579 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_SS], 1580 &vmcb->state.ss); 1581 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_GDT], 1582 &vmcb->state.gdt); 1583 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_IDT], 1584 &vmcb->state.idt); 1585 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_LDT], 1586 &vmcb->state.ldt); 1587 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_TR], 1588 &vmcb->state.tr); 1589 1590 vmcb->state.cpl = state->segs[NVMM_X64_SEG_SS].attrib.dpl; 1591 } 1592 1593 CTASSERT(sizeof(cpudata->gprs) == sizeof(state->gprs)); 1594 if (flags & NVMM_X64_STATE_GPRS) { 1595 memcpy(cpudata->gprs, state->gprs, sizeof(state->gprs)); 1596 1597 vmcb->state.rip = state->gprs[NVMM_X64_GPR_RIP]; 1598 vmcb->state.rsp = state->gprs[NVMM_X64_GPR_RSP]; 1599 vmcb->state.rax = state->gprs[NVMM_X64_GPR_RAX]; 1600 vmcb->state.rflags = state->gprs[NVMM_X64_GPR_RFLAGS]; 1601 } 1602 1603 if (flags & NVMM_X64_STATE_CRS) { 1604 vmcb->state.cr0 = state->crs[NVMM_X64_CR_CR0]; 1605 vmcb->state.cr2 = state->crs[NVMM_X64_CR_CR2]; 1606 vmcb->state.cr3 = state->crs[NVMM_X64_CR_CR3]; 1607 vmcb->state.cr4 = state->crs[NVMM_X64_CR_CR4]; 1608 1609 vmcb->ctrl.v &= ~VMCB_CTRL_V_TPR; 1610 vmcb->ctrl.v |= __SHIFTIN(state->crs[NVMM_X64_CR_CR8], 1611 VMCB_CTRL_V_TPR); 1612 1613 if (svm_xcr0_mask != 0) { 1614 /* Clear illegal XCR0 bits, set mandatory X87 bit. */ 1615 cpudata->gxcr0 = state->crs[NVMM_X64_CR_XCR0]; 1616 cpudata->gxcr0 &= svm_xcr0_mask; 1617 cpudata->gxcr0 |= XCR0_X87; 1618 } 1619 } 1620 1621 CTASSERT(sizeof(cpudata->drs) == sizeof(state->drs)); 1622 if (flags & NVMM_X64_STATE_DRS) { 1623 memcpy(cpudata->drs, state->drs, sizeof(state->drs)); 1624 1625 vmcb->state.dr6 = state->drs[NVMM_X64_DR_DR6]; 1626 vmcb->state.dr7 = state->drs[NVMM_X64_DR_DR7]; 1627 } 1628 1629 if (flags & NVMM_X64_STATE_MSRS) { 1630 /* 1631 * EFER_SVME is mandatory. 1632 */ 1633 vmcb->state.efer = state->msrs[NVMM_X64_MSR_EFER] | EFER_SVME; 1634 vmcb->state.star = state->msrs[NVMM_X64_MSR_STAR]; 1635 vmcb->state.lstar = state->msrs[NVMM_X64_MSR_LSTAR]; 1636 vmcb->state.cstar = state->msrs[NVMM_X64_MSR_CSTAR]; 1637 vmcb->state.sfmask = state->msrs[NVMM_X64_MSR_SFMASK]; 1638 vmcb->state.kernelgsbase = 1639 state->msrs[NVMM_X64_MSR_KERNELGSBASE]; 1640 vmcb->state.sysenter_cs = 1641 state->msrs[NVMM_X64_MSR_SYSENTER_CS]; 1642 vmcb->state.sysenter_esp = 1643 state->msrs[NVMM_X64_MSR_SYSENTER_ESP]; 1644 vmcb->state.sysenter_eip = 1645 state->msrs[NVMM_X64_MSR_SYSENTER_EIP]; 1646 vmcb->state.g_pat = state->msrs[NVMM_X64_MSR_PAT]; 1647 } 1648 1649 if (flags & NVMM_X64_STATE_MISC) { 1650 if (state->misc[NVMM_X64_MISC_INT_SHADOW]) { 1651 vmcb->ctrl.intr |= VMCB_CTRL_INTR_SHADOW; 1652 } else { 1653 vmcb->ctrl.intr &= ~VMCB_CTRL_INTR_SHADOW; 1654 } 1655 1656 if (state->misc[NVMM_X64_MISC_INT_WINDOW_EXIT]) { 1657 svm_event_waitexit_enable(vcpu, false); 1658 } else { 1659 svm_event_waitexit_disable(vcpu, false); 1660 } 1661 1662 if (state->misc[NVMM_X64_MISC_NMI_WINDOW_EXIT]) { 1663 svm_event_waitexit_enable(vcpu, true); 1664 } else { 1665 svm_event_waitexit_disable(vcpu, true); 1666 } 1667 } 1668 1669 CTASSERT(sizeof(cpudata->gfpu.xsh_fxsave) == sizeof(state->fpu)); 1670 if (flags & NVMM_X64_STATE_FPU) { 1671 memcpy(cpudata->gfpu.xsh_fxsave, &state->fpu, 1672 sizeof(state->fpu)); 1673 1674 fpustate = (struct fxsave *)cpudata->gfpu.xsh_fxsave; 1675 fpustate->fx_mxcsr_mask &= x86_fpu_mxcsr_mask; 1676 fpustate->fx_mxcsr &= fpustate->fx_mxcsr_mask; 1677 1678 if (svm_xcr0_mask != 0) { 1679 /* Reset XSTATE_BV, to force a reload. */ 1680 cpudata->gfpu.xsh_xstate_bv = svm_xcr0_mask; 1681 } 1682 } 1683 1684 svm_vmcb_cache_update(vmcb, flags); 1685 } 1686 1687 static void 1688 svm_vcpu_getstate(struct nvmm_cpu *vcpu, void *data, uint64_t flags) 1689 { 1690 struct nvmm_x64_state *state = (struct nvmm_x64_state *)data; 1691 struct svm_cpudata *cpudata = vcpu->cpudata; 1692 struct vmcb *vmcb = cpudata->vmcb; 1693 1694 if (flags & NVMM_X64_STATE_SEGS) { 1695 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_CS], 1696 &vmcb->state.cs); 1697 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_DS], 1698 &vmcb->state.ds); 1699 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_ES], 1700 &vmcb->state.es); 1701 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_FS], 1702 &vmcb->state.fs); 1703 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_GS], 1704 &vmcb->state.gs); 1705 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_SS], 1706 &vmcb->state.ss); 1707 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_GDT], 1708 &vmcb->state.gdt); 1709 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_IDT], 1710 &vmcb->state.idt); 1711 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_LDT], 1712 &vmcb->state.ldt); 1713 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_TR], 1714 &vmcb->state.tr); 1715 1716 state->segs[NVMM_X64_SEG_SS].attrib.dpl = vmcb->state.cpl; 1717 } 1718 1719 CTASSERT(sizeof(cpudata->gprs) == sizeof(state->gprs)); 1720 if (flags & NVMM_X64_STATE_GPRS) { 1721 memcpy(state->gprs, cpudata->gprs, sizeof(state->gprs)); 1722 1723 state->gprs[NVMM_X64_GPR_RIP] = vmcb->state.rip; 1724 state->gprs[NVMM_X64_GPR_RSP] = vmcb->state.rsp; 1725 state->gprs[NVMM_X64_GPR_RAX] = vmcb->state.rax; 1726 state->gprs[NVMM_X64_GPR_RFLAGS] = vmcb->state.rflags; 1727 } 1728 1729 if (flags & NVMM_X64_STATE_CRS) { 1730 state->crs[NVMM_X64_CR_CR0] = vmcb->state.cr0; 1731 state->crs[NVMM_X64_CR_CR2] = vmcb->state.cr2; 1732 state->crs[NVMM_X64_CR_CR3] = vmcb->state.cr3; 1733 state->crs[NVMM_X64_CR_CR4] = vmcb->state.cr4; 1734 state->crs[NVMM_X64_CR_CR8] = __SHIFTOUT(vmcb->ctrl.v, 1735 VMCB_CTRL_V_TPR); 1736 state->crs[NVMM_X64_CR_XCR0] = cpudata->gxcr0; 1737 } 1738 1739 CTASSERT(sizeof(cpudata->drs) == sizeof(state->drs)); 1740 if (flags & NVMM_X64_STATE_DRS) { 1741 memcpy(state->drs, cpudata->drs, sizeof(state->drs)); 1742 1743 state->drs[NVMM_X64_DR_DR6] = vmcb->state.dr6; 1744 state->drs[NVMM_X64_DR_DR7] = vmcb->state.dr7; 1745 } 1746 1747 if (flags & NVMM_X64_STATE_MSRS) { 1748 state->msrs[NVMM_X64_MSR_EFER] = vmcb->state.efer; 1749 state->msrs[NVMM_X64_MSR_STAR] = vmcb->state.star; 1750 state->msrs[NVMM_X64_MSR_LSTAR] = vmcb->state.lstar; 1751 state->msrs[NVMM_X64_MSR_CSTAR] = vmcb->state.cstar; 1752 state->msrs[NVMM_X64_MSR_SFMASK] = vmcb->state.sfmask; 1753 state->msrs[NVMM_X64_MSR_KERNELGSBASE] = 1754 vmcb->state.kernelgsbase; 1755 state->msrs[NVMM_X64_MSR_SYSENTER_CS] = 1756 vmcb->state.sysenter_cs; 1757 state->msrs[NVMM_X64_MSR_SYSENTER_ESP] = 1758 vmcb->state.sysenter_esp; 1759 state->msrs[NVMM_X64_MSR_SYSENTER_EIP] = 1760 vmcb->state.sysenter_eip; 1761 state->msrs[NVMM_X64_MSR_PAT] = vmcb->state.g_pat; 1762 1763 /* Hide SVME. */ 1764 state->msrs[NVMM_X64_MSR_EFER] &= ~EFER_SVME; 1765 } 1766 1767 if (flags & NVMM_X64_STATE_MISC) { 1768 state->misc[NVMM_X64_MISC_INT_SHADOW] = 1769 (vmcb->ctrl.intr & VMCB_CTRL_INTR_SHADOW) != 0; 1770 state->misc[NVMM_X64_MISC_INT_WINDOW_EXIT] = 1771 cpudata->int_window_exit; 1772 state->misc[NVMM_X64_MISC_NMI_WINDOW_EXIT] = 1773 cpudata->nmi_window_exit; 1774 } 1775 1776 CTASSERT(sizeof(cpudata->gfpu.xsh_fxsave) == sizeof(state->fpu)); 1777 if (flags & NVMM_X64_STATE_FPU) { 1778 memcpy(&state->fpu, cpudata->gfpu.xsh_fxsave, 1779 sizeof(state->fpu)); 1780 } 1781 } 1782 1783 /* -------------------------------------------------------------------------- */ 1784 1785 static void 1786 svm_asid_alloc(struct nvmm_cpu *vcpu) 1787 { 1788 struct svm_cpudata *cpudata = vcpu->cpudata; 1789 struct vmcb *vmcb = cpudata->vmcb; 1790 size_t i, oct, bit; 1791 1792 mutex_enter(&svm_asidlock); 1793 1794 for (i = 0; i < svm_maxasid; i++) { 1795 oct = i / 8; 1796 bit = i % 8; 1797 1798 if (svm_asidmap[oct] & __BIT(bit)) { 1799 continue; 1800 } 1801 1802 svm_asidmap[oct] |= __BIT(bit); 1803 vmcb->ctrl.guest_asid = i; 1804 mutex_exit(&svm_asidlock); 1805 return; 1806 } 1807 1808 /* 1809 * No free ASID. Use the last one, which is shared and requires 1810 * special TLB handling. 1811 */ 1812 cpudata->shared_asid = true; 1813 vmcb->ctrl.guest_asid = svm_maxasid - 1; 1814 mutex_exit(&svm_asidlock); 1815 } 1816 1817 static void 1818 svm_asid_free(struct nvmm_cpu *vcpu) 1819 { 1820 struct svm_cpudata *cpudata = vcpu->cpudata; 1821 struct vmcb *vmcb = cpudata->vmcb; 1822 size_t oct, bit; 1823 1824 if (cpudata->shared_asid) { 1825 return; 1826 } 1827 1828 oct = vmcb->ctrl.guest_asid / 8; 1829 bit = vmcb->ctrl.guest_asid % 8; 1830 1831 mutex_enter(&svm_asidlock); 1832 svm_asidmap[oct] &= ~__BIT(bit); 1833 mutex_exit(&svm_asidlock); 1834 } 1835 1836 static void 1837 svm_vcpu_init(struct nvmm_machine *mach, struct nvmm_cpu *vcpu) 1838 { 1839 struct svm_cpudata *cpudata = vcpu->cpudata; 1840 struct vmcb *vmcb = cpudata->vmcb; 1841 1842 /* Allow reads/writes of Control Registers. */ 1843 vmcb->ctrl.intercept_cr = 0; 1844 1845 /* Allow reads/writes of Debug Registers. */ 1846 vmcb->ctrl.intercept_dr = 0; 1847 1848 /* Allow exceptions 0 to 31. */ 1849 vmcb->ctrl.intercept_vec = 0; 1850 1851 /* 1852 * Allow: 1853 * - SMI [smm interrupts] 1854 * - VINTR [virtual interrupts] 1855 * - CR0_SPEC [CR0 writes changing other fields than CR0.TS or CR0.MP] 1856 * - RIDTR [reads of IDTR] 1857 * - RGDTR [reads of GDTR] 1858 * - RLDTR [reads of LDTR] 1859 * - RTR [reads of TR] 1860 * - WIDTR [writes of IDTR] 1861 * - WGDTR [writes of GDTR] 1862 * - WLDTR [writes of LDTR] 1863 * - WTR [writes of TR] 1864 * - RDTSC [rdtsc instruction] 1865 * - PUSHF [pushf instruction] 1866 * - POPF [popf instruction] 1867 * - IRET [iret instruction] 1868 * - INTN [int $n instructions] 1869 * - INVD [invd instruction] 1870 * - PAUSE [pause instruction] 1871 * - INVLPG [invplg instruction] 1872 * - TASKSW [task switches] 1873 * 1874 * Intercept the rest below. 1875 */ 1876 vmcb->ctrl.intercept_misc1 = 1877 VMCB_CTRL_INTERCEPT_INTR | 1878 VMCB_CTRL_INTERCEPT_NMI | 1879 VMCB_CTRL_INTERCEPT_INIT | 1880 VMCB_CTRL_INTERCEPT_RDPMC | 1881 VMCB_CTRL_INTERCEPT_CPUID | 1882 VMCB_CTRL_INTERCEPT_RSM | 1883 VMCB_CTRL_INTERCEPT_HLT | 1884 VMCB_CTRL_INTERCEPT_INVLPGA | 1885 VMCB_CTRL_INTERCEPT_IOIO_PROT | 1886 VMCB_CTRL_INTERCEPT_MSR_PROT | 1887 VMCB_CTRL_INTERCEPT_FERR_FREEZE | 1888 VMCB_CTRL_INTERCEPT_SHUTDOWN; 1889 1890 /* 1891 * Allow: 1892 * - ICEBP [icebp instruction] 1893 * - WBINVD [wbinvd instruction] 1894 * - WCR_SPEC(0..15) [writes of CR0-15, received after instruction] 1895 * 1896 * Intercept the rest below. 1897 */ 1898 vmcb->ctrl.intercept_misc2 = 1899 VMCB_CTRL_INTERCEPT_VMRUN | 1900 VMCB_CTRL_INTERCEPT_VMMCALL | 1901 VMCB_CTRL_INTERCEPT_VMLOAD | 1902 VMCB_CTRL_INTERCEPT_VMSAVE | 1903 VMCB_CTRL_INTERCEPT_STGI | 1904 VMCB_CTRL_INTERCEPT_CLGI | 1905 VMCB_CTRL_INTERCEPT_SKINIT | 1906 VMCB_CTRL_INTERCEPT_RDTSCP | 1907 VMCB_CTRL_INTERCEPT_MONITOR | 1908 VMCB_CTRL_INTERCEPT_MWAIT | 1909 VMCB_CTRL_INTERCEPT_XSETBV; 1910 1911 /* Intercept all I/O accesses. */ 1912 memset(cpudata->iobm, 0xFF, IOBM_SIZE); 1913 vmcb->ctrl.iopm_base_pa = cpudata->iobm_pa; 1914 1915 /* Allow direct access to certain MSRs. */ 1916 memset(cpudata->msrbm, 0xFF, MSRBM_SIZE); 1917 svm_vcpu_msr_allow(cpudata->msrbm, MSR_EFER, true, false); 1918 svm_vcpu_msr_allow(cpudata->msrbm, MSR_STAR, true, true); 1919 svm_vcpu_msr_allow(cpudata->msrbm, MSR_LSTAR, true, true); 1920 svm_vcpu_msr_allow(cpudata->msrbm, MSR_CSTAR, true, true); 1921 svm_vcpu_msr_allow(cpudata->msrbm, MSR_SFMASK, true, true); 1922 svm_vcpu_msr_allow(cpudata->msrbm, MSR_KERNELGSBASE, true, true); 1923 svm_vcpu_msr_allow(cpudata->msrbm, MSR_SYSENTER_CS, true, true); 1924 svm_vcpu_msr_allow(cpudata->msrbm, MSR_SYSENTER_ESP, true, true); 1925 svm_vcpu_msr_allow(cpudata->msrbm, MSR_SYSENTER_EIP, true, true); 1926 svm_vcpu_msr_allow(cpudata->msrbm, MSR_FSBASE, true, true); 1927 svm_vcpu_msr_allow(cpudata->msrbm, MSR_GSBASE, true, true); 1928 svm_vcpu_msr_allow(cpudata->msrbm, MSR_CR_PAT, true, true); 1929 svm_vcpu_msr_allow(cpudata->msrbm, MSR_TSC, true, false); 1930 vmcb->ctrl.msrpm_base_pa = cpudata->msrbm_pa; 1931 1932 /* Generate ASID. */ 1933 svm_asid_alloc(vcpu); 1934 1935 /* Virtual TPR. */ 1936 vmcb->ctrl.v = VMCB_CTRL_V_INTR_MASKING; 1937 1938 /* Enable Nested Paging. */ 1939 vmcb->ctrl.enable1 = VMCB_CTRL_ENABLE_NP; 1940 vmcb->ctrl.n_cr3 = mach->vm->vm_map.pmap->pm_pdirpa[0]; 1941 1942 /* Init XSAVE header. */ 1943 cpudata->gfpu.xsh_xstate_bv = svm_xcr0_mask; 1944 cpudata->gfpu.xsh_xcomp_bv = 0; 1945 1946 /* Set guest TSC to zero, more or less. */ 1947 cpudata->tsc_offset = -cpu_counter(); 1948 1949 /* These MSRs are static. */ 1950 cpudata->star = rdmsr(MSR_STAR); 1951 cpudata->lstar = rdmsr(MSR_LSTAR); 1952 cpudata->cstar = rdmsr(MSR_CSTAR); 1953 cpudata->sfmask = rdmsr(MSR_SFMASK); 1954 1955 /* Install the RESET state. */ 1956 svm_vcpu_setstate(vcpu, &nvmm_x86_reset_state, NVMM_X64_STATE_ALL); 1957 } 1958 1959 static int 1960 svm_vcpu_create(struct nvmm_machine *mach, struct nvmm_cpu *vcpu) 1961 { 1962 struct svm_cpudata *cpudata; 1963 int error; 1964 1965 /* Allocate the SVM cpudata. */ 1966 cpudata = (struct svm_cpudata *)uvm_km_alloc(kernel_map, 1967 roundup(sizeof(*cpudata), PAGE_SIZE), 0, 1968 UVM_KMF_WIRED|UVM_KMF_ZERO); 1969 vcpu->cpudata = cpudata; 1970 1971 /* VMCB */ 1972 error = svm_memalloc(&cpudata->vmcb_pa, (vaddr_t *)&cpudata->vmcb, 1973 VMCB_NPAGES); 1974 if (error) 1975 goto error; 1976 1977 /* I/O Bitmap */ 1978 error = svm_memalloc(&cpudata->iobm_pa, (vaddr_t *)&cpudata->iobm, 1979 IOBM_NPAGES); 1980 if (error) 1981 goto error; 1982 1983 /* MSR Bitmap */ 1984 error = svm_memalloc(&cpudata->msrbm_pa, (vaddr_t *)&cpudata->msrbm, 1985 MSRBM_NPAGES); 1986 if (error) 1987 goto error; 1988 1989 /* Init the VCPU info. */ 1990 svm_vcpu_init(mach, vcpu); 1991 1992 return 0; 1993 1994 error: 1995 if (cpudata->vmcb_pa) { 1996 svm_memfree(cpudata->vmcb_pa, (vaddr_t)cpudata->vmcb, 1997 VMCB_NPAGES); 1998 } 1999 if (cpudata->iobm_pa) { 2000 svm_memfree(cpudata->iobm_pa, (vaddr_t)cpudata->iobm, 2001 IOBM_NPAGES); 2002 } 2003 if (cpudata->msrbm_pa) { 2004 svm_memfree(cpudata->msrbm_pa, (vaddr_t)cpudata->msrbm, 2005 MSRBM_NPAGES); 2006 } 2007 uvm_km_free(kernel_map, (vaddr_t)cpudata, 2008 roundup(sizeof(*cpudata), PAGE_SIZE), UVM_KMF_WIRED); 2009 return error; 2010 } 2011 2012 static void 2013 svm_vcpu_destroy(struct nvmm_machine *mach, struct nvmm_cpu *vcpu) 2014 { 2015 struct svm_cpudata *cpudata = vcpu->cpudata; 2016 2017 svm_asid_free(vcpu); 2018 2019 svm_memfree(cpudata->vmcb_pa, (vaddr_t)cpudata->vmcb, VMCB_NPAGES); 2020 svm_memfree(cpudata->iobm_pa, (vaddr_t)cpudata->iobm, IOBM_NPAGES); 2021 svm_memfree(cpudata->msrbm_pa, (vaddr_t)cpudata->msrbm, MSRBM_NPAGES); 2022 2023 uvm_km_free(kernel_map, (vaddr_t)cpudata, 2024 roundup(sizeof(*cpudata), PAGE_SIZE), UVM_KMF_WIRED); 2025 } 2026 2027 /* -------------------------------------------------------------------------- */ 2028 2029 static void 2030 svm_tlb_flush(struct pmap *pm) 2031 { 2032 struct nvmm_machine *mach = pm->pm_data; 2033 struct svm_machdata *machdata = mach->machdata; 2034 2035 atomic_inc_64(&machdata->mach_htlb_gen); 2036 2037 /* Generates IPIs, which cause #VMEXITs. */ 2038 pmap_tlb_shootdown(pmap_kernel(), -1, PG_G, TLBSHOOT_UPDATE); 2039 } 2040 2041 static void 2042 svm_machine_create(struct nvmm_machine *mach) 2043 { 2044 struct svm_machdata *machdata; 2045 2046 /* Fill in pmap info. */ 2047 mach->vm->vm_map.pmap->pm_data = (void *)mach; 2048 mach->vm->vm_map.pmap->pm_tlb_flush = svm_tlb_flush; 2049 2050 machdata = kmem_zalloc(sizeof(struct svm_machdata), KM_SLEEP); 2051 mach->machdata = machdata; 2052 2053 /* Start with an hTLB flush everywhere. */ 2054 machdata->mach_htlb_gen = 1; 2055 } 2056 2057 static void 2058 svm_machine_destroy(struct nvmm_machine *mach) 2059 { 2060 kmem_free(mach->machdata, sizeof(struct svm_machdata)); 2061 } 2062 2063 static int 2064 svm_machine_configure(struct nvmm_machine *mach, uint64_t op, void *data) 2065 { 2066 struct nvmm_x86_conf_cpuid *cpuid = data; 2067 struct svm_machdata *machdata = (struct svm_machdata *)mach->machdata; 2068 size_t i; 2069 2070 if (__predict_false(op != NVMM_X86_CONF_CPUID)) { 2071 return EINVAL; 2072 } 2073 2074 if (__predict_false((cpuid->set.eax & cpuid->del.eax) || 2075 (cpuid->set.ebx & cpuid->del.ebx) || 2076 (cpuid->set.ecx & cpuid->del.ecx) || 2077 (cpuid->set.edx & cpuid->del.edx))) { 2078 return EINVAL; 2079 } 2080 2081 /* If already here, replace. */ 2082 for (i = 0; i < SVM_NCPUIDS; i++) { 2083 if (!machdata->cpuidpresent[i]) { 2084 continue; 2085 } 2086 if (machdata->cpuid[i].leaf == cpuid->leaf) { 2087 memcpy(&machdata->cpuid[i], cpuid, 2088 sizeof(struct nvmm_x86_conf_cpuid)); 2089 return 0; 2090 } 2091 } 2092 2093 /* Not here, insert. */ 2094 for (i = 0; i < SVM_NCPUIDS; i++) { 2095 if (!machdata->cpuidpresent[i]) { 2096 machdata->cpuidpresent[i] = true; 2097 memcpy(&machdata->cpuid[i], cpuid, 2098 sizeof(struct nvmm_x86_conf_cpuid)); 2099 return 0; 2100 } 2101 } 2102 2103 return ENOBUFS; 2104 } 2105 2106 /* -------------------------------------------------------------------------- */ 2107 2108 static bool 2109 svm_ident(void) 2110 { 2111 u_int descs[4]; 2112 uint64_t msr; 2113 2114 if (cpu_vendor != CPUVENDOR_AMD) { 2115 return false; 2116 } 2117 if (!(cpu_feature[3] & CPUID_SVM)) { 2118 return false; 2119 } 2120 2121 if (curcpu()->ci_max_ext_cpuid < 0x8000000a) { 2122 return false; 2123 } 2124 x86_cpuid(0x8000000a, descs); 2125 2126 /* Want Nested Paging. */ 2127 if (!(descs[3] & CPUID_AMD_SVM_NP)) { 2128 return false; 2129 } 2130 2131 /* Want nRIP. */ 2132 if (!(descs[3] & CPUID_AMD_SVM_NRIPS)) { 2133 return false; 2134 } 2135 2136 svm_decode_assist = (descs[3] & CPUID_AMD_SVM_DecodeAssist) != 0; 2137 2138 msr = rdmsr(MSR_VMCR); 2139 if ((msr & VMCR_SVMED) && (msr & VMCR_LOCK)) { 2140 return false; 2141 } 2142 2143 return true; 2144 } 2145 2146 static void 2147 svm_init_asid(uint32_t maxasid) 2148 { 2149 size_t i, j, allocsz; 2150 2151 mutex_init(&svm_asidlock, MUTEX_DEFAULT, IPL_NONE); 2152 2153 /* Arbitrarily limit. */ 2154 maxasid = uimin(maxasid, 8192); 2155 2156 svm_maxasid = maxasid; 2157 allocsz = roundup(maxasid, 8) / 8; 2158 svm_asidmap = kmem_zalloc(allocsz, KM_SLEEP); 2159 2160 /* ASID 0 is reserved for the host. */ 2161 svm_asidmap[0] |= __BIT(0); 2162 2163 /* ASID n-1 is special, we share it. */ 2164 i = (maxasid - 1) / 8; 2165 j = (maxasid - 1) % 8; 2166 svm_asidmap[i] |= __BIT(j); 2167 } 2168 2169 static void 2170 svm_change_cpu(void *arg1, void *arg2) 2171 { 2172 bool enable = (bool)arg1; 2173 uint64_t msr; 2174 2175 msr = rdmsr(MSR_VMCR); 2176 if (msr & VMCR_SVMED) { 2177 wrmsr(MSR_VMCR, msr & ~VMCR_SVMED); 2178 } 2179 2180 if (!enable) { 2181 wrmsr(MSR_VM_HSAVE_PA, 0); 2182 } 2183 2184 msr = rdmsr(MSR_EFER); 2185 if (enable) { 2186 msr |= EFER_SVME; 2187 } else { 2188 msr &= ~EFER_SVME; 2189 } 2190 wrmsr(MSR_EFER, msr); 2191 2192 if (enable) { 2193 wrmsr(MSR_VM_HSAVE_PA, hsave[cpu_index(curcpu())].pa); 2194 } 2195 } 2196 2197 static void 2198 svm_init(void) 2199 { 2200 CPU_INFO_ITERATOR cii; 2201 struct cpu_info *ci; 2202 struct vm_page *pg; 2203 u_int descs[4]; 2204 uint64_t xc; 2205 2206 x86_cpuid(0x8000000a, descs); 2207 2208 /* The guest TLB flush command. */ 2209 if (descs[3] & CPUID_AMD_SVM_FlushByASID) { 2210 svm_ctrl_tlb_flush = VMCB_CTRL_TLB_CTRL_FLUSH_GUEST; 2211 } else { 2212 svm_ctrl_tlb_flush = VMCB_CTRL_TLB_CTRL_FLUSH_ALL; 2213 } 2214 2215 /* Init the ASID. */ 2216 svm_init_asid(descs[1]); 2217 2218 /* Init the XCR0 mask. */ 2219 svm_xcr0_mask = SVM_XCR0_MASK_DEFAULT & x86_xsave_features; 2220 2221 memset(hsave, 0, sizeof(hsave)); 2222 for (CPU_INFO_FOREACH(cii, ci)) { 2223 pg = uvm_pagealloc(NULL, 0, NULL, UVM_PGA_ZERO); 2224 hsave[cpu_index(ci)].pa = VM_PAGE_TO_PHYS(pg); 2225 } 2226 2227 xc = xc_broadcast(0, svm_change_cpu, (void *)true, NULL); 2228 xc_wait(xc); 2229 } 2230 2231 static void 2232 svm_fini_asid(void) 2233 { 2234 size_t allocsz; 2235 2236 allocsz = roundup(svm_maxasid, 8) / 8; 2237 kmem_free(svm_asidmap, allocsz); 2238 2239 mutex_destroy(&svm_asidlock); 2240 } 2241 2242 static void 2243 svm_fini(void) 2244 { 2245 uint64_t xc; 2246 size_t i; 2247 2248 xc = xc_broadcast(0, svm_change_cpu, (void *)false, NULL); 2249 xc_wait(xc); 2250 2251 for (i = 0; i < MAXCPUS; i++) { 2252 if (hsave[i].pa != 0) 2253 uvm_pagefree(PHYS_TO_VM_PAGE(hsave[i].pa)); 2254 } 2255 2256 svm_fini_asid(); 2257 } 2258 2259 static void 2260 svm_capability(struct nvmm_capability *cap) 2261 { 2262 cap->u.x86.xcr0_mask = svm_xcr0_mask; 2263 cap->u.x86.mxcsr_mask = x86_fpu_mxcsr_mask; 2264 cap->u.x86.conf_cpuid_maxops = SVM_NCPUIDS; 2265 } 2266 2267 const struct nvmm_impl nvmm_x86_svm = { 2268 .ident = svm_ident, 2269 .init = svm_init, 2270 .fini = svm_fini, 2271 .capability = svm_capability, 2272 .conf_max = NVMM_X86_NCONF, 2273 .conf_sizes = svm_conf_sizes, 2274 .state_size = sizeof(struct nvmm_x64_state), 2275 .machine_create = svm_machine_create, 2276 .machine_destroy = svm_machine_destroy, 2277 .machine_configure = svm_machine_configure, 2278 .vcpu_create = svm_vcpu_create, 2279 .vcpu_destroy = svm_vcpu_destroy, 2280 .vcpu_setstate = svm_vcpu_setstate, 2281 .vcpu_getstate = svm_vcpu_getstate, 2282 .vcpu_inject = svm_vcpu_inject, 2283 .vcpu_run = svm_vcpu_run 2284 }; 2285
Indexes created Wed Oct 01 15:09:59 GMT 2025