nvmm_x86_svm.c revision 1.41
1 /* $NetBSD: nvmm_x86_svm.c,v 1.41 2019/04/27 09:06:18 maxv Exp $ */ 2 3 /* 4 * Copyright (c) 2018 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Maxime Villard. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: nvmm_x86_svm.c,v 1.41 2019/04/27 09:06:18 maxv Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/kmem.h> 39 #include <sys/cpu.h> 40 #include <sys/xcall.h> 41 #include <sys/mman.h> 42 43 #include <uvm/uvm.h> 44 #include <uvm/uvm_page.h> 45 46 #include <x86/cputypes.h> 47 #include <x86/specialreg.h> 48 #include <x86/pmap.h> 49 #include <x86/dbregs.h> 50 #include <x86/cpu_counter.h> 51 #include <machine/cpuvar.h> 52 53 #include <dev/nvmm/nvmm.h> 54 #include <dev/nvmm/nvmm_internal.h> 55 #include <dev/nvmm/x86/nvmm_x86.h> 56 57 int svm_vmrun(paddr_t, uint64_t *); 58 59 #define MSR_VM_HSAVE_PA 0xC0010117 60 61 /* -------------------------------------------------------------------------- */ 62 63 #define VMCB_EXITCODE_CR0_READ 0x0000 64 #define VMCB_EXITCODE_CR1_READ 0x0001 65 #define VMCB_EXITCODE_CR2_READ 0x0002 66 #define VMCB_EXITCODE_CR3_READ 0x0003 67 #define VMCB_EXITCODE_CR4_READ 0x0004 68 #define VMCB_EXITCODE_CR5_READ 0x0005 69 #define VMCB_EXITCODE_CR6_READ 0x0006 70 #define VMCB_EXITCODE_CR7_READ 0x0007 71 #define VMCB_EXITCODE_CR8_READ 0x0008 72 #define VMCB_EXITCODE_CR9_READ 0x0009 73 #define VMCB_EXITCODE_CR10_READ 0x000A 74 #define VMCB_EXITCODE_CR11_READ 0x000B 75 #define VMCB_EXITCODE_CR12_READ 0x000C 76 #define VMCB_EXITCODE_CR13_READ 0x000D 77 #define VMCB_EXITCODE_CR14_READ 0x000E 78 #define VMCB_EXITCODE_CR15_READ 0x000F 79 #define VMCB_EXITCODE_CR0_WRITE 0x0010 80 #define VMCB_EXITCODE_CR1_WRITE 0x0011 81 #define VMCB_EXITCODE_CR2_WRITE 0x0012 82 #define VMCB_EXITCODE_CR3_WRITE 0x0013 83 #define VMCB_EXITCODE_CR4_WRITE 0x0014 84 #define VMCB_EXITCODE_CR5_WRITE 0x0015 85 #define VMCB_EXITCODE_CR6_WRITE 0x0016 86 #define VMCB_EXITCODE_CR7_WRITE 0x0017 87 #define VMCB_EXITCODE_CR8_WRITE 0x0018 88 #define VMCB_EXITCODE_CR9_WRITE 0x0019 89 #define VMCB_EXITCODE_CR10_WRITE 0x001A 90 #define VMCB_EXITCODE_CR11_WRITE 0x001B 91 #define VMCB_EXITCODE_CR12_WRITE 0x001C 92 #define VMCB_EXITCODE_CR13_WRITE 0x001D 93 #define VMCB_EXITCODE_CR14_WRITE 0x001E 94 #define VMCB_EXITCODE_CR15_WRITE 0x001F 95 #define VMCB_EXITCODE_DR0_READ 0x0020 96 #define VMCB_EXITCODE_DR1_READ 0x0021 97 #define VMCB_EXITCODE_DR2_READ 0x0022 98 #define VMCB_EXITCODE_DR3_READ 0x0023 99 #define VMCB_EXITCODE_DR4_READ 0x0024 100 #define VMCB_EXITCODE_DR5_READ 0x0025 101 #define VMCB_EXITCODE_DR6_READ 0x0026 102 #define VMCB_EXITCODE_DR7_READ 0x0027 103 #define VMCB_EXITCODE_DR8_READ 0x0028 104 #define VMCB_EXITCODE_DR9_READ 0x0029 105 #define VMCB_EXITCODE_DR10_READ 0x002A 106 #define VMCB_EXITCODE_DR11_READ 0x002B 107 #define VMCB_EXITCODE_DR12_READ 0x002C 108 #define VMCB_EXITCODE_DR13_READ 0x002D 109 #define VMCB_EXITCODE_DR14_READ 0x002E 110 #define VMCB_EXITCODE_DR15_READ 0x002F 111 #define VMCB_EXITCODE_DR0_WRITE 0x0030 112 #define VMCB_EXITCODE_DR1_WRITE 0x0031 113 #define VMCB_EXITCODE_DR2_WRITE 0x0032 114 #define VMCB_EXITCODE_DR3_WRITE 0x0033 115 #define VMCB_EXITCODE_DR4_WRITE 0x0034 116 #define VMCB_EXITCODE_DR5_WRITE 0x0035 117 #define VMCB_EXITCODE_DR6_WRITE 0x0036 118 #define VMCB_EXITCODE_DR7_WRITE 0x0037 119 #define VMCB_EXITCODE_DR8_WRITE 0x0038 120 #define VMCB_EXITCODE_DR9_WRITE 0x0039 121 #define VMCB_EXITCODE_DR10_WRITE 0x003A 122 #define VMCB_EXITCODE_DR11_WRITE 0x003B 123 #define VMCB_EXITCODE_DR12_WRITE 0x003C 124 #define VMCB_EXITCODE_DR13_WRITE 0x003D 125 #define VMCB_EXITCODE_DR14_WRITE 0x003E 126 #define VMCB_EXITCODE_DR15_WRITE 0x003F 127 #define VMCB_EXITCODE_EXCP0 0x0040 128 #define VMCB_EXITCODE_EXCP1 0x0041 129 #define VMCB_EXITCODE_EXCP2 0x0042 130 #define VMCB_EXITCODE_EXCP3 0x0043 131 #define VMCB_EXITCODE_EXCP4 0x0044 132 #define VMCB_EXITCODE_EXCP5 0x0045 133 #define VMCB_EXITCODE_EXCP6 0x0046 134 #define VMCB_EXITCODE_EXCP7 0x0047 135 #define VMCB_EXITCODE_EXCP8 0x0048 136 #define VMCB_EXITCODE_EXCP9 0x0049 137 #define VMCB_EXITCODE_EXCP10 0x004A 138 #define VMCB_EXITCODE_EXCP11 0x004B 139 #define VMCB_EXITCODE_EXCP12 0x004C 140 #define VMCB_EXITCODE_EXCP13 0x004D 141 #define VMCB_EXITCODE_EXCP14 0x004E 142 #define VMCB_EXITCODE_EXCP15 0x004F 143 #define VMCB_EXITCODE_EXCP16 0x0050 144 #define VMCB_EXITCODE_EXCP17 0x0051 145 #define VMCB_EXITCODE_EXCP18 0x0052 146 #define VMCB_EXITCODE_EXCP19 0x0053 147 #define VMCB_EXITCODE_EXCP20 0x0054 148 #define VMCB_EXITCODE_EXCP21 0x0055 149 #define VMCB_EXITCODE_EXCP22 0x0056 150 #define VMCB_EXITCODE_EXCP23 0x0057 151 #define VMCB_EXITCODE_EXCP24 0x0058 152 #define VMCB_EXITCODE_EXCP25 0x0059 153 #define VMCB_EXITCODE_EXCP26 0x005A 154 #define VMCB_EXITCODE_EXCP27 0x005B 155 #define VMCB_EXITCODE_EXCP28 0x005C 156 #define VMCB_EXITCODE_EXCP29 0x005D 157 #define VMCB_EXITCODE_EXCP30 0x005E 158 #define VMCB_EXITCODE_EXCP31 0x005F 159 #define VMCB_EXITCODE_INTR 0x0060 160 #define VMCB_EXITCODE_NMI 0x0061 161 #define VMCB_EXITCODE_SMI 0x0062 162 #define VMCB_EXITCODE_INIT 0x0063 163 #define VMCB_EXITCODE_VINTR 0x0064 164 #define VMCB_EXITCODE_CR0_SEL_WRITE 0x0065 165 #define VMCB_EXITCODE_IDTR_READ 0x0066 166 #define VMCB_EXITCODE_GDTR_READ 0x0067 167 #define VMCB_EXITCODE_LDTR_READ 0x0068 168 #define VMCB_EXITCODE_TR_READ 0x0069 169 #define VMCB_EXITCODE_IDTR_WRITE 0x006A 170 #define VMCB_EXITCODE_GDTR_WRITE 0x006B 171 #define VMCB_EXITCODE_LDTR_WRITE 0x006C 172 #define VMCB_EXITCODE_TR_WRITE 0x006D 173 #define VMCB_EXITCODE_RDTSC 0x006E 174 #define VMCB_EXITCODE_RDPMC 0x006F 175 #define VMCB_EXITCODE_PUSHF 0x0070 176 #define VMCB_EXITCODE_POPF 0x0071 177 #define VMCB_EXITCODE_CPUID 0x0072 178 #define VMCB_EXITCODE_RSM 0x0073 179 #define VMCB_EXITCODE_IRET 0x0074 180 #define VMCB_EXITCODE_SWINT 0x0075 181 #define VMCB_EXITCODE_INVD 0x0076 182 #define VMCB_EXITCODE_PAUSE 0x0077 183 #define VMCB_EXITCODE_HLT 0x0078 184 #define VMCB_EXITCODE_INVLPG 0x0079 185 #define VMCB_EXITCODE_INVLPGA 0x007A 186 #define VMCB_EXITCODE_IOIO 0x007B 187 #define VMCB_EXITCODE_MSR 0x007C 188 #define VMCB_EXITCODE_TASK_SWITCH 0x007D 189 #define VMCB_EXITCODE_FERR_FREEZE 0x007E 190 #define VMCB_EXITCODE_SHUTDOWN 0x007F 191 #define VMCB_EXITCODE_VMRUN 0x0080 192 #define VMCB_EXITCODE_VMMCALL 0x0081 193 #define VMCB_EXITCODE_VMLOAD 0x0082 194 #define VMCB_EXITCODE_VMSAVE 0x0083 195 #define VMCB_EXITCODE_STGI 0x0084 196 #define VMCB_EXITCODE_CLGI 0x0085 197 #define VMCB_EXITCODE_SKINIT 0x0086 198 #define VMCB_EXITCODE_RDTSCP 0x0087 199 #define VMCB_EXITCODE_ICEBP 0x0088 200 #define VMCB_EXITCODE_WBINVD 0x0089 201 #define VMCB_EXITCODE_MONITOR 0x008A 202 #define VMCB_EXITCODE_MWAIT 0x008B 203 #define VMCB_EXITCODE_MWAIT_CONDITIONAL 0x008C 204 #define VMCB_EXITCODE_XSETBV 0x008D 205 #define VMCB_EXITCODE_EFER_WRITE_TRAP 0x008F 206 #define VMCB_EXITCODE_CR0_WRITE_TRAP 0x0090 207 #define VMCB_EXITCODE_CR1_WRITE_TRAP 0x0091 208 #define VMCB_EXITCODE_CR2_WRITE_TRAP 0x0092 209 #define VMCB_EXITCODE_CR3_WRITE_TRAP 0x0093 210 #define VMCB_EXITCODE_CR4_WRITE_TRAP 0x0094 211 #define VMCB_EXITCODE_CR5_WRITE_TRAP 0x0095 212 #define VMCB_EXITCODE_CR6_WRITE_TRAP 0x0096 213 #define VMCB_EXITCODE_CR7_WRITE_TRAP 0x0097 214 #define VMCB_EXITCODE_CR8_WRITE_TRAP 0x0098 215 #define VMCB_EXITCODE_CR9_WRITE_TRAP 0x0099 216 #define VMCB_EXITCODE_CR10_WRITE_TRAP 0x009A 217 #define VMCB_EXITCODE_CR11_WRITE_TRAP 0x009B 218 #define VMCB_EXITCODE_CR12_WRITE_TRAP 0x009C 219 #define VMCB_EXITCODE_CR13_WRITE_TRAP 0x009D 220 #define VMCB_EXITCODE_CR14_WRITE_TRAP 0x009E 221 #define VMCB_EXITCODE_CR15_WRITE_TRAP 0x009F 222 #define VMCB_EXITCODE_NPF 0x0400 223 #define VMCB_EXITCODE_AVIC_INCOMP_IPI 0x0401 224 #define VMCB_EXITCODE_AVIC_NOACCEL 0x0402 225 #define VMCB_EXITCODE_VMGEXIT 0x0403 226 #define VMCB_EXITCODE_INVALID -1 227 228 /* -------------------------------------------------------------------------- */ 229 230 struct vmcb_ctrl { 231 uint32_t intercept_cr; 232 #define VMCB_CTRL_INTERCEPT_RCR(x) __BIT( 0 + x) 233 #define VMCB_CTRL_INTERCEPT_WCR(x) __BIT(16 + x) 234 235 uint32_t intercept_dr; 236 #define VMCB_CTRL_INTERCEPT_RDR(x) __BIT( 0 + x) 237 #define VMCB_CTRL_INTERCEPT_WDR(x) __BIT(16 + x) 238 239 uint32_t intercept_vec; 240 #define VMCB_CTRL_INTERCEPT_VEC(x) __BIT(x) 241 242 uint32_t intercept_misc1; 243 #define VMCB_CTRL_INTERCEPT_INTR __BIT(0) 244 #define VMCB_CTRL_INTERCEPT_NMI __BIT(1) 245 #define VMCB_CTRL_INTERCEPT_SMI __BIT(2) 246 #define VMCB_CTRL_INTERCEPT_INIT __BIT(3) 247 #define VMCB_CTRL_INTERCEPT_VINTR __BIT(4) 248 #define VMCB_CTRL_INTERCEPT_CR0_SPEC __BIT(5) 249 #define VMCB_CTRL_INTERCEPT_RIDTR __BIT(6) 250 #define VMCB_CTRL_INTERCEPT_RGDTR __BIT(7) 251 #define VMCB_CTRL_INTERCEPT_RLDTR __BIT(8) 252 #define VMCB_CTRL_INTERCEPT_RTR __BIT(9) 253 #define VMCB_CTRL_INTERCEPT_WIDTR __BIT(10) 254 #define VMCB_CTRL_INTERCEPT_WGDTR __BIT(11) 255 #define VMCB_CTRL_INTERCEPT_WLDTR __BIT(12) 256 #define VMCB_CTRL_INTERCEPT_WTR __BIT(13) 257 #define VMCB_CTRL_INTERCEPT_RDTSC __BIT(14) 258 #define VMCB_CTRL_INTERCEPT_RDPMC __BIT(15) 259 #define VMCB_CTRL_INTERCEPT_PUSHF __BIT(16) 260 #define VMCB_CTRL_INTERCEPT_POPF __BIT(17) 261 #define VMCB_CTRL_INTERCEPT_CPUID __BIT(18) 262 #define VMCB_CTRL_INTERCEPT_RSM __BIT(19) 263 #define VMCB_CTRL_INTERCEPT_IRET __BIT(20) 264 #define VMCB_CTRL_INTERCEPT_INTN __BIT(21) 265 #define VMCB_CTRL_INTERCEPT_INVD __BIT(22) 266 #define VMCB_CTRL_INTERCEPT_PAUSE __BIT(23) 267 #define VMCB_CTRL_INTERCEPT_HLT __BIT(24) 268 #define VMCB_CTRL_INTERCEPT_INVLPG __BIT(25) 269 #define VMCB_CTRL_INTERCEPT_INVLPGA __BIT(26) 270 #define VMCB_CTRL_INTERCEPT_IOIO_PROT __BIT(27) 271 #define VMCB_CTRL_INTERCEPT_MSR_PROT __BIT(28) 272 #define VMCB_CTRL_INTERCEPT_TASKSW __BIT(29) 273 #define VMCB_CTRL_INTERCEPT_FERR_FREEZE __BIT(30) 274 #define VMCB_CTRL_INTERCEPT_SHUTDOWN __BIT(31) 275 276 uint32_t intercept_misc2; 277 #define VMCB_CTRL_INTERCEPT_VMRUN __BIT(0) 278 #define VMCB_CTRL_INTERCEPT_VMMCALL __BIT(1) 279 #define VMCB_CTRL_INTERCEPT_VMLOAD __BIT(2) 280 #define VMCB_CTRL_INTERCEPT_VMSAVE __BIT(3) 281 #define VMCB_CTRL_INTERCEPT_STGI __BIT(4) 282 #define VMCB_CTRL_INTERCEPT_CLGI __BIT(5) 283 #define VMCB_CTRL_INTERCEPT_SKINIT __BIT(6) 284 #define VMCB_CTRL_INTERCEPT_RDTSCP __BIT(7) 285 #define VMCB_CTRL_INTERCEPT_ICEBP __BIT(8) 286 #define VMCB_CTRL_INTERCEPT_WBINVD __BIT(9) 287 #define VMCB_CTRL_INTERCEPT_MONITOR __BIT(10) 288 #define VMCB_CTRL_INTERCEPT_MWAIT __BIT(12) 289 #define VMCB_CTRL_INTERCEPT_XSETBV __BIT(13) 290 #define VMCB_CTRL_INTERCEPT_EFER_SPEC __BIT(15) 291 #define VMCB_CTRL_INTERCEPT_WCR_SPEC(x) __BIT(16 + x) 292 293 uint8_t rsvd1[40]; 294 uint16_t pause_filt_thresh; 295 uint16_t pause_filt_cnt; 296 uint64_t iopm_base_pa; 297 uint64_t msrpm_base_pa; 298 uint64_t tsc_offset; 299 uint32_t guest_asid; 300 301 uint32_t tlb_ctrl; 302 #define VMCB_CTRL_TLB_CTRL_FLUSH_ALL 0x01 303 #define VMCB_CTRL_TLB_CTRL_FLUSH_GUEST 0x03 304 #define VMCB_CTRL_TLB_CTRL_FLUSH_GUEST_NONGLOBAL 0x07 305 306 uint64_t v; 307 #define VMCB_CTRL_V_TPR __BITS(3,0) 308 #define VMCB_CTRL_V_IRQ __BIT(8) 309 #define VMCB_CTRL_V_VGIF __BIT(9) 310 #define VMCB_CTRL_V_INTR_PRIO __BITS(19,16) 311 #define VMCB_CTRL_V_IGN_TPR __BIT(20) 312 #define VMCB_CTRL_V_INTR_MASKING __BIT(24) 313 #define VMCB_CTRL_V_GUEST_VGIF __BIT(25) 314 #define VMCB_CTRL_V_AVIC_EN __BIT(31) 315 #define VMCB_CTRL_V_INTR_VECTOR __BITS(39,32) 316 317 uint64_t intr; 318 #define VMCB_CTRL_INTR_SHADOW __BIT(0) 319 320 uint64_t exitcode; 321 uint64_t exitinfo1; 322 uint64_t exitinfo2; 323 324 uint64_t exitintinfo; 325 #define VMCB_CTRL_EXITINTINFO_VECTOR __BITS(7,0) 326 #define VMCB_CTRL_EXITINTINFO_TYPE __BITS(10,8) 327 #define VMCB_CTRL_EXITINTINFO_EV __BIT(11) 328 #define VMCB_CTRL_EXITINTINFO_V __BIT(31) 329 #define VMCB_CTRL_EXITINTINFO_ERRORCODE __BITS(63,32) 330 331 uint64_t enable1; 332 #define VMCB_CTRL_ENABLE_NP __BIT(0) 333 #define VMCB_CTRL_ENABLE_SEV __BIT(1) 334 #define VMCB_CTRL_ENABLE_ES_SEV __BIT(2) 335 336 uint64_t avic; 337 #define VMCB_CTRL_AVIC_APIC_BAR __BITS(51,0) 338 339 uint64_t ghcb; 340 341 uint64_t eventinj; 342 #define VMCB_CTRL_EVENTINJ_VECTOR __BITS(7,0) 343 #define VMCB_CTRL_EVENTINJ_TYPE __BITS(10,8) 344 #define VMCB_CTRL_EVENTINJ_EV __BIT(11) 345 #define VMCB_CTRL_EVENTINJ_V __BIT(31) 346 #define VMCB_CTRL_EVENTINJ_ERRORCODE __BITS(63,32) 347 348 uint64_t n_cr3; 349 350 uint64_t enable2; 351 #define VMCB_CTRL_ENABLE_LBR __BIT(0) 352 #define VMCB_CTRL_ENABLE_VVMSAVE __BIT(1) 353 354 uint32_t vmcb_clean; 355 #define VMCB_CTRL_VMCB_CLEAN_I __BIT(0) 356 #define VMCB_CTRL_VMCB_CLEAN_IOPM __BIT(1) 357 #define VMCB_CTRL_VMCB_CLEAN_ASID __BIT(2) 358 #define VMCB_CTRL_VMCB_CLEAN_TPR __BIT(3) 359 #define VMCB_CTRL_VMCB_CLEAN_NP __BIT(4) 360 #define VMCB_CTRL_VMCB_CLEAN_CR __BIT(5) 361 #define VMCB_CTRL_VMCB_CLEAN_DR __BIT(6) 362 #define VMCB_CTRL_VMCB_CLEAN_DT __BIT(7) 363 #define VMCB_CTRL_VMCB_CLEAN_SEG __BIT(8) 364 #define VMCB_CTRL_VMCB_CLEAN_CR2 __BIT(9) 365 #define VMCB_CTRL_VMCB_CLEAN_LBR __BIT(10) 366 #define VMCB_CTRL_VMCB_CLEAN_AVIC __BIT(11) 367 368 uint32_t rsvd2; 369 uint64_t nrip; 370 uint8_t inst_len; 371 uint8_t inst_bytes[15]; 372 uint64_t avic_abpp; 373 uint64_t rsvd3; 374 uint64_t avic_ltp; 375 376 uint64_t avic_phys; 377 #define VMCB_CTRL_AVIC_PHYS_TABLE_PTR __BITS(51,12) 378 #define VMCB_CTRL_AVIC_PHYS_MAX_INDEX __BITS(7,0) 379 380 uint64_t rsvd4; 381 uint64_t vmcb_ptr; 382 383 uint8_t pad[752]; 384 } __packed; 385 386 CTASSERT(sizeof(struct vmcb_ctrl) == 1024); 387 388 struct vmcb_segment { 389 uint16_t selector; 390 uint16_t attrib; /* hidden */ 391 uint32_t limit; /* hidden */ 392 uint64_t base; /* hidden */ 393 } __packed; 394 395 CTASSERT(sizeof(struct vmcb_segment) == 16); 396 397 struct vmcb_state { 398 struct vmcb_segment es; 399 struct vmcb_segment cs; 400 struct vmcb_segment ss; 401 struct vmcb_segment ds; 402 struct vmcb_segment fs; 403 struct vmcb_segment gs; 404 struct vmcb_segment gdt; 405 struct vmcb_segment ldt; 406 struct vmcb_segment idt; 407 struct vmcb_segment tr; 408 uint8_t rsvd1[43]; 409 uint8_t cpl; 410 uint8_t rsvd2[4]; 411 uint64_t efer; 412 uint8_t rsvd3[112]; 413 uint64_t cr4; 414 uint64_t cr3; 415 uint64_t cr0; 416 uint64_t dr7; 417 uint64_t dr6; 418 uint64_t rflags; 419 uint64_t rip; 420 uint8_t rsvd4[88]; 421 uint64_t rsp; 422 uint8_t rsvd5[24]; 423 uint64_t rax; 424 uint64_t star; 425 uint64_t lstar; 426 uint64_t cstar; 427 uint64_t sfmask; 428 uint64_t kernelgsbase; 429 uint64_t sysenter_cs; 430 uint64_t sysenter_esp; 431 uint64_t sysenter_eip; 432 uint64_t cr2; 433 uint8_t rsvd6[32]; 434 uint64_t g_pat; 435 uint64_t dbgctl; 436 uint64_t br_from; 437 uint64_t br_to; 438 uint64_t int_from; 439 uint64_t int_to; 440 uint8_t pad[2408]; 441 } __packed; 442 443 CTASSERT(sizeof(struct vmcb_state) == 0xC00); 444 445 struct vmcb { 446 struct vmcb_ctrl ctrl; 447 struct vmcb_state state; 448 } __packed; 449 450 CTASSERT(sizeof(struct vmcb) == PAGE_SIZE); 451 CTASSERT(offsetof(struct vmcb, state) == 0x400); 452 453 /* -------------------------------------------------------------------------- */ 454 455 struct svm_hsave { 456 paddr_t pa; 457 }; 458 459 static struct svm_hsave hsave[MAXCPUS]; 460 461 static uint8_t *svm_asidmap __read_mostly; 462 static uint32_t svm_maxasid __read_mostly; 463 static kmutex_t svm_asidlock __cacheline_aligned; 464 465 static bool svm_decode_assist __read_mostly; 466 static uint32_t svm_ctrl_tlb_flush __read_mostly; 467 468 #define SVM_XCR0_MASK_DEFAULT (XCR0_X87|XCR0_SSE) 469 static uint64_t svm_xcr0_mask __read_mostly; 470 471 #define SVM_NCPUIDS 32 472 473 #define VMCB_NPAGES 1 474 475 #define MSRBM_NPAGES 2 476 #define MSRBM_SIZE (MSRBM_NPAGES * PAGE_SIZE) 477 478 #define IOBM_NPAGES 3 479 #define IOBM_SIZE (IOBM_NPAGES * PAGE_SIZE) 480 481 /* Does not include EFER_LMSLE. */ 482 #define EFER_VALID \ 483 (EFER_SCE|EFER_LME|EFER_LMA|EFER_NXE|EFER_SVME|EFER_FFXSR|EFER_TCE) 484 485 #define EFER_TLB_FLUSH \ 486 (EFER_NXE|EFER_LMA|EFER_LME) 487 #define CR0_TLB_FLUSH \ 488 (CR0_PG|CR0_WP|CR0_CD|CR0_NW) 489 #define CR4_TLB_FLUSH \ 490 (CR4_PGE|CR4_PAE|CR4_PSE) 491 492 /* -------------------------------------------------------------------------- */ 493 494 struct svm_machdata { 495 bool cpuidpresent[SVM_NCPUIDS]; 496 struct nvmm_x86_conf_cpuid cpuid[SVM_NCPUIDS]; 497 volatile uint64_t mach_htlb_gen; 498 }; 499 500 static const size_t svm_conf_sizes[NVMM_X86_NCONF] = { 501 [NVMM_X86_CONF_CPUID] = sizeof(struct nvmm_x86_conf_cpuid) 502 }; 503 504 struct svm_cpudata { 505 /* General */ 506 bool shared_asid; 507 bool gtlb_want_flush; 508 bool gtsc_want_update; 509 uint64_t vcpu_htlb_gen; 510 511 /* VMCB */ 512 struct vmcb *vmcb; 513 paddr_t vmcb_pa; 514 515 /* I/O bitmap */ 516 uint8_t *iobm; 517 paddr_t iobm_pa; 518 519 /* MSR bitmap */ 520 uint8_t *msrbm; 521 paddr_t msrbm_pa; 522 523 /* Host state */ 524 uint64_t hxcr0; 525 uint64_t star; 526 uint64_t lstar; 527 uint64_t cstar; 528 uint64_t sfmask; 529 uint64_t fsbase; 530 uint64_t kernelgsbase; 531 bool ts_set; 532 struct xsave_header hfpu __aligned(64); 533 534 /* Intr state */ 535 bool int_window_exit; 536 bool nmi_window_exit; 537 bool evt_pending; 538 539 /* Guest state */ 540 uint64_t gxcr0; 541 uint64_t gprs[NVMM_X64_NGPR]; 542 uint64_t drs[NVMM_X64_NDR]; 543 uint64_t gtsc; 544 struct xsave_header gfpu __aligned(64); 545 }; 546 547 static void 548 svm_vmcb_cache_default(struct vmcb *vmcb) 549 { 550 vmcb->ctrl.vmcb_clean = 551 VMCB_CTRL_VMCB_CLEAN_I | 552 VMCB_CTRL_VMCB_CLEAN_IOPM | 553 VMCB_CTRL_VMCB_CLEAN_ASID | 554 VMCB_CTRL_VMCB_CLEAN_TPR | 555 VMCB_CTRL_VMCB_CLEAN_NP | 556 VMCB_CTRL_VMCB_CLEAN_CR | 557 VMCB_CTRL_VMCB_CLEAN_DR | 558 VMCB_CTRL_VMCB_CLEAN_DT | 559 VMCB_CTRL_VMCB_CLEAN_SEG | 560 VMCB_CTRL_VMCB_CLEAN_CR2 | 561 VMCB_CTRL_VMCB_CLEAN_LBR | 562 VMCB_CTRL_VMCB_CLEAN_AVIC; 563 } 564 565 static void 566 svm_vmcb_cache_update(struct vmcb *vmcb, uint64_t flags) 567 { 568 if (flags & NVMM_X64_STATE_SEGS) { 569 vmcb->ctrl.vmcb_clean &= 570 ~(VMCB_CTRL_VMCB_CLEAN_SEG | VMCB_CTRL_VMCB_CLEAN_DT); 571 } 572 if (flags & NVMM_X64_STATE_CRS) { 573 vmcb->ctrl.vmcb_clean &= 574 ~(VMCB_CTRL_VMCB_CLEAN_CR | VMCB_CTRL_VMCB_CLEAN_CR2 | 575 VMCB_CTRL_VMCB_CLEAN_TPR); 576 } 577 if (flags & NVMM_X64_STATE_DRS) { 578 vmcb->ctrl.vmcb_clean &= ~VMCB_CTRL_VMCB_CLEAN_DR; 579 } 580 if (flags & NVMM_X64_STATE_MSRS) { 581 /* CR for EFER, NP for PAT. */ 582 vmcb->ctrl.vmcb_clean &= 583 ~(VMCB_CTRL_VMCB_CLEAN_CR | VMCB_CTRL_VMCB_CLEAN_NP); 584 } 585 } 586 587 static inline void 588 svm_vmcb_cache_flush(struct vmcb *vmcb, uint64_t flags) 589 { 590 vmcb->ctrl.vmcb_clean &= ~flags; 591 } 592 593 static inline void 594 svm_vmcb_cache_flush_all(struct vmcb *vmcb) 595 { 596 vmcb->ctrl.vmcb_clean = 0; 597 } 598 599 #define SVM_EVENT_TYPE_HW_INT 0 600 #define SVM_EVENT_TYPE_NMI 2 601 #define SVM_EVENT_TYPE_EXC 3 602 #define SVM_EVENT_TYPE_SW_INT 4 603 604 static void 605 svm_event_waitexit_enable(struct nvmm_cpu *vcpu, bool nmi) 606 { 607 struct svm_cpudata *cpudata = vcpu->cpudata; 608 struct vmcb *vmcb = cpudata->vmcb; 609 610 if (nmi) { 611 vmcb->ctrl.intercept_misc1 |= VMCB_CTRL_INTERCEPT_IRET; 612 cpudata->nmi_window_exit = true; 613 } else { 614 vmcb->ctrl.intercept_misc1 |= VMCB_CTRL_INTERCEPT_VINTR; 615 vmcb->ctrl.v |= (VMCB_CTRL_V_IRQ | VMCB_CTRL_V_IGN_TPR); 616 svm_vmcb_cache_flush(vmcb, VMCB_CTRL_VMCB_CLEAN_TPR); 617 cpudata->int_window_exit = true; 618 } 619 620 svm_vmcb_cache_flush(vmcb, VMCB_CTRL_VMCB_CLEAN_I); 621 } 622 623 static void 624 svm_event_waitexit_disable(struct nvmm_cpu *vcpu, bool nmi) 625 { 626 struct svm_cpudata *cpudata = vcpu->cpudata; 627 struct vmcb *vmcb = cpudata->vmcb; 628 629 if (nmi) { 630 vmcb->ctrl.intercept_misc1 &= ~VMCB_CTRL_INTERCEPT_IRET; 631 cpudata->nmi_window_exit = false; 632 } else { 633 vmcb->ctrl.intercept_misc1 &= ~VMCB_CTRL_INTERCEPT_VINTR; 634 vmcb->ctrl.v &= ~(VMCB_CTRL_V_IRQ | VMCB_CTRL_V_IGN_TPR); 635 svm_vmcb_cache_flush(vmcb, VMCB_CTRL_VMCB_CLEAN_TPR); 636 cpudata->int_window_exit = false; 637 } 638 639 svm_vmcb_cache_flush(vmcb, VMCB_CTRL_VMCB_CLEAN_I); 640 } 641 642 static inline int 643 svm_event_has_error(uint64_t vector) 644 { 645 switch (vector) { 646 case 8: /* #DF */ 647 case 10: /* #TS */ 648 case 11: /* #NP */ 649 case 12: /* #SS */ 650 case 13: /* #GP */ 651 case 14: /* #PF */ 652 case 17: /* #AC */ 653 case 30: /* #SX */ 654 return 1; 655 default: 656 return 0; 657 } 658 } 659 660 static int 661 svm_vcpu_inject(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 662 struct nvmm_event *event) 663 { 664 struct svm_cpudata *cpudata = vcpu->cpudata; 665 struct vmcb *vmcb = cpudata->vmcb; 666 int type = 0, err = 0; 667 668 if (event->vector >= 256) { 669 return EINVAL; 670 } 671 672 switch (event->type) { 673 case NVMM_EVENT_INTERRUPT_HW: 674 type = SVM_EVENT_TYPE_HW_INT; 675 if (event->vector == 2) { 676 type = SVM_EVENT_TYPE_NMI; 677 } 678 if (type == SVM_EVENT_TYPE_NMI) { 679 if (cpudata->nmi_window_exit) { 680 return EAGAIN; 681 } 682 svm_event_waitexit_enable(vcpu, true); 683 } else { 684 if (((vmcb->state.rflags & PSL_I) == 0) || 685 ((vmcb->ctrl.intr & VMCB_CTRL_INTR_SHADOW) != 0)) { 686 svm_event_waitexit_enable(vcpu, false); 687 return EAGAIN; 688 } 689 } 690 err = 0; 691 break; 692 case NVMM_EVENT_INTERRUPT_SW: 693 return EINVAL; 694 case NVMM_EVENT_EXCEPTION: 695 type = SVM_EVENT_TYPE_EXC; 696 if (event->vector == 2 || event->vector >= 32) 697 return EINVAL; 698 if (event->vector == 3 || event->vector == 0) 699 return EINVAL; 700 err = svm_event_has_error(event->vector); 701 break; 702 default: 703 return EINVAL; 704 } 705 706 vmcb->ctrl.eventinj = 707 __SHIFTIN(event->vector, VMCB_CTRL_EVENTINJ_VECTOR) | 708 __SHIFTIN(type, VMCB_CTRL_EVENTINJ_TYPE) | 709 __SHIFTIN(err, VMCB_CTRL_EVENTINJ_EV) | 710 __SHIFTIN(1, VMCB_CTRL_EVENTINJ_V) | 711 __SHIFTIN(event->u.error, VMCB_CTRL_EVENTINJ_ERRORCODE); 712 713 cpudata->evt_pending = true; 714 715 return 0; 716 } 717 718 static void 719 svm_inject_ud(struct nvmm_machine *mach, struct nvmm_cpu *vcpu) 720 { 721 struct nvmm_event event; 722 int ret __diagused; 723 724 event.type = NVMM_EVENT_EXCEPTION; 725 event.vector = 6; 726 event.u.error = 0; 727 728 ret = svm_vcpu_inject(mach, vcpu, &event); 729 KASSERT(ret == 0); 730 } 731 732 static void 733 svm_inject_gp(struct nvmm_machine *mach, struct nvmm_cpu *vcpu) 734 { 735 struct nvmm_event event; 736 int ret __diagused; 737 738 event.type = NVMM_EVENT_EXCEPTION; 739 event.vector = 13; 740 event.u.error = 0; 741 742 ret = svm_vcpu_inject(mach, vcpu, &event); 743 KASSERT(ret == 0); 744 } 745 746 static inline void 747 svm_inkernel_advance(struct vmcb *vmcb) 748 { 749 /* 750 * Maybe we should also apply single-stepping and debug exceptions. 751 * Matters for guest-ring3, because it can execute 'cpuid' under a 752 * debugger. 753 */ 754 vmcb->state.rip = vmcb->ctrl.nrip; 755 vmcb->ctrl.intr &= ~VMCB_CTRL_INTR_SHADOW; 756 } 757 758 static void 759 svm_inkernel_handle_cpuid(struct nvmm_cpu *vcpu, uint64_t eax, uint64_t ecx) 760 { 761 struct svm_cpudata *cpudata = vcpu->cpudata; 762 uint64_t cr4; 763 764 switch (eax) { 765 case 0x00000001: 766 cpudata->vmcb->state.rax &= nvmm_cpuid_00000001.eax; 767 768 cpudata->gprs[NVMM_X64_GPR_RBX] &= ~CPUID_LOCAL_APIC_ID; 769 cpudata->gprs[NVMM_X64_GPR_RBX] |= __SHIFTIN(vcpu->cpuid, 770 CPUID_LOCAL_APIC_ID); 771 772 cpudata->gprs[NVMM_X64_GPR_RCX] &= nvmm_cpuid_00000001.ecx; 773 cpudata->gprs[NVMM_X64_GPR_RCX] |= CPUID2_RAZ; 774 775 cpudata->gprs[NVMM_X64_GPR_RDX] &= nvmm_cpuid_00000001.edx; 776 777 /* CPUID2_OSXSAVE depends on CR4. */ 778 cr4 = cpudata->vmcb->state.cr4; 779 if (!(cr4 & CR4_OSXSAVE)) { 780 cpudata->gprs[NVMM_X64_GPR_RCX] &= ~CPUID2_OSXSAVE; 781 } 782 break; 783 case 0x00000005: 784 case 0x00000006: 785 cpudata->vmcb->state.rax = 0; 786 cpudata->gprs[NVMM_X64_GPR_RBX] = 0; 787 cpudata->gprs[NVMM_X64_GPR_RCX] = 0; 788 cpudata->gprs[NVMM_X64_GPR_RDX] = 0; 789 break; 790 case 0x00000007: 791 cpudata->vmcb->state.rax &= nvmm_cpuid_00000007.eax; 792 cpudata->gprs[NVMM_X64_GPR_RBX] &= nvmm_cpuid_00000007.ebx; 793 cpudata->gprs[NVMM_X64_GPR_RCX] &= nvmm_cpuid_00000007.ecx; 794 cpudata->gprs[NVMM_X64_GPR_RDX] &= nvmm_cpuid_00000007.edx; 795 break; 796 case 0x0000000D: 797 if (svm_xcr0_mask == 0) { 798 break; 799 } 800 switch (ecx) { 801 case 0: 802 cpudata->vmcb->state.rax = svm_xcr0_mask & 0xFFFFFFFF; 803 if (cpudata->gxcr0 & XCR0_SSE) { 804 cpudata->gprs[NVMM_X64_GPR_RBX] = sizeof(struct fxsave); 805 } else { 806 cpudata->gprs[NVMM_X64_GPR_RBX] = sizeof(struct save87); 807 } 808 cpudata->gprs[NVMM_X64_GPR_RBX] += 64; /* XSAVE header */ 809 cpudata->gprs[NVMM_X64_GPR_RCX] = sizeof(struct fxsave) + 64; 810 cpudata->gprs[NVMM_X64_GPR_RDX] = svm_xcr0_mask >> 32; 811 break; 812 case 1: 813 cpudata->vmcb->state.rax &= ~CPUID_PES1_XSAVES; 814 break; 815 } 816 break; 817 case 0x40000000: 818 cpudata->gprs[NVMM_X64_GPR_RBX] = 0; 819 cpudata->gprs[NVMM_X64_GPR_RCX] = 0; 820 cpudata->gprs[NVMM_X64_GPR_RDX] = 0; 821 memcpy(&cpudata->gprs[NVMM_X64_GPR_RBX], "___ ", 4); 822 memcpy(&cpudata->gprs[NVMM_X64_GPR_RCX], "NVMM", 4); 823 memcpy(&cpudata->gprs[NVMM_X64_GPR_RDX], " ___", 4); 824 break; 825 case 0x80000001: 826 cpudata->vmcb->state.rax &= nvmm_cpuid_80000001.eax; 827 cpudata->gprs[NVMM_X64_GPR_RBX] &= nvmm_cpuid_80000001.ebx; 828 cpudata->gprs[NVMM_X64_GPR_RCX] &= nvmm_cpuid_80000001.ecx; 829 cpudata->gprs[NVMM_X64_GPR_RDX] &= nvmm_cpuid_80000001.edx; 830 break; 831 default: 832 break; 833 } 834 } 835 836 static void 837 svm_exit_cpuid(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 838 struct nvmm_exit *exit) 839 { 840 struct svm_machdata *machdata = mach->machdata; 841 struct svm_cpudata *cpudata = vcpu->cpudata; 842 struct nvmm_x86_conf_cpuid *cpuid; 843 uint64_t eax, ecx; 844 u_int descs[4]; 845 size_t i; 846 847 eax = cpudata->vmcb->state.rax; 848 ecx = cpudata->gprs[NVMM_X64_GPR_RCX]; 849 x86_cpuid2(eax, ecx, descs); 850 851 cpudata->vmcb->state.rax = descs[0]; 852 cpudata->gprs[NVMM_X64_GPR_RBX] = descs[1]; 853 cpudata->gprs[NVMM_X64_GPR_RCX] = descs[2]; 854 cpudata->gprs[NVMM_X64_GPR_RDX] = descs[3]; 855 856 svm_inkernel_handle_cpuid(vcpu, eax, ecx); 857 858 for (i = 0; i < SVM_NCPUIDS; i++) { 859 cpuid = &machdata->cpuid[i]; 860 if (!machdata->cpuidpresent[i]) { 861 continue; 862 } 863 if (cpuid->leaf != eax) { 864 continue; 865 } 866 867 /* del */ 868 cpudata->vmcb->state.rax &= ~cpuid->del.eax; 869 cpudata->gprs[NVMM_X64_GPR_RBX] &= ~cpuid->del.ebx; 870 cpudata->gprs[NVMM_X64_GPR_RCX] &= ~cpuid->del.ecx; 871 cpudata->gprs[NVMM_X64_GPR_RDX] &= ~cpuid->del.edx; 872 873 /* set */ 874 cpudata->vmcb->state.rax |= cpuid->set.eax; 875 cpudata->gprs[NVMM_X64_GPR_RBX] |= cpuid->set.ebx; 876 cpudata->gprs[NVMM_X64_GPR_RCX] |= cpuid->set.ecx; 877 cpudata->gprs[NVMM_X64_GPR_RDX] |= cpuid->set.edx; 878 879 break; 880 } 881 882 svm_inkernel_advance(cpudata->vmcb); 883 exit->reason = NVMM_EXIT_NONE; 884 } 885 886 static void 887 svm_exit_hlt(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 888 struct nvmm_exit *exit) 889 { 890 struct svm_cpudata *cpudata = vcpu->cpudata; 891 struct vmcb *vmcb = cpudata->vmcb; 892 893 if (cpudata->int_window_exit && (vmcb->state.rflags & PSL_I)) { 894 svm_event_waitexit_disable(vcpu, false); 895 } 896 897 svm_inkernel_advance(cpudata->vmcb); 898 exit->reason = NVMM_EXIT_HALTED; 899 } 900 901 #define SVM_EXIT_IO_PORT __BITS(31,16) 902 #define SVM_EXIT_IO_SEG __BITS(12,10) 903 #define SVM_EXIT_IO_A64 __BIT(9) 904 #define SVM_EXIT_IO_A32 __BIT(8) 905 #define SVM_EXIT_IO_A16 __BIT(7) 906 #define SVM_EXIT_IO_SZ32 __BIT(6) 907 #define SVM_EXIT_IO_SZ16 __BIT(5) 908 #define SVM_EXIT_IO_SZ8 __BIT(4) 909 #define SVM_EXIT_IO_REP __BIT(3) 910 #define SVM_EXIT_IO_STR __BIT(2) 911 #define SVM_EXIT_IO_IN __BIT(0) 912 913 static void 914 svm_exit_io(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 915 struct nvmm_exit *exit) 916 { 917 struct svm_cpudata *cpudata = vcpu->cpudata; 918 uint64_t info = cpudata->vmcb->ctrl.exitinfo1; 919 uint64_t nextpc = cpudata->vmcb->ctrl.exitinfo2; 920 921 exit->reason = NVMM_EXIT_IO; 922 923 if (info & SVM_EXIT_IO_IN) { 924 exit->u.io.type = NVMM_EXIT_IO_IN; 925 } else { 926 exit->u.io.type = NVMM_EXIT_IO_OUT; 927 } 928 929 exit->u.io.port = __SHIFTOUT(info, SVM_EXIT_IO_PORT); 930 931 if (svm_decode_assist) { 932 KASSERT(__SHIFTOUT(info, SVM_EXIT_IO_SEG) < 6); 933 exit->u.io.seg = __SHIFTOUT(info, SVM_EXIT_IO_SEG); 934 } else { 935 exit->u.io.seg = -1; 936 } 937 938 if (info & SVM_EXIT_IO_A64) { 939 exit->u.io.address_size = 8; 940 } else if (info & SVM_EXIT_IO_A32) { 941 exit->u.io.address_size = 4; 942 } else if (info & SVM_EXIT_IO_A16) { 943 exit->u.io.address_size = 2; 944 } 945 946 if (info & SVM_EXIT_IO_SZ32) { 947 exit->u.io.operand_size = 4; 948 } else if (info & SVM_EXIT_IO_SZ16) { 949 exit->u.io.operand_size = 2; 950 } else if (info & SVM_EXIT_IO_SZ8) { 951 exit->u.io.operand_size = 1; 952 } 953 954 exit->u.io.rep = (info & SVM_EXIT_IO_REP) != 0; 955 exit->u.io.str = (info & SVM_EXIT_IO_STR) != 0; 956 exit->u.io.npc = nextpc; 957 } 958 959 static const uint64_t msr_ignore_list[] = { 960 0xc0010055, /* MSR_CMPHALT */ 961 MSR_DE_CFG, 962 MSR_IC_CFG, 963 MSR_UCODE_AMD_PATCHLEVEL 964 }; 965 966 static bool 967 svm_inkernel_handle_msr(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 968 struct nvmm_exit *exit) 969 { 970 struct svm_cpudata *cpudata = vcpu->cpudata; 971 struct vmcb *vmcb = cpudata->vmcb; 972 uint64_t val; 973 size_t i; 974 975 switch (exit->u.msr.type) { 976 case NVMM_EXIT_MSR_RDMSR: 977 if (exit->u.msr.msr == MSR_NB_CFG) { 978 val = NB_CFG_INITAPICCPUIDLO; 979 vmcb->state.rax = (val & 0xFFFFFFFF); 980 cpudata->gprs[NVMM_X64_GPR_RDX] = (val >> 32); 981 goto handled; 982 } 983 for (i = 0; i < __arraycount(msr_ignore_list); i++) { 984 if (msr_ignore_list[i] != exit->u.msr.msr) 985 continue; 986 val = 0; 987 vmcb->state.rax = (val & 0xFFFFFFFF); 988 cpudata->gprs[NVMM_X64_GPR_RDX] = (val >> 32); 989 goto handled; 990 } 991 break; 992 case NVMM_EXIT_MSR_WRMSR: 993 if (exit->u.msr.msr == MSR_EFER) { 994 if (__predict_false(exit->u.msr.val & ~EFER_VALID)) { 995 goto error; 996 } 997 if ((vmcb->state.efer ^ exit->u.msr.val) & 998 EFER_TLB_FLUSH) { 999 cpudata->gtlb_want_flush = true; 1000 } 1001 vmcb->state.efer = exit->u.msr.val | EFER_SVME; 1002 svm_vmcb_cache_flush(vmcb, VMCB_CTRL_VMCB_CLEAN_CR); 1003 goto handled; 1004 } 1005 if (exit->u.msr.msr == MSR_TSC) { 1006 cpudata->gtsc = exit->u.msr.val; 1007 cpudata->gtsc_want_update = true; 1008 goto handled; 1009 } 1010 for (i = 0; i < __arraycount(msr_ignore_list); i++) { 1011 if (msr_ignore_list[i] != exit->u.msr.msr) 1012 continue; 1013 goto handled; 1014 } 1015 break; 1016 } 1017 1018 return false; 1019 1020 handled: 1021 svm_inkernel_advance(cpudata->vmcb); 1022 return true; 1023 1024 error: 1025 svm_inject_gp(mach, vcpu); 1026 return true; 1027 } 1028 1029 static void 1030 svm_exit_msr(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 1031 struct nvmm_exit *exit) 1032 { 1033 struct svm_cpudata *cpudata = vcpu->cpudata; 1034 uint64_t info = cpudata->vmcb->ctrl.exitinfo1; 1035 1036 if (info == 0) { 1037 exit->u.msr.type = NVMM_EXIT_MSR_RDMSR; 1038 } else { 1039 exit->u.msr.type = NVMM_EXIT_MSR_WRMSR; 1040 } 1041 1042 exit->u.msr.msr = (cpudata->gprs[NVMM_X64_GPR_RCX] & 0xFFFFFFFF); 1043 1044 if (info == 1) { 1045 uint64_t rdx, rax; 1046 rdx = cpudata->gprs[NVMM_X64_GPR_RDX]; 1047 rax = cpudata->vmcb->state.rax; 1048 exit->u.msr.val = (rdx << 32) | (rax & 0xFFFFFFFF); 1049 } else { 1050 exit->u.msr.val = 0; 1051 } 1052 1053 if (svm_inkernel_handle_msr(mach, vcpu, exit)) { 1054 exit->reason = NVMM_EXIT_NONE; 1055 return; 1056 } 1057 1058 exit->reason = NVMM_EXIT_MSR; 1059 exit->u.msr.npc = cpudata->vmcb->ctrl.nrip; 1060 } 1061 1062 static void 1063 svm_exit_npf(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 1064 struct nvmm_exit *exit) 1065 { 1066 struct svm_cpudata *cpudata = vcpu->cpudata; 1067 gpaddr_t gpa = cpudata->vmcb->ctrl.exitinfo2; 1068 1069 exit->reason = NVMM_EXIT_MEMORY; 1070 if (cpudata->vmcb->ctrl.exitinfo1 & PGEX_W) 1071 exit->u.mem.prot = PROT_WRITE; 1072 else if (cpudata->vmcb->ctrl.exitinfo1 & PGEX_X) 1073 exit->u.mem.prot = PROT_EXEC; 1074 else 1075 exit->u.mem.prot = PROT_READ; 1076 exit->u.mem.gpa = gpa; 1077 exit->u.mem.inst_len = cpudata->vmcb->ctrl.inst_len; 1078 memcpy(exit->u.mem.inst_bytes, cpudata->vmcb->ctrl.inst_bytes, 1079 sizeof(exit->u.mem.inst_bytes)); 1080 } 1081 1082 static void 1083 svm_exit_insn(struct vmcb *vmcb, struct nvmm_exit *exit, uint64_t reason) 1084 { 1085 exit->u.insn.npc = vmcb->ctrl.nrip; 1086 exit->reason = reason; 1087 } 1088 1089 static void 1090 svm_exit_xsetbv(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 1091 struct nvmm_exit *exit) 1092 { 1093 struct svm_cpudata *cpudata = vcpu->cpudata; 1094 struct vmcb *vmcb = cpudata->vmcb; 1095 uint64_t val; 1096 1097 exit->reason = NVMM_EXIT_NONE; 1098 1099 val = (cpudata->gprs[NVMM_X64_GPR_RDX] << 32) | 1100 (vmcb->state.rax & 0xFFFFFFFF); 1101 1102 if (__predict_false(cpudata->gprs[NVMM_X64_GPR_RCX] != 0)) { 1103 goto error; 1104 } else if (__predict_false(vmcb->state.cpl != 0)) { 1105 goto error; 1106 } else if (__predict_false((val & ~svm_xcr0_mask) != 0)) { 1107 goto error; 1108 } else if (__predict_false((val & XCR0_X87) == 0)) { 1109 goto error; 1110 } 1111 1112 cpudata->gxcr0 = val; 1113 1114 svm_inkernel_advance(cpudata->vmcb); 1115 return; 1116 1117 error: 1118 svm_inject_gp(mach, vcpu); 1119 } 1120 1121 static void 1122 svm_exit_invalid(struct nvmm_exit *exit, uint64_t code) 1123 { 1124 exit->u.inv.hwcode = code; 1125 exit->reason = NVMM_EXIT_INVALID; 1126 } 1127 1128 /* -------------------------------------------------------------------------- */ 1129 1130 static void 1131 svm_vcpu_guest_fpu_enter(struct nvmm_cpu *vcpu) 1132 { 1133 struct svm_cpudata *cpudata = vcpu->cpudata; 1134 1135 cpudata->ts_set = (rcr0() & CR0_TS) != 0; 1136 1137 fpu_area_save(&cpudata->hfpu, svm_xcr0_mask); 1138 fpu_area_restore(&cpudata->gfpu, svm_xcr0_mask); 1139 1140 if (svm_xcr0_mask != 0) { 1141 cpudata->hxcr0 = rdxcr(0); 1142 wrxcr(0, cpudata->gxcr0); 1143 } 1144 } 1145 1146 static void 1147 svm_vcpu_guest_fpu_leave(struct nvmm_cpu *vcpu) 1148 { 1149 struct svm_cpudata *cpudata = vcpu->cpudata; 1150 1151 if (svm_xcr0_mask != 0) { 1152 cpudata->gxcr0 = rdxcr(0); 1153 wrxcr(0, cpudata->hxcr0); 1154 } 1155 1156 fpu_area_save(&cpudata->gfpu, svm_xcr0_mask); 1157 fpu_area_restore(&cpudata->hfpu, svm_xcr0_mask); 1158 1159 if (cpudata->ts_set) { 1160 stts(); 1161 } 1162 } 1163 1164 static void 1165 svm_vcpu_guest_dbregs_enter(struct nvmm_cpu *vcpu) 1166 { 1167 struct svm_cpudata *cpudata = vcpu->cpudata; 1168 1169 x86_dbregs_save(curlwp); 1170 1171 ldr7(0); 1172 1173 ldr0(cpudata->drs[NVMM_X64_DR_DR0]); 1174 ldr1(cpudata->drs[NVMM_X64_DR_DR1]); 1175 ldr2(cpudata->drs[NVMM_X64_DR_DR2]); 1176 ldr3(cpudata->drs[NVMM_X64_DR_DR3]); 1177 } 1178 1179 static void 1180 svm_vcpu_guest_dbregs_leave(struct nvmm_cpu *vcpu) 1181 { 1182 struct svm_cpudata *cpudata = vcpu->cpudata; 1183 1184 cpudata->drs[NVMM_X64_DR_DR0] = rdr0(); 1185 cpudata->drs[NVMM_X64_DR_DR1] = rdr1(); 1186 cpudata->drs[NVMM_X64_DR_DR2] = rdr2(); 1187 cpudata->drs[NVMM_X64_DR_DR3] = rdr3(); 1188 1189 x86_dbregs_restore(curlwp); 1190 } 1191 1192 static void 1193 svm_vcpu_guest_misc_enter(struct nvmm_cpu *vcpu) 1194 { 1195 struct svm_cpudata *cpudata = vcpu->cpudata; 1196 1197 cpudata->fsbase = rdmsr(MSR_FSBASE); 1198 cpudata->kernelgsbase = rdmsr(MSR_KERNELGSBASE); 1199 } 1200 1201 static void 1202 svm_vcpu_guest_misc_leave(struct nvmm_cpu *vcpu) 1203 { 1204 struct svm_cpudata *cpudata = vcpu->cpudata; 1205 1206 wrmsr(MSR_STAR, cpudata->star); 1207 wrmsr(MSR_LSTAR, cpudata->lstar); 1208 wrmsr(MSR_CSTAR, cpudata->cstar); 1209 wrmsr(MSR_SFMASK, cpudata->sfmask); 1210 wrmsr(MSR_FSBASE, cpudata->fsbase); 1211 wrmsr(MSR_KERNELGSBASE, cpudata->kernelgsbase); 1212 } 1213 1214 /* -------------------------------------------------------------------------- */ 1215 1216 static inline void 1217 svm_gtlb_catchup(struct nvmm_cpu *vcpu, int hcpu) 1218 { 1219 struct svm_cpudata *cpudata = vcpu->cpudata; 1220 1221 if (vcpu->hcpu_last != hcpu || cpudata->shared_asid) { 1222 cpudata->gtlb_want_flush = true; 1223 } 1224 } 1225 1226 static inline void 1227 svm_htlb_catchup(struct nvmm_cpu *vcpu, int hcpu) 1228 { 1229 /* 1230 * Nothing to do. If an hTLB flush was needed, either the VCPU was 1231 * executing on this hCPU and the hTLB already got flushed, or it 1232 * was executing on another hCPU in which case the catchup is done 1233 * in svm_gtlb_catchup(). 1234 */ 1235 } 1236 1237 static inline uint64_t 1238 svm_htlb_flush(struct svm_machdata *machdata, struct svm_cpudata *cpudata) 1239 { 1240 struct vmcb *vmcb = cpudata->vmcb; 1241 uint64_t machgen; 1242 1243 machgen = machdata->mach_htlb_gen; 1244 if (__predict_true(machgen == cpudata->vcpu_htlb_gen)) { 1245 return machgen; 1246 } 1247 1248 vmcb->ctrl.tlb_ctrl = svm_ctrl_tlb_flush; 1249 return machgen; 1250 } 1251 1252 static inline void 1253 svm_htlb_flush_ack(struct svm_cpudata *cpudata, uint64_t machgen) 1254 { 1255 struct vmcb *vmcb = cpudata->vmcb; 1256 1257 if (__predict_true(vmcb->ctrl.exitcode != VMCB_EXITCODE_INVALID)) { 1258 cpudata->vcpu_htlb_gen = machgen; 1259 } 1260 } 1261 1262 static inline void 1263 svm_exit_evt(struct svm_cpudata *cpudata, struct vmcb *vmcb) 1264 { 1265 cpudata->evt_pending = false; 1266 1267 if (__predict_false(vmcb->ctrl.exitintinfo & VMCB_CTRL_EXITINTINFO_V)) { 1268 vmcb->ctrl.eventinj = vmcb->ctrl.exitintinfo; 1269 cpudata->evt_pending = true; 1270 } 1271 } 1272 1273 static int 1274 svm_vcpu_run(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 1275 struct nvmm_exit *exit) 1276 { 1277 struct svm_machdata *machdata = mach->machdata; 1278 struct svm_cpudata *cpudata = vcpu->cpudata; 1279 struct vmcb *vmcb = cpudata->vmcb; 1280 uint64_t machgen; 1281 int hcpu, s; 1282 1283 kpreempt_disable(); 1284 hcpu = cpu_number(); 1285 1286 svm_gtlb_catchup(vcpu, hcpu); 1287 svm_htlb_catchup(vcpu, hcpu); 1288 1289 if (vcpu->hcpu_last != hcpu) { 1290 svm_vmcb_cache_flush_all(vmcb); 1291 cpudata->gtsc_want_update = true; 1292 } 1293 1294 svm_vcpu_guest_dbregs_enter(vcpu); 1295 svm_vcpu_guest_misc_enter(vcpu); 1296 1297 while (1) { 1298 if (cpudata->gtlb_want_flush) { 1299 vmcb->ctrl.tlb_ctrl = svm_ctrl_tlb_flush; 1300 } else { 1301 vmcb->ctrl.tlb_ctrl = 0; 1302 } 1303 1304 if (__predict_false(cpudata->gtsc_want_update)) { 1305 vmcb->ctrl.tsc_offset = cpudata->gtsc - rdtsc(); 1306 svm_vmcb_cache_flush(vmcb, VMCB_CTRL_VMCB_CLEAN_I); 1307 } 1308 1309 s = splhigh(); 1310 machgen = svm_htlb_flush(machdata, cpudata); 1311 svm_vcpu_guest_fpu_enter(vcpu); 1312 svm_vmrun(cpudata->vmcb_pa, cpudata->gprs); 1313 svm_vcpu_guest_fpu_leave(vcpu); 1314 svm_htlb_flush_ack(cpudata, machgen); 1315 splx(s); 1316 1317 svm_vmcb_cache_default(vmcb); 1318 1319 if (vmcb->ctrl.exitcode != VMCB_EXITCODE_INVALID) { 1320 cpudata->gtlb_want_flush = false; 1321 cpudata->gtsc_want_update = false; 1322 vcpu->hcpu_last = hcpu; 1323 } 1324 svm_exit_evt(cpudata, vmcb); 1325 1326 switch (vmcb->ctrl.exitcode) { 1327 case VMCB_EXITCODE_INTR: 1328 case VMCB_EXITCODE_NMI: 1329 exit->reason = NVMM_EXIT_NONE; 1330 break; 1331 case VMCB_EXITCODE_VINTR: 1332 svm_event_waitexit_disable(vcpu, false); 1333 exit->reason = NVMM_EXIT_INT_READY; 1334 break; 1335 case VMCB_EXITCODE_IRET: 1336 svm_event_waitexit_disable(vcpu, true); 1337 exit->reason = NVMM_EXIT_NMI_READY; 1338 break; 1339 case VMCB_EXITCODE_CPUID: 1340 svm_exit_cpuid(mach, vcpu, exit); 1341 break; 1342 case VMCB_EXITCODE_HLT: 1343 svm_exit_hlt(mach, vcpu, exit); 1344 break; 1345 case VMCB_EXITCODE_IOIO: 1346 svm_exit_io(mach, vcpu, exit); 1347 break; 1348 case VMCB_EXITCODE_MSR: 1349 svm_exit_msr(mach, vcpu, exit); 1350 break; 1351 case VMCB_EXITCODE_SHUTDOWN: 1352 exit->reason = NVMM_EXIT_SHUTDOWN; 1353 break; 1354 case VMCB_EXITCODE_RDPMC: 1355 case VMCB_EXITCODE_RSM: 1356 case VMCB_EXITCODE_INVLPGA: 1357 case VMCB_EXITCODE_VMRUN: 1358 case VMCB_EXITCODE_VMMCALL: 1359 case VMCB_EXITCODE_VMLOAD: 1360 case VMCB_EXITCODE_VMSAVE: 1361 case VMCB_EXITCODE_STGI: 1362 case VMCB_EXITCODE_CLGI: 1363 case VMCB_EXITCODE_SKINIT: 1364 case VMCB_EXITCODE_RDTSCP: 1365 svm_inject_ud(mach, vcpu); 1366 exit->reason = NVMM_EXIT_NONE; 1367 break; 1368 case VMCB_EXITCODE_MONITOR: 1369 svm_exit_insn(vmcb, exit, NVMM_EXIT_MONITOR); 1370 break; 1371 case VMCB_EXITCODE_MWAIT: 1372 svm_exit_insn(vmcb, exit, NVMM_EXIT_MWAIT); 1373 break; 1374 case VMCB_EXITCODE_MWAIT_CONDITIONAL: 1375 svm_exit_insn(vmcb, exit, NVMM_EXIT_MWAIT_COND); 1376 break; 1377 case VMCB_EXITCODE_XSETBV: 1378 svm_exit_xsetbv(mach, vcpu, exit); 1379 break; 1380 case VMCB_EXITCODE_NPF: 1381 svm_exit_npf(mach, vcpu, exit); 1382 break; 1383 case VMCB_EXITCODE_FERR_FREEZE: /* ? */ 1384 default: 1385 svm_exit_invalid(exit, vmcb->ctrl.exitcode); 1386 break; 1387 } 1388 1389 /* If no reason to return to userland, keep rolling. */ 1390 if (curcpu()->ci_schedstate.spc_flags & SPCF_SHOULDYIELD) { 1391 break; 1392 } 1393 if (curcpu()->ci_data.cpu_softints != 0) { 1394 break; 1395 } 1396 if (curlwp->l_flag & LW_USERRET) { 1397 break; 1398 } 1399 if (exit->reason != NVMM_EXIT_NONE) { 1400 break; 1401 } 1402 } 1403 1404 cpudata->gtsc = rdtsc() + vmcb->ctrl.tsc_offset; 1405 1406 svm_vcpu_guest_misc_leave(vcpu); 1407 svm_vcpu_guest_dbregs_leave(vcpu); 1408 1409 kpreempt_enable(); 1410 1411 exit->exitstate[NVMM_X64_EXITSTATE_CR8] = __SHIFTOUT(vmcb->ctrl.v, 1412 VMCB_CTRL_V_TPR); 1413 exit->exitstate[NVMM_X64_EXITSTATE_RFLAGS] = vmcb->state.rflags; 1414 1415 exit->exitstate[NVMM_X64_EXITSTATE_INT_SHADOW] = 1416 ((vmcb->ctrl.intr & VMCB_CTRL_INTR_SHADOW) != 0); 1417 exit->exitstate[NVMM_X64_EXITSTATE_INT_WINDOW_EXIT] = 1418 cpudata->int_window_exit; 1419 exit->exitstate[NVMM_X64_EXITSTATE_NMI_WINDOW_EXIT] = 1420 cpudata->nmi_window_exit; 1421 exit->exitstate[NVMM_X64_EXITSTATE_EVT_PENDING] = 1422 cpudata->evt_pending; 1423 1424 return 0; 1425 } 1426 1427 /* -------------------------------------------------------------------------- */ 1428 1429 static int 1430 svm_memalloc(paddr_t *pa, vaddr_t *va, size_t npages) 1431 { 1432 struct pglist pglist; 1433 paddr_t _pa; 1434 vaddr_t _va; 1435 size_t i; 1436 int ret; 1437 1438 ret = uvm_pglistalloc(npages * PAGE_SIZE, 0, ~0UL, PAGE_SIZE, 0, 1439 &pglist, 1, 0); 1440 if (ret != 0) 1441 return ENOMEM; 1442 _pa = TAILQ_FIRST(&pglist)->phys_addr; 1443 _va = uvm_km_alloc(kernel_map, npages * PAGE_SIZE, 0, 1444 UVM_KMF_VAONLY | UVM_KMF_NOWAIT); 1445 if (_va == 0) 1446 goto error; 1447 1448 for (i = 0; i < npages; i++) { 1449 pmap_kenter_pa(_va + i * PAGE_SIZE, _pa + i * PAGE_SIZE, 1450 VM_PROT_READ | VM_PROT_WRITE, PMAP_WRITE_BACK); 1451 } 1452 pmap_update(pmap_kernel()); 1453 1454 memset((void *)_va, 0, npages * PAGE_SIZE); 1455 1456 *pa = _pa; 1457 *va = _va; 1458 return 0; 1459 1460 error: 1461 for (i = 0; i < npages; i++) { 1462 uvm_pagefree(PHYS_TO_VM_PAGE(_pa + i * PAGE_SIZE)); 1463 } 1464 return ENOMEM; 1465 } 1466 1467 static void 1468 svm_memfree(paddr_t pa, vaddr_t va, size_t npages) 1469 { 1470 size_t i; 1471 1472 pmap_kremove(va, npages * PAGE_SIZE); 1473 pmap_update(pmap_kernel()); 1474 uvm_km_free(kernel_map, va, npages * PAGE_SIZE, UVM_KMF_VAONLY); 1475 for (i = 0; i < npages; i++) { 1476 uvm_pagefree(PHYS_TO_VM_PAGE(pa + i * PAGE_SIZE)); 1477 } 1478 } 1479 1480 /* -------------------------------------------------------------------------- */ 1481 1482 #define SVM_MSRBM_READ __BIT(0) 1483 #define SVM_MSRBM_WRITE __BIT(1) 1484 1485 static void 1486 svm_vcpu_msr_allow(uint8_t *bitmap, uint64_t msr, bool read, bool write) 1487 { 1488 uint64_t byte; 1489 uint8_t bitoff; 1490 1491 if (msr < 0x00002000) { 1492 /* Range 1 */ 1493 byte = ((msr - 0x00000000) >> 2UL) + 0x0000; 1494 } else if (msr >= 0xC0000000 && msr < 0xC0002000) { 1495 /* Range 2 */ 1496 byte = ((msr - 0xC0000000) >> 2UL) + 0x0800; 1497 } else if (msr >= 0xC0010000 && msr < 0xC0012000) { 1498 /* Range 3 */ 1499 byte = ((msr - 0xC0010000) >> 2UL) + 0x1000; 1500 } else { 1501 panic("%s: wrong range", __func__); 1502 } 1503 1504 bitoff = (msr & 0x3) << 1; 1505 1506 if (read) { 1507 bitmap[byte] &= ~(SVM_MSRBM_READ << bitoff); 1508 } 1509 if (write) { 1510 bitmap[byte] &= ~(SVM_MSRBM_WRITE << bitoff); 1511 } 1512 } 1513 1514 #define SVM_SEG_ATTRIB_TYPE __BITS(3,0) 1515 #define SVM_SEG_ATTRIB_S __BIT(4) 1516 #define SVM_SEG_ATTRIB_DPL __BITS(6,5) 1517 #define SVM_SEG_ATTRIB_P __BIT(7) 1518 #define SVM_SEG_ATTRIB_AVL __BIT(8) 1519 #define SVM_SEG_ATTRIB_L __BIT(9) 1520 #define SVM_SEG_ATTRIB_DEF __BIT(10) 1521 #define SVM_SEG_ATTRIB_G __BIT(11) 1522 1523 static void 1524 svm_vcpu_setstate_seg(const struct nvmm_x64_state_seg *seg, 1525 struct vmcb_segment *vseg) 1526 { 1527 vseg->selector = seg->selector; 1528 vseg->attrib = 1529 __SHIFTIN(seg->attrib.type, SVM_SEG_ATTRIB_TYPE) | 1530 __SHIFTIN(seg->attrib.s, SVM_SEG_ATTRIB_S) | 1531 __SHIFTIN(seg->attrib.dpl, SVM_SEG_ATTRIB_DPL) | 1532 __SHIFTIN(seg->attrib.p, SVM_SEG_ATTRIB_P) | 1533 __SHIFTIN(seg->attrib.avl, SVM_SEG_ATTRIB_AVL) | 1534 __SHIFTIN(seg->attrib.l, SVM_SEG_ATTRIB_L) | 1535 __SHIFTIN(seg->attrib.def, SVM_SEG_ATTRIB_DEF) | 1536 __SHIFTIN(seg->attrib.g, SVM_SEG_ATTRIB_G); 1537 vseg->limit = seg->limit; 1538 vseg->base = seg->base; 1539 } 1540 1541 static void 1542 svm_vcpu_getstate_seg(struct nvmm_x64_state_seg *seg, struct vmcb_segment *vseg) 1543 { 1544 seg->selector = vseg->selector; 1545 seg->attrib.type = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_TYPE); 1546 seg->attrib.s = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_S); 1547 seg->attrib.dpl = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_DPL); 1548 seg->attrib.p = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_P); 1549 seg->attrib.avl = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_AVL); 1550 seg->attrib.l = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_L); 1551 seg->attrib.def = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_DEF); 1552 seg->attrib.g = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_G); 1553 seg->limit = vseg->limit; 1554 seg->base = vseg->base; 1555 } 1556 1557 static inline bool 1558 svm_state_tlb_flush(const struct vmcb *vmcb, const struct nvmm_x64_state *state, 1559 uint64_t flags) 1560 { 1561 if (flags & NVMM_X64_STATE_CRS) { 1562 if ((vmcb->state.cr0 ^ 1563 state->crs[NVMM_X64_CR_CR0]) & CR0_TLB_FLUSH) { 1564 return true; 1565 } 1566 if (vmcb->state.cr3 != state->crs[NVMM_X64_CR_CR3]) { 1567 return true; 1568 } 1569 if ((vmcb->state.cr4 ^ 1570 state->crs[NVMM_X64_CR_CR4]) & CR4_TLB_FLUSH) { 1571 return true; 1572 } 1573 } 1574 1575 if (flags & NVMM_X64_STATE_MSRS) { 1576 if ((vmcb->state.efer ^ 1577 state->msrs[NVMM_X64_MSR_EFER]) & EFER_TLB_FLUSH) { 1578 return true; 1579 } 1580 } 1581 1582 return false; 1583 } 1584 1585 static void 1586 svm_vcpu_setstate(struct nvmm_cpu *vcpu, const void *data, uint64_t flags) 1587 { 1588 const struct nvmm_x64_state *state = data; 1589 struct svm_cpudata *cpudata = vcpu->cpudata; 1590 struct vmcb *vmcb = cpudata->vmcb; 1591 struct fxsave *fpustate; 1592 1593 if (svm_state_tlb_flush(vmcb, state, flags)) { 1594 cpudata->gtlb_want_flush = true; 1595 } 1596 1597 if (flags & NVMM_X64_STATE_SEGS) { 1598 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_CS], 1599 &vmcb->state.cs); 1600 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_DS], 1601 &vmcb->state.ds); 1602 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_ES], 1603 &vmcb->state.es); 1604 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_FS], 1605 &vmcb->state.fs); 1606 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_GS], 1607 &vmcb->state.gs); 1608 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_SS], 1609 &vmcb->state.ss); 1610 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_GDT], 1611 &vmcb->state.gdt); 1612 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_IDT], 1613 &vmcb->state.idt); 1614 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_LDT], 1615 &vmcb->state.ldt); 1616 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_TR], 1617 &vmcb->state.tr); 1618 1619 vmcb->state.cpl = state->segs[NVMM_X64_SEG_SS].attrib.dpl; 1620 } 1621 1622 CTASSERT(sizeof(cpudata->gprs) == sizeof(state->gprs)); 1623 if (flags & NVMM_X64_STATE_GPRS) { 1624 memcpy(cpudata->gprs, state->gprs, sizeof(state->gprs)); 1625 1626 vmcb->state.rip = state->gprs[NVMM_X64_GPR_RIP]; 1627 vmcb->state.rsp = state->gprs[NVMM_X64_GPR_RSP]; 1628 vmcb->state.rax = state->gprs[NVMM_X64_GPR_RAX]; 1629 vmcb->state.rflags = state->gprs[NVMM_X64_GPR_RFLAGS]; 1630 } 1631 1632 if (flags & NVMM_X64_STATE_CRS) { 1633 vmcb->state.cr0 = state->crs[NVMM_X64_CR_CR0]; 1634 vmcb->state.cr2 = state->crs[NVMM_X64_CR_CR2]; 1635 vmcb->state.cr3 = state->crs[NVMM_X64_CR_CR3]; 1636 vmcb->state.cr4 = state->crs[NVMM_X64_CR_CR4]; 1637 1638 vmcb->ctrl.v &= ~VMCB_CTRL_V_TPR; 1639 vmcb->ctrl.v |= __SHIFTIN(state->crs[NVMM_X64_CR_CR8], 1640 VMCB_CTRL_V_TPR); 1641 1642 if (svm_xcr0_mask != 0) { 1643 /* Clear illegal XCR0 bits, set mandatory X87 bit. */ 1644 cpudata->gxcr0 = state->crs[NVMM_X64_CR_XCR0]; 1645 cpudata->gxcr0 &= svm_xcr0_mask; 1646 cpudata->gxcr0 |= XCR0_X87; 1647 } 1648 } 1649 1650 CTASSERT(sizeof(cpudata->drs) == sizeof(state->drs)); 1651 if (flags & NVMM_X64_STATE_DRS) { 1652 memcpy(cpudata->drs, state->drs, sizeof(state->drs)); 1653 1654 vmcb->state.dr6 = state->drs[NVMM_X64_DR_DR6]; 1655 vmcb->state.dr7 = state->drs[NVMM_X64_DR_DR7]; 1656 } 1657 1658 if (flags & NVMM_X64_STATE_MSRS) { 1659 /* 1660 * EFER_SVME is mandatory. 1661 */ 1662 vmcb->state.efer = state->msrs[NVMM_X64_MSR_EFER] | EFER_SVME; 1663 vmcb->state.star = state->msrs[NVMM_X64_MSR_STAR]; 1664 vmcb->state.lstar = state->msrs[NVMM_X64_MSR_LSTAR]; 1665 vmcb->state.cstar = state->msrs[NVMM_X64_MSR_CSTAR]; 1666 vmcb->state.sfmask = state->msrs[NVMM_X64_MSR_SFMASK]; 1667 vmcb->state.kernelgsbase = 1668 state->msrs[NVMM_X64_MSR_KERNELGSBASE]; 1669 vmcb->state.sysenter_cs = 1670 state->msrs[NVMM_X64_MSR_SYSENTER_CS]; 1671 vmcb->state.sysenter_esp = 1672 state->msrs[NVMM_X64_MSR_SYSENTER_ESP]; 1673 vmcb->state.sysenter_eip = 1674 state->msrs[NVMM_X64_MSR_SYSENTER_EIP]; 1675 vmcb->state.g_pat = state->msrs[NVMM_X64_MSR_PAT]; 1676 1677 cpudata->gtsc = state->msrs[NVMM_X64_MSR_TSC]; 1678 cpudata->gtsc_want_update = true; 1679 } 1680 1681 if (flags & NVMM_X64_STATE_INTR) { 1682 if (state->intr.int_shadow) { 1683 vmcb->ctrl.intr |= VMCB_CTRL_INTR_SHADOW; 1684 } else { 1685 vmcb->ctrl.intr &= ~VMCB_CTRL_INTR_SHADOW; 1686 } 1687 1688 if (state->intr.int_window_exiting) { 1689 svm_event_waitexit_enable(vcpu, false); 1690 } else { 1691 svm_event_waitexit_disable(vcpu, false); 1692 } 1693 1694 if (state->intr.nmi_window_exiting) { 1695 svm_event_waitexit_enable(vcpu, true); 1696 } else { 1697 svm_event_waitexit_disable(vcpu, true); 1698 } 1699 } 1700 1701 CTASSERT(sizeof(cpudata->gfpu.xsh_fxsave) == sizeof(state->fpu)); 1702 if (flags & NVMM_X64_STATE_FPU) { 1703 memcpy(cpudata->gfpu.xsh_fxsave, &state->fpu, 1704 sizeof(state->fpu)); 1705 1706 fpustate = (struct fxsave *)cpudata->gfpu.xsh_fxsave; 1707 fpustate->fx_mxcsr_mask &= x86_fpu_mxcsr_mask; 1708 fpustate->fx_mxcsr &= fpustate->fx_mxcsr_mask; 1709 1710 if (svm_xcr0_mask != 0) { 1711 /* Reset XSTATE_BV, to force a reload. */ 1712 cpudata->gfpu.xsh_xstate_bv = svm_xcr0_mask; 1713 } 1714 } 1715 1716 svm_vmcb_cache_update(vmcb, flags); 1717 } 1718 1719 static void 1720 svm_vcpu_getstate(struct nvmm_cpu *vcpu, void *data, uint64_t flags) 1721 { 1722 struct nvmm_x64_state *state = (struct nvmm_x64_state *)data; 1723 struct svm_cpudata *cpudata = vcpu->cpudata; 1724 struct vmcb *vmcb = cpudata->vmcb; 1725 1726 if (flags & NVMM_X64_STATE_SEGS) { 1727 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_CS], 1728 &vmcb->state.cs); 1729 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_DS], 1730 &vmcb->state.ds); 1731 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_ES], 1732 &vmcb->state.es); 1733 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_FS], 1734 &vmcb->state.fs); 1735 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_GS], 1736 &vmcb->state.gs); 1737 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_SS], 1738 &vmcb->state.ss); 1739 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_GDT], 1740 &vmcb->state.gdt); 1741 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_IDT], 1742 &vmcb->state.idt); 1743 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_LDT], 1744 &vmcb->state.ldt); 1745 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_TR], 1746 &vmcb->state.tr); 1747 1748 state->segs[NVMM_X64_SEG_SS].attrib.dpl = vmcb->state.cpl; 1749 } 1750 1751 CTASSERT(sizeof(cpudata->gprs) == sizeof(state->gprs)); 1752 if (flags & NVMM_X64_STATE_GPRS) { 1753 memcpy(state->gprs, cpudata->gprs, sizeof(state->gprs)); 1754 1755 state->gprs[NVMM_X64_GPR_RIP] = vmcb->state.rip; 1756 state->gprs[NVMM_X64_GPR_RSP] = vmcb->state.rsp; 1757 state->gprs[NVMM_X64_GPR_RAX] = vmcb->state.rax; 1758 state->gprs[NVMM_X64_GPR_RFLAGS] = vmcb->state.rflags; 1759 } 1760 1761 if (flags & NVMM_X64_STATE_CRS) { 1762 state->crs[NVMM_X64_CR_CR0] = vmcb->state.cr0; 1763 state->crs[NVMM_X64_CR_CR2] = vmcb->state.cr2; 1764 state->crs[NVMM_X64_CR_CR3] = vmcb->state.cr3; 1765 state->crs[NVMM_X64_CR_CR4] = vmcb->state.cr4; 1766 state->crs[NVMM_X64_CR_CR8] = __SHIFTOUT(vmcb->ctrl.v, 1767 VMCB_CTRL_V_TPR); 1768 state->crs[NVMM_X64_CR_XCR0] = cpudata->gxcr0; 1769 } 1770 1771 CTASSERT(sizeof(cpudata->drs) == sizeof(state->drs)); 1772 if (flags & NVMM_X64_STATE_DRS) { 1773 memcpy(state->drs, cpudata->drs, sizeof(state->drs)); 1774 1775 state->drs[NVMM_X64_DR_DR6] = vmcb->state.dr6; 1776 state->drs[NVMM_X64_DR_DR7] = vmcb->state.dr7; 1777 } 1778 1779 if (flags & NVMM_X64_STATE_MSRS) { 1780 state->msrs[NVMM_X64_MSR_EFER] = vmcb->state.efer; 1781 state->msrs[NVMM_X64_MSR_STAR] = vmcb->state.star; 1782 state->msrs[NVMM_X64_MSR_LSTAR] = vmcb->state.lstar; 1783 state->msrs[NVMM_X64_MSR_CSTAR] = vmcb->state.cstar; 1784 state->msrs[NVMM_X64_MSR_SFMASK] = vmcb->state.sfmask; 1785 state->msrs[NVMM_X64_MSR_KERNELGSBASE] = 1786 vmcb->state.kernelgsbase; 1787 state->msrs[NVMM_X64_MSR_SYSENTER_CS] = 1788 vmcb->state.sysenter_cs; 1789 state->msrs[NVMM_X64_MSR_SYSENTER_ESP] = 1790 vmcb->state.sysenter_esp; 1791 state->msrs[NVMM_X64_MSR_SYSENTER_EIP] = 1792 vmcb->state.sysenter_eip; 1793 state->msrs[NVMM_X64_MSR_PAT] = vmcb->state.g_pat; 1794 state->msrs[NVMM_X64_MSR_TSC] = cpudata->gtsc; 1795 1796 /* Hide SVME. */ 1797 state->msrs[NVMM_X64_MSR_EFER] &= ~EFER_SVME; 1798 } 1799 1800 if (flags & NVMM_X64_STATE_INTR) { 1801 state->intr.int_shadow = 1802 (vmcb->ctrl.intr & VMCB_CTRL_INTR_SHADOW) != 0; 1803 state->intr.int_window_exiting = cpudata->int_window_exit; 1804 state->intr.nmi_window_exiting = cpudata->nmi_window_exit; 1805 state->intr.evt_pending = cpudata->evt_pending; 1806 } 1807 1808 CTASSERT(sizeof(cpudata->gfpu.xsh_fxsave) == sizeof(state->fpu)); 1809 if (flags & NVMM_X64_STATE_FPU) { 1810 memcpy(&state->fpu, cpudata->gfpu.xsh_fxsave, 1811 sizeof(state->fpu)); 1812 } 1813 } 1814 1815 /* -------------------------------------------------------------------------- */ 1816 1817 static void 1818 svm_asid_alloc(struct nvmm_cpu *vcpu) 1819 { 1820 struct svm_cpudata *cpudata = vcpu->cpudata; 1821 struct vmcb *vmcb = cpudata->vmcb; 1822 size_t i, oct, bit; 1823 1824 mutex_enter(&svm_asidlock); 1825 1826 for (i = 0; i < svm_maxasid; i++) { 1827 oct = i / 8; 1828 bit = i % 8; 1829 1830 if (svm_asidmap[oct] & __BIT(bit)) { 1831 continue; 1832 } 1833 1834 svm_asidmap[oct] |= __BIT(bit); 1835 vmcb->ctrl.guest_asid = i; 1836 mutex_exit(&svm_asidlock); 1837 return; 1838 } 1839 1840 /* 1841 * No free ASID. Use the last one, which is shared and requires 1842 * special TLB handling. 1843 */ 1844 cpudata->shared_asid = true; 1845 vmcb->ctrl.guest_asid = svm_maxasid - 1; 1846 mutex_exit(&svm_asidlock); 1847 } 1848 1849 static void 1850 svm_asid_free(struct nvmm_cpu *vcpu) 1851 { 1852 struct svm_cpudata *cpudata = vcpu->cpudata; 1853 struct vmcb *vmcb = cpudata->vmcb; 1854 size_t oct, bit; 1855 1856 if (cpudata->shared_asid) { 1857 return; 1858 } 1859 1860 oct = vmcb->ctrl.guest_asid / 8; 1861 bit = vmcb->ctrl.guest_asid % 8; 1862 1863 mutex_enter(&svm_asidlock); 1864 svm_asidmap[oct] &= ~__BIT(bit); 1865 mutex_exit(&svm_asidlock); 1866 } 1867 1868 static void 1869 svm_vcpu_init(struct nvmm_machine *mach, struct nvmm_cpu *vcpu) 1870 { 1871 struct svm_cpudata *cpudata = vcpu->cpudata; 1872 struct vmcb *vmcb = cpudata->vmcb; 1873 1874 /* Allow reads/writes of Control Registers. */ 1875 vmcb->ctrl.intercept_cr = 0; 1876 1877 /* Allow reads/writes of Debug Registers. */ 1878 vmcb->ctrl.intercept_dr = 0; 1879 1880 /* Allow exceptions 0 to 31. */ 1881 vmcb->ctrl.intercept_vec = 0; 1882 1883 /* 1884 * Allow: 1885 * - SMI [smm interrupts] 1886 * - VINTR [virtual interrupts] 1887 * - CR0_SPEC [CR0 writes changing other fields than CR0.TS or CR0.MP] 1888 * - RIDTR [reads of IDTR] 1889 * - RGDTR [reads of GDTR] 1890 * - RLDTR [reads of LDTR] 1891 * - RTR [reads of TR] 1892 * - WIDTR [writes of IDTR] 1893 * - WGDTR [writes of GDTR] 1894 * - WLDTR [writes of LDTR] 1895 * - WTR [writes of TR] 1896 * - RDTSC [rdtsc instruction] 1897 * - PUSHF [pushf instruction] 1898 * - POPF [popf instruction] 1899 * - IRET [iret instruction] 1900 * - INTN [int $n instructions] 1901 * - INVD [invd instruction] 1902 * - PAUSE [pause instruction] 1903 * - INVLPG [invplg instruction] 1904 * - TASKSW [task switches] 1905 * 1906 * Intercept the rest below. 1907 */ 1908 vmcb->ctrl.intercept_misc1 = 1909 VMCB_CTRL_INTERCEPT_INTR | 1910 VMCB_CTRL_INTERCEPT_NMI | 1911 VMCB_CTRL_INTERCEPT_INIT | 1912 VMCB_CTRL_INTERCEPT_RDPMC | 1913 VMCB_CTRL_INTERCEPT_CPUID | 1914 VMCB_CTRL_INTERCEPT_RSM | 1915 VMCB_CTRL_INTERCEPT_HLT | 1916 VMCB_CTRL_INTERCEPT_INVLPGA | 1917 VMCB_CTRL_INTERCEPT_IOIO_PROT | 1918 VMCB_CTRL_INTERCEPT_MSR_PROT | 1919 VMCB_CTRL_INTERCEPT_FERR_FREEZE | 1920 VMCB_CTRL_INTERCEPT_SHUTDOWN; 1921 1922 /* 1923 * Allow: 1924 * - ICEBP [icebp instruction] 1925 * - WBINVD [wbinvd instruction] 1926 * - WCR_SPEC(0..15) [writes of CR0-15, received after instruction] 1927 * 1928 * Intercept the rest below. 1929 */ 1930 vmcb->ctrl.intercept_misc2 = 1931 VMCB_CTRL_INTERCEPT_VMRUN | 1932 VMCB_CTRL_INTERCEPT_VMMCALL | 1933 VMCB_CTRL_INTERCEPT_VMLOAD | 1934 VMCB_CTRL_INTERCEPT_VMSAVE | 1935 VMCB_CTRL_INTERCEPT_STGI | 1936 VMCB_CTRL_INTERCEPT_CLGI | 1937 VMCB_CTRL_INTERCEPT_SKINIT | 1938 VMCB_CTRL_INTERCEPT_RDTSCP | 1939 VMCB_CTRL_INTERCEPT_MONITOR | 1940 VMCB_CTRL_INTERCEPT_MWAIT | 1941 VMCB_CTRL_INTERCEPT_XSETBV; 1942 1943 /* Intercept all I/O accesses. */ 1944 memset(cpudata->iobm, 0xFF, IOBM_SIZE); 1945 vmcb->ctrl.iopm_base_pa = cpudata->iobm_pa; 1946 1947 /* Allow direct access to certain MSRs. */ 1948 memset(cpudata->msrbm, 0xFF, MSRBM_SIZE); 1949 svm_vcpu_msr_allow(cpudata->msrbm, MSR_EFER, true, false); 1950 svm_vcpu_msr_allow(cpudata->msrbm, MSR_STAR, true, true); 1951 svm_vcpu_msr_allow(cpudata->msrbm, MSR_LSTAR, true, true); 1952 svm_vcpu_msr_allow(cpudata->msrbm, MSR_CSTAR, true, true); 1953 svm_vcpu_msr_allow(cpudata->msrbm, MSR_SFMASK, true, true); 1954 svm_vcpu_msr_allow(cpudata->msrbm, MSR_KERNELGSBASE, true, true); 1955 svm_vcpu_msr_allow(cpudata->msrbm, MSR_SYSENTER_CS, true, true); 1956 svm_vcpu_msr_allow(cpudata->msrbm, MSR_SYSENTER_ESP, true, true); 1957 svm_vcpu_msr_allow(cpudata->msrbm, MSR_SYSENTER_EIP, true, true); 1958 svm_vcpu_msr_allow(cpudata->msrbm, MSR_FSBASE, true, true); 1959 svm_vcpu_msr_allow(cpudata->msrbm, MSR_GSBASE, true, true); 1960 svm_vcpu_msr_allow(cpudata->msrbm, MSR_CR_PAT, true, true); 1961 svm_vcpu_msr_allow(cpudata->msrbm, MSR_TSC, true, false); 1962 vmcb->ctrl.msrpm_base_pa = cpudata->msrbm_pa; 1963 1964 /* Generate ASID. */ 1965 svm_asid_alloc(vcpu); 1966 1967 /* Virtual TPR. */ 1968 vmcb->ctrl.v = VMCB_CTRL_V_INTR_MASKING; 1969 1970 /* Enable Nested Paging. */ 1971 vmcb->ctrl.enable1 = VMCB_CTRL_ENABLE_NP; 1972 vmcb->ctrl.n_cr3 = mach->vm->vm_map.pmap->pm_pdirpa[0]; 1973 1974 /* Init XSAVE header. */ 1975 cpudata->gfpu.xsh_xstate_bv = svm_xcr0_mask; 1976 cpudata->gfpu.xsh_xcomp_bv = 0; 1977 1978 /* These MSRs are static. */ 1979 cpudata->star = rdmsr(MSR_STAR); 1980 cpudata->lstar = rdmsr(MSR_LSTAR); 1981 cpudata->cstar = rdmsr(MSR_CSTAR); 1982 cpudata->sfmask = rdmsr(MSR_SFMASK); 1983 1984 /* Install the RESET state. */ 1985 svm_vcpu_setstate(vcpu, &nvmm_x86_reset_state, NVMM_X64_STATE_ALL); 1986 } 1987 1988 static int 1989 svm_vcpu_create(struct nvmm_machine *mach, struct nvmm_cpu *vcpu) 1990 { 1991 struct svm_cpudata *cpudata; 1992 int error; 1993 1994 /* Allocate the SVM cpudata. */ 1995 cpudata = (struct svm_cpudata *)uvm_km_alloc(kernel_map, 1996 roundup(sizeof(*cpudata), PAGE_SIZE), 0, 1997 UVM_KMF_WIRED|UVM_KMF_ZERO); 1998 vcpu->cpudata = cpudata; 1999 2000 /* VMCB */ 2001 error = svm_memalloc(&cpudata->vmcb_pa, (vaddr_t *)&cpudata->vmcb, 2002 VMCB_NPAGES); 2003 if (error) 2004 goto error; 2005 2006 /* I/O Bitmap */ 2007 error = svm_memalloc(&cpudata->iobm_pa, (vaddr_t *)&cpudata->iobm, 2008 IOBM_NPAGES); 2009 if (error) 2010 goto error; 2011 2012 /* MSR Bitmap */ 2013 error = svm_memalloc(&cpudata->msrbm_pa, (vaddr_t *)&cpudata->msrbm, 2014 MSRBM_NPAGES); 2015 if (error) 2016 goto error; 2017 2018 /* Init the VCPU info. */ 2019 svm_vcpu_init(mach, vcpu); 2020 2021 return 0; 2022 2023 error: 2024 if (cpudata->vmcb_pa) { 2025 svm_memfree(cpudata->vmcb_pa, (vaddr_t)cpudata->vmcb, 2026 VMCB_NPAGES); 2027 } 2028 if (cpudata->iobm_pa) { 2029 svm_memfree(cpudata->iobm_pa, (vaddr_t)cpudata->iobm, 2030 IOBM_NPAGES); 2031 } 2032 if (cpudata->msrbm_pa) { 2033 svm_memfree(cpudata->msrbm_pa, (vaddr_t)cpudata->msrbm, 2034 MSRBM_NPAGES); 2035 } 2036 uvm_km_free(kernel_map, (vaddr_t)cpudata, 2037 roundup(sizeof(*cpudata), PAGE_SIZE), UVM_KMF_WIRED); 2038 return error; 2039 } 2040 2041 static void 2042 svm_vcpu_destroy(struct nvmm_machine *mach, struct nvmm_cpu *vcpu) 2043 { 2044 struct svm_cpudata *cpudata = vcpu->cpudata; 2045 2046 svm_asid_free(vcpu); 2047 2048 svm_memfree(cpudata->vmcb_pa, (vaddr_t)cpudata->vmcb, VMCB_NPAGES); 2049 svm_memfree(cpudata->iobm_pa, (vaddr_t)cpudata->iobm, IOBM_NPAGES); 2050 svm_memfree(cpudata->msrbm_pa, (vaddr_t)cpudata->msrbm, MSRBM_NPAGES); 2051 2052 uvm_km_free(kernel_map, (vaddr_t)cpudata, 2053 roundup(sizeof(*cpudata), PAGE_SIZE), UVM_KMF_WIRED); 2054 } 2055 2056 /* -------------------------------------------------------------------------- */ 2057 2058 static void 2059 svm_tlb_flush(struct pmap *pm) 2060 { 2061 struct nvmm_machine *mach = pm->pm_data; 2062 struct svm_machdata *machdata = mach->machdata; 2063 2064 atomic_inc_64(&machdata->mach_htlb_gen); 2065 2066 /* Generates IPIs, which cause #VMEXITs. */ 2067 pmap_tlb_shootdown(pmap_kernel(), -1, PG_G, TLBSHOOT_UPDATE); 2068 } 2069 2070 static void 2071 svm_machine_create(struct nvmm_machine *mach) 2072 { 2073 struct svm_machdata *machdata; 2074 2075 /* Fill in pmap info. */ 2076 mach->vm->vm_map.pmap->pm_data = (void *)mach; 2077 mach->vm->vm_map.pmap->pm_tlb_flush = svm_tlb_flush; 2078 2079 machdata = kmem_zalloc(sizeof(struct svm_machdata), KM_SLEEP); 2080 mach->machdata = machdata; 2081 2082 /* Start with an hTLB flush everywhere. */ 2083 machdata->mach_htlb_gen = 1; 2084 } 2085 2086 static void 2087 svm_machine_destroy(struct nvmm_machine *mach) 2088 { 2089 kmem_free(mach->machdata, sizeof(struct svm_machdata)); 2090 } 2091 2092 static int 2093 svm_machine_configure(struct nvmm_machine *mach, uint64_t op, void *data) 2094 { 2095 struct nvmm_x86_conf_cpuid *cpuid = data; 2096 struct svm_machdata *machdata = (struct svm_machdata *)mach->machdata; 2097 size_t i; 2098 2099 if (__predict_false(op != NVMM_X86_CONF_CPUID)) { 2100 return EINVAL; 2101 } 2102 2103 if (__predict_false((cpuid->set.eax & cpuid->del.eax) || 2104 (cpuid->set.ebx & cpuid->del.ebx) || 2105 (cpuid->set.ecx & cpuid->del.ecx) || 2106 (cpuid->set.edx & cpuid->del.edx))) { 2107 return EINVAL; 2108 } 2109 2110 /* If already here, replace. */ 2111 for (i = 0; i < SVM_NCPUIDS; i++) { 2112 if (!machdata->cpuidpresent[i]) { 2113 continue; 2114 } 2115 if (machdata->cpuid[i].leaf == cpuid->leaf) { 2116 memcpy(&machdata->cpuid[i], cpuid, 2117 sizeof(struct nvmm_x86_conf_cpuid)); 2118 return 0; 2119 } 2120 } 2121 2122 /* Not here, insert. */ 2123 for (i = 0; i < SVM_NCPUIDS; i++) { 2124 if (!machdata->cpuidpresent[i]) { 2125 machdata->cpuidpresent[i] = true; 2126 memcpy(&machdata->cpuid[i], cpuid, 2127 sizeof(struct nvmm_x86_conf_cpuid)); 2128 return 0; 2129 } 2130 } 2131 2132 return ENOBUFS; 2133 } 2134 2135 /* -------------------------------------------------------------------------- */ 2136 2137 static bool 2138 svm_ident(void) 2139 { 2140 u_int descs[4]; 2141 uint64_t msr; 2142 2143 if (cpu_vendor != CPUVENDOR_AMD) { 2144 return false; 2145 } 2146 if (!(cpu_feature[3] & CPUID_SVM)) { 2147 return false; 2148 } 2149 2150 if (curcpu()->ci_max_ext_cpuid < 0x8000000a) { 2151 return false; 2152 } 2153 x86_cpuid(0x8000000a, descs); 2154 2155 /* Want Nested Paging. */ 2156 if (!(descs[3] & CPUID_AMD_SVM_NP)) { 2157 return false; 2158 } 2159 2160 /* Want nRIP. */ 2161 if (!(descs[3] & CPUID_AMD_SVM_NRIPS)) { 2162 return false; 2163 } 2164 2165 svm_decode_assist = (descs[3] & CPUID_AMD_SVM_DecodeAssist) != 0; 2166 2167 msr = rdmsr(MSR_VMCR); 2168 if ((msr & VMCR_SVMED) && (msr & VMCR_LOCK)) { 2169 return false; 2170 } 2171 2172 return true; 2173 } 2174 2175 static void 2176 svm_init_asid(uint32_t maxasid) 2177 { 2178 size_t i, j, allocsz; 2179 2180 mutex_init(&svm_asidlock, MUTEX_DEFAULT, IPL_NONE); 2181 2182 /* Arbitrarily limit. */ 2183 maxasid = uimin(maxasid, 8192); 2184 2185 svm_maxasid = maxasid; 2186 allocsz = roundup(maxasid, 8) / 8; 2187 svm_asidmap = kmem_zalloc(allocsz, KM_SLEEP); 2188 2189 /* ASID 0 is reserved for the host. */ 2190 svm_asidmap[0] |= __BIT(0); 2191 2192 /* ASID n-1 is special, we share it. */ 2193 i = (maxasid - 1) / 8; 2194 j = (maxasid - 1) % 8; 2195 svm_asidmap[i] |= __BIT(j); 2196 } 2197 2198 static void 2199 svm_change_cpu(void *arg1, void *arg2) 2200 { 2201 bool enable = (bool)arg1; 2202 uint64_t msr; 2203 2204 msr = rdmsr(MSR_VMCR); 2205 if (msr & VMCR_SVMED) { 2206 wrmsr(MSR_VMCR, msr & ~VMCR_SVMED); 2207 } 2208 2209 if (!enable) { 2210 wrmsr(MSR_VM_HSAVE_PA, 0); 2211 } 2212 2213 msr = rdmsr(MSR_EFER); 2214 if (enable) { 2215 msr |= EFER_SVME; 2216 } else { 2217 msr &= ~EFER_SVME; 2218 } 2219 wrmsr(MSR_EFER, msr); 2220 2221 if (enable) { 2222 wrmsr(MSR_VM_HSAVE_PA, hsave[cpu_index(curcpu())].pa); 2223 } 2224 } 2225 2226 static void 2227 svm_init(void) 2228 { 2229 CPU_INFO_ITERATOR cii; 2230 struct cpu_info *ci; 2231 struct vm_page *pg; 2232 u_int descs[4]; 2233 uint64_t xc; 2234 2235 x86_cpuid(0x8000000a, descs); 2236 2237 /* The guest TLB flush command. */ 2238 if (descs[3] & CPUID_AMD_SVM_FlushByASID) { 2239 svm_ctrl_tlb_flush = VMCB_CTRL_TLB_CTRL_FLUSH_GUEST; 2240 } else { 2241 svm_ctrl_tlb_flush = VMCB_CTRL_TLB_CTRL_FLUSH_ALL; 2242 } 2243 2244 /* Init the ASID. */ 2245 svm_init_asid(descs[1]); 2246 2247 /* Init the XCR0 mask. */ 2248 svm_xcr0_mask = SVM_XCR0_MASK_DEFAULT & x86_xsave_features; 2249 2250 memset(hsave, 0, sizeof(hsave)); 2251 for (CPU_INFO_FOREACH(cii, ci)) { 2252 pg = uvm_pagealloc(NULL, 0, NULL, UVM_PGA_ZERO); 2253 hsave[cpu_index(ci)].pa = VM_PAGE_TO_PHYS(pg); 2254 } 2255 2256 xc = xc_broadcast(0, svm_change_cpu, (void *)true, NULL); 2257 xc_wait(xc); 2258 } 2259 2260 static void 2261 svm_fini_asid(void) 2262 { 2263 size_t allocsz; 2264 2265 allocsz = roundup(svm_maxasid, 8) / 8; 2266 kmem_free(svm_asidmap, allocsz); 2267 2268 mutex_destroy(&svm_asidlock); 2269 } 2270 2271 static void 2272 svm_fini(void) 2273 { 2274 uint64_t xc; 2275 size_t i; 2276 2277 xc = xc_broadcast(0, svm_change_cpu, (void *)false, NULL); 2278 xc_wait(xc); 2279 2280 for (i = 0; i < MAXCPUS; i++) { 2281 if (hsave[i].pa != 0) 2282 uvm_pagefree(PHYS_TO_VM_PAGE(hsave[i].pa)); 2283 } 2284 2285 svm_fini_asid(); 2286 } 2287 2288 static void 2289 svm_capability(struct nvmm_capability *cap) 2290 { 2291 cap->u.x86.xcr0_mask = svm_xcr0_mask; 2292 cap->u.x86.mxcsr_mask = x86_fpu_mxcsr_mask; 2293 cap->u.x86.conf_cpuid_maxops = SVM_NCPUIDS; 2294 } 2295 2296 const struct nvmm_impl nvmm_x86_svm = { 2297 .ident = svm_ident, 2298 .init = svm_init, 2299 .fini = svm_fini, 2300 .capability = svm_capability, 2301 .conf_max = NVMM_X86_NCONF, 2302 .conf_sizes = svm_conf_sizes, 2303 .state_size = sizeof(struct nvmm_x64_state), 2304 .machine_create = svm_machine_create, 2305 .machine_destroy = svm_machine_destroy, 2306 .machine_configure = svm_machine_configure, 2307 .vcpu_create = svm_vcpu_create, 2308 .vcpu_destroy = svm_vcpu_destroy, 2309 .vcpu_setstate = svm_vcpu_setstate, 2310 .vcpu_getstate = svm_vcpu_getstate, 2311 .vcpu_inject = svm_vcpu_inject, 2312 .vcpu_run = svm_vcpu_run 2313 }; 2314
Indexes created Tue Sep 30 20:09:53 GMT 2025