nvmm_x86_svm.c revision 1.46.4.2
1 /* $NetBSD: nvmm_x86_svm.c,v 1.46.4.2 2019/11/10 12:58:30 martin Exp $ */ 2 3 /* 4 * Copyright (c) 2018-2019 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Maxime Villard. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: nvmm_x86_svm.c,v 1.46.4.2 2019/11/10 12:58:30 martin Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/kmem.h> 39 #include <sys/cpu.h> 40 #include <sys/xcall.h> 41 #include <sys/mman.h> 42 43 #include <uvm/uvm.h> 44 #include <uvm/uvm_page.h> 45 46 #include <x86/cputypes.h> 47 #include <x86/specialreg.h> 48 #include <x86/pmap.h> 49 #include <x86/dbregs.h> 50 #include <x86/cpu_counter.h> 51 #include <machine/cpuvar.h> 52 53 #include <dev/nvmm/nvmm.h> 54 #include <dev/nvmm/nvmm_internal.h> 55 #include <dev/nvmm/x86/nvmm_x86.h> 56 57 int svm_vmrun(paddr_t, uint64_t *); 58 59 #define MSR_VM_HSAVE_PA 0xC0010117 60 61 /* -------------------------------------------------------------------------- */ 62 63 #define VMCB_EXITCODE_CR0_READ 0x0000 64 #define VMCB_EXITCODE_CR1_READ 0x0001 65 #define VMCB_EXITCODE_CR2_READ 0x0002 66 #define VMCB_EXITCODE_CR3_READ 0x0003 67 #define VMCB_EXITCODE_CR4_READ 0x0004 68 #define VMCB_EXITCODE_CR5_READ 0x0005 69 #define VMCB_EXITCODE_CR6_READ 0x0006 70 #define VMCB_EXITCODE_CR7_READ 0x0007 71 #define VMCB_EXITCODE_CR8_READ 0x0008 72 #define VMCB_EXITCODE_CR9_READ 0x0009 73 #define VMCB_EXITCODE_CR10_READ 0x000A 74 #define VMCB_EXITCODE_CR11_READ 0x000B 75 #define VMCB_EXITCODE_CR12_READ 0x000C 76 #define VMCB_EXITCODE_CR13_READ 0x000D 77 #define VMCB_EXITCODE_CR14_READ 0x000E 78 #define VMCB_EXITCODE_CR15_READ 0x000F 79 #define VMCB_EXITCODE_CR0_WRITE 0x0010 80 #define VMCB_EXITCODE_CR1_WRITE 0x0011 81 #define VMCB_EXITCODE_CR2_WRITE 0x0012 82 #define VMCB_EXITCODE_CR3_WRITE 0x0013 83 #define VMCB_EXITCODE_CR4_WRITE 0x0014 84 #define VMCB_EXITCODE_CR5_WRITE 0x0015 85 #define VMCB_EXITCODE_CR6_WRITE 0x0016 86 #define VMCB_EXITCODE_CR7_WRITE 0x0017 87 #define VMCB_EXITCODE_CR8_WRITE 0x0018 88 #define VMCB_EXITCODE_CR9_WRITE 0x0019 89 #define VMCB_EXITCODE_CR10_WRITE 0x001A 90 #define VMCB_EXITCODE_CR11_WRITE 0x001B 91 #define VMCB_EXITCODE_CR12_WRITE 0x001C 92 #define VMCB_EXITCODE_CR13_WRITE 0x001D 93 #define VMCB_EXITCODE_CR14_WRITE 0x001E 94 #define VMCB_EXITCODE_CR15_WRITE 0x001F 95 #define VMCB_EXITCODE_DR0_READ 0x0020 96 #define VMCB_EXITCODE_DR1_READ 0x0021 97 #define VMCB_EXITCODE_DR2_READ 0x0022 98 #define VMCB_EXITCODE_DR3_READ 0x0023 99 #define VMCB_EXITCODE_DR4_READ 0x0024 100 #define VMCB_EXITCODE_DR5_READ 0x0025 101 #define VMCB_EXITCODE_DR6_READ 0x0026 102 #define VMCB_EXITCODE_DR7_READ 0x0027 103 #define VMCB_EXITCODE_DR8_READ 0x0028 104 #define VMCB_EXITCODE_DR9_READ 0x0029 105 #define VMCB_EXITCODE_DR10_READ 0x002A 106 #define VMCB_EXITCODE_DR11_READ 0x002B 107 #define VMCB_EXITCODE_DR12_READ 0x002C 108 #define VMCB_EXITCODE_DR13_READ 0x002D 109 #define VMCB_EXITCODE_DR14_READ 0x002E 110 #define VMCB_EXITCODE_DR15_READ 0x002F 111 #define VMCB_EXITCODE_DR0_WRITE 0x0030 112 #define VMCB_EXITCODE_DR1_WRITE 0x0031 113 #define VMCB_EXITCODE_DR2_WRITE 0x0032 114 #define VMCB_EXITCODE_DR3_WRITE 0x0033 115 #define VMCB_EXITCODE_DR4_WRITE 0x0034 116 #define VMCB_EXITCODE_DR5_WRITE 0x0035 117 #define VMCB_EXITCODE_DR6_WRITE 0x0036 118 #define VMCB_EXITCODE_DR7_WRITE 0x0037 119 #define VMCB_EXITCODE_DR8_WRITE 0x0038 120 #define VMCB_EXITCODE_DR9_WRITE 0x0039 121 #define VMCB_EXITCODE_DR10_WRITE 0x003A 122 #define VMCB_EXITCODE_DR11_WRITE 0x003B 123 #define VMCB_EXITCODE_DR12_WRITE 0x003C 124 #define VMCB_EXITCODE_DR13_WRITE 0x003D 125 #define VMCB_EXITCODE_DR14_WRITE 0x003E 126 #define VMCB_EXITCODE_DR15_WRITE 0x003F 127 #define VMCB_EXITCODE_EXCP0 0x0040 128 #define VMCB_EXITCODE_EXCP1 0x0041 129 #define VMCB_EXITCODE_EXCP2 0x0042 130 #define VMCB_EXITCODE_EXCP3 0x0043 131 #define VMCB_EXITCODE_EXCP4 0x0044 132 #define VMCB_EXITCODE_EXCP5 0x0045 133 #define VMCB_EXITCODE_EXCP6 0x0046 134 #define VMCB_EXITCODE_EXCP7 0x0047 135 #define VMCB_EXITCODE_EXCP8 0x0048 136 #define VMCB_EXITCODE_EXCP9 0x0049 137 #define VMCB_EXITCODE_EXCP10 0x004A 138 #define VMCB_EXITCODE_EXCP11 0x004B 139 #define VMCB_EXITCODE_EXCP12 0x004C 140 #define VMCB_EXITCODE_EXCP13 0x004D 141 #define VMCB_EXITCODE_EXCP14 0x004E 142 #define VMCB_EXITCODE_EXCP15 0x004F 143 #define VMCB_EXITCODE_EXCP16 0x0050 144 #define VMCB_EXITCODE_EXCP17 0x0051 145 #define VMCB_EXITCODE_EXCP18 0x0052 146 #define VMCB_EXITCODE_EXCP19 0x0053 147 #define VMCB_EXITCODE_EXCP20 0x0054 148 #define VMCB_EXITCODE_EXCP21 0x0055 149 #define VMCB_EXITCODE_EXCP22 0x0056 150 #define VMCB_EXITCODE_EXCP23 0x0057 151 #define VMCB_EXITCODE_EXCP24 0x0058 152 #define VMCB_EXITCODE_EXCP25 0x0059 153 #define VMCB_EXITCODE_EXCP26 0x005A 154 #define VMCB_EXITCODE_EXCP27 0x005B 155 #define VMCB_EXITCODE_EXCP28 0x005C 156 #define VMCB_EXITCODE_EXCP29 0x005D 157 #define VMCB_EXITCODE_EXCP30 0x005E 158 #define VMCB_EXITCODE_EXCP31 0x005F 159 #define VMCB_EXITCODE_INTR 0x0060 160 #define VMCB_EXITCODE_NMI 0x0061 161 #define VMCB_EXITCODE_SMI 0x0062 162 #define VMCB_EXITCODE_INIT 0x0063 163 #define VMCB_EXITCODE_VINTR 0x0064 164 #define VMCB_EXITCODE_CR0_SEL_WRITE 0x0065 165 #define VMCB_EXITCODE_IDTR_READ 0x0066 166 #define VMCB_EXITCODE_GDTR_READ 0x0067 167 #define VMCB_EXITCODE_LDTR_READ 0x0068 168 #define VMCB_EXITCODE_TR_READ 0x0069 169 #define VMCB_EXITCODE_IDTR_WRITE 0x006A 170 #define VMCB_EXITCODE_GDTR_WRITE 0x006B 171 #define VMCB_EXITCODE_LDTR_WRITE 0x006C 172 #define VMCB_EXITCODE_TR_WRITE 0x006D 173 #define VMCB_EXITCODE_RDTSC 0x006E 174 #define VMCB_EXITCODE_RDPMC 0x006F 175 #define VMCB_EXITCODE_PUSHF 0x0070 176 #define VMCB_EXITCODE_POPF 0x0071 177 #define VMCB_EXITCODE_CPUID 0x0072 178 #define VMCB_EXITCODE_RSM 0x0073 179 #define VMCB_EXITCODE_IRET 0x0074 180 #define VMCB_EXITCODE_SWINT 0x0075 181 #define VMCB_EXITCODE_INVD 0x0076 182 #define VMCB_EXITCODE_PAUSE 0x0077 183 #define VMCB_EXITCODE_HLT 0x0078 184 #define VMCB_EXITCODE_INVLPG 0x0079 185 #define VMCB_EXITCODE_INVLPGA 0x007A 186 #define VMCB_EXITCODE_IOIO 0x007B 187 #define VMCB_EXITCODE_MSR 0x007C 188 #define VMCB_EXITCODE_TASK_SWITCH 0x007D 189 #define VMCB_EXITCODE_FERR_FREEZE 0x007E 190 #define VMCB_EXITCODE_SHUTDOWN 0x007F 191 #define VMCB_EXITCODE_VMRUN 0x0080 192 #define VMCB_EXITCODE_VMMCALL 0x0081 193 #define VMCB_EXITCODE_VMLOAD 0x0082 194 #define VMCB_EXITCODE_VMSAVE 0x0083 195 #define VMCB_EXITCODE_STGI 0x0084 196 #define VMCB_EXITCODE_CLGI 0x0085 197 #define VMCB_EXITCODE_SKINIT 0x0086 198 #define VMCB_EXITCODE_RDTSCP 0x0087 199 #define VMCB_EXITCODE_ICEBP 0x0088 200 #define VMCB_EXITCODE_WBINVD 0x0089 201 #define VMCB_EXITCODE_MONITOR 0x008A 202 #define VMCB_EXITCODE_MWAIT 0x008B 203 #define VMCB_EXITCODE_MWAIT_CONDITIONAL 0x008C 204 #define VMCB_EXITCODE_XSETBV 0x008D 205 #define VMCB_EXITCODE_RDPRU 0x008E 206 #define VMCB_EXITCODE_EFER_WRITE_TRAP 0x008F 207 #define VMCB_EXITCODE_CR0_WRITE_TRAP 0x0090 208 #define VMCB_EXITCODE_CR1_WRITE_TRAP 0x0091 209 #define VMCB_EXITCODE_CR2_WRITE_TRAP 0x0092 210 #define VMCB_EXITCODE_CR3_WRITE_TRAP 0x0093 211 #define VMCB_EXITCODE_CR4_WRITE_TRAP 0x0094 212 #define VMCB_EXITCODE_CR5_WRITE_TRAP 0x0095 213 #define VMCB_EXITCODE_CR6_WRITE_TRAP 0x0096 214 #define VMCB_EXITCODE_CR7_WRITE_TRAP 0x0097 215 #define VMCB_EXITCODE_CR8_WRITE_TRAP 0x0098 216 #define VMCB_EXITCODE_CR9_WRITE_TRAP 0x0099 217 #define VMCB_EXITCODE_CR10_WRITE_TRAP 0x009A 218 #define VMCB_EXITCODE_CR11_WRITE_TRAP 0x009B 219 #define VMCB_EXITCODE_CR12_WRITE_TRAP 0x009C 220 #define VMCB_EXITCODE_CR13_WRITE_TRAP 0x009D 221 #define VMCB_EXITCODE_CR14_WRITE_TRAP 0x009E 222 #define VMCB_EXITCODE_CR15_WRITE_TRAP 0x009F 223 #define VMCB_EXITCODE_MCOMMIT 0x00A3 224 #define VMCB_EXITCODE_NPF 0x0400 225 #define VMCB_EXITCODE_AVIC_INCOMP_IPI 0x0401 226 #define VMCB_EXITCODE_AVIC_NOACCEL 0x0402 227 #define VMCB_EXITCODE_VMGEXIT 0x0403 228 #define VMCB_EXITCODE_INVALID -1 229 230 /* -------------------------------------------------------------------------- */ 231 232 struct vmcb_ctrl { 233 uint32_t intercept_cr; 234 #define VMCB_CTRL_INTERCEPT_RCR(x) __BIT( 0 + x) 235 #define VMCB_CTRL_INTERCEPT_WCR(x) __BIT(16 + x) 236 237 uint32_t intercept_dr; 238 #define VMCB_CTRL_INTERCEPT_RDR(x) __BIT( 0 + x) 239 #define VMCB_CTRL_INTERCEPT_WDR(x) __BIT(16 + x) 240 241 uint32_t intercept_vec; 242 #define VMCB_CTRL_INTERCEPT_VEC(x) __BIT(x) 243 244 uint32_t intercept_misc1; 245 #define VMCB_CTRL_INTERCEPT_INTR __BIT(0) 246 #define VMCB_CTRL_INTERCEPT_NMI __BIT(1) 247 #define VMCB_CTRL_INTERCEPT_SMI __BIT(2) 248 #define VMCB_CTRL_INTERCEPT_INIT __BIT(3) 249 #define VMCB_CTRL_INTERCEPT_VINTR __BIT(4) 250 #define VMCB_CTRL_INTERCEPT_CR0_SPEC __BIT(5) 251 #define VMCB_CTRL_INTERCEPT_RIDTR __BIT(6) 252 #define VMCB_CTRL_INTERCEPT_RGDTR __BIT(7) 253 #define VMCB_CTRL_INTERCEPT_RLDTR __BIT(8) 254 #define VMCB_CTRL_INTERCEPT_RTR __BIT(9) 255 #define VMCB_CTRL_INTERCEPT_WIDTR __BIT(10) 256 #define VMCB_CTRL_INTERCEPT_WGDTR __BIT(11) 257 #define VMCB_CTRL_INTERCEPT_WLDTR __BIT(12) 258 #define VMCB_CTRL_INTERCEPT_WTR __BIT(13) 259 #define VMCB_CTRL_INTERCEPT_RDTSC __BIT(14) 260 #define VMCB_CTRL_INTERCEPT_RDPMC __BIT(15) 261 #define VMCB_CTRL_INTERCEPT_PUSHF __BIT(16) 262 #define VMCB_CTRL_INTERCEPT_POPF __BIT(17) 263 #define VMCB_CTRL_INTERCEPT_CPUID __BIT(18) 264 #define VMCB_CTRL_INTERCEPT_RSM __BIT(19) 265 #define VMCB_CTRL_INTERCEPT_IRET __BIT(20) 266 #define VMCB_CTRL_INTERCEPT_INTN __BIT(21) 267 #define VMCB_CTRL_INTERCEPT_INVD __BIT(22) 268 #define VMCB_CTRL_INTERCEPT_PAUSE __BIT(23) 269 #define VMCB_CTRL_INTERCEPT_HLT __BIT(24) 270 #define VMCB_CTRL_INTERCEPT_INVLPG __BIT(25) 271 #define VMCB_CTRL_INTERCEPT_INVLPGA __BIT(26) 272 #define VMCB_CTRL_INTERCEPT_IOIO_PROT __BIT(27) 273 #define VMCB_CTRL_INTERCEPT_MSR_PROT __BIT(28) 274 #define VMCB_CTRL_INTERCEPT_TASKSW __BIT(29) 275 #define VMCB_CTRL_INTERCEPT_FERR_FREEZE __BIT(30) 276 #define VMCB_CTRL_INTERCEPT_SHUTDOWN __BIT(31) 277 278 uint32_t intercept_misc2; 279 #define VMCB_CTRL_INTERCEPT_VMRUN __BIT(0) 280 #define VMCB_CTRL_INTERCEPT_VMMCALL __BIT(1) 281 #define VMCB_CTRL_INTERCEPT_VMLOAD __BIT(2) 282 #define VMCB_CTRL_INTERCEPT_VMSAVE __BIT(3) 283 #define VMCB_CTRL_INTERCEPT_STGI __BIT(4) 284 #define VMCB_CTRL_INTERCEPT_CLGI __BIT(5) 285 #define VMCB_CTRL_INTERCEPT_SKINIT __BIT(6) 286 #define VMCB_CTRL_INTERCEPT_RDTSCP __BIT(7) 287 #define VMCB_CTRL_INTERCEPT_ICEBP __BIT(8) 288 #define VMCB_CTRL_INTERCEPT_WBINVD __BIT(9) 289 #define VMCB_CTRL_INTERCEPT_MONITOR __BIT(10) 290 #define VMCB_CTRL_INTERCEPT_MWAIT __BIT(11) 291 #define VMCB_CTRL_INTERCEPT_MWAIT_ARMED __BIT(12) 292 #define VMCB_CTRL_INTERCEPT_XSETBV __BIT(13) 293 #define VMCB_CTRL_INTERCEPT_RDPRU __BIT(14) 294 #define VMCB_CTRL_INTERCEPT_EFER_SPEC __BIT(15) 295 #define VMCB_CTRL_INTERCEPT_WCR_SPEC(x) __BIT(16 + x) 296 297 uint32_t intercept_misc3; 298 #define VMCB_CTRL_INTERCEPT_MCOMMIT __BIT(3) 299 300 uint8_t rsvd1[36]; 301 uint16_t pause_filt_thresh; 302 uint16_t pause_filt_cnt; 303 uint64_t iopm_base_pa; 304 uint64_t msrpm_base_pa; 305 uint64_t tsc_offset; 306 uint32_t guest_asid; 307 308 uint32_t tlb_ctrl; 309 #define VMCB_CTRL_TLB_CTRL_FLUSH_ALL 0x01 310 #define VMCB_CTRL_TLB_CTRL_FLUSH_GUEST 0x03 311 #define VMCB_CTRL_TLB_CTRL_FLUSH_GUEST_NONGLOBAL 0x07 312 313 uint64_t v; 314 #define VMCB_CTRL_V_TPR __BITS(3,0) 315 #define VMCB_CTRL_V_IRQ __BIT(8) 316 #define VMCB_CTRL_V_VGIF __BIT(9) 317 #define VMCB_CTRL_V_INTR_PRIO __BITS(19,16) 318 #define VMCB_CTRL_V_IGN_TPR __BIT(20) 319 #define VMCB_CTRL_V_INTR_MASKING __BIT(24) 320 #define VMCB_CTRL_V_GUEST_VGIF __BIT(25) 321 #define VMCB_CTRL_V_AVIC_EN __BIT(31) 322 #define VMCB_CTRL_V_INTR_VECTOR __BITS(39,32) 323 324 uint64_t intr; 325 #define VMCB_CTRL_INTR_SHADOW __BIT(0) 326 327 uint64_t exitcode; 328 uint64_t exitinfo1; 329 uint64_t exitinfo2; 330 331 uint64_t exitintinfo; 332 #define VMCB_CTRL_EXITINTINFO_VECTOR __BITS(7,0) 333 #define VMCB_CTRL_EXITINTINFO_TYPE __BITS(10,8) 334 #define VMCB_CTRL_EXITINTINFO_EV __BIT(11) 335 #define VMCB_CTRL_EXITINTINFO_V __BIT(31) 336 #define VMCB_CTRL_EXITINTINFO_ERRORCODE __BITS(63,32) 337 338 uint64_t enable1; 339 #define VMCB_CTRL_ENABLE_NP __BIT(0) 340 #define VMCB_CTRL_ENABLE_SEV __BIT(1) 341 #define VMCB_CTRL_ENABLE_ES_SEV __BIT(2) 342 #define VMCB_CTRL_ENABLE_GMET __BIT(3) 343 #define VMCB_CTRL_ENABLE_VTE __BIT(5) 344 345 uint64_t avic; 346 #define VMCB_CTRL_AVIC_APIC_BAR __BITS(51,0) 347 348 uint64_t ghcb; 349 350 uint64_t eventinj; 351 #define VMCB_CTRL_EVENTINJ_VECTOR __BITS(7,0) 352 #define VMCB_CTRL_EVENTINJ_TYPE __BITS(10,8) 353 #define VMCB_CTRL_EVENTINJ_EV __BIT(11) 354 #define VMCB_CTRL_EVENTINJ_V __BIT(31) 355 #define VMCB_CTRL_EVENTINJ_ERRORCODE __BITS(63,32) 356 357 uint64_t n_cr3; 358 359 uint64_t enable2; 360 #define VMCB_CTRL_ENABLE_LBR __BIT(0) 361 #define VMCB_CTRL_ENABLE_VVMSAVE __BIT(1) 362 363 uint32_t vmcb_clean; 364 #define VMCB_CTRL_VMCB_CLEAN_I __BIT(0) 365 #define VMCB_CTRL_VMCB_CLEAN_IOPM __BIT(1) 366 #define VMCB_CTRL_VMCB_CLEAN_ASID __BIT(2) 367 #define VMCB_CTRL_VMCB_CLEAN_TPR __BIT(3) 368 #define VMCB_CTRL_VMCB_CLEAN_NP __BIT(4) 369 #define VMCB_CTRL_VMCB_CLEAN_CR __BIT(5) 370 #define VMCB_CTRL_VMCB_CLEAN_DR __BIT(6) 371 #define VMCB_CTRL_VMCB_CLEAN_DT __BIT(7) 372 #define VMCB_CTRL_VMCB_CLEAN_SEG __BIT(8) 373 #define VMCB_CTRL_VMCB_CLEAN_CR2 __BIT(9) 374 #define VMCB_CTRL_VMCB_CLEAN_LBR __BIT(10) 375 #define VMCB_CTRL_VMCB_CLEAN_AVIC __BIT(11) 376 377 uint32_t rsvd2; 378 uint64_t nrip; 379 uint8_t inst_len; 380 uint8_t inst_bytes[15]; 381 uint64_t avic_abpp; 382 uint64_t rsvd3; 383 uint64_t avic_ltp; 384 385 uint64_t avic_phys; 386 #define VMCB_CTRL_AVIC_PHYS_TABLE_PTR __BITS(51,12) 387 #define VMCB_CTRL_AVIC_PHYS_MAX_INDEX __BITS(7,0) 388 389 uint64_t rsvd4; 390 uint64_t vmcb_ptr; 391 392 uint8_t pad[752]; 393 } __packed; 394 395 CTASSERT(sizeof(struct vmcb_ctrl) == 1024); 396 397 struct vmcb_segment { 398 uint16_t selector; 399 uint16_t attrib; /* hidden */ 400 uint32_t limit; /* hidden */ 401 uint64_t base; /* hidden */ 402 } __packed; 403 404 CTASSERT(sizeof(struct vmcb_segment) == 16); 405 406 struct vmcb_state { 407 struct vmcb_segment es; 408 struct vmcb_segment cs; 409 struct vmcb_segment ss; 410 struct vmcb_segment ds; 411 struct vmcb_segment fs; 412 struct vmcb_segment gs; 413 struct vmcb_segment gdt; 414 struct vmcb_segment ldt; 415 struct vmcb_segment idt; 416 struct vmcb_segment tr; 417 uint8_t rsvd1[43]; 418 uint8_t cpl; 419 uint8_t rsvd2[4]; 420 uint64_t efer; 421 uint8_t rsvd3[112]; 422 uint64_t cr4; 423 uint64_t cr3; 424 uint64_t cr0; 425 uint64_t dr7; 426 uint64_t dr6; 427 uint64_t rflags; 428 uint64_t rip; 429 uint8_t rsvd4[88]; 430 uint64_t rsp; 431 uint8_t rsvd5[24]; 432 uint64_t rax; 433 uint64_t star; 434 uint64_t lstar; 435 uint64_t cstar; 436 uint64_t sfmask; 437 uint64_t kernelgsbase; 438 uint64_t sysenter_cs; 439 uint64_t sysenter_esp; 440 uint64_t sysenter_eip; 441 uint64_t cr2; 442 uint8_t rsvd6[32]; 443 uint64_t g_pat; 444 uint64_t dbgctl; 445 uint64_t br_from; 446 uint64_t br_to; 447 uint64_t int_from; 448 uint64_t int_to; 449 uint8_t pad[2408]; 450 } __packed; 451 452 CTASSERT(sizeof(struct vmcb_state) == 0xC00); 453 454 struct vmcb { 455 struct vmcb_ctrl ctrl; 456 struct vmcb_state state; 457 } __packed; 458 459 CTASSERT(sizeof(struct vmcb) == PAGE_SIZE); 460 CTASSERT(offsetof(struct vmcb, state) == 0x400); 461 462 /* -------------------------------------------------------------------------- */ 463 464 static void svm_vcpu_state_provide(struct nvmm_cpu *, uint64_t); 465 static void svm_vcpu_state_commit(struct nvmm_cpu *); 466 467 struct svm_hsave { 468 paddr_t pa; 469 }; 470 471 static struct svm_hsave hsave[MAXCPUS]; 472 473 static uint8_t *svm_asidmap __read_mostly; 474 static uint32_t svm_maxasid __read_mostly; 475 static kmutex_t svm_asidlock __cacheline_aligned; 476 477 static bool svm_decode_assist __read_mostly; 478 static uint32_t svm_ctrl_tlb_flush __read_mostly; 479 480 #define SVM_XCR0_MASK_DEFAULT (XCR0_X87|XCR0_SSE) 481 static uint64_t svm_xcr0_mask __read_mostly; 482 483 #define SVM_NCPUIDS 32 484 485 #define VMCB_NPAGES 1 486 487 #define MSRBM_NPAGES 2 488 #define MSRBM_SIZE (MSRBM_NPAGES * PAGE_SIZE) 489 490 #define IOBM_NPAGES 3 491 #define IOBM_SIZE (IOBM_NPAGES * PAGE_SIZE) 492 493 /* Does not include EFER_LMSLE. */ 494 #define EFER_VALID \ 495 (EFER_SCE|EFER_LME|EFER_LMA|EFER_NXE|EFER_SVME|EFER_FFXSR|EFER_TCE) 496 497 #define EFER_TLB_FLUSH \ 498 (EFER_NXE|EFER_LMA|EFER_LME) 499 #define CR0_TLB_FLUSH \ 500 (CR0_PG|CR0_WP|CR0_CD|CR0_NW) 501 #define CR4_TLB_FLUSH \ 502 (CR4_PGE|CR4_PAE|CR4_PSE) 503 504 /* -------------------------------------------------------------------------- */ 505 506 struct svm_machdata { 507 volatile uint64_t mach_htlb_gen; 508 }; 509 510 static const size_t svm_vcpu_conf_sizes[NVMM_X86_VCPU_NCONF] = { 511 [NVMM_VCPU_CONF_MD(NVMM_VCPU_CONF_CPUID)] = 512 sizeof(struct nvmm_vcpu_conf_cpuid), 513 [NVMM_VCPU_CONF_MD(NVMM_VCPU_CONF_TPR)] = 514 sizeof(struct nvmm_vcpu_conf_tpr) 515 }; 516 517 struct svm_cpudata { 518 /* General */ 519 bool shared_asid; 520 bool gtlb_want_flush; 521 bool gtsc_want_update; 522 uint64_t vcpu_htlb_gen; 523 524 /* VMCB */ 525 struct vmcb *vmcb; 526 paddr_t vmcb_pa; 527 528 /* I/O bitmap */ 529 uint8_t *iobm; 530 paddr_t iobm_pa; 531 532 /* MSR bitmap */ 533 uint8_t *msrbm; 534 paddr_t msrbm_pa; 535 536 /* Host state */ 537 uint64_t hxcr0; 538 uint64_t star; 539 uint64_t lstar; 540 uint64_t cstar; 541 uint64_t sfmask; 542 uint64_t fsbase; 543 uint64_t kernelgsbase; 544 bool ts_set; 545 struct xsave_header hfpu __aligned(64); 546 547 /* Intr state */ 548 bool int_window_exit; 549 bool nmi_window_exit; 550 bool evt_pending; 551 552 /* Guest state */ 553 uint64_t gxcr0; 554 uint64_t gprs[NVMM_X64_NGPR]; 555 uint64_t drs[NVMM_X64_NDR]; 556 uint64_t gtsc; 557 struct xsave_header gfpu __aligned(64); 558 559 /* VCPU configuration. */ 560 bool cpuidpresent[SVM_NCPUIDS]; 561 struct nvmm_vcpu_conf_cpuid cpuid[SVM_NCPUIDS]; 562 }; 563 564 static void 565 svm_vmcb_cache_default(struct vmcb *vmcb) 566 { 567 vmcb->ctrl.vmcb_clean = 568 VMCB_CTRL_VMCB_CLEAN_I | 569 VMCB_CTRL_VMCB_CLEAN_IOPM | 570 VMCB_CTRL_VMCB_CLEAN_ASID | 571 VMCB_CTRL_VMCB_CLEAN_TPR | 572 VMCB_CTRL_VMCB_CLEAN_NP | 573 VMCB_CTRL_VMCB_CLEAN_CR | 574 VMCB_CTRL_VMCB_CLEAN_DR | 575 VMCB_CTRL_VMCB_CLEAN_DT | 576 VMCB_CTRL_VMCB_CLEAN_SEG | 577 VMCB_CTRL_VMCB_CLEAN_CR2 | 578 VMCB_CTRL_VMCB_CLEAN_LBR | 579 VMCB_CTRL_VMCB_CLEAN_AVIC; 580 } 581 582 static void 583 svm_vmcb_cache_update(struct vmcb *vmcb, uint64_t flags) 584 { 585 if (flags & NVMM_X64_STATE_SEGS) { 586 vmcb->ctrl.vmcb_clean &= 587 ~(VMCB_CTRL_VMCB_CLEAN_SEG | VMCB_CTRL_VMCB_CLEAN_DT); 588 } 589 if (flags & NVMM_X64_STATE_CRS) { 590 vmcb->ctrl.vmcb_clean &= 591 ~(VMCB_CTRL_VMCB_CLEAN_CR | VMCB_CTRL_VMCB_CLEAN_CR2 | 592 VMCB_CTRL_VMCB_CLEAN_TPR); 593 } 594 if (flags & NVMM_X64_STATE_DRS) { 595 vmcb->ctrl.vmcb_clean &= ~VMCB_CTRL_VMCB_CLEAN_DR; 596 } 597 if (flags & NVMM_X64_STATE_MSRS) { 598 /* CR for EFER, NP for PAT. */ 599 vmcb->ctrl.vmcb_clean &= 600 ~(VMCB_CTRL_VMCB_CLEAN_CR | VMCB_CTRL_VMCB_CLEAN_NP); 601 } 602 } 603 604 static inline void 605 svm_vmcb_cache_flush(struct vmcb *vmcb, uint64_t flags) 606 { 607 vmcb->ctrl.vmcb_clean &= ~flags; 608 } 609 610 static inline void 611 svm_vmcb_cache_flush_all(struct vmcb *vmcb) 612 { 613 vmcb->ctrl.vmcb_clean = 0; 614 } 615 616 #define SVM_EVENT_TYPE_HW_INT 0 617 #define SVM_EVENT_TYPE_NMI 2 618 #define SVM_EVENT_TYPE_EXC 3 619 #define SVM_EVENT_TYPE_SW_INT 4 620 621 static void 622 svm_event_waitexit_enable(struct nvmm_cpu *vcpu, bool nmi) 623 { 624 struct svm_cpudata *cpudata = vcpu->cpudata; 625 struct vmcb *vmcb = cpudata->vmcb; 626 627 if (nmi) { 628 vmcb->ctrl.intercept_misc1 |= VMCB_CTRL_INTERCEPT_IRET; 629 cpudata->nmi_window_exit = true; 630 } else { 631 vmcb->ctrl.intercept_misc1 |= VMCB_CTRL_INTERCEPT_VINTR; 632 vmcb->ctrl.v |= (VMCB_CTRL_V_IRQ | VMCB_CTRL_V_IGN_TPR); 633 svm_vmcb_cache_flush(vmcb, VMCB_CTRL_VMCB_CLEAN_TPR); 634 cpudata->int_window_exit = true; 635 } 636 637 svm_vmcb_cache_flush(vmcb, VMCB_CTRL_VMCB_CLEAN_I); 638 } 639 640 static void 641 svm_event_waitexit_disable(struct nvmm_cpu *vcpu, bool nmi) 642 { 643 struct svm_cpudata *cpudata = vcpu->cpudata; 644 struct vmcb *vmcb = cpudata->vmcb; 645 646 if (nmi) { 647 vmcb->ctrl.intercept_misc1 &= ~VMCB_CTRL_INTERCEPT_IRET; 648 cpudata->nmi_window_exit = false; 649 } else { 650 vmcb->ctrl.intercept_misc1 &= ~VMCB_CTRL_INTERCEPT_VINTR; 651 vmcb->ctrl.v &= ~(VMCB_CTRL_V_IRQ | VMCB_CTRL_V_IGN_TPR); 652 svm_vmcb_cache_flush(vmcb, VMCB_CTRL_VMCB_CLEAN_TPR); 653 cpudata->int_window_exit = false; 654 } 655 656 svm_vmcb_cache_flush(vmcb, VMCB_CTRL_VMCB_CLEAN_I); 657 } 658 659 static inline int 660 svm_event_has_error(uint8_t vector) 661 { 662 switch (vector) { 663 case 8: /* #DF */ 664 case 10: /* #TS */ 665 case 11: /* #NP */ 666 case 12: /* #SS */ 667 case 13: /* #GP */ 668 case 14: /* #PF */ 669 case 17: /* #AC */ 670 case 30: /* #SX */ 671 return 1; 672 default: 673 return 0; 674 } 675 } 676 677 static int 678 svm_vcpu_inject(struct nvmm_cpu *vcpu) 679 { 680 struct nvmm_comm_page *comm = vcpu->comm; 681 struct svm_cpudata *cpudata = vcpu->cpudata; 682 struct vmcb *vmcb = cpudata->vmcb; 683 u_int evtype; 684 uint8_t vector; 685 uint64_t error; 686 int type = 0, err = 0; 687 688 evtype = comm->event.type; 689 vector = comm->event.vector; 690 error = comm->event.u.excp.error; 691 __insn_barrier(); 692 693 switch (evtype) { 694 case NVMM_VCPU_EVENT_EXCP: 695 type = SVM_EVENT_TYPE_EXC; 696 if (vector == 2 || vector >= 32) 697 return EINVAL; 698 if (vector == 3 || vector == 0) 699 return EINVAL; 700 err = svm_event_has_error(vector); 701 break; 702 case NVMM_VCPU_EVENT_INTR: 703 type = SVM_EVENT_TYPE_HW_INT; 704 if (vector == 2) { 705 type = SVM_EVENT_TYPE_NMI; 706 svm_event_waitexit_enable(vcpu, true); 707 } 708 err = 0; 709 break; 710 default: 711 return EINVAL; 712 } 713 714 vmcb->ctrl.eventinj = 715 __SHIFTIN((uint64_t)vector, VMCB_CTRL_EVENTINJ_VECTOR) | 716 __SHIFTIN((uint64_t)type, VMCB_CTRL_EVENTINJ_TYPE) | 717 __SHIFTIN((uint64_t)err, VMCB_CTRL_EVENTINJ_EV) | 718 __SHIFTIN((uint64_t)1, VMCB_CTRL_EVENTINJ_V) | 719 __SHIFTIN((uint64_t)error, VMCB_CTRL_EVENTINJ_ERRORCODE); 720 721 cpudata->evt_pending = true; 722 723 return 0; 724 } 725 726 static void 727 svm_inject_ud(struct nvmm_cpu *vcpu) 728 { 729 struct nvmm_comm_page *comm = vcpu->comm; 730 int ret __diagused; 731 732 comm->event.type = NVMM_VCPU_EVENT_EXCP; 733 comm->event.vector = 6; 734 comm->event.u.excp.error = 0; 735 736 ret = svm_vcpu_inject(vcpu); 737 KASSERT(ret == 0); 738 } 739 740 static void 741 svm_inject_gp(struct nvmm_cpu *vcpu) 742 { 743 struct nvmm_comm_page *comm = vcpu->comm; 744 int ret __diagused; 745 746 comm->event.type = NVMM_VCPU_EVENT_EXCP; 747 comm->event.vector = 13; 748 comm->event.u.excp.error = 0; 749 750 ret = svm_vcpu_inject(vcpu); 751 KASSERT(ret == 0); 752 } 753 754 static inline int 755 svm_vcpu_event_commit(struct nvmm_cpu *vcpu) 756 { 757 if (__predict_true(!vcpu->comm->event_commit)) { 758 return 0; 759 } 760 vcpu->comm->event_commit = false; 761 return svm_vcpu_inject(vcpu); 762 } 763 764 static inline void 765 svm_inkernel_advance(struct vmcb *vmcb) 766 { 767 /* 768 * Maybe we should also apply single-stepping and debug exceptions. 769 * Matters for guest-ring3, because it can execute 'cpuid' under a 770 * debugger. 771 */ 772 vmcb->state.rip = vmcb->ctrl.nrip; 773 vmcb->ctrl.intr &= ~VMCB_CTRL_INTR_SHADOW; 774 } 775 776 static void 777 svm_inkernel_handle_cpuid(struct nvmm_cpu *vcpu, uint64_t eax, uint64_t ecx) 778 { 779 struct svm_cpudata *cpudata = vcpu->cpudata; 780 uint64_t cr4; 781 782 switch (eax) { 783 case 0x00000001: 784 cpudata->vmcb->state.rax &= nvmm_cpuid_00000001.eax; 785 786 cpudata->gprs[NVMM_X64_GPR_RBX] &= ~CPUID_LOCAL_APIC_ID; 787 cpudata->gprs[NVMM_X64_GPR_RBX] |= __SHIFTIN(vcpu->cpuid, 788 CPUID_LOCAL_APIC_ID); 789 790 cpudata->gprs[NVMM_X64_GPR_RCX] &= nvmm_cpuid_00000001.ecx; 791 cpudata->gprs[NVMM_X64_GPR_RCX] |= CPUID2_RAZ; 792 793 cpudata->gprs[NVMM_X64_GPR_RDX] &= nvmm_cpuid_00000001.edx; 794 795 /* CPUID2_OSXSAVE depends on CR4. */ 796 cr4 = cpudata->vmcb->state.cr4; 797 if (!(cr4 & CR4_OSXSAVE)) { 798 cpudata->gprs[NVMM_X64_GPR_RCX] &= ~CPUID2_OSXSAVE; 799 } 800 break; 801 case 0x00000005: 802 case 0x00000006: 803 cpudata->vmcb->state.rax = 0; 804 cpudata->gprs[NVMM_X64_GPR_RBX] = 0; 805 cpudata->gprs[NVMM_X64_GPR_RCX] = 0; 806 cpudata->gprs[NVMM_X64_GPR_RDX] = 0; 807 break; 808 case 0x00000007: 809 cpudata->vmcb->state.rax &= nvmm_cpuid_00000007.eax; 810 cpudata->gprs[NVMM_X64_GPR_RBX] &= nvmm_cpuid_00000007.ebx; 811 cpudata->gprs[NVMM_X64_GPR_RCX] &= nvmm_cpuid_00000007.ecx; 812 cpudata->gprs[NVMM_X64_GPR_RDX] &= nvmm_cpuid_00000007.edx; 813 break; 814 case 0x0000000D: 815 if (svm_xcr0_mask == 0) { 816 break; 817 } 818 switch (ecx) { 819 case 0: 820 cpudata->vmcb->state.rax = svm_xcr0_mask & 0xFFFFFFFF; 821 if (cpudata->gxcr0 & XCR0_SSE) { 822 cpudata->gprs[NVMM_X64_GPR_RBX] = sizeof(struct fxsave); 823 } else { 824 cpudata->gprs[NVMM_X64_GPR_RBX] = sizeof(struct save87); 825 } 826 cpudata->gprs[NVMM_X64_GPR_RBX] += 64; /* XSAVE header */ 827 cpudata->gprs[NVMM_X64_GPR_RCX] = sizeof(struct fxsave) + 64; 828 cpudata->gprs[NVMM_X64_GPR_RDX] = svm_xcr0_mask >> 32; 829 break; 830 case 1: 831 cpudata->vmcb->state.rax &= ~CPUID_PES1_XSAVES; 832 break; 833 } 834 break; 835 case 0x40000000: 836 cpudata->gprs[NVMM_X64_GPR_RBX] = 0; 837 cpudata->gprs[NVMM_X64_GPR_RCX] = 0; 838 cpudata->gprs[NVMM_X64_GPR_RDX] = 0; 839 memcpy(&cpudata->gprs[NVMM_X64_GPR_RBX], "___ ", 4); 840 memcpy(&cpudata->gprs[NVMM_X64_GPR_RCX], "NVMM", 4); 841 memcpy(&cpudata->gprs[NVMM_X64_GPR_RDX], " ___", 4); 842 break; 843 case 0x80000001: 844 cpudata->vmcb->state.rax &= nvmm_cpuid_80000001.eax; 845 cpudata->gprs[NVMM_X64_GPR_RBX] &= nvmm_cpuid_80000001.ebx; 846 cpudata->gprs[NVMM_X64_GPR_RCX] &= nvmm_cpuid_80000001.ecx; 847 cpudata->gprs[NVMM_X64_GPR_RDX] &= nvmm_cpuid_80000001.edx; 848 break; 849 default: 850 break; 851 } 852 } 853 854 static void 855 svm_exit_insn(struct vmcb *vmcb, struct nvmm_vcpu_exit *exit, uint64_t reason) 856 { 857 exit->u.insn.npc = vmcb->ctrl.nrip; 858 exit->reason = reason; 859 } 860 861 static void 862 svm_exit_cpuid(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 863 struct nvmm_vcpu_exit *exit) 864 { 865 struct svm_cpudata *cpudata = vcpu->cpudata; 866 struct nvmm_vcpu_conf_cpuid *cpuid; 867 uint64_t eax, ecx; 868 u_int descs[4]; 869 size_t i; 870 871 eax = cpudata->vmcb->state.rax; 872 ecx = cpudata->gprs[NVMM_X64_GPR_RCX]; 873 x86_cpuid2(eax, ecx, descs); 874 875 cpudata->vmcb->state.rax = descs[0]; 876 cpudata->gprs[NVMM_X64_GPR_RBX] = descs[1]; 877 cpudata->gprs[NVMM_X64_GPR_RCX] = descs[2]; 878 cpudata->gprs[NVMM_X64_GPR_RDX] = descs[3]; 879 880 svm_inkernel_handle_cpuid(vcpu, eax, ecx); 881 882 for (i = 0; i < SVM_NCPUIDS; i++) { 883 if (!cpudata->cpuidpresent[i]) { 884 continue; 885 } 886 cpuid = &cpudata->cpuid[i]; 887 if (cpuid->leaf != eax) { 888 continue; 889 } 890 891 if (cpuid->exit) { 892 svm_exit_insn(cpudata->vmcb, exit, NVMM_VCPU_EXIT_CPUID); 893 return; 894 } 895 KASSERT(cpuid->mask); 896 897 /* del */ 898 cpudata->vmcb->state.rax &= ~cpuid->u.mask.del.eax; 899 cpudata->gprs[NVMM_X64_GPR_RBX] &= ~cpuid->u.mask.del.ebx; 900 cpudata->gprs[NVMM_X64_GPR_RCX] &= ~cpuid->u.mask.del.ecx; 901 cpudata->gprs[NVMM_X64_GPR_RDX] &= ~cpuid->u.mask.del.edx; 902 903 /* set */ 904 cpudata->vmcb->state.rax |= cpuid->u.mask.set.eax; 905 cpudata->gprs[NVMM_X64_GPR_RBX] |= cpuid->u.mask.set.ebx; 906 cpudata->gprs[NVMM_X64_GPR_RCX] |= cpuid->u.mask.set.ecx; 907 cpudata->gprs[NVMM_X64_GPR_RDX] |= cpuid->u.mask.set.edx; 908 909 break; 910 } 911 912 svm_inkernel_advance(cpudata->vmcb); 913 exit->reason = NVMM_VCPU_EXIT_NONE; 914 } 915 916 static void 917 svm_exit_hlt(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 918 struct nvmm_vcpu_exit *exit) 919 { 920 struct svm_cpudata *cpudata = vcpu->cpudata; 921 struct vmcb *vmcb = cpudata->vmcb; 922 923 if (cpudata->int_window_exit && (vmcb->state.rflags & PSL_I)) { 924 svm_event_waitexit_disable(vcpu, false); 925 } 926 927 svm_inkernel_advance(cpudata->vmcb); 928 exit->reason = NVMM_VCPU_EXIT_HALTED; 929 } 930 931 #define SVM_EXIT_IO_PORT __BITS(31,16) 932 #define SVM_EXIT_IO_SEG __BITS(12,10) 933 #define SVM_EXIT_IO_A64 __BIT(9) 934 #define SVM_EXIT_IO_A32 __BIT(8) 935 #define SVM_EXIT_IO_A16 __BIT(7) 936 #define SVM_EXIT_IO_SZ32 __BIT(6) 937 #define SVM_EXIT_IO_SZ16 __BIT(5) 938 #define SVM_EXIT_IO_SZ8 __BIT(4) 939 #define SVM_EXIT_IO_REP __BIT(3) 940 #define SVM_EXIT_IO_STR __BIT(2) 941 #define SVM_EXIT_IO_IN __BIT(0) 942 943 static void 944 svm_exit_io(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 945 struct nvmm_vcpu_exit *exit) 946 { 947 struct svm_cpudata *cpudata = vcpu->cpudata; 948 uint64_t info = cpudata->vmcb->ctrl.exitinfo1; 949 uint64_t nextpc = cpudata->vmcb->ctrl.exitinfo2; 950 951 exit->reason = NVMM_VCPU_EXIT_IO; 952 953 exit->u.io.in = (info & SVM_EXIT_IO_IN) != 0; 954 exit->u.io.port = __SHIFTOUT(info, SVM_EXIT_IO_PORT); 955 956 if (svm_decode_assist) { 957 KASSERT(__SHIFTOUT(info, SVM_EXIT_IO_SEG) < 6); 958 exit->u.io.seg = __SHIFTOUT(info, SVM_EXIT_IO_SEG); 959 } else { 960 exit->u.io.seg = -1; 961 } 962 963 if (info & SVM_EXIT_IO_A64) { 964 exit->u.io.address_size = 8; 965 } else if (info & SVM_EXIT_IO_A32) { 966 exit->u.io.address_size = 4; 967 } else if (info & SVM_EXIT_IO_A16) { 968 exit->u.io.address_size = 2; 969 } 970 971 if (info & SVM_EXIT_IO_SZ32) { 972 exit->u.io.operand_size = 4; 973 } else if (info & SVM_EXIT_IO_SZ16) { 974 exit->u.io.operand_size = 2; 975 } else if (info & SVM_EXIT_IO_SZ8) { 976 exit->u.io.operand_size = 1; 977 } 978 979 exit->u.io.rep = (info & SVM_EXIT_IO_REP) != 0; 980 exit->u.io.str = (info & SVM_EXIT_IO_STR) != 0; 981 exit->u.io.npc = nextpc; 982 983 svm_vcpu_state_provide(vcpu, 984 NVMM_X64_STATE_GPRS | NVMM_X64_STATE_SEGS | 985 NVMM_X64_STATE_CRS | NVMM_X64_STATE_MSRS); 986 } 987 988 static const uint64_t msr_ignore_list[] = { 989 0xc0010055, /* MSR_CMPHALT */ 990 MSR_DE_CFG, 991 MSR_IC_CFG, 992 MSR_UCODE_AMD_PATCHLEVEL 993 }; 994 995 static bool 996 svm_inkernel_handle_msr(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 997 struct nvmm_vcpu_exit *exit) 998 { 999 struct svm_cpudata *cpudata = vcpu->cpudata; 1000 struct vmcb *vmcb = cpudata->vmcb; 1001 uint64_t val; 1002 size_t i; 1003 1004 if (exit->reason == NVMM_VCPU_EXIT_RDMSR) { 1005 if (exit->u.rdmsr.msr == MSR_NB_CFG) { 1006 val = NB_CFG_INITAPICCPUIDLO; 1007 vmcb->state.rax = (val & 0xFFFFFFFF); 1008 cpudata->gprs[NVMM_X64_GPR_RDX] = (val >> 32); 1009 goto handled; 1010 } 1011 for (i = 0; i < __arraycount(msr_ignore_list); i++) { 1012 if (msr_ignore_list[i] != exit->u.rdmsr.msr) 1013 continue; 1014 val = 0; 1015 vmcb->state.rax = (val & 0xFFFFFFFF); 1016 cpudata->gprs[NVMM_X64_GPR_RDX] = (val >> 32); 1017 goto handled; 1018 } 1019 } else { 1020 if (exit->u.wrmsr.msr == MSR_EFER) { 1021 if (__predict_false(exit->u.wrmsr.val & ~EFER_VALID)) { 1022 goto error; 1023 } 1024 if ((vmcb->state.efer ^ exit->u.wrmsr.val) & 1025 EFER_TLB_FLUSH) { 1026 cpudata->gtlb_want_flush = true; 1027 } 1028 vmcb->state.efer = exit->u.wrmsr.val | EFER_SVME; 1029 svm_vmcb_cache_flush(vmcb, VMCB_CTRL_VMCB_CLEAN_CR); 1030 goto handled; 1031 } 1032 if (exit->u.wrmsr.msr == MSR_TSC) { 1033 cpudata->gtsc = exit->u.wrmsr.val; 1034 cpudata->gtsc_want_update = true; 1035 goto handled; 1036 } 1037 for (i = 0; i < __arraycount(msr_ignore_list); i++) { 1038 if (msr_ignore_list[i] != exit->u.wrmsr.msr) 1039 continue; 1040 goto handled; 1041 } 1042 } 1043 1044 return false; 1045 1046 handled: 1047 svm_inkernel_advance(cpudata->vmcb); 1048 return true; 1049 1050 error: 1051 svm_inject_gp(vcpu); 1052 return true; 1053 } 1054 1055 static inline void 1056 svm_exit_rdmsr(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 1057 struct nvmm_vcpu_exit *exit) 1058 { 1059 struct svm_cpudata *cpudata = vcpu->cpudata; 1060 1061 exit->reason = NVMM_VCPU_EXIT_RDMSR; 1062 exit->u.rdmsr.msr = (cpudata->gprs[NVMM_X64_GPR_RCX] & 0xFFFFFFFF); 1063 exit->u.rdmsr.npc = cpudata->vmcb->ctrl.nrip; 1064 1065 if (svm_inkernel_handle_msr(mach, vcpu, exit)) { 1066 exit->reason = NVMM_VCPU_EXIT_NONE; 1067 return; 1068 } 1069 1070 svm_vcpu_state_provide(vcpu, NVMM_X64_STATE_GPRS); 1071 } 1072 1073 static inline void 1074 svm_exit_wrmsr(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 1075 struct nvmm_vcpu_exit *exit) 1076 { 1077 struct svm_cpudata *cpudata = vcpu->cpudata; 1078 uint64_t rdx, rax; 1079 1080 rdx = cpudata->gprs[NVMM_X64_GPR_RDX]; 1081 rax = cpudata->vmcb->state.rax; 1082 1083 exit->reason = NVMM_VCPU_EXIT_WRMSR; 1084 exit->u.wrmsr.msr = (cpudata->gprs[NVMM_X64_GPR_RCX] & 0xFFFFFFFF); 1085 exit->u.wrmsr.val = (rdx << 32) | (rax & 0xFFFFFFFF); 1086 exit->u.wrmsr.npc = cpudata->vmcb->ctrl.nrip; 1087 1088 if (svm_inkernel_handle_msr(mach, vcpu, exit)) { 1089 exit->reason = NVMM_VCPU_EXIT_NONE; 1090 return; 1091 } 1092 1093 svm_vcpu_state_provide(vcpu, NVMM_X64_STATE_GPRS); 1094 } 1095 1096 static void 1097 svm_exit_msr(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 1098 struct nvmm_vcpu_exit *exit) 1099 { 1100 struct svm_cpudata *cpudata = vcpu->cpudata; 1101 uint64_t info = cpudata->vmcb->ctrl.exitinfo1; 1102 1103 if (info == 0) { 1104 svm_exit_rdmsr(mach, vcpu, exit); 1105 } else { 1106 svm_exit_wrmsr(mach, vcpu, exit); 1107 } 1108 } 1109 1110 static void 1111 svm_exit_npf(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 1112 struct nvmm_vcpu_exit *exit) 1113 { 1114 struct svm_cpudata *cpudata = vcpu->cpudata; 1115 gpaddr_t gpa = cpudata->vmcb->ctrl.exitinfo2; 1116 1117 exit->reason = NVMM_VCPU_EXIT_MEMORY; 1118 if (cpudata->vmcb->ctrl.exitinfo1 & PGEX_W) 1119 exit->u.mem.prot = PROT_WRITE; 1120 else if (cpudata->vmcb->ctrl.exitinfo1 & PGEX_X) 1121 exit->u.mem.prot = PROT_EXEC; 1122 else 1123 exit->u.mem.prot = PROT_READ; 1124 exit->u.mem.gpa = gpa; 1125 exit->u.mem.inst_len = cpudata->vmcb->ctrl.inst_len; 1126 memcpy(exit->u.mem.inst_bytes, cpudata->vmcb->ctrl.inst_bytes, 1127 sizeof(exit->u.mem.inst_bytes)); 1128 1129 svm_vcpu_state_provide(vcpu, 1130 NVMM_X64_STATE_GPRS | NVMM_X64_STATE_SEGS | 1131 NVMM_X64_STATE_CRS | NVMM_X64_STATE_MSRS); 1132 } 1133 1134 static void 1135 svm_exit_xsetbv(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 1136 struct nvmm_vcpu_exit *exit) 1137 { 1138 struct svm_cpudata *cpudata = vcpu->cpudata; 1139 struct vmcb *vmcb = cpudata->vmcb; 1140 uint64_t val; 1141 1142 exit->reason = NVMM_VCPU_EXIT_NONE; 1143 1144 val = (cpudata->gprs[NVMM_X64_GPR_RDX] << 32) | 1145 (vmcb->state.rax & 0xFFFFFFFF); 1146 1147 if (__predict_false(cpudata->gprs[NVMM_X64_GPR_RCX] != 0)) { 1148 goto error; 1149 } else if (__predict_false(vmcb->state.cpl != 0)) { 1150 goto error; 1151 } else if (__predict_false((val & ~svm_xcr0_mask) != 0)) { 1152 goto error; 1153 } else if (__predict_false((val & XCR0_X87) == 0)) { 1154 goto error; 1155 } 1156 1157 cpudata->gxcr0 = val; 1158 1159 svm_inkernel_advance(cpudata->vmcb); 1160 return; 1161 1162 error: 1163 svm_inject_gp(vcpu); 1164 } 1165 1166 static void 1167 svm_exit_invalid(struct nvmm_vcpu_exit *exit, uint64_t code) 1168 { 1169 exit->u.inv.hwcode = code; 1170 exit->reason = NVMM_VCPU_EXIT_INVALID; 1171 } 1172 1173 /* -------------------------------------------------------------------------- */ 1174 1175 static void 1176 svm_vcpu_guest_fpu_enter(struct nvmm_cpu *vcpu) 1177 { 1178 struct svm_cpudata *cpudata = vcpu->cpudata; 1179 1180 cpudata->ts_set = (rcr0() & CR0_TS) != 0; 1181 1182 fpu_area_save(&cpudata->hfpu, svm_xcr0_mask); 1183 fpu_area_restore(&cpudata->gfpu, svm_xcr0_mask); 1184 1185 if (svm_xcr0_mask != 0) { 1186 cpudata->hxcr0 = rdxcr(0); 1187 wrxcr(0, cpudata->gxcr0); 1188 } 1189 } 1190 1191 static void 1192 svm_vcpu_guest_fpu_leave(struct nvmm_cpu *vcpu) 1193 { 1194 struct svm_cpudata *cpudata = vcpu->cpudata; 1195 1196 if (svm_xcr0_mask != 0) { 1197 cpudata->gxcr0 = rdxcr(0); 1198 wrxcr(0, cpudata->hxcr0); 1199 } 1200 1201 fpu_area_save(&cpudata->gfpu, svm_xcr0_mask); 1202 fpu_area_restore(&cpudata->hfpu, svm_xcr0_mask); 1203 1204 if (cpudata->ts_set) { 1205 stts(); 1206 } 1207 } 1208 1209 static void 1210 svm_vcpu_guest_dbregs_enter(struct nvmm_cpu *vcpu) 1211 { 1212 struct svm_cpudata *cpudata = vcpu->cpudata; 1213 1214 x86_dbregs_save(curlwp); 1215 1216 ldr7(0); 1217 1218 ldr0(cpudata->drs[NVMM_X64_DR_DR0]); 1219 ldr1(cpudata->drs[NVMM_X64_DR_DR1]); 1220 ldr2(cpudata->drs[NVMM_X64_DR_DR2]); 1221 ldr3(cpudata->drs[NVMM_X64_DR_DR3]); 1222 } 1223 1224 static void 1225 svm_vcpu_guest_dbregs_leave(struct nvmm_cpu *vcpu) 1226 { 1227 struct svm_cpudata *cpudata = vcpu->cpudata; 1228 1229 cpudata->drs[NVMM_X64_DR_DR0] = rdr0(); 1230 cpudata->drs[NVMM_X64_DR_DR1] = rdr1(); 1231 cpudata->drs[NVMM_X64_DR_DR2] = rdr2(); 1232 cpudata->drs[NVMM_X64_DR_DR3] = rdr3(); 1233 1234 x86_dbregs_restore(curlwp); 1235 } 1236 1237 static void 1238 svm_vcpu_guest_misc_enter(struct nvmm_cpu *vcpu) 1239 { 1240 struct svm_cpudata *cpudata = vcpu->cpudata; 1241 1242 cpudata->fsbase = rdmsr(MSR_FSBASE); 1243 cpudata->kernelgsbase = rdmsr(MSR_KERNELGSBASE); 1244 } 1245 1246 static void 1247 svm_vcpu_guest_misc_leave(struct nvmm_cpu *vcpu) 1248 { 1249 struct svm_cpudata *cpudata = vcpu->cpudata; 1250 1251 wrmsr(MSR_STAR, cpudata->star); 1252 wrmsr(MSR_LSTAR, cpudata->lstar); 1253 wrmsr(MSR_CSTAR, cpudata->cstar); 1254 wrmsr(MSR_SFMASK, cpudata->sfmask); 1255 wrmsr(MSR_FSBASE, cpudata->fsbase); 1256 wrmsr(MSR_KERNELGSBASE, cpudata->kernelgsbase); 1257 } 1258 1259 /* -------------------------------------------------------------------------- */ 1260 1261 static inline void 1262 svm_gtlb_catchup(struct nvmm_cpu *vcpu, int hcpu) 1263 { 1264 struct svm_cpudata *cpudata = vcpu->cpudata; 1265 1266 if (vcpu->hcpu_last != hcpu || cpudata->shared_asid) { 1267 cpudata->gtlb_want_flush = true; 1268 } 1269 } 1270 1271 static inline void 1272 svm_htlb_catchup(struct nvmm_cpu *vcpu, int hcpu) 1273 { 1274 /* 1275 * Nothing to do. If an hTLB flush was needed, either the VCPU was 1276 * executing on this hCPU and the hTLB already got flushed, or it 1277 * was executing on another hCPU in which case the catchup is done 1278 * in svm_gtlb_catchup(). 1279 */ 1280 } 1281 1282 static inline uint64_t 1283 svm_htlb_flush(struct svm_machdata *machdata, struct svm_cpudata *cpudata) 1284 { 1285 struct vmcb *vmcb = cpudata->vmcb; 1286 uint64_t machgen; 1287 1288 machgen = machdata->mach_htlb_gen; 1289 if (__predict_true(machgen == cpudata->vcpu_htlb_gen)) { 1290 return machgen; 1291 } 1292 1293 vmcb->ctrl.tlb_ctrl = svm_ctrl_tlb_flush; 1294 return machgen; 1295 } 1296 1297 static inline void 1298 svm_htlb_flush_ack(struct svm_cpudata *cpudata, uint64_t machgen) 1299 { 1300 struct vmcb *vmcb = cpudata->vmcb; 1301 1302 if (__predict_true(vmcb->ctrl.exitcode != VMCB_EXITCODE_INVALID)) { 1303 cpudata->vcpu_htlb_gen = machgen; 1304 } 1305 } 1306 1307 static inline void 1308 svm_exit_evt(struct svm_cpudata *cpudata, struct vmcb *vmcb) 1309 { 1310 cpudata->evt_pending = false; 1311 1312 if (__predict_false(vmcb->ctrl.exitintinfo & VMCB_CTRL_EXITINTINFO_V)) { 1313 vmcb->ctrl.eventinj = vmcb->ctrl.exitintinfo; 1314 cpudata->evt_pending = true; 1315 } 1316 } 1317 1318 static int 1319 svm_vcpu_run(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 1320 struct nvmm_vcpu_exit *exit) 1321 { 1322 struct nvmm_comm_page *comm = vcpu->comm; 1323 struct svm_machdata *machdata = mach->machdata; 1324 struct svm_cpudata *cpudata = vcpu->cpudata; 1325 struct vmcb *vmcb = cpudata->vmcb; 1326 uint64_t machgen; 1327 int hcpu, s; 1328 1329 if (__predict_false(svm_vcpu_event_commit(vcpu) != 0)) { 1330 return EINVAL; 1331 } 1332 svm_vcpu_state_commit(vcpu); 1333 comm->state_cached = 0; 1334 1335 kpreempt_disable(); 1336 hcpu = cpu_number(); 1337 1338 svm_gtlb_catchup(vcpu, hcpu); 1339 svm_htlb_catchup(vcpu, hcpu); 1340 1341 if (vcpu->hcpu_last != hcpu) { 1342 svm_vmcb_cache_flush_all(vmcb); 1343 cpudata->gtsc_want_update = true; 1344 } 1345 1346 svm_vcpu_guest_dbregs_enter(vcpu); 1347 svm_vcpu_guest_misc_enter(vcpu); 1348 1349 while (1) { 1350 if (cpudata->gtlb_want_flush) { 1351 vmcb->ctrl.tlb_ctrl = svm_ctrl_tlb_flush; 1352 } else { 1353 vmcb->ctrl.tlb_ctrl = 0; 1354 } 1355 1356 if (__predict_false(cpudata->gtsc_want_update)) { 1357 vmcb->ctrl.tsc_offset = cpudata->gtsc - rdtsc(); 1358 svm_vmcb_cache_flush(vmcb, VMCB_CTRL_VMCB_CLEAN_I); 1359 } 1360 1361 s = splhigh(); 1362 machgen = svm_htlb_flush(machdata, cpudata); 1363 svm_vcpu_guest_fpu_enter(vcpu); 1364 svm_vmrun(cpudata->vmcb_pa, cpudata->gprs); 1365 svm_vcpu_guest_fpu_leave(vcpu); 1366 svm_htlb_flush_ack(cpudata, machgen); 1367 splx(s); 1368 1369 svm_vmcb_cache_default(vmcb); 1370 1371 if (vmcb->ctrl.exitcode != VMCB_EXITCODE_INVALID) { 1372 cpudata->gtlb_want_flush = false; 1373 cpudata->gtsc_want_update = false; 1374 vcpu->hcpu_last = hcpu; 1375 } 1376 svm_exit_evt(cpudata, vmcb); 1377 1378 switch (vmcb->ctrl.exitcode) { 1379 case VMCB_EXITCODE_INTR: 1380 case VMCB_EXITCODE_NMI: 1381 exit->reason = NVMM_VCPU_EXIT_NONE; 1382 break; 1383 case VMCB_EXITCODE_VINTR: 1384 svm_event_waitexit_disable(vcpu, false); 1385 exit->reason = NVMM_VCPU_EXIT_INT_READY; 1386 break; 1387 case VMCB_EXITCODE_IRET: 1388 svm_event_waitexit_disable(vcpu, true); 1389 exit->reason = NVMM_VCPU_EXIT_NMI_READY; 1390 break; 1391 case VMCB_EXITCODE_CPUID: 1392 svm_exit_cpuid(mach, vcpu, exit); 1393 break; 1394 case VMCB_EXITCODE_HLT: 1395 svm_exit_hlt(mach, vcpu, exit); 1396 break; 1397 case VMCB_EXITCODE_IOIO: 1398 svm_exit_io(mach, vcpu, exit); 1399 break; 1400 case VMCB_EXITCODE_MSR: 1401 svm_exit_msr(mach, vcpu, exit); 1402 break; 1403 case VMCB_EXITCODE_SHUTDOWN: 1404 exit->reason = NVMM_VCPU_EXIT_SHUTDOWN; 1405 break; 1406 case VMCB_EXITCODE_RDPMC: 1407 case VMCB_EXITCODE_RSM: 1408 case VMCB_EXITCODE_INVLPGA: 1409 case VMCB_EXITCODE_VMRUN: 1410 case VMCB_EXITCODE_VMMCALL: 1411 case VMCB_EXITCODE_VMLOAD: 1412 case VMCB_EXITCODE_VMSAVE: 1413 case VMCB_EXITCODE_STGI: 1414 case VMCB_EXITCODE_CLGI: 1415 case VMCB_EXITCODE_SKINIT: 1416 case VMCB_EXITCODE_RDTSCP: 1417 svm_inject_ud(vcpu); 1418 exit->reason = NVMM_VCPU_EXIT_NONE; 1419 break; 1420 case VMCB_EXITCODE_MONITOR: 1421 svm_exit_insn(vmcb, exit, NVMM_VCPU_EXIT_MONITOR); 1422 break; 1423 case VMCB_EXITCODE_MWAIT: 1424 case VMCB_EXITCODE_MWAIT_CONDITIONAL: 1425 svm_exit_insn(vmcb, exit, NVMM_VCPU_EXIT_MWAIT); 1426 break; 1427 case VMCB_EXITCODE_XSETBV: 1428 svm_exit_xsetbv(mach, vcpu, exit); 1429 break; 1430 case VMCB_EXITCODE_NPF: 1431 svm_exit_npf(mach, vcpu, exit); 1432 break; 1433 case VMCB_EXITCODE_FERR_FREEZE: /* ? */ 1434 default: 1435 svm_exit_invalid(exit, vmcb->ctrl.exitcode); 1436 break; 1437 } 1438 1439 /* If no reason to return to userland, keep rolling. */ 1440 if (curcpu()->ci_schedstate.spc_flags & SPCF_SHOULDYIELD) { 1441 break; 1442 } 1443 if (curcpu()->ci_data.cpu_softints != 0) { 1444 break; 1445 } 1446 if (curlwp->l_flag & LW_USERRET) { 1447 break; 1448 } 1449 if (exit->reason != NVMM_VCPU_EXIT_NONE) { 1450 break; 1451 } 1452 } 1453 1454 cpudata->gtsc = rdtsc() + vmcb->ctrl.tsc_offset; 1455 1456 svm_vcpu_guest_misc_leave(vcpu); 1457 svm_vcpu_guest_dbregs_leave(vcpu); 1458 1459 kpreempt_enable(); 1460 1461 exit->exitstate.rflags = vmcb->state.rflags; 1462 exit->exitstate.cr8 = __SHIFTOUT(vmcb->ctrl.v, VMCB_CTRL_V_TPR); 1463 exit->exitstate.int_shadow = 1464 ((vmcb->ctrl.intr & VMCB_CTRL_INTR_SHADOW) != 0); 1465 exit->exitstate.int_window_exiting = cpudata->int_window_exit; 1466 exit->exitstate.nmi_window_exiting = cpudata->nmi_window_exit; 1467 exit->exitstate.evt_pending = cpudata->evt_pending; 1468 1469 return 0; 1470 } 1471 1472 /* -------------------------------------------------------------------------- */ 1473 1474 static int 1475 svm_memalloc(paddr_t *pa, vaddr_t *va, size_t npages) 1476 { 1477 struct pglist pglist; 1478 paddr_t _pa; 1479 vaddr_t _va; 1480 size_t i; 1481 int ret; 1482 1483 ret = uvm_pglistalloc(npages * PAGE_SIZE, 0, ~0UL, PAGE_SIZE, 0, 1484 &pglist, 1, 0); 1485 if (ret != 0) 1486 return ENOMEM; 1487 _pa = TAILQ_FIRST(&pglist)->phys_addr; 1488 _va = uvm_km_alloc(kernel_map, npages * PAGE_SIZE, 0, 1489 UVM_KMF_VAONLY | UVM_KMF_NOWAIT); 1490 if (_va == 0) 1491 goto error; 1492 1493 for (i = 0; i < npages; i++) { 1494 pmap_kenter_pa(_va + i * PAGE_SIZE, _pa + i * PAGE_SIZE, 1495 VM_PROT_READ | VM_PROT_WRITE, PMAP_WRITE_BACK); 1496 } 1497 pmap_update(pmap_kernel()); 1498 1499 memset((void *)_va, 0, npages * PAGE_SIZE); 1500 1501 *pa = _pa; 1502 *va = _va; 1503 return 0; 1504 1505 error: 1506 for (i = 0; i < npages; i++) { 1507 uvm_pagefree(PHYS_TO_VM_PAGE(_pa + i * PAGE_SIZE)); 1508 } 1509 return ENOMEM; 1510 } 1511 1512 static void 1513 svm_memfree(paddr_t pa, vaddr_t va, size_t npages) 1514 { 1515 size_t i; 1516 1517 pmap_kremove(va, npages * PAGE_SIZE); 1518 pmap_update(pmap_kernel()); 1519 uvm_km_free(kernel_map, va, npages * PAGE_SIZE, UVM_KMF_VAONLY); 1520 for (i = 0; i < npages; i++) { 1521 uvm_pagefree(PHYS_TO_VM_PAGE(pa + i * PAGE_SIZE)); 1522 } 1523 } 1524 1525 /* -------------------------------------------------------------------------- */ 1526 1527 #define SVM_MSRBM_READ __BIT(0) 1528 #define SVM_MSRBM_WRITE __BIT(1) 1529 1530 static void 1531 svm_vcpu_msr_allow(uint8_t *bitmap, uint64_t msr, bool read, bool write) 1532 { 1533 uint64_t byte; 1534 uint8_t bitoff; 1535 1536 if (msr < 0x00002000) { 1537 /* Range 1 */ 1538 byte = ((msr - 0x00000000) >> 2UL) + 0x0000; 1539 } else if (msr >= 0xC0000000 && msr < 0xC0002000) { 1540 /* Range 2 */ 1541 byte = ((msr - 0xC0000000) >> 2UL) + 0x0800; 1542 } else if (msr >= 0xC0010000 && msr < 0xC0012000) { 1543 /* Range 3 */ 1544 byte = ((msr - 0xC0010000) >> 2UL) + 0x1000; 1545 } else { 1546 panic("%s: wrong range", __func__); 1547 } 1548 1549 bitoff = (msr & 0x3) << 1; 1550 1551 if (read) { 1552 bitmap[byte] &= ~(SVM_MSRBM_READ << bitoff); 1553 } 1554 if (write) { 1555 bitmap[byte] &= ~(SVM_MSRBM_WRITE << bitoff); 1556 } 1557 } 1558 1559 #define SVM_SEG_ATTRIB_TYPE __BITS(3,0) 1560 #define SVM_SEG_ATTRIB_S __BIT(4) 1561 #define SVM_SEG_ATTRIB_DPL __BITS(6,5) 1562 #define SVM_SEG_ATTRIB_P __BIT(7) 1563 #define SVM_SEG_ATTRIB_AVL __BIT(8) 1564 #define SVM_SEG_ATTRIB_L __BIT(9) 1565 #define SVM_SEG_ATTRIB_DEF __BIT(10) 1566 #define SVM_SEG_ATTRIB_G __BIT(11) 1567 1568 static void 1569 svm_vcpu_setstate_seg(const struct nvmm_x64_state_seg *seg, 1570 struct vmcb_segment *vseg) 1571 { 1572 vseg->selector = seg->selector; 1573 vseg->attrib = 1574 __SHIFTIN(seg->attrib.type, SVM_SEG_ATTRIB_TYPE) | 1575 __SHIFTIN(seg->attrib.s, SVM_SEG_ATTRIB_S) | 1576 __SHIFTIN(seg->attrib.dpl, SVM_SEG_ATTRIB_DPL) | 1577 __SHIFTIN(seg->attrib.p, SVM_SEG_ATTRIB_P) | 1578 __SHIFTIN(seg->attrib.avl, SVM_SEG_ATTRIB_AVL) | 1579 __SHIFTIN(seg->attrib.l, SVM_SEG_ATTRIB_L) | 1580 __SHIFTIN(seg->attrib.def, SVM_SEG_ATTRIB_DEF) | 1581 __SHIFTIN(seg->attrib.g, SVM_SEG_ATTRIB_G); 1582 vseg->limit = seg->limit; 1583 vseg->base = seg->base; 1584 } 1585 1586 static void 1587 svm_vcpu_getstate_seg(struct nvmm_x64_state_seg *seg, struct vmcb_segment *vseg) 1588 { 1589 seg->selector = vseg->selector; 1590 seg->attrib.type = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_TYPE); 1591 seg->attrib.s = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_S); 1592 seg->attrib.dpl = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_DPL); 1593 seg->attrib.p = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_P); 1594 seg->attrib.avl = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_AVL); 1595 seg->attrib.l = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_L); 1596 seg->attrib.def = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_DEF); 1597 seg->attrib.g = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_G); 1598 seg->limit = vseg->limit; 1599 seg->base = vseg->base; 1600 } 1601 1602 static inline bool 1603 svm_state_tlb_flush(const struct vmcb *vmcb, const struct nvmm_x64_state *state, 1604 uint64_t flags) 1605 { 1606 if (flags & NVMM_X64_STATE_CRS) { 1607 if ((vmcb->state.cr0 ^ 1608 state->crs[NVMM_X64_CR_CR0]) & CR0_TLB_FLUSH) { 1609 return true; 1610 } 1611 if (vmcb->state.cr3 != state->crs[NVMM_X64_CR_CR3]) { 1612 return true; 1613 } 1614 if ((vmcb->state.cr4 ^ 1615 state->crs[NVMM_X64_CR_CR4]) & CR4_TLB_FLUSH) { 1616 return true; 1617 } 1618 } 1619 1620 if (flags & NVMM_X64_STATE_MSRS) { 1621 if ((vmcb->state.efer ^ 1622 state->msrs[NVMM_X64_MSR_EFER]) & EFER_TLB_FLUSH) { 1623 return true; 1624 } 1625 } 1626 1627 return false; 1628 } 1629 1630 static void 1631 svm_vcpu_setstate(struct nvmm_cpu *vcpu) 1632 { 1633 struct nvmm_comm_page *comm = vcpu->comm; 1634 const struct nvmm_x64_state *state = &comm->state; 1635 struct svm_cpudata *cpudata = vcpu->cpudata; 1636 struct vmcb *vmcb = cpudata->vmcb; 1637 struct fxsave *fpustate; 1638 uint64_t flags; 1639 1640 flags = comm->state_wanted; 1641 1642 if (svm_state_tlb_flush(vmcb, state, flags)) { 1643 cpudata->gtlb_want_flush = true; 1644 } 1645 1646 if (flags & NVMM_X64_STATE_SEGS) { 1647 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_CS], 1648 &vmcb->state.cs); 1649 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_DS], 1650 &vmcb->state.ds); 1651 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_ES], 1652 &vmcb->state.es); 1653 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_FS], 1654 &vmcb->state.fs); 1655 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_GS], 1656 &vmcb->state.gs); 1657 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_SS], 1658 &vmcb->state.ss); 1659 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_GDT], 1660 &vmcb->state.gdt); 1661 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_IDT], 1662 &vmcb->state.idt); 1663 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_LDT], 1664 &vmcb->state.ldt); 1665 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_TR], 1666 &vmcb->state.tr); 1667 1668 vmcb->state.cpl = state->segs[NVMM_X64_SEG_SS].attrib.dpl; 1669 } 1670 1671 CTASSERT(sizeof(cpudata->gprs) == sizeof(state->gprs)); 1672 if (flags & NVMM_X64_STATE_GPRS) { 1673 memcpy(cpudata->gprs, state->gprs, sizeof(state->gprs)); 1674 1675 vmcb->state.rip = state->gprs[NVMM_X64_GPR_RIP]; 1676 vmcb->state.rsp = state->gprs[NVMM_X64_GPR_RSP]; 1677 vmcb->state.rax = state->gprs[NVMM_X64_GPR_RAX]; 1678 vmcb->state.rflags = state->gprs[NVMM_X64_GPR_RFLAGS]; 1679 } 1680 1681 if (flags & NVMM_X64_STATE_CRS) { 1682 vmcb->state.cr0 = state->crs[NVMM_X64_CR_CR0]; 1683 vmcb->state.cr2 = state->crs[NVMM_X64_CR_CR2]; 1684 vmcb->state.cr3 = state->crs[NVMM_X64_CR_CR3]; 1685 vmcb->state.cr4 = state->crs[NVMM_X64_CR_CR4]; 1686 1687 vmcb->ctrl.v &= ~VMCB_CTRL_V_TPR; 1688 vmcb->ctrl.v |= __SHIFTIN(state->crs[NVMM_X64_CR_CR8], 1689 VMCB_CTRL_V_TPR); 1690 1691 if (svm_xcr0_mask != 0) { 1692 /* Clear illegal XCR0 bits, set mandatory X87 bit. */ 1693 cpudata->gxcr0 = state->crs[NVMM_X64_CR_XCR0]; 1694 cpudata->gxcr0 &= svm_xcr0_mask; 1695 cpudata->gxcr0 |= XCR0_X87; 1696 } 1697 } 1698 1699 CTASSERT(sizeof(cpudata->drs) == sizeof(state->drs)); 1700 if (flags & NVMM_X64_STATE_DRS) { 1701 memcpy(cpudata->drs, state->drs, sizeof(state->drs)); 1702 1703 vmcb->state.dr6 = state->drs[NVMM_X64_DR_DR6]; 1704 vmcb->state.dr7 = state->drs[NVMM_X64_DR_DR7]; 1705 } 1706 1707 if (flags & NVMM_X64_STATE_MSRS) { 1708 /* 1709 * EFER_SVME is mandatory. 1710 */ 1711 vmcb->state.efer = state->msrs[NVMM_X64_MSR_EFER] | EFER_SVME; 1712 vmcb->state.star = state->msrs[NVMM_X64_MSR_STAR]; 1713 vmcb->state.lstar = state->msrs[NVMM_X64_MSR_LSTAR]; 1714 vmcb->state.cstar = state->msrs[NVMM_X64_MSR_CSTAR]; 1715 vmcb->state.sfmask = state->msrs[NVMM_X64_MSR_SFMASK]; 1716 vmcb->state.kernelgsbase = 1717 state->msrs[NVMM_X64_MSR_KERNELGSBASE]; 1718 vmcb->state.sysenter_cs = 1719 state->msrs[NVMM_X64_MSR_SYSENTER_CS]; 1720 vmcb->state.sysenter_esp = 1721 state->msrs[NVMM_X64_MSR_SYSENTER_ESP]; 1722 vmcb->state.sysenter_eip = 1723 state->msrs[NVMM_X64_MSR_SYSENTER_EIP]; 1724 vmcb->state.g_pat = state->msrs[NVMM_X64_MSR_PAT]; 1725 1726 cpudata->gtsc = state->msrs[NVMM_X64_MSR_TSC]; 1727 cpudata->gtsc_want_update = true; 1728 } 1729 1730 if (flags & NVMM_X64_STATE_INTR) { 1731 if (state->intr.int_shadow) { 1732 vmcb->ctrl.intr |= VMCB_CTRL_INTR_SHADOW; 1733 } else { 1734 vmcb->ctrl.intr &= ~VMCB_CTRL_INTR_SHADOW; 1735 } 1736 1737 if (state->intr.int_window_exiting) { 1738 svm_event_waitexit_enable(vcpu, false); 1739 } else { 1740 svm_event_waitexit_disable(vcpu, false); 1741 } 1742 1743 if (state->intr.nmi_window_exiting) { 1744 svm_event_waitexit_enable(vcpu, true); 1745 } else { 1746 svm_event_waitexit_disable(vcpu, true); 1747 } 1748 } 1749 1750 CTASSERT(sizeof(cpudata->gfpu.xsh_fxsave) == sizeof(state->fpu)); 1751 if (flags & NVMM_X64_STATE_FPU) { 1752 memcpy(cpudata->gfpu.xsh_fxsave, &state->fpu, 1753 sizeof(state->fpu)); 1754 1755 fpustate = (struct fxsave *)cpudata->gfpu.xsh_fxsave; 1756 fpustate->fx_mxcsr_mask &= x86_fpu_mxcsr_mask; 1757 fpustate->fx_mxcsr &= fpustate->fx_mxcsr_mask; 1758 1759 if (svm_xcr0_mask != 0) { 1760 /* Reset XSTATE_BV, to force a reload. */ 1761 cpudata->gfpu.xsh_xstate_bv = svm_xcr0_mask; 1762 } 1763 } 1764 1765 svm_vmcb_cache_update(vmcb, flags); 1766 1767 comm->state_wanted = 0; 1768 comm->state_cached |= flags; 1769 } 1770 1771 static void 1772 svm_vcpu_getstate(struct nvmm_cpu *vcpu) 1773 { 1774 struct nvmm_comm_page *comm = vcpu->comm; 1775 struct nvmm_x64_state *state = &comm->state; 1776 struct svm_cpudata *cpudata = vcpu->cpudata; 1777 struct vmcb *vmcb = cpudata->vmcb; 1778 uint64_t flags; 1779 1780 flags = comm->state_wanted; 1781 1782 if (flags & NVMM_X64_STATE_SEGS) { 1783 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_CS], 1784 &vmcb->state.cs); 1785 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_DS], 1786 &vmcb->state.ds); 1787 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_ES], 1788 &vmcb->state.es); 1789 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_FS], 1790 &vmcb->state.fs); 1791 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_GS], 1792 &vmcb->state.gs); 1793 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_SS], 1794 &vmcb->state.ss); 1795 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_GDT], 1796 &vmcb->state.gdt); 1797 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_IDT], 1798 &vmcb->state.idt); 1799 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_LDT], 1800 &vmcb->state.ldt); 1801 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_TR], 1802 &vmcb->state.tr); 1803 1804 state->segs[NVMM_X64_SEG_SS].attrib.dpl = vmcb->state.cpl; 1805 } 1806 1807 CTASSERT(sizeof(cpudata->gprs) == sizeof(state->gprs)); 1808 if (flags & NVMM_X64_STATE_GPRS) { 1809 memcpy(state->gprs, cpudata->gprs, sizeof(state->gprs)); 1810 1811 state->gprs[NVMM_X64_GPR_RIP] = vmcb->state.rip; 1812 state->gprs[NVMM_X64_GPR_RSP] = vmcb->state.rsp; 1813 state->gprs[NVMM_X64_GPR_RAX] = vmcb->state.rax; 1814 state->gprs[NVMM_X64_GPR_RFLAGS] = vmcb->state.rflags; 1815 } 1816 1817 if (flags & NVMM_X64_STATE_CRS) { 1818 state->crs[NVMM_X64_CR_CR0] = vmcb->state.cr0; 1819 state->crs[NVMM_X64_CR_CR2] = vmcb->state.cr2; 1820 state->crs[NVMM_X64_CR_CR3] = vmcb->state.cr3; 1821 state->crs[NVMM_X64_CR_CR4] = vmcb->state.cr4; 1822 state->crs[NVMM_X64_CR_CR8] = __SHIFTOUT(vmcb->ctrl.v, 1823 VMCB_CTRL_V_TPR); 1824 state->crs[NVMM_X64_CR_XCR0] = cpudata->gxcr0; 1825 } 1826 1827 CTASSERT(sizeof(cpudata->drs) == sizeof(state->drs)); 1828 if (flags & NVMM_X64_STATE_DRS) { 1829 memcpy(state->drs, cpudata->drs, sizeof(state->drs)); 1830 1831 state->drs[NVMM_X64_DR_DR6] = vmcb->state.dr6; 1832 state->drs[NVMM_X64_DR_DR7] = vmcb->state.dr7; 1833 } 1834 1835 if (flags & NVMM_X64_STATE_MSRS) { 1836 state->msrs[NVMM_X64_MSR_EFER] = vmcb->state.efer; 1837 state->msrs[NVMM_X64_MSR_STAR] = vmcb->state.star; 1838 state->msrs[NVMM_X64_MSR_LSTAR] = vmcb->state.lstar; 1839 state->msrs[NVMM_X64_MSR_CSTAR] = vmcb->state.cstar; 1840 state->msrs[NVMM_X64_MSR_SFMASK] = vmcb->state.sfmask; 1841 state->msrs[NVMM_X64_MSR_KERNELGSBASE] = 1842 vmcb->state.kernelgsbase; 1843 state->msrs[NVMM_X64_MSR_SYSENTER_CS] = 1844 vmcb->state.sysenter_cs; 1845 state->msrs[NVMM_X64_MSR_SYSENTER_ESP] = 1846 vmcb->state.sysenter_esp; 1847 state->msrs[NVMM_X64_MSR_SYSENTER_EIP] = 1848 vmcb->state.sysenter_eip; 1849 state->msrs[NVMM_X64_MSR_PAT] = vmcb->state.g_pat; 1850 state->msrs[NVMM_X64_MSR_TSC] = cpudata->gtsc; 1851 1852 /* Hide SVME. */ 1853 state->msrs[NVMM_X64_MSR_EFER] &= ~EFER_SVME; 1854 } 1855 1856 if (flags & NVMM_X64_STATE_INTR) { 1857 state->intr.int_shadow = 1858 (vmcb->ctrl.intr & VMCB_CTRL_INTR_SHADOW) != 0; 1859 state->intr.int_window_exiting = cpudata->int_window_exit; 1860 state->intr.nmi_window_exiting = cpudata->nmi_window_exit; 1861 state->intr.evt_pending = cpudata->evt_pending; 1862 } 1863 1864 CTASSERT(sizeof(cpudata->gfpu.xsh_fxsave) == sizeof(state->fpu)); 1865 if (flags & NVMM_X64_STATE_FPU) { 1866 memcpy(&state->fpu, cpudata->gfpu.xsh_fxsave, 1867 sizeof(state->fpu)); 1868 } 1869 1870 comm->state_wanted = 0; 1871 comm->state_cached |= flags; 1872 } 1873 1874 static void 1875 svm_vcpu_state_provide(struct nvmm_cpu *vcpu, uint64_t flags) 1876 { 1877 vcpu->comm->state_wanted = flags; 1878 svm_vcpu_getstate(vcpu); 1879 } 1880 1881 static void 1882 svm_vcpu_state_commit(struct nvmm_cpu *vcpu) 1883 { 1884 vcpu->comm->state_wanted = vcpu->comm->state_commit; 1885 vcpu->comm->state_commit = 0; 1886 svm_vcpu_setstate(vcpu); 1887 } 1888 1889 /* -------------------------------------------------------------------------- */ 1890 1891 static void 1892 svm_asid_alloc(struct nvmm_cpu *vcpu) 1893 { 1894 struct svm_cpudata *cpudata = vcpu->cpudata; 1895 struct vmcb *vmcb = cpudata->vmcb; 1896 size_t i, oct, bit; 1897 1898 mutex_enter(&svm_asidlock); 1899 1900 for (i = 0; i < svm_maxasid; i++) { 1901 oct = i / 8; 1902 bit = i % 8; 1903 1904 if (svm_asidmap[oct] & __BIT(bit)) { 1905 continue; 1906 } 1907 1908 svm_asidmap[oct] |= __BIT(bit); 1909 vmcb->ctrl.guest_asid = i; 1910 mutex_exit(&svm_asidlock); 1911 return; 1912 } 1913 1914 /* 1915 * No free ASID. Use the last one, which is shared and requires 1916 * special TLB handling. 1917 */ 1918 cpudata->shared_asid = true; 1919 vmcb->ctrl.guest_asid = svm_maxasid - 1; 1920 mutex_exit(&svm_asidlock); 1921 } 1922 1923 static void 1924 svm_asid_free(struct nvmm_cpu *vcpu) 1925 { 1926 struct svm_cpudata *cpudata = vcpu->cpudata; 1927 struct vmcb *vmcb = cpudata->vmcb; 1928 size_t oct, bit; 1929 1930 if (cpudata->shared_asid) { 1931 return; 1932 } 1933 1934 oct = vmcb->ctrl.guest_asid / 8; 1935 bit = vmcb->ctrl.guest_asid % 8; 1936 1937 mutex_enter(&svm_asidlock); 1938 svm_asidmap[oct] &= ~__BIT(bit); 1939 mutex_exit(&svm_asidlock); 1940 } 1941 1942 static void 1943 svm_vcpu_init(struct nvmm_machine *mach, struct nvmm_cpu *vcpu) 1944 { 1945 struct svm_cpudata *cpudata = vcpu->cpudata; 1946 struct vmcb *vmcb = cpudata->vmcb; 1947 1948 /* Allow reads/writes of Control Registers. */ 1949 vmcb->ctrl.intercept_cr = 0; 1950 1951 /* Allow reads/writes of Debug Registers. */ 1952 vmcb->ctrl.intercept_dr = 0; 1953 1954 /* Allow exceptions 0 to 31. */ 1955 vmcb->ctrl.intercept_vec = 0; 1956 1957 /* 1958 * Allow: 1959 * - SMI [smm interrupts] 1960 * - VINTR [virtual interrupts] 1961 * - CR0_SPEC [CR0 writes changing other fields than CR0.TS or CR0.MP] 1962 * - RIDTR [reads of IDTR] 1963 * - RGDTR [reads of GDTR] 1964 * - RLDTR [reads of LDTR] 1965 * - RTR [reads of TR] 1966 * - WIDTR [writes of IDTR] 1967 * - WGDTR [writes of GDTR] 1968 * - WLDTR [writes of LDTR] 1969 * - WTR [writes of TR] 1970 * - RDTSC [rdtsc instruction] 1971 * - PUSHF [pushf instruction] 1972 * - POPF [popf instruction] 1973 * - IRET [iret instruction] 1974 * - INTN [int $n instructions] 1975 * - INVD [invd instruction] 1976 * - PAUSE [pause instruction] 1977 * - INVLPG [invplg instruction] 1978 * - TASKSW [task switches] 1979 * 1980 * Intercept the rest below. 1981 */ 1982 vmcb->ctrl.intercept_misc1 = 1983 VMCB_CTRL_INTERCEPT_INTR | 1984 VMCB_CTRL_INTERCEPT_NMI | 1985 VMCB_CTRL_INTERCEPT_INIT | 1986 VMCB_CTRL_INTERCEPT_RDPMC | 1987 VMCB_CTRL_INTERCEPT_CPUID | 1988 VMCB_CTRL_INTERCEPT_RSM | 1989 VMCB_CTRL_INTERCEPT_HLT | 1990 VMCB_CTRL_INTERCEPT_INVLPGA | 1991 VMCB_CTRL_INTERCEPT_IOIO_PROT | 1992 VMCB_CTRL_INTERCEPT_MSR_PROT | 1993 VMCB_CTRL_INTERCEPT_FERR_FREEZE | 1994 VMCB_CTRL_INTERCEPT_SHUTDOWN; 1995 1996 /* 1997 * Allow: 1998 * - ICEBP [icebp instruction] 1999 * - WBINVD [wbinvd instruction] 2000 * - WCR_SPEC(0..15) [writes of CR0-15, received after instruction] 2001 * 2002 * Intercept the rest below. 2003 */ 2004 vmcb->ctrl.intercept_misc2 = 2005 VMCB_CTRL_INTERCEPT_VMRUN | 2006 VMCB_CTRL_INTERCEPT_VMMCALL | 2007 VMCB_CTRL_INTERCEPT_VMLOAD | 2008 VMCB_CTRL_INTERCEPT_VMSAVE | 2009 VMCB_CTRL_INTERCEPT_STGI | 2010 VMCB_CTRL_INTERCEPT_CLGI | 2011 VMCB_CTRL_INTERCEPT_SKINIT | 2012 VMCB_CTRL_INTERCEPT_RDTSCP | 2013 VMCB_CTRL_INTERCEPT_MONITOR | 2014 VMCB_CTRL_INTERCEPT_MWAIT | 2015 VMCB_CTRL_INTERCEPT_XSETBV; 2016 2017 /* Intercept all I/O accesses. */ 2018 memset(cpudata->iobm, 0xFF, IOBM_SIZE); 2019 vmcb->ctrl.iopm_base_pa = cpudata->iobm_pa; 2020 2021 /* Allow direct access to certain MSRs. */ 2022 memset(cpudata->msrbm, 0xFF, MSRBM_SIZE); 2023 svm_vcpu_msr_allow(cpudata->msrbm, MSR_EFER, true, false); 2024 svm_vcpu_msr_allow(cpudata->msrbm, MSR_STAR, true, true); 2025 svm_vcpu_msr_allow(cpudata->msrbm, MSR_LSTAR, true, true); 2026 svm_vcpu_msr_allow(cpudata->msrbm, MSR_CSTAR, true, true); 2027 svm_vcpu_msr_allow(cpudata->msrbm, MSR_SFMASK, true, true); 2028 svm_vcpu_msr_allow(cpudata->msrbm, MSR_KERNELGSBASE, true, true); 2029 svm_vcpu_msr_allow(cpudata->msrbm, MSR_SYSENTER_CS, true, true); 2030 svm_vcpu_msr_allow(cpudata->msrbm, MSR_SYSENTER_ESP, true, true); 2031 svm_vcpu_msr_allow(cpudata->msrbm, MSR_SYSENTER_EIP, true, true); 2032 svm_vcpu_msr_allow(cpudata->msrbm, MSR_FSBASE, true, true); 2033 svm_vcpu_msr_allow(cpudata->msrbm, MSR_GSBASE, true, true); 2034 svm_vcpu_msr_allow(cpudata->msrbm, MSR_CR_PAT, true, true); 2035 svm_vcpu_msr_allow(cpudata->msrbm, MSR_TSC, true, false); 2036 vmcb->ctrl.msrpm_base_pa = cpudata->msrbm_pa; 2037 2038 /* Generate ASID. */ 2039 svm_asid_alloc(vcpu); 2040 2041 /* Virtual TPR. */ 2042 vmcb->ctrl.v = VMCB_CTRL_V_INTR_MASKING; 2043 2044 /* Enable Nested Paging. */ 2045 vmcb->ctrl.enable1 = VMCB_CTRL_ENABLE_NP; 2046 vmcb->ctrl.n_cr3 = mach->vm->vm_map.pmap->pm_pdirpa[0]; 2047 2048 /* Init XSAVE header. */ 2049 cpudata->gfpu.xsh_xstate_bv = svm_xcr0_mask; 2050 cpudata->gfpu.xsh_xcomp_bv = 0; 2051 2052 /* These MSRs are static. */ 2053 cpudata->star = rdmsr(MSR_STAR); 2054 cpudata->lstar = rdmsr(MSR_LSTAR); 2055 cpudata->cstar = rdmsr(MSR_CSTAR); 2056 cpudata->sfmask = rdmsr(MSR_SFMASK); 2057 2058 /* Install the RESET state. */ 2059 memcpy(&vcpu->comm->state, &nvmm_x86_reset_state, 2060 sizeof(nvmm_x86_reset_state)); 2061 vcpu->comm->state_wanted = NVMM_X64_STATE_ALL; 2062 vcpu->comm->state_cached = 0; 2063 svm_vcpu_setstate(vcpu); 2064 } 2065 2066 static int 2067 svm_vcpu_create(struct nvmm_machine *mach, struct nvmm_cpu *vcpu) 2068 { 2069 struct svm_cpudata *cpudata; 2070 int error; 2071 2072 /* Allocate the SVM cpudata. */ 2073 cpudata = (struct svm_cpudata *)uvm_km_alloc(kernel_map, 2074 roundup(sizeof(*cpudata), PAGE_SIZE), 0, 2075 UVM_KMF_WIRED|UVM_KMF_ZERO); 2076 vcpu->cpudata = cpudata; 2077 2078 /* VMCB */ 2079 error = svm_memalloc(&cpudata->vmcb_pa, (vaddr_t *)&cpudata->vmcb, 2080 VMCB_NPAGES); 2081 if (error) 2082 goto error; 2083 2084 /* I/O Bitmap */ 2085 error = svm_memalloc(&cpudata->iobm_pa, (vaddr_t *)&cpudata->iobm, 2086 IOBM_NPAGES); 2087 if (error) 2088 goto error; 2089 2090 /* MSR Bitmap */ 2091 error = svm_memalloc(&cpudata->msrbm_pa, (vaddr_t *)&cpudata->msrbm, 2092 MSRBM_NPAGES); 2093 if (error) 2094 goto error; 2095 2096 /* Init the VCPU info. */ 2097 svm_vcpu_init(mach, vcpu); 2098 2099 return 0; 2100 2101 error: 2102 if (cpudata->vmcb_pa) { 2103 svm_memfree(cpudata->vmcb_pa, (vaddr_t)cpudata->vmcb, 2104 VMCB_NPAGES); 2105 } 2106 if (cpudata->iobm_pa) { 2107 svm_memfree(cpudata->iobm_pa, (vaddr_t)cpudata->iobm, 2108 IOBM_NPAGES); 2109 } 2110 if (cpudata->msrbm_pa) { 2111 svm_memfree(cpudata->msrbm_pa, (vaddr_t)cpudata->msrbm, 2112 MSRBM_NPAGES); 2113 } 2114 uvm_km_free(kernel_map, (vaddr_t)cpudata, 2115 roundup(sizeof(*cpudata), PAGE_SIZE), UVM_KMF_WIRED); 2116 return error; 2117 } 2118 2119 static void 2120 svm_vcpu_destroy(struct nvmm_machine *mach, struct nvmm_cpu *vcpu) 2121 { 2122 struct svm_cpudata *cpudata = vcpu->cpudata; 2123 2124 svm_asid_free(vcpu); 2125 2126 svm_memfree(cpudata->vmcb_pa, (vaddr_t)cpudata->vmcb, VMCB_NPAGES); 2127 svm_memfree(cpudata->iobm_pa, (vaddr_t)cpudata->iobm, IOBM_NPAGES); 2128 svm_memfree(cpudata->msrbm_pa, (vaddr_t)cpudata->msrbm, MSRBM_NPAGES); 2129 2130 uvm_km_free(kernel_map, (vaddr_t)cpudata, 2131 roundup(sizeof(*cpudata), PAGE_SIZE), UVM_KMF_WIRED); 2132 } 2133 2134 /* -------------------------------------------------------------------------- */ 2135 2136 static int 2137 svm_vcpu_configure_cpuid(struct svm_cpudata *cpudata, void *data) 2138 { 2139 struct nvmm_vcpu_conf_cpuid *cpuid = data; 2140 size_t i; 2141 2142 if (__predict_false(cpuid->mask && cpuid->exit)) { 2143 return EINVAL; 2144 } 2145 if (__predict_false(cpuid->mask && 2146 ((cpuid->u.mask.set.eax & cpuid->u.mask.del.eax) || 2147 (cpuid->u.mask.set.ebx & cpuid->u.mask.del.ebx) || 2148 (cpuid->u.mask.set.ecx & cpuid->u.mask.del.ecx) || 2149 (cpuid->u.mask.set.edx & cpuid->u.mask.del.edx)))) { 2150 return EINVAL; 2151 } 2152 2153 /* If unset, delete, to restore the default behavior. */ 2154 if (!cpuid->mask && !cpuid->exit) { 2155 for (i = 0; i < SVM_NCPUIDS; i++) { 2156 if (!cpudata->cpuidpresent[i]) { 2157 continue; 2158 } 2159 if (cpudata->cpuid[i].leaf == cpuid->leaf) { 2160 cpudata->cpuidpresent[i] = false; 2161 } 2162 } 2163 return 0; 2164 } 2165 2166 /* If already here, replace. */ 2167 for (i = 0; i < SVM_NCPUIDS; i++) { 2168 if (!cpudata->cpuidpresent[i]) { 2169 continue; 2170 } 2171 if (cpudata->cpuid[i].leaf == cpuid->leaf) { 2172 memcpy(&cpudata->cpuid[i], cpuid, 2173 sizeof(struct nvmm_vcpu_conf_cpuid)); 2174 return 0; 2175 } 2176 } 2177 2178 /* Not here, insert. */ 2179 for (i = 0; i < SVM_NCPUIDS; i++) { 2180 if (!cpudata->cpuidpresent[i]) { 2181 cpudata->cpuidpresent[i] = true; 2182 memcpy(&cpudata->cpuid[i], cpuid, 2183 sizeof(struct nvmm_vcpu_conf_cpuid)); 2184 return 0; 2185 } 2186 } 2187 2188 return ENOBUFS; 2189 } 2190 2191 static int 2192 svm_vcpu_configure(struct nvmm_cpu *vcpu, uint64_t op, void *data) 2193 { 2194 struct svm_cpudata *cpudata = vcpu->cpudata; 2195 2196 switch (op) { 2197 case NVMM_VCPU_CONF_MD(NVMM_VCPU_CONF_CPUID): 2198 return svm_vcpu_configure_cpuid(cpudata, data); 2199 default: 2200 return EINVAL; 2201 } 2202 } 2203 2204 /* -------------------------------------------------------------------------- */ 2205 2206 static void 2207 svm_tlb_flush(struct pmap *pm) 2208 { 2209 struct nvmm_machine *mach = pm->pm_data; 2210 struct svm_machdata *machdata = mach->machdata; 2211 2212 atomic_inc_64(&machdata->mach_htlb_gen); 2213 2214 /* Generates IPIs, which cause #VMEXITs. */ 2215 pmap_tlb_shootdown(pmap_kernel(), -1, PTE_G, TLBSHOOT_UPDATE); 2216 } 2217 2218 static void 2219 svm_machine_create(struct nvmm_machine *mach) 2220 { 2221 struct svm_machdata *machdata; 2222 2223 /* Fill in pmap info. */ 2224 mach->vm->vm_map.pmap->pm_data = (void *)mach; 2225 mach->vm->vm_map.pmap->pm_tlb_flush = svm_tlb_flush; 2226 2227 machdata = kmem_zalloc(sizeof(struct svm_machdata), KM_SLEEP); 2228 mach->machdata = machdata; 2229 2230 /* Start with an hTLB flush everywhere. */ 2231 machdata->mach_htlb_gen = 1; 2232 } 2233 2234 static void 2235 svm_machine_destroy(struct nvmm_machine *mach) 2236 { 2237 kmem_free(mach->machdata, sizeof(struct svm_machdata)); 2238 } 2239 2240 static int 2241 svm_machine_configure(struct nvmm_machine *mach, uint64_t op, void *data) 2242 { 2243 panic("%s: impossible", __func__); 2244 } 2245 2246 /* -------------------------------------------------------------------------- */ 2247 2248 static bool 2249 svm_ident(void) 2250 { 2251 u_int descs[4]; 2252 uint64_t msr; 2253 2254 if (cpu_vendor != CPUVENDOR_AMD) { 2255 return false; 2256 } 2257 if (!(cpu_feature[3] & CPUID_SVM)) { 2258 return false; 2259 } 2260 2261 if (curcpu()->ci_max_ext_cpuid < 0x8000000a) { 2262 return false; 2263 } 2264 x86_cpuid(0x8000000a, descs); 2265 2266 /* Want Nested Paging. */ 2267 if (!(descs[3] & CPUID_AMD_SVM_NP)) { 2268 return false; 2269 } 2270 2271 /* Want nRIP. */ 2272 if (!(descs[3] & CPUID_AMD_SVM_NRIPS)) { 2273 return false; 2274 } 2275 2276 svm_decode_assist = (descs[3] & CPUID_AMD_SVM_DecodeAssist) != 0; 2277 2278 msr = rdmsr(MSR_VMCR); 2279 if ((msr & VMCR_SVMED) && (msr & VMCR_LOCK)) { 2280 return false; 2281 } 2282 2283 return true; 2284 } 2285 2286 static void 2287 svm_init_asid(uint32_t maxasid) 2288 { 2289 size_t i, j, allocsz; 2290 2291 mutex_init(&svm_asidlock, MUTEX_DEFAULT, IPL_NONE); 2292 2293 /* Arbitrarily limit. */ 2294 maxasid = uimin(maxasid, 8192); 2295 2296 svm_maxasid = maxasid; 2297 allocsz = roundup(maxasid, 8) / 8; 2298 svm_asidmap = kmem_zalloc(allocsz, KM_SLEEP); 2299 2300 /* ASID 0 is reserved for the host. */ 2301 svm_asidmap[0] |= __BIT(0); 2302 2303 /* ASID n-1 is special, we share it. */ 2304 i = (maxasid - 1) / 8; 2305 j = (maxasid - 1) % 8; 2306 svm_asidmap[i] |= __BIT(j); 2307 } 2308 2309 static void 2310 svm_change_cpu(void *arg1, void *arg2) 2311 { 2312 bool enable = (bool)arg1; 2313 uint64_t msr; 2314 2315 msr = rdmsr(MSR_VMCR); 2316 if (msr & VMCR_SVMED) { 2317 wrmsr(MSR_VMCR, msr & ~VMCR_SVMED); 2318 } 2319 2320 if (!enable) { 2321 wrmsr(MSR_VM_HSAVE_PA, 0); 2322 } 2323 2324 msr = rdmsr(MSR_EFER); 2325 if (enable) { 2326 msr |= EFER_SVME; 2327 } else { 2328 msr &= ~EFER_SVME; 2329 } 2330 wrmsr(MSR_EFER, msr); 2331 2332 if (enable) { 2333 wrmsr(MSR_VM_HSAVE_PA, hsave[cpu_index(curcpu())].pa); 2334 } 2335 } 2336 2337 static void 2338 svm_init(void) 2339 { 2340 CPU_INFO_ITERATOR cii; 2341 struct cpu_info *ci; 2342 struct vm_page *pg; 2343 u_int descs[4]; 2344 uint64_t xc; 2345 2346 x86_cpuid(0x8000000a, descs); 2347 2348 /* The guest TLB flush command. */ 2349 if (descs[3] & CPUID_AMD_SVM_FlushByASID) { 2350 svm_ctrl_tlb_flush = VMCB_CTRL_TLB_CTRL_FLUSH_GUEST; 2351 } else { 2352 svm_ctrl_tlb_flush = VMCB_CTRL_TLB_CTRL_FLUSH_ALL; 2353 } 2354 2355 /* Init the ASID. */ 2356 svm_init_asid(descs[1]); 2357 2358 /* Init the XCR0 mask. */ 2359 svm_xcr0_mask = SVM_XCR0_MASK_DEFAULT & x86_xsave_features; 2360 2361 memset(hsave, 0, sizeof(hsave)); 2362 for (CPU_INFO_FOREACH(cii, ci)) { 2363 pg = uvm_pagealloc(NULL, 0, NULL, UVM_PGA_ZERO); 2364 hsave[cpu_index(ci)].pa = VM_PAGE_TO_PHYS(pg); 2365 } 2366 2367 xc = xc_broadcast(0, svm_change_cpu, (void *)true, NULL); 2368 xc_wait(xc); 2369 } 2370 2371 static void 2372 svm_fini_asid(void) 2373 { 2374 size_t allocsz; 2375 2376 allocsz = roundup(svm_maxasid, 8) / 8; 2377 kmem_free(svm_asidmap, allocsz); 2378 2379 mutex_destroy(&svm_asidlock); 2380 } 2381 2382 static void 2383 svm_fini(void) 2384 { 2385 uint64_t xc; 2386 size_t i; 2387 2388 xc = xc_broadcast(0, svm_change_cpu, (void *)false, NULL); 2389 xc_wait(xc); 2390 2391 for (i = 0; i < MAXCPUS; i++) { 2392 if (hsave[i].pa != 0) 2393 uvm_pagefree(PHYS_TO_VM_PAGE(hsave[i].pa)); 2394 } 2395 2396 svm_fini_asid(); 2397 } 2398 2399 static void 2400 svm_capability(struct nvmm_capability *cap) 2401 { 2402 cap->arch.mach_conf_support = 0; 2403 cap->arch.vcpu_conf_support = 2404 NVMM_CAP_ARCH_VCPU_CONF_CPUID; 2405 cap->arch.xcr0_mask = svm_xcr0_mask; 2406 cap->arch.mxcsr_mask = x86_fpu_mxcsr_mask; 2407 cap->arch.conf_cpuid_maxops = SVM_NCPUIDS; 2408 } 2409 2410 const struct nvmm_impl nvmm_x86_svm = { 2411 .ident = svm_ident, 2412 .init = svm_init, 2413 .fini = svm_fini, 2414 .capability = svm_capability, 2415 .mach_conf_max = NVMM_X86_MACH_NCONF, 2416 .mach_conf_sizes = NULL, 2417 .vcpu_conf_max = NVMM_X86_VCPU_NCONF, 2418 .vcpu_conf_sizes = svm_vcpu_conf_sizes, 2419 .state_size = sizeof(struct nvmm_x64_state), 2420 .machine_create = svm_machine_create, 2421 .machine_destroy = svm_machine_destroy, 2422 .machine_configure = svm_machine_configure, 2423 .vcpu_create = svm_vcpu_create, 2424 .vcpu_destroy = svm_vcpu_destroy, 2425 .vcpu_configure = svm_vcpu_configure, 2426 .vcpu_setstate = svm_vcpu_setstate, 2427 .vcpu_getstate = svm_vcpu_getstate, 2428 .vcpu_inject = svm_vcpu_inject, 2429 .vcpu_run = svm_vcpu_run 2430 }; 2431
Indexes created Mon Oct 27 08:10:08 GMT 2025