nvmm_x86_svm.c revision 1.46.4.3
1 /* $NetBSD: nvmm_x86_svm.c,v 1.46.4.3 2019/11/25 16:39:30 martin Exp $ */ 2 3 /* 4 * Copyright (c) 2018-2019 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Maxime Villard. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: nvmm_x86_svm.c,v 1.46.4.3 2019/11/25 16:39:30 martin Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/kmem.h> 39 #include <sys/cpu.h> 40 #include <sys/xcall.h> 41 #include <sys/mman.h> 42 43 #include <uvm/uvm.h> 44 #include <uvm/uvm_page.h> 45 46 #include <x86/cputypes.h> 47 #include <x86/specialreg.h> 48 #include <x86/pmap.h> 49 #include <x86/dbregs.h> 50 #include <x86/cpu_counter.h> 51 #include <machine/cpuvar.h> 52 53 #include <dev/nvmm/nvmm.h> 54 #include <dev/nvmm/nvmm_internal.h> 55 #include <dev/nvmm/x86/nvmm_x86.h> 56 57 int svm_vmrun(paddr_t, uint64_t *); 58 59 #define MSR_VM_HSAVE_PA 0xC0010117 60 61 /* -------------------------------------------------------------------------- */ 62 63 #define VMCB_EXITCODE_CR0_READ 0x0000 64 #define VMCB_EXITCODE_CR1_READ 0x0001 65 #define VMCB_EXITCODE_CR2_READ 0x0002 66 #define VMCB_EXITCODE_CR3_READ 0x0003 67 #define VMCB_EXITCODE_CR4_READ 0x0004 68 #define VMCB_EXITCODE_CR5_READ 0x0005 69 #define VMCB_EXITCODE_CR6_READ 0x0006 70 #define VMCB_EXITCODE_CR7_READ 0x0007 71 #define VMCB_EXITCODE_CR8_READ 0x0008 72 #define VMCB_EXITCODE_CR9_READ 0x0009 73 #define VMCB_EXITCODE_CR10_READ 0x000A 74 #define VMCB_EXITCODE_CR11_READ 0x000B 75 #define VMCB_EXITCODE_CR12_READ 0x000C 76 #define VMCB_EXITCODE_CR13_READ 0x000D 77 #define VMCB_EXITCODE_CR14_READ 0x000E 78 #define VMCB_EXITCODE_CR15_READ 0x000F 79 #define VMCB_EXITCODE_CR0_WRITE 0x0010 80 #define VMCB_EXITCODE_CR1_WRITE 0x0011 81 #define VMCB_EXITCODE_CR2_WRITE 0x0012 82 #define VMCB_EXITCODE_CR3_WRITE 0x0013 83 #define VMCB_EXITCODE_CR4_WRITE 0x0014 84 #define VMCB_EXITCODE_CR5_WRITE 0x0015 85 #define VMCB_EXITCODE_CR6_WRITE 0x0016 86 #define VMCB_EXITCODE_CR7_WRITE 0x0017 87 #define VMCB_EXITCODE_CR8_WRITE 0x0018 88 #define VMCB_EXITCODE_CR9_WRITE 0x0019 89 #define VMCB_EXITCODE_CR10_WRITE 0x001A 90 #define VMCB_EXITCODE_CR11_WRITE 0x001B 91 #define VMCB_EXITCODE_CR12_WRITE 0x001C 92 #define VMCB_EXITCODE_CR13_WRITE 0x001D 93 #define VMCB_EXITCODE_CR14_WRITE 0x001E 94 #define VMCB_EXITCODE_CR15_WRITE 0x001F 95 #define VMCB_EXITCODE_DR0_READ 0x0020 96 #define VMCB_EXITCODE_DR1_READ 0x0021 97 #define VMCB_EXITCODE_DR2_READ 0x0022 98 #define VMCB_EXITCODE_DR3_READ 0x0023 99 #define VMCB_EXITCODE_DR4_READ 0x0024 100 #define VMCB_EXITCODE_DR5_READ 0x0025 101 #define VMCB_EXITCODE_DR6_READ 0x0026 102 #define VMCB_EXITCODE_DR7_READ 0x0027 103 #define VMCB_EXITCODE_DR8_READ 0x0028 104 #define VMCB_EXITCODE_DR9_READ 0x0029 105 #define VMCB_EXITCODE_DR10_READ 0x002A 106 #define VMCB_EXITCODE_DR11_READ 0x002B 107 #define VMCB_EXITCODE_DR12_READ 0x002C 108 #define VMCB_EXITCODE_DR13_READ 0x002D 109 #define VMCB_EXITCODE_DR14_READ 0x002E 110 #define VMCB_EXITCODE_DR15_READ 0x002F 111 #define VMCB_EXITCODE_DR0_WRITE 0x0030 112 #define VMCB_EXITCODE_DR1_WRITE 0x0031 113 #define VMCB_EXITCODE_DR2_WRITE 0x0032 114 #define VMCB_EXITCODE_DR3_WRITE 0x0033 115 #define VMCB_EXITCODE_DR4_WRITE 0x0034 116 #define VMCB_EXITCODE_DR5_WRITE 0x0035 117 #define VMCB_EXITCODE_DR6_WRITE 0x0036 118 #define VMCB_EXITCODE_DR7_WRITE 0x0037 119 #define VMCB_EXITCODE_DR8_WRITE 0x0038 120 #define VMCB_EXITCODE_DR9_WRITE 0x0039 121 #define VMCB_EXITCODE_DR10_WRITE 0x003A 122 #define VMCB_EXITCODE_DR11_WRITE 0x003B 123 #define VMCB_EXITCODE_DR12_WRITE 0x003C 124 #define VMCB_EXITCODE_DR13_WRITE 0x003D 125 #define VMCB_EXITCODE_DR14_WRITE 0x003E 126 #define VMCB_EXITCODE_DR15_WRITE 0x003F 127 #define VMCB_EXITCODE_EXCP0 0x0040 128 #define VMCB_EXITCODE_EXCP1 0x0041 129 #define VMCB_EXITCODE_EXCP2 0x0042 130 #define VMCB_EXITCODE_EXCP3 0x0043 131 #define VMCB_EXITCODE_EXCP4 0x0044 132 #define VMCB_EXITCODE_EXCP5 0x0045 133 #define VMCB_EXITCODE_EXCP6 0x0046 134 #define VMCB_EXITCODE_EXCP7 0x0047 135 #define VMCB_EXITCODE_EXCP8 0x0048 136 #define VMCB_EXITCODE_EXCP9 0x0049 137 #define VMCB_EXITCODE_EXCP10 0x004A 138 #define VMCB_EXITCODE_EXCP11 0x004B 139 #define VMCB_EXITCODE_EXCP12 0x004C 140 #define VMCB_EXITCODE_EXCP13 0x004D 141 #define VMCB_EXITCODE_EXCP14 0x004E 142 #define VMCB_EXITCODE_EXCP15 0x004F 143 #define VMCB_EXITCODE_EXCP16 0x0050 144 #define VMCB_EXITCODE_EXCP17 0x0051 145 #define VMCB_EXITCODE_EXCP18 0x0052 146 #define VMCB_EXITCODE_EXCP19 0x0053 147 #define VMCB_EXITCODE_EXCP20 0x0054 148 #define VMCB_EXITCODE_EXCP21 0x0055 149 #define VMCB_EXITCODE_EXCP22 0x0056 150 #define VMCB_EXITCODE_EXCP23 0x0057 151 #define VMCB_EXITCODE_EXCP24 0x0058 152 #define VMCB_EXITCODE_EXCP25 0x0059 153 #define VMCB_EXITCODE_EXCP26 0x005A 154 #define VMCB_EXITCODE_EXCP27 0x005B 155 #define VMCB_EXITCODE_EXCP28 0x005C 156 #define VMCB_EXITCODE_EXCP29 0x005D 157 #define VMCB_EXITCODE_EXCP30 0x005E 158 #define VMCB_EXITCODE_EXCP31 0x005F 159 #define VMCB_EXITCODE_INTR 0x0060 160 #define VMCB_EXITCODE_NMI 0x0061 161 #define VMCB_EXITCODE_SMI 0x0062 162 #define VMCB_EXITCODE_INIT 0x0063 163 #define VMCB_EXITCODE_VINTR 0x0064 164 #define VMCB_EXITCODE_CR0_SEL_WRITE 0x0065 165 #define VMCB_EXITCODE_IDTR_READ 0x0066 166 #define VMCB_EXITCODE_GDTR_READ 0x0067 167 #define VMCB_EXITCODE_LDTR_READ 0x0068 168 #define VMCB_EXITCODE_TR_READ 0x0069 169 #define VMCB_EXITCODE_IDTR_WRITE 0x006A 170 #define VMCB_EXITCODE_GDTR_WRITE 0x006B 171 #define VMCB_EXITCODE_LDTR_WRITE 0x006C 172 #define VMCB_EXITCODE_TR_WRITE 0x006D 173 #define VMCB_EXITCODE_RDTSC 0x006E 174 #define VMCB_EXITCODE_RDPMC 0x006F 175 #define VMCB_EXITCODE_PUSHF 0x0070 176 #define VMCB_EXITCODE_POPF 0x0071 177 #define VMCB_EXITCODE_CPUID 0x0072 178 #define VMCB_EXITCODE_RSM 0x0073 179 #define VMCB_EXITCODE_IRET 0x0074 180 #define VMCB_EXITCODE_SWINT 0x0075 181 #define VMCB_EXITCODE_INVD 0x0076 182 #define VMCB_EXITCODE_PAUSE 0x0077 183 #define VMCB_EXITCODE_HLT 0x0078 184 #define VMCB_EXITCODE_INVLPG 0x0079 185 #define VMCB_EXITCODE_INVLPGA 0x007A 186 #define VMCB_EXITCODE_IOIO 0x007B 187 #define VMCB_EXITCODE_MSR 0x007C 188 #define VMCB_EXITCODE_TASK_SWITCH 0x007D 189 #define VMCB_EXITCODE_FERR_FREEZE 0x007E 190 #define VMCB_EXITCODE_SHUTDOWN 0x007F 191 #define VMCB_EXITCODE_VMRUN 0x0080 192 #define VMCB_EXITCODE_VMMCALL 0x0081 193 #define VMCB_EXITCODE_VMLOAD 0x0082 194 #define VMCB_EXITCODE_VMSAVE 0x0083 195 #define VMCB_EXITCODE_STGI 0x0084 196 #define VMCB_EXITCODE_CLGI 0x0085 197 #define VMCB_EXITCODE_SKINIT 0x0086 198 #define VMCB_EXITCODE_RDTSCP 0x0087 199 #define VMCB_EXITCODE_ICEBP 0x0088 200 #define VMCB_EXITCODE_WBINVD 0x0089 201 #define VMCB_EXITCODE_MONITOR 0x008A 202 #define VMCB_EXITCODE_MWAIT 0x008B 203 #define VMCB_EXITCODE_MWAIT_CONDITIONAL 0x008C 204 #define VMCB_EXITCODE_XSETBV 0x008D 205 #define VMCB_EXITCODE_RDPRU 0x008E 206 #define VMCB_EXITCODE_EFER_WRITE_TRAP 0x008F 207 #define VMCB_EXITCODE_CR0_WRITE_TRAP 0x0090 208 #define VMCB_EXITCODE_CR1_WRITE_TRAP 0x0091 209 #define VMCB_EXITCODE_CR2_WRITE_TRAP 0x0092 210 #define VMCB_EXITCODE_CR3_WRITE_TRAP 0x0093 211 #define VMCB_EXITCODE_CR4_WRITE_TRAP 0x0094 212 #define VMCB_EXITCODE_CR5_WRITE_TRAP 0x0095 213 #define VMCB_EXITCODE_CR6_WRITE_TRAP 0x0096 214 #define VMCB_EXITCODE_CR7_WRITE_TRAP 0x0097 215 #define VMCB_EXITCODE_CR8_WRITE_TRAP 0x0098 216 #define VMCB_EXITCODE_CR9_WRITE_TRAP 0x0099 217 #define VMCB_EXITCODE_CR10_WRITE_TRAP 0x009A 218 #define VMCB_EXITCODE_CR11_WRITE_TRAP 0x009B 219 #define VMCB_EXITCODE_CR12_WRITE_TRAP 0x009C 220 #define VMCB_EXITCODE_CR13_WRITE_TRAP 0x009D 221 #define VMCB_EXITCODE_CR14_WRITE_TRAP 0x009E 222 #define VMCB_EXITCODE_CR15_WRITE_TRAP 0x009F 223 #define VMCB_EXITCODE_MCOMMIT 0x00A3 224 #define VMCB_EXITCODE_NPF 0x0400 225 #define VMCB_EXITCODE_AVIC_INCOMP_IPI 0x0401 226 #define VMCB_EXITCODE_AVIC_NOACCEL 0x0402 227 #define VMCB_EXITCODE_VMGEXIT 0x0403 228 #define VMCB_EXITCODE_INVALID -1 229 230 /* -------------------------------------------------------------------------- */ 231 232 struct vmcb_ctrl { 233 uint32_t intercept_cr; 234 #define VMCB_CTRL_INTERCEPT_RCR(x) __BIT( 0 + x) 235 #define VMCB_CTRL_INTERCEPT_WCR(x) __BIT(16 + x) 236 237 uint32_t intercept_dr; 238 #define VMCB_CTRL_INTERCEPT_RDR(x) __BIT( 0 + x) 239 #define VMCB_CTRL_INTERCEPT_WDR(x) __BIT(16 + x) 240 241 uint32_t intercept_vec; 242 #define VMCB_CTRL_INTERCEPT_VEC(x) __BIT(x) 243 244 uint32_t intercept_misc1; 245 #define VMCB_CTRL_INTERCEPT_INTR __BIT(0) 246 #define VMCB_CTRL_INTERCEPT_NMI __BIT(1) 247 #define VMCB_CTRL_INTERCEPT_SMI __BIT(2) 248 #define VMCB_CTRL_INTERCEPT_INIT __BIT(3) 249 #define VMCB_CTRL_INTERCEPT_VINTR __BIT(4) 250 #define VMCB_CTRL_INTERCEPT_CR0_SPEC __BIT(5) 251 #define VMCB_CTRL_INTERCEPT_RIDTR __BIT(6) 252 #define VMCB_CTRL_INTERCEPT_RGDTR __BIT(7) 253 #define VMCB_CTRL_INTERCEPT_RLDTR __BIT(8) 254 #define VMCB_CTRL_INTERCEPT_RTR __BIT(9) 255 #define VMCB_CTRL_INTERCEPT_WIDTR __BIT(10) 256 #define VMCB_CTRL_INTERCEPT_WGDTR __BIT(11) 257 #define VMCB_CTRL_INTERCEPT_WLDTR __BIT(12) 258 #define VMCB_CTRL_INTERCEPT_WTR __BIT(13) 259 #define VMCB_CTRL_INTERCEPT_RDTSC __BIT(14) 260 #define VMCB_CTRL_INTERCEPT_RDPMC __BIT(15) 261 #define VMCB_CTRL_INTERCEPT_PUSHF __BIT(16) 262 #define VMCB_CTRL_INTERCEPT_POPF __BIT(17) 263 #define VMCB_CTRL_INTERCEPT_CPUID __BIT(18) 264 #define VMCB_CTRL_INTERCEPT_RSM __BIT(19) 265 #define VMCB_CTRL_INTERCEPT_IRET __BIT(20) 266 #define VMCB_CTRL_INTERCEPT_INTN __BIT(21) 267 #define VMCB_CTRL_INTERCEPT_INVD __BIT(22) 268 #define VMCB_CTRL_INTERCEPT_PAUSE __BIT(23) 269 #define VMCB_CTRL_INTERCEPT_HLT __BIT(24) 270 #define VMCB_CTRL_INTERCEPT_INVLPG __BIT(25) 271 #define VMCB_CTRL_INTERCEPT_INVLPGA __BIT(26) 272 #define VMCB_CTRL_INTERCEPT_IOIO_PROT __BIT(27) 273 #define VMCB_CTRL_INTERCEPT_MSR_PROT __BIT(28) 274 #define VMCB_CTRL_INTERCEPT_TASKSW __BIT(29) 275 #define VMCB_CTRL_INTERCEPT_FERR_FREEZE __BIT(30) 276 #define VMCB_CTRL_INTERCEPT_SHUTDOWN __BIT(31) 277 278 uint32_t intercept_misc2; 279 #define VMCB_CTRL_INTERCEPT_VMRUN __BIT(0) 280 #define VMCB_CTRL_INTERCEPT_VMMCALL __BIT(1) 281 #define VMCB_CTRL_INTERCEPT_VMLOAD __BIT(2) 282 #define VMCB_CTRL_INTERCEPT_VMSAVE __BIT(3) 283 #define VMCB_CTRL_INTERCEPT_STGI __BIT(4) 284 #define VMCB_CTRL_INTERCEPT_CLGI __BIT(5) 285 #define VMCB_CTRL_INTERCEPT_SKINIT __BIT(6) 286 #define VMCB_CTRL_INTERCEPT_RDTSCP __BIT(7) 287 #define VMCB_CTRL_INTERCEPT_ICEBP __BIT(8) 288 #define VMCB_CTRL_INTERCEPT_WBINVD __BIT(9) 289 #define VMCB_CTRL_INTERCEPT_MONITOR __BIT(10) 290 #define VMCB_CTRL_INTERCEPT_MWAIT __BIT(11) 291 #define VMCB_CTRL_INTERCEPT_MWAIT_ARMED __BIT(12) 292 #define VMCB_CTRL_INTERCEPT_XSETBV __BIT(13) 293 #define VMCB_CTRL_INTERCEPT_RDPRU __BIT(14) 294 #define VMCB_CTRL_INTERCEPT_EFER_SPEC __BIT(15) 295 #define VMCB_CTRL_INTERCEPT_WCR_SPEC(x) __BIT(16 + x) 296 297 uint32_t intercept_misc3; 298 #define VMCB_CTRL_INTERCEPT_MCOMMIT __BIT(3) 299 300 uint8_t rsvd1[36]; 301 uint16_t pause_filt_thresh; 302 uint16_t pause_filt_cnt; 303 uint64_t iopm_base_pa; 304 uint64_t msrpm_base_pa; 305 uint64_t tsc_offset; 306 uint32_t guest_asid; 307 308 uint32_t tlb_ctrl; 309 #define VMCB_CTRL_TLB_CTRL_FLUSH_ALL 0x01 310 #define VMCB_CTRL_TLB_CTRL_FLUSH_GUEST 0x03 311 #define VMCB_CTRL_TLB_CTRL_FLUSH_GUEST_NONGLOBAL 0x07 312 313 uint64_t v; 314 #define VMCB_CTRL_V_TPR __BITS(3,0) 315 #define VMCB_CTRL_V_IRQ __BIT(8) 316 #define VMCB_CTRL_V_VGIF __BIT(9) 317 #define VMCB_CTRL_V_INTR_PRIO __BITS(19,16) 318 #define VMCB_CTRL_V_IGN_TPR __BIT(20) 319 #define VMCB_CTRL_V_INTR_MASKING __BIT(24) 320 #define VMCB_CTRL_V_GUEST_VGIF __BIT(25) 321 #define VMCB_CTRL_V_AVIC_EN __BIT(31) 322 #define VMCB_CTRL_V_INTR_VECTOR __BITS(39,32) 323 324 uint64_t intr; 325 #define VMCB_CTRL_INTR_SHADOW __BIT(0) 326 327 uint64_t exitcode; 328 uint64_t exitinfo1; 329 uint64_t exitinfo2; 330 331 uint64_t exitintinfo; 332 #define VMCB_CTRL_EXITINTINFO_VECTOR __BITS(7,0) 333 #define VMCB_CTRL_EXITINTINFO_TYPE __BITS(10,8) 334 #define VMCB_CTRL_EXITINTINFO_EV __BIT(11) 335 #define VMCB_CTRL_EXITINTINFO_V __BIT(31) 336 #define VMCB_CTRL_EXITINTINFO_ERRORCODE __BITS(63,32) 337 338 uint64_t enable1; 339 #define VMCB_CTRL_ENABLE_NP __BIT(0) 340 #define VMCB_CTRL_ENABLE_SEV __BIT(1) 341 #define VMCB_CTRL_ENABLE_ES_SEV __BIT(2) 342 #define VMCB_CTRL_ENABLE_GMET __BIT(3) 343 #define VMCB_CTRL_ENABLE_VTE __BIT(5) 344 345 uint64_t avic; 346 #define VMCB_CTRL_AVIC_APIC_BAR __BITS(51,0) 347 348 uint64_t ghcb; 349 350 uint64_t eventinj; 351 #define VMCB_CTRL_EVENTINJ_VECTOR __BITS(7,0) 352 #define VMCB_CTRL_EVENTINJ_TYPE __BITS(10,8) 353 #define VMCB_CTRL_EVENTINJ_EV __BIT(11) 354 #define VMCB_CTRL_EVENTINJ_V __BIT(31) 355 #define VMCB_CTRL_EVENTINJ_ERRORCODE __BITS(63,32) 356 357 uint64_t n_cr3; 358 359 uint64_t enable2; 360 #define VMCB_CTRL_ENABLE_LBR __BIT(0) 361 #define VMCB_CTRL_ENABLE_VVMSAVE __BIT(1) 362 363 uint32_t vmcb_clean; 364 #define VMCB_CTRL_VMCB_CLEAN_I __BIT(0) 365 #define VMCB_CTRL_VMCB_CLEAN_IOPM __BIT(1) 366 #define VMCB_CTRL_VMCB_CLEAN_ASID __BIT(2) 367 #define VMCB_CTRL_VMCB_CLEAN_TPR __BIT(3) 368 #define VMCB_CTRL_VMCB_CLEAN_NP __BIT(4) 369 #define VMCB_CTRL_VMCB_CLEAN_CR __BIT(5) 370 #define VMCB_CTRL_VMCB_CLEAN_DR __BIT(6) 371 #define VMCB_CTRL_VMCB_CLEAN_DT __BIT(7) 372 #define VMCB_CTRL_VMCB_CLEAN_SEG __BIT(8) 373 #define VMCB_CTRL_VMCB_CLEAN_CR2 __BIT(9) 374 #define VMCB_CTRL_VMCB_CLEAN_LBR __BIT(10) 375 #define VMCB_CTRL_VMCB_CLEAN_AVIC __BIT(11) 376 377 uint32_t rsvd2; 378 uint64_t nrip; 379 uint8_t inst_len; 380 uint8_t inst_bytes[15]; 381 uint64_t avic_abpp; 382 uint64_t rsvd3; 383 uint64_t avic_ltp; 384 385 uint64_t avic_phys; 386 #define VMCB_CTRL_AVIC_PHYS_TABLE_PTR __BITS(51,12) 387 #define VMCB_CTRL_AVIC_PHYS_MAX_INDEX __BITS(7,0) 388 389 uint64_t rsvd4; 390 uint64_t vmcb_ptr; 391 392 uint8_t pad[752]; 393 } __packed; 394 395 CTASSERT(sizeof(struct vmcb_ctrl) == 1024); 396 397 struct vmcb_segment { 398 uint16_t selector; 399 uint16_t attrib; /* hidden */ 400 uint32_t limit; /* hidden */ 401 uint64_t base; /* hidden */ 402 } __packed; 403 404 CTASSERT(sizeof(struct vmcb_segment) == 16); 405 406 struct vmcb_state { 407 struct vmcb_segment es; 408 struct vmcb_segment cs; 409 struct vmcb_segment ss; 410 struct vmcb_segment ds; 411 struct vmcb_segment fs; 412 struct vmcb_segment gs; 413 struct vmcb_segment gdt; 414 struct vmcb_segment ldt; 415 struct vmcb_segment idt; 416 struct vmcb_segment tr; 417 uint8_t rsvd1[43]; 418 uint8_t cpl; 419 uint8_t rsvd2[4]; 420 uint64_t efer; 421 uint8_t rsvd3[112]; 422 uint64_t cr4; 423 uint64_t cr3; 424 uint64_t cr0; 425 uint64_t dr7; 426 uint64_t dr6; 427 uint64_t rflags; 428 uint64_t rip; 429 uint8_t rsvd4[88]; 430 uint64_t rsp; 431 uint8_t rsvd5[24]; 432 uint64_t rax; 433 uint64_t star; 434 uint64_t lstar; 435 uint64_t cstar; 436 uint64_t sfmask; 437 uint64_t kernelgsbase; 438 uint64_t sysenter_cs; 439 uint64_t sysenter_esp; 440 uint64_t sysenter_eip; 441 uint64_t cr2; 442 uint8_t rsvd6[32]; 443 uint64_t g_pat; 444 uint64_t dbgctl; 445 uint64_t br_from; 446 uint64_t br_to; 447 uint64_t int_from; 448 uint64_t int_to; 449 uint8_t pad[2408]; 450 } __packed; 451 452 CTASSERT(sizeof(struct vmcb_state) == 0xC00); 453 454 struct vmcb { 455 struct vmcb_ctrl ctrl; 456 struct vmcb_state state; 457 } __packed; 458 459 CTASSERT(sizeof(struct vmcb) == PAGE_SIZE); 460 CTASSERT(offsetof(struct vmcb, state) == 0x400); 461 462 /* -------------------------------------------------------------------------- */ 463 464 static void svm_vcpu_state_provide(struct nvmm_cpu *, uint64_t); 465 static void svm_vcpu_state_commit(struct nvmm_cpu *); 466 467 struct svm_hsave { 468 paddr_t pa; 469 }; 470 471 static struct svm_hsave hsave[MAXCPUS]; 472 473 static uint8_t *svm_asidmap __read_mostly; 474 static uint32_t svm_maxasid __read_mostly; 475 static kmutex_t svm_asidlock __cacheline_aligned; 476 477 static bool svm_decode_assist __read_mostly; 478 static uint32_t svm_ctrl_tlb_flush __read_mostly; 479 480 #define SVM_XCR0_MASK_DEFAULT (XCR0_X87|XCR0_SSE) 481 static uint64_t svm_xcr0_mask __read_mostly; 482 483 #define SVM_NCPUIDS 32 484 485 #define VMCB_NPAGES 1 486 487 #define MSRBM_NPAGES 2 488 #define MSRBM_SIZE (MSRBM_NPAGES * PAGE_SIZE) 489 490 #define IOBM_NPAGES 3 491 #define IOBM_SIZE (IOBM_NPAGES * PAGE_SIZE) 492 493 /* Does not include EFER_LMSLE. */ 494 #define EFER_VALID \ 495 (EFER_SCE|EFER_LME|EFER_LMA|EFER_NXE|EFER_SVME|EFER_FFXSR|EFER_TCE) 496 497 #define EFER_TLB_FLUSH \ 498 (EFER_NXE|EFER_LMA|EFER_LME) 499 #define CR0_TLB_FLUSH \ 500 (CR0_PG|CR0_WP|CR0_CD|CR0_NW) 501 #define CR4_TLB_FLUSH \ 502 (CR4_PGE|CR4_PAE|CR4_PSE) 503 504 /* -------------------------------------------------------------------------- */ 505 506 struct svm_machdata { 507 volatile uint64_t mach_htlb_gen; 508 }; 509 510 static const size_t svm_vcpu_conf_sizes[NVMM_X86_VCPU_NCONF] = { 511 [NVMM_VCPU_CONF_MD(NVMM_VCPU_CONF_CPUID)] = 512 sizeof(struct nvmm_vcpu_conf_cpuid), 513 [NVMM_VCPU_CONF_MD(NVMM_VCPU_CONF_TPR)] = 514 sizeof(struct nvmm_vcpu_conf_tpr) 515 }; 516 517 struct svm_cpudata { 518 /* General */ 519 bool shared_asid; 520 bool gtlb_want_flush; 521 bool gtsc_want_update; 522 uint64_t vcpu_htlb_gen; 523 524 /* VMCB */ 525 struct vmcb *vmcb; 526 paddr_t vmcb_pa; 527 528 /* I/O bitmap */ 529 uint8_t *iobm; 530 paddr_t iobm_pa; 531 532 /* MSR bitmap */ 533 uint8_t *msrbm; 534 paddr_t msrbm_pa; 535 536 /* Host state */ 537 uint64_t hxcr0; 538 uint64_t star; 539 uint64_t lstar; 540 uint64_t cstar; 541 uint64_t sfmask; 542 uint64_t fsbase; 543 uint64_t kernelgsbase; 544 bool ts_set; 545 struct xsave_header hfpu __aligned(64); 546 547 /* Intr state */ 548 bool int_window_exit; 549 bool nmi_window_exit; 550 bool evt_pending; 551 552 /* Guest state */ 553 uint64_t gxcr0; 554 uint64_t gprs[NVMM_X64_NGPR]; 555 uint64_t drs[NVMM_X64_NDR]; 556 uint64_t gtsc; 557 struct xsave_header gfpu __aligned(64); 558 559 /* VCPU configuration. */ 560 bool cpuidpresent[SVM_NCPUIDS]; 561 struct nvmm_vcpu_conf_cpuid cpuid[SVM_NCPUIDS]; 562 }; 563 564 static void 565 svm_vmcb_cache_default(struct vmcb *vmcb) 566 { 567 vmcb->ctrl.vmcb_clean = 568 VMCB_CTRL_VMCB_CLEAN_I | 569 VMCB_CTRL_VMCB_CLEAN_IOPM | 570 VMCB_CTRL_VMCB_CLEAN_ASID | 571 VMCB_CTRL_VMCB_CLEAN_TPR | 572 VMCB_CTRL_VMCB_CLEAN_NP | 573 VMCB_CTRL_VMCB_CLEAN_CR | 574 VMCB_CTRL_VMCB_CLEAN_DR | 575 VMCB_CTRL_VMCB_CLEAN_DT | 576 VMCB_CTRL_VMCB_CLEAN_SEG | 577 VMCB_CTRL_VMCB_CLEAN_CR2 | 578 VMCB_CTRL_VMCB_CLEAN_LBR | 579 VMCB_CTRL_VMCB_CLEAN_AVIC; 580 } 581 582 static void 583 svm_vmcb_cache_update(struct vmcb *vmcb, uint64_t flags) 584 { 585 if (flags & NVMM_X64_STATE_SEGS) { 586 vmcb->ctrl.vmcb_clean &= 587 ~(VMCB_CTRL_VMCB_CLEAN_SEG | VMCB_CTRL_VMCB_CLEAN_DT); 588 } 589 if (flags & NVMM_X64_STATE_CRS) { 590 vmcb->ctrl.vmcb_clean &= 591 ~(VMCB_CTRL_VMCB_CLEAN_CR | VMCB_CTRL_VMCB_CLEAN_CR2 | 592 VMCB_CTRL_VMCB_CLEAN_TPR); 593 } 594 if (flags & NVMM_X64_STATE_DRS) { 595 vmcb->ctrl.vmcb_clean &= ~VMCB_CTRL_VMCB_CLEAN_DR; 596 } 597 if (flags & NVMM_X64_STATE_MSRS) { 598 /* CR for EFER, NP for PAT. */ 599 vmcb->ctrl.vmcb_clean &= 600 ~(VMCB_CTRL_VMCB_CLEAN_CR | VMCB_CTRL_VMCB_CLEAN_NP); 601 } 602 } 603 604 static inline void 605 svm_vmcb_cache_flush(struct vmcb *vmcb, uint64_t flags) 606 { 607 vmcb->ctrl.vmcb_clean &= ~flags; 608 } 609 610 static inline void 611 svm_vmcb_cache_flush_all(struct vmcb *vmcb) 612 { 613 vmcb->ctrl.vmcb_clean = 0; 614 } 615 616 #define SVM_EVENT_TYPE_HW_INT 0 617 #define SVM_EVENT_TYPE_NMI 2 618 #define SVM_EVENT_TYPE_EXC 3 619 #define SVM_EVENT_TYPE_SW_INT 4 620 621 static void 622 svm_event_waitexit_enable(struct nvmm_cpu *vcpu, bool nmi) 623 { 624 struct svm_cpudata *cpudata = vcpu->cpudata; 625 struct vmcb *vmcb = cpudata->vmcb; 626 627 if (nmi) { 628 vmcb->ctrl.intercept_misc1 |= VMCB_CTRL_INTERCEPT_IRET; 629 cpudata->nmi_window_exit = true; 630 } else { 631 vmcb->ctrl.intercept_misc1 |= VMCB_CTRL_INTERCEPT_VINTR; 632 vmcb->ctrl.v |= (VMCB_CTRL_V_IRQ | VMCB_CTRL_V_IGN_TPR); 633 svm_vmcb_cache_flush(vmcb, VMCB_CTRL_VMCB_CLEAN_TPR); 634 cpudata->int_window_exit = true; 635 } 636 637 svm_vmcb_cache_flush(vmcb, VMCB_CTRL_VMCB_CLEAN_I); 638 } 639 640 static void 641 svm_event_waitexit_disable(struct nvmm_cpu *vcpu, bool nmi) 642 { 643 struct svm_cpudata *cpudata = vcpu->cpudata; 644 struct vmcb *vmcb = cpudata->vmcb; 645 646 if (nmi) { 647 vmcb->ctrl.intercept_misc1 &= ~VMCB_CTRL_INTERCEPT_IRET; 648 cpudata->nmi_window_exit = false; 649 } else { 650 vmcb->ctrl.intercept_misc1 &= ~VMCB_CTRL_INTERCEPT_VINTR; 651 vmcb->ctrl.v &= ~(VMCB_CTRL_V_IRQ | VMCB_CTRL_V_IGN_TPR); 652 svm_vmcb_cache_flush(vmcb, VMCB_CTRL_VMCB_CLEAN_TPR); 653 cpudata->int_window_exit = false; 654 } 655 656 svm_vmcb_cache_flush(vmcb, VMCB_CTRL_VMCB_CLEAN_I); 657 } 658 659 static inline int 660 svm_event_has_error(uint8_t vector) 661 { 662 switch (vector) { 663 case 8: /* #DF */ 664 case 10: /* #TS */ 665 case 11: /* #NP */ 666 case 12: /* #SS */ 667 case 13: /* #GP */ 668 case 14: /* #PF */ 669 case 17: /* #AC */ 670 case 30: /* #SX */ 671 return 1; 672 default: 673 return 0; 674 } 675 } 676 677 static int 678 svm_vcpu_inject(struct nvmm_cpu *vcpu) 679 { 680 struct nvmm_comm_page *comm = vcpu->comm; 681 struct svm_cpudata *cpudata = vcpu->cpudata; 682 struct vmcb *vmcb = cpudata->vmcb; 683 u_int evtype; 684 uint8_t vector; 685 uint64_t error; 686 int type = 0, err = 0; 687 688 evtype = comm->event.type; 689 vector = comm->event.vector; 690 error = comm->event.u.excp.error; 691 __insn_barrier(); 692 693 switch (evtype) { 694 case NVMM_VCPU_EVENT_EXCP: 695 type = SVM_EVENT_TYPE_EXC; 696 if (vector == 2 || vector >= 32) 697 return EINVAL; 698 if (vector == 3 || vector == 0) 699 return EINVAL; 700 err = svm_event_has_error(vector); 701 break; 702 case NVMM_VCPU_EVENT_INTR: 703 type = SVM_EVENT_TYPE_HW_INT; 704 if (vector == 2) { 705 type = SVM_EVENT_TYPE_NMI; 706 svm_event_waitexit_enable(vcpu, true); 707 } 708 err = 0; 709 break; 710 default: 711 return EINVAL; 712 } 713 714 vmcb->ctrl.eventinj = 715 __SHIFTIN((uint64_t)vector, VMCB_CTRL_EVENTINJ_VECTOR) | 716 __SHIFTIN((uint64_t)type, VMCB_CTRL_EVENTINJ_TYPE) | 717 __SHIFTIN((uint64_t)err, VMCB_CTRL_EVENTINJ_EV) | 718 __SHIFTIN((uint64_t)1, VMCB_CTRL_EVENTINJ_V) | 719 __SHIFTIN((uint64_t)error, VMCB_CTRL_EVENTINJ_ERRORCODE); 720 721 cpudata->evt_pending = true; 722 723 return 0; 724 } 725 726 static void 727 svm_inject_ud(struct nvmm_cpu *vcpu) 728 { 729 struct nvmm_comm_page *comm = vcpu->comm; 730 int ret __diagused; 731 732 comm->event.type = NVMM_VCPU_EVENT_EXCP; 733 comm->event.vector = 6; 734 comm->event.u.excp.error = 0; 735 736 ret = svm_vcpu_inject(vcpu); 737 KASSERT(ret == 0); 738 } 739 740 static void 741 svm_inject_gp(struct nvmm_cpu *vcpu) 742 { 743 struct nvmm_comm_page *comm = vcpu->comm; 744 int ret __diagused; 745 746 comm->event.type = NVMM_VCPU_EVENT_EXCP; 747 comm->event.vector = 13; 748 comm->event.u.excp.error = 0; 749 750 ret = svm_vcpu_inject(vcpu); 751 KASSERT(ret == 0); 752 } 753 754 static inline int 755 svm_vcpu_event_commit(struct nvmm_cpu *vcpu) 756 { 757 if (__predict_true(!vcpu->comm->event_commit)) { 758 return 0; 759 } 760 vcpu->comm->event_commit = false; 761 return svm_vcpu_inject(vcpu); 762 } 763 764 static inline void 765 svm_inkernel_advance(struct vmcb *vmcb) 766 { 767 /* 768 * Maybe we should also apply single-stepping and debug exceptions. 769 * Matters for guest-ring3, because it can execute 'cpuid' under a 770 * debugger. 771 */ 772 vmcb->state.rip = vmcb->ctrl.nrip; 773 vmcb->ctrl.intr &= ~VMCB_CTRL_INTR_SHADOW; 774 } 775 776 static void 777 svm_inkernel_handle_cpuid(struct nvmm_cpu *vcpu, uint64_t eax, uint64_t ecx) 778 { 779 struct svm_cpudata *cpudata = vcpu->cpudata; 780 uint64_t cr4; 781 782 switch (eax) { 783 case 0x00000001: 784 cpudata->vmcb->state.rax &= nvmm_cpuid_00000001.eax; 785 786 cpudata->gprs[NVMM_X64_GPR_RBX] &= ~CPUID_LOCAL_APIC_ID; 787 cpudata->gprs[NVMM_X64_GPR_RBX] |= __SHIFTIN(vcpu->cpuid, 788 CPUID_LOCAL_APIC_ID); 789 790 cpudata->gprs[NVMM_X64_GPR_RCX] &= nvmm_cpuid_00000001.ecx; 791 cpudata->gprs[NVMM_X64_GPR_RCX] |= CPUID2_RAZ; 792 793 cpudata->gprs[NVMM_X64_GPR_RDX] &= nvmm_cpuid_00000001.edx; 794 795 /* CPUID2_OSXSAVE depends on CR4. */ 796 cr4 = cpudata->vmcb->state.cr4; 797 if (!(cr4 & CR4_OSXSAVE)) { 798 cpudata->gprs[NVMM_X64_GPR_RCX] &= ~CPUID2_OSXSAVE; 799 } 800 break; 801 case 0x00000005: 802 case 0x00000006: 803 cpudata->vmcb->state.rax = 0; 804 cpudata->gprs[NVMM_X64_GPR_RBX] = 0; 805 cpudata->gprs[NVMM_X64_GPR_RCX] = 0; 806 cpudata->gprs[NVMM_X64_GPR_RDX] = 0; 807 break; 808 case 0x00000007: 809 cpudata->vmcb->state.rax &= nvmm_cpuid_00000007.eax; 810 cpudata->gprs[NVMM_X64_GPR_RBX] &= nvmm_cpuid_00000007.ebx; 811 cpudata->gprs[NVMM_X64_GPR_RCX] &= nvmm_cpuid_00000007.ecx; 812 cpudata->gprs[NVMM_X64_GPR_RDX] &= nvmm_cpuid_00000007.edx; 813 break; 814 case 0x0000000D: 815 if (svm_xcr0_mask == 0) { 816 break; 817 } 818 switch (ecx) { 819 case 0: 820 cpudata->vmcb->state.rax = svm_xcr0_mask & 0xFFFFFFFF; 821 if (cpudata->gxcr0 & XCR0_SSE) { 822 cpudata->gprs[NVMM_X64_GPR_RBX] = sizeof(struct fxsave); 823 } else { 824 cpudata->gprs[NVMM_X64_GPR_RBX] = sizeof(struct save87); 825 } 826 cpudata->gprs[NVMM_X64_GPR_RBX] += 64; /* XSAVE header */ 827 cpudata->gprs[NVMM_X64_GPR_RCX] = sizeof(struct fxsave) + 64; 828 cpudata->gprs[NVMM_X64_GPR_RDX] = svm_xcr0_mask >> 32; 829 break; 830 case 1: 831 cpudata->vmcb->state.rax &= 832 (CPUID_PES1_XSAVEOPT | CPUID_PES1_XSAVEC | 833 CPUID_PES1_XGETBV); 834 cpudata->gprs[NVMM_X64_GPR_RBX] = 0; 835 cpudata->gprs[NVMM_X64_GPR_RCX] = 0; 836 cpudata->gprs[NVMM_X64_GPR_RDX] = 0; 837 break; 838 default: 839 cpudata->vmcb->state.rax = 0; 840 cpudata->gprs[NVMM_X64_GPR_RBX] = 0; 841 cpudata->gprs[NVMM_X64_GPR_RCX] = 0; 842 cpudata->gprs[NVMM_X64_GPR_RDX] = 0; 843 break; 844 } 845 break; 846 case 0x40000000: 847 cpudata->gprs[NVMM_X64_GPR_RBX] = 0; 848 cpudata->gprs[NVMM_X64_GPR_RCX] = 0; 849 cpudata->gprs[NVMM_X64_GPR_RDX] = 0; 850 memcpy(&cpudata->gprs[NVMM_X64_GPR_RBX], "___ ", 4); 851 memcpy(&cpudata->gprs[NVMM_X64_GPR_RCX], "NVMM", 4); 852 memcpy(&cpudata->gprs[NVMM_X64_GPR_RDX], " ___", 4); 853 break; 854 case 0x80000001: 855 cpudata->vmcb->state.rax &= nvmm_cpuid_80000001.eax; 856 cpudata->gprs[NVMM_X64_GPR_RBX] &= nvmm_cpuid_80000001.ebx; 857 cpudata->gprs[NVMM_X64_GPR_RCX] &= nvmm_cpuid_80000001.ecx; 858 cpudata->gprs[NVMM_X64_GPR_RDX] &= nvmm_cpuid_80000001.edx; 859 break; 860 default: 861 break; 862 } 863 } 864 865 static void 866 svm_exit_insn(struct vmcb *vmcb, struct nvmm_vcpu_exit *exit, uint64_t reason) 867 { 868 exit->u.insn.npc = vmcb->ctrl.nrip; 869 exit->reason = reason; 870 } 871 872 static void 873 svm_exit_cpuid(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 874 struct nvmm_vcpu_exit *exit) 875 { 876 struct svm_cpudata *cpudata = vcpu->cpudata; 877 struct nvmm_vcpu_conf_cpuid *cpuid; 878 uint64_t eax, ecx; 879 u_int descs[4]; 880 size_t i; 881 882 eax = cpudata->vmcb->state.rax; 883 ecx = cpudata->gprs[NVMM_X64_GPR_RCX]; 884 x86_cpuid2(eax, ecx, descs); 885 886 cpudata->vmcb->state.rax = descs[0]; 887 cpudata->gprs[NVMM_X64_GPR_RBX] = descs[1]; 888 cpudata->gprs[NVMM_X64_GPR_RCX] = descs[2]; 889 cpudata->gprs[NVMM_X64_GPR_RDX] = descs[3]; 890 891 svm_inkernel_handle_cpuid(vcpu, eax, ecx); 892 893 for (i = 0; i < SVM_NCPUIDS; i++) { 894 if (!cpudata->cpuidpresent[i]) { 895 continue; 896 } 897 cpuid = &cpudata->cpuid[i]; 898 if (cpuid->leaf != eax) { 899 continue; 900 } 901 902 if (cpuid->exit) { 903 svm_exit_insn(cpudata->vmcb, exit, NVMM_VCPU_EXIT_CPUID); 904 return; 905 } 906 KASSERT(cpuid->mask); 907 908 /* del */ 909 cpudata->vmcb->state.rax &= ~cpuid->u.mask.del.eax; 910 cpudata->gprs[NVMM_X64_GPR_RBX] &= ~cpuid->u.mask.del.ebx; 911 cpudata->gprs[NVMM_X64_GPR_RCX] &= ~cpuid->u.mask.del.ecx; 912 cpudata->gprs[NVMM_X64_GPR_RDX] &= ~cpuid->u.mask.del.edx; 913 914 /* set */ 915 cpudata->vmcb->state.rax |= cpuid->u.mask.set.eax; 916 cpudata->gprs[NVMM_X64_GPR_RBX] |= cpuid->u.mask.set.ebx; 917 cpudata->gprs[NVMM_X64_GPR_RCX] |= cpuid->u.mask.set.ecx; 918 cpudata->gprs[NVMM_X64_GPR_RDX] |= cpuid->u.mask.set.edx; 919 920 break; 921 } 922 923 svm_inkernel_advance(cpudata->vmcb); 924 exit->reason = NVMM_VCPU_EXIT_NONE; 925 } 926 927 static void 928 svm_exit_hlt(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 929 struct nvmm_vcpu_exit *exit) 930 { 931 struct svm_cpudata *cpudata = vcpu->cpudata; 932 struct vmcb *vmcb = cpudata->vmcb; 933 934 if (cpudata->int_window_exit && (vmcb->state.rflags & PSL_I)) { 935 svm_event_waitexit_disable(vcpu, false); 936 } 937 938 svm_inkernel_advance(cpudata->vmcb); 939 exit->reason = NVMM_VCPU_EXIT_HALTED; 940 } 941 942 #define SVM_EXIT_IO_PORT __BITS(31,16) 943 #define SVM_EXIT_IO_SEG __BITS(12,10) 944 #define SVM_EXIT_IO_A64 __BIT(9) 945 #define SVM_EXIT_IO_A32 __BIT(8) 946 #define SVM_EXIT_IO_A16 __BIT(7) 947 #define SVM_EXIT_IO_SZ32 __BIT(6) 948 #define SVM_EXIT_IO_SZ16 __BIT(5) 949 #define SVM_EXIT_IO_SZ8 __BIT(4) 950 #define SVM_EXIT_IO_REP __BIT(3) 951 #define SVM_EXIT_IO_STR __BIT(2) 952 #define SVM_EXIT_IO_IN __BIT(0) 953 954 static void 955 svm_exit_io(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 956 struct nvmm_vcpu_exit *exit) 957 { 958 struct svm_cpudata *cpudata = vcpu->cpudata; 959 uint64_t info = cpudata->vmcb->ctrl.exitinfo1; 960 uint64_t nextpc = cpudata->vmcb->ctrl.exitinfo2; 961 962 exit->reason = NVMM_VCPU_EXIT_IO; 963 964 exit->u.io.in = (info & SVM_EXIT_IO_IN) != 0; 965 exit->u.io.port = __SHIFTOUT(info, SVM_EXIT_IO_PORT); 966 967 if (svm_decode_assist) { 968 KASSERT(__SHIFTOUT(info, SVM_EXIT_IO_SEG) < 6); 969 exit->u.io.seg = __SHIFTOUT(info, SVM_EXIT_IO_SEG); 970 } else { 971 exit->u.io.seg = -1; 972 } 973 974 if (info & SVM_EXIT_IO_A64) { 975 exit->u.io.address_size = 8; 976 } else if (info & SVM_EXIT_IO_A32) { 977 exit->u.io.address_size = 4; 978 } else if (info & SVM_EXIT_IO_A16) { 979 exit->u.io.address_size = 2; 980 } 981 982 if (info & SVM_EXIT_IO_SZ32) { 983 exit->u.io.operand_size = 4; 984 } else if (info & SVM_EXIT_IO_SZ16) { 985 exit->u.io.operand_size = 2; 986 } else if (info & SVM_EXIT_IO_SZ8) { 987 exit->u.io.operand_size = 1; 988 } 989 990 exit->u.io.rep = (info & SVM_EXIT_IO_REP) != 0; 991 exit->u.io.str = (info & SVM_EXIT_IO_STR) != 0; 992 exit->u.io.npc = nextpc; 993 994 svm_vcpu_state_provide(vcpu, 995 NVMM_X64_STATE_GPRS | NVMM_X64_STATE_SEGS | 996 NVMM_X64_STATE_CRS | NVMM_X64_STATE_MSRS); 997 } 998 999 static const uint64_t msr_ignore_list[] = { 1000 0xc0010055, /* MSR_CMPHALT */ 1001 MSR_DE_CFG, 1002 MSR_IC_CFG, 1003 MSR_UCODE_AMD_PATCHLEVEL 1004 }; 1005 1006 static bool 1007 svm_inkernel_handle_msr(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 1008 struct nvmm_vcpu_exit *exit) 1009 { 1010 struct svm_cpudata *cpudata = vcpu->cpudata; 1011 struct vmcb *vmcb = cpudata->vmcb; 1012 uint64_t val; 1013 size_t i; 1014 1015 if (exit->reason == NVMM_VCPU_EXIT_RDMSR) { 1016 if (exit->u.rdmsr.msr == MSR_NB_CFG) { 1017 val = NB_CFG_INITAPICCPUIDLO; 1018 vmcb->state.rax = (val & 0xFFFFFFFF); 1019 cpudata->gprs[NVMM_X64_GPR_RDX] = (val >> 32); 1020 goto handled; 1021 } 1022 for (i = 0; i < __arraycount(msr_ignore_list); i++) { 1023 if (msr_ignore_list[i] != exit->u.rdmsr.msr) 1024 continue; 1025 val = 0; 1026 vmcb->state.rax = (val & 0xFFFFFFFF); 1027 cpudata->gprs[NVMM_X64_GPR_RDX] = (val >> 32); 1028 goto handled; 1029 } 1030 } else { 1031 if (exit->u.wrmsr.msr == MSR_EFER) { 1032 if (__predict_false(exit->u.wrmsr.val & ~EFER_VALID)) { 1033 goto error; 1034 } 1035 if ((vmcb->state.efer ^ exit->u.wrmsr.val) & 1036 EFER_TLB_FLUSH) { 1037 cpudata->gtlb_want_flush = true; 1038 } 1039 vmcb->state.efer = exit->u.wrmsr.val | EFER_SVME; 1040 svm_vmcb_cache_flush(vmcb, VMCB_CTRL_VMCB_CLEAN_CR); 1041 goto handled; 1042 } 1043 if (exit->u.wrmsr.msr == MSR_TSC) { 1044 cpudata->gtsc = exit->u.wrmsr.val; 1045 cpudata->gtsc_want_update = true; 1046 goto handled; 1047 } 1048 for (i = 0; i < __arraycount(msr_ignore_list); i++) { 1049 if (msr_ignore_list[i] != exit->u.wrmsr.msr) 1050 continue; 1051 goto handled; 1052 } 1053 } 1054 1055 return false; 1056 1057 handled: 1058 svm_inkernel_advance(cpudata->vmcb); 1059 return true; 1060 1061 error: 1062 svm_inject_gp(vcpu); 1063 return true; 1064 } 1065 1066 static inline void 1067 svm_exit_rdmsr(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 1068 struct nvmm_vcpu_exit *exit) 1069 { 1070 struct svm_cpudata *cpudata = vcpu->cpudata; 1071 1072 exit->reason = NVMM_VCPU_EXIT_RDMSR; 1073 exit->u.rdmsr.msr = (cpudata->gprs[NVMM_X64_GPR_RCX] & 0xFFFFFFFF); 1074 exit->u.rdmsr.npc = cpudata->vmcb->ctrl.nrip; 1075 1076 if (svm_inkernel_handle_msr(mach, vcpu, exit)) { 1077 exit->reason = NVMM_VCPU_EXIT_NONE; 1078 return; 1079 } 1080 1081 svm_vcpu_state_provide(vcpu, NVMM_X64_STATE_GPRS); 1082 } 1083 1084 static inline void 1085 svm_exit_wrmsr(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 1086 struct nvmm_vcpu_exit *exit) 1087 { 1088 struct svm_cpudata *cpudata = vcpu->cpudata; 1089 uint64_t rdx, rax; 1090 1091 rdx = cpudata->gprs[NVMM_X64_GPR_RDX]; 1092 rax = cpudata->vmcb->state.rax; 1093 1094 exit->reason = NVMM_VCPU_EXIT_WRMSR; 1095 exit->u.wrmsr.msr = (cpudata->gprs[NVMM_X64_GPR_RCX] & 0xFFFFFFFF); 1096 exit->u.wrmsr.val = (rdx << 32) | (rax & 0xFFFFFFFF); 1097 exit->u.wrmsr.npc = cpudata->vmcb->ctrl.nrip; 1098 1099 if (svm_inkernel_handle_msr(mach, vcpu, exit)) { 1100 exit->reason = NVMM_VCPU_EXIT_NONE; 1101 return; 1102 } 1103 1104 svm_vcpu_state_provide(vcpu, NVMM_X64_STATE_GPRS); 1105 } 1106 1107 static void 1108 svm_exit_msr(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 1109 struct nvmm_vcpu_exit *exit) 1110 { 1111 struct svm_cpudata *cpudata = vcpu->cpudata; 1112 uint64_t info = cpudata->vmcb->ctrl.exitinfo1; 1113 1114 if (info == 0) { 1115 svm_exit_rdmsr(mach, vcpu, exit); 1116 } else { 1117 svm_exit_wrmsr(mach, vcpu, exit); 1118 } 1119 } 1120 1121 static void 1122 svm_exit_npf(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 1123 struct nvmm_vcpu_exit *exit) 1124 { 1125 struct svm_cpudata *cpudata = vcpu->cpudata; 1126 gpaddr_t gpa = cpudata->vmcb->ctrl.exitinfo2; 1127 1128 exit->reason = NVMM_VCPU_EXIT_MEMORY; 1129 if (cpudata->vmcb->ctrl.exitinfo1 & PGEX_W) 1130 exit->u.mem.prot = PROT_WRITE; 1131 else if (cpudata->vmcb->ctrl.exitinfo1 & PGEX_X) 1132 exit->u.mem.prot = PROT_EXEC; 1133 else 1134 exit->u.mem.prot = PROT_READ; 1135 exit->u.mem.gpa = gpa; 1136 exit->u.mem.inst_len = cpudata->vmcb->ctrl.inst_len; 1137 memcpy(exit->u.mem.inst_bytes, cpudata->vmcb->ctrl.inst_bytes, 1138 sizeof(exit->u.mem.inst_bytes)); 1139 1140 svm_vcpu_state_provide(vcpu, 1141 NVMM_X64_STATE_GPRS | NVMM_X64_STATE_SEGS | 1142 NVMM_X64_STATE_CRS | NVMM_X64_STATE_MSRS); 1143 } 1144 1145 static void 1146 svm_exit_xsetbv(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 1147 struct nvmm_vcpu_exit *exit) 1148 { 1149 struct svm_cpudata *cpudata = vcpu->cpudata; 1150 struct vmcb *vmcb = cpudata->vmcb; 1151 uint64_t val; 1152 1153 exit->reason = NVMM_VCPU_EXIT_NONE; 1154 1155 val = (cpudata->gprs[NVMM_X64_GPR_RDX] << 32) | 1156 (vmcb->state.rax & 0xFFFFFFFF); 1157 1158 if (__predict_false(cpudata->gprs[NVMM_X64_GPR_RCX] != 0)) { 1159 goto error; 1160 } else if (__predict_false(vmcb->state.cpl != 0)) { 1161 goto error; 1162 } else if (__predict_false((val & ~svm_xcr0_mask) != 0)) { 1163 goto error; 1164 } else if (__predict_false((val & XCR0_X87) == 0)) { 1165 goto error; 1166 } 1167 1168 cpudata->gxcr0 = val; 1169 1170 svm_inkernel_advance(cpudata->vmcb); 1171 return; 1172 1173 error: 1174 svm_inject_gp(vcpu); 1175 } 1176 1177 static void 1178 svm_exit_invalid(struct nvmm_vcpu_exit *exit, uint64_t code) 1179 { 1180 exit->u.inv.hwcode = code; 1181 exit->reason = NVMM_VCPU_EXIT_INVALID; 1182 } 1183 1184 /* -------------------------------------------------------------------------- */ 1185 1186 static void 1187 svm_vcpu_guest_fpu_enter(struct nvmm_cpu *vcpu) 1188 { 1189 struct svm_cpudata *cpudata = vcpu->cpudata; 1190 1191 cpudata->ts_set = (rcr0() & CR0_TS) != 0; 1192 1193 fpu_area_save(&cpudata->hfpu, svm_xcr0_mask); 1194 fpu_area_restore(&cpudata->gfpu, svm_xcr0_mask); 1195 1196 if (svm_xcr0_mask != 0) { 1197 cpudata->hxcr0 = rdxcr(0); 1198 wrxcr(0, cpudata->gxcr0); 1199 } 1200 } 1201 1202 static void 1203 svm_vcpu_guest_fpu_leave(struct nvmm_cpu *vcpu) 1204 { 1205 struct svm_cpudata *cpudata = vcpu->cpudata; 1206 1207 if (svm_xcr0_mask != 0) { 1208 cpudata->gxcr0 = rdxcr(0); 1209 wrxcr(0, cpudata->hxcr0); 1210 } 1211 1212 fpu_area_save(&cpudata->gfpu, svm_xcr0_mask); 1213 fpu_area_restore(&cpudata->hfpu, svm_xcr0_mask); 1214 1215 if (cpudata->ts_set) { 1216 stts(); 1217 } 1218 } 1219 1220 static void 1221 svm_vcpu_guest_dbregs_enter(struct nvmm_cpu *vcpu) 1222 { 1223 struct svm_cpudata *cpudata = vcpu->cpudata; 1224 1225 x86_dbregs_save(curlwp); 1226 1227 ldr7(0); 1228 1229 ldr0(cpudata->drs[NVMM_X64_DR_DR0]); 1230 ldr1(cpudata->drs[NVMM_X64_DR_DR1]); 1231 ldr2(cpudata->drs[NVMM_X64_DR_DR2]); 1232 ldr3(cpudata->drs[NVMM_X64_DR_DR3]); 1233 } 1234 1235 static void 1236 svm_vcpu_guest_dbregs_leave(struct nvmm_cpu *vcpu) 1237 { 1238 struct svm_cpudata *cpudata = vcpu->cpudata; 1239 1240 cpudata->drs[NVMM_X64_DR_DR0] = rdr0(); 1241 cpudata->drs[NVMM_X64_DR_DR1] = rdr1(); 1242 cpudata->drs[NVMM_X64_DR_DR2] = rdr2(); 1243 cpudata->drs[NVMM_X64_DR_DR3] = rdr3(); 1244 1245 x86_dbregs_restore(curlwp); 1246 } 1247 1248 static void 1249 svm_vcpu_guest_misc_enter(struct nvmm_cpu *vcpu) 1250 { 1251 struct svm_cpudata *cpudata = vcpu->cpudata; 1252 1253 cpudata->fsbase = rdmsr(MSR_FSBASE); 1254 cpudata->kernelgsbase = rdmsr(MSR_KERNELGSBASE); 1255 } 1256 1257 static void 1258 svm_vcpu_guest_misc_leave(struct nvmm_cpu *vcpu) 1259 { 1260 struct svm_cpudata *cpudata = vcpu->cpudata; 1261 1262 wrmsr(MSR_STAR, cpudata->star); 1263 wrmsr(MSR_LSTAR, cpudata->lstar); 1264 wrmsr(MSR_CSTAR, cpudata->cstar); 1265 wrmsr(MSR_SFMASK, cpudata->sfmask); 1266 wrmsr(MSR_FSBASE, cpudata->fsbase); 1267 wrmsr(MSR_KERNELGSBASE, cpudata->kernelgsbase); 1268 } 1269 1270 /* -------------------------------------------------------------------------- */ 1271 1272 static inline void 1273 svm_gtlb_catchup(struct nvmm_cpu *vcpu, int hcpu) 1274 { 1275 struct svm_cpudata *cpudata = vcpu->cpudata; 1276 1277 if (vcpu->hcpu_last != hcpu || cpudata->shared_asid) { 1278 cpudata->gtlb_want_flush = true; 1279 } 1280 } 1281 1282 static inline void 1283 svm_htlb_catchup(struct nvmm_cpu *vcpu, int hcpu) 1284 { 1285 /* 1286 * Nothing to do. If an hTLB flush was needed, either the VCPU was 1287 * executing on this hCPU and the hTLB already got flushed, or it 1288 * was executing on another hCPU in which case the catchup is done 1289 * in svm_gtlb_catchup(). 1290 */ 1291 } 1292 1293 static inline uint64_t 1294 svm_htlb_flush(struct svm_machdata *machdata, struct svm_cpudata *cpudata) 1295 { 1296 struct vmcb *vmcb = cpudata->vmcb; 1297 uint64_t machgen; 1298 1299 machgen = machdata->mach_htlb_gen; 1300 if (__predict_true(machgen == cpudata->vcpu_htlb_gen)) { 1301 return machgen; 1302 } 1303 1304 vmcb->ctrl.tlb_ctrl = svm_ctrl_tlb_flush; 1305 return machgen; 1306 } 1307 1308 static inline void 1309 svm_htlb_flush_ack(struct svm_cpudata *cpudata, uint64_t machgen) 1310 { 1311 struct vmcb *vmcb = cpudata->vmcb; 1312 1313 if (__predict_true(vmcb->ctrl.exitcode != VMCB_EXITCODE_INVALID)) { 1314 cpudata->vcpu_htlb_gen = machgen; 1315 } 1316 } 1317 1318 static inline void 1319 svm_exit_evt(struct svm_cpudata *cpudata, struct vmcb *vmcb) 1320 { 1321 cpudata->evt_pending = false; 1322 1323 if (__predict_false(vmcb->ctrl.exitintinfo & VMCB_CTRL_EXITINTINFO_V)) { 1324 vmcb->ctrl.eventinj = vmcb->ctrl.exitintinfo; 1325 cpudata->evt_pending = true; 1326 } 1327 } 1328 1329 static int 1330 svm_vcpu_run(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 1331 struct nvmm_vcpu_exit *exit) 1332 { 1333 struct nvmm_comm_page *comm = vcpu->comm; 1334 struct svm_machdata *machdata = mach->machdata; 1335 struct svm_cpudata *cpudata = vcpu->cpudata; 1336 struct vmcb *vmcb = cpudata->vmcb; 1337 uint64_t machgen; 1338 int hcpu, s; 1339 1340 if (__predict_false(svm_vcpu_event_commit(vcpu) != 0)) { 1341 return EINVAL; 1342 } 1343 svm_vcpu_state_commit(vcpu); 1344 comm->state_cached = 0; 1345 1346 kpreempt_disable(); 1347 hcpu = cpu_number(); 1348 1349 svm_gtlb_catchup(vcpu, hcpu); 1350 svm_htlb_catchup(vcpu, hcpu); 1351 1352 if (vcpu->hcpu_last != hcpu) { 1353 svm_vmcb_cache_flush_all(vmcb); 1354 cpudata->gtsc_want_update = true; 1355 } 1356 1357 svm_vcpu_guest_dbregs_enter(vcpu); 1358 svm_vcpu_guest_misc_enter(vcpu); 1359 1360 while (1) { 1361 if (cpudata->gtlb_want_flush) { 1362 vmcb->ctrl.tlb_ctrl = svm_ctrl_tlb_flush; 1363 } else { 1364 vmcb->ctrl.tlb_ctrl = 0; 1365 } 1366 1367 if (__predict_false(cpudata->gtsc_want_update)) { 1368 vmcb->ctrl.tsc_offset = cpudata->gtsc - rdtsc(); 1369 svm_vmcb_cache_flush(vmcb, VMCB_CTRL_VMCB_CLEAN_I); 1370 } 1371 1372 s = splhigh(); 1373 machgen = svm_htlb_flush(machdata, cpudata); 1374 svm_vcpu_guest_fpu_enter(vcpu); 1375 svm_vmrun(cpudata->vmcb_pa, cpudata->gprs); 1376 svm_vcpu_guest_fpu_leave(vcpu); 1377 svm_htlb_flush_ack(cpudata, machgen); 1378 splx(s); 1379 1380 svm_vmcb_cache_default(vmcb); 1381 1382 if (vmcb->ctrl.exitcode != VMCB_EXITCODE_INVALID) { 1383 cpudata->gtlb_want_flush = false; 1384 cpudata->gtsc_want_update = false; 1385 vcpu->hcpu_last = hcpu; 1386 } 1387 svm_exit_evt(cpudata, vmcb); 1388 1389 switch (vmcb->ctrl.exitcode) { 1390 case VMCB_EXITCODE_INTR: 1391 case VMCB_EXITCODE_NMI: 1392 exit->reason = NVMM_VCPU_EXIT_NONE; 1393 break; 1394 case VMCB_EXITCODE_VINTR: 1395 svm_event_waitexit_disable(vcpu, false); 1396 exit->reason = NVMM_VCPU_EXIT_INT_READY; 1397 break; 1398 case VMCB_EXITCODE_IRET: 1399 svm_event_waitexit_disable(vcpu, true); 1400 exit->reason = NVMM_VCPU_EXIT_NMI_READY; 1401 break; 1402 case VMCB_EXITCODE_CPUID: 1403 svm_exit_cpuid(mach, vcpu, exit); 1404 break; 1405 case VMCB_EXITCODE_HLT: 1406 svm_exit_hlt(mach, vcpu, exit); 1407 break; 1408 case VMCB_EXITCODE_IOIO: 1409 svm_exit_io(mach, vcpu, exit); 1410 break; 1411 case VMCB_EXITCODE_MSR: 1412 svm_exit_msr(mach, vcpu, exit); 1413 break; 1414 case VMCB_EXITCODE_SHUTDOWN: 1415 exit->reason = NVMM_VCPU_EXIT_SHUTDOWN; 1416 break; 1417 case VMCB_EXITCODE_RDPMC: 1418 case VMCB_EXITCODE_RSM: 1419 case VMCB_EXITCODE_INVLPGA: 1420 case VMCB_EXITCODE_VMRUN: 1421 case VMCB_EXITCODE_VMMCALL: 1422 case VMCB_EXITCODE_VMLOAD: 1423 case VMCB_EXITCODE_VMSAVE: 1424 case VMCB_EXITCODE_STGI: 1425 case VMCB_EXITCODE_CLGI: 1426 case VMCB_EXITCODE_SKINIT: 1427 case VMCB_EXITCODE_RDTSCP: 1428 svm_inject_ud(vcpu); 1429 exit->reason = NVMM_VCPU_EXIT_NONE; 1430 break; 1431 case VMCB_EXITCODE_MONITOR: 1432 svm_exit_insn(vmcb, exit, NVMM_VCPU_EXIT_MONITOR); 1433 break; 1434 case VMCB_EXITCODE_MWAIT: 1435 case VMCB_EXITCODE_MWAIT_CONDITIONAL: 1436 svm_exit_insn(vmcb, exit, NVMM_VCPU_EXIT_MWAIT); 1437 break; 1438 case VMCB_EXITCODE_XSETBV: 1439 svm_exit_xsetbv(mach, vcpu, exit); 1440 break; 1441 case VMCB_EXITCODE_NPF: 1442 svm_exit_npf(mach, vcpu, exit); 1443 break; 1444 case VMCB_EXITCODE_FERR_FREEZE: /* ? */ 1445 default: 1446 svm_exit_invalid(exit, vmcb->ctrl.exitcode); 1447 break; 1448 } 1449 1450 /* If no reason to return to userland, keep rolling. */ 1451 if (curcpu()->ci_schedstate.spc_flags & SPCF_SHOULDYIELD) { 1452 break; 1453 } 1454 if (curcpu()->ci_data.cpu_softints != 0) { 1455 break; 1456 } 1457 if (curlwp->l_flag & LW_USERRET) { 1458 break; 1459 } 1460 if (exit->reason != NVMM_VCPU_EXIT_NONE) { 1461 break; 1462 } 1463 } 1464 1465 cpudata->gtsc = rdtsc() + vmcb->ctrl.tsc_offset; 1466 1467 svm_vcpu_guest_misc_leave(vcpu); 1468 svm_vcpu_guest_dbregs_leave(vcpu); 1469 1470 kpreempt_enable(); 1471 1472 exit->exitstate.rflags = vmcb->state.rflags; 1473 exit->exitstate.cr8 = __SHIFTOUT(vmcb->ctrl.v, VMCB_CTRL_V_TPR); 1474 exit->exitstate.int_shadow = 1475 ((vmcb->ctrl.intr & VMCB_CTRL_INTR_SHADOW) != 0); 1476 exit->exitstate.int_window_exiting = cpudata->int_window_exit; 1477 exit->exitstate.nmi_window_exiting = cpudata->nmi_window_exit; 1478 exit->exitstate.evt_pending = cpudata->evt_pending; 1479 1480 return 0; 1481 } 1482 1483 /* -------------------------------------------------------------------------- */ 1484 1485 static int 1486 svm_memalloc(paddr_t *pa, vaddr_t *va, size_t npages) 1487 { 1488 struct pglist pglist; 1489 paddr_t _pa; 1490 vaddr_t _va; 1491 size_t i; 1492 int ret; 1493 1494 ret = uvm_pglistalloc(npages * PAGE_SIZE, 0, ~0UL, PAGE_SIZE, 0, 1495 &pglist, 1, 0); 1496 if (ret != 0) 1497 return ENOMEM; 1498 _pa = TAILQ_FIRST(&pglist)->phys_addr; 1499 _va = uvm_km_alloc(kernel_map, npages * PAGE_SIZE, 0, 1500 UVM_KMF_VAONLY | UVM_KMF_NOWAIT); 1501 if (_va == 0) 1502 goto error; 1503 1504 for (i = 0; i < npages; i++) { 1505 pmap_kenter_pa(_va + i * PAGE_SIZE, _pa + i * PAGE_SIZE, 1506 VM_PROT_READ | VM_PROT_WRITE, PMAP_WRITE_BACK); 1507 } 1508 pmap_update(pmap_kernel()); 1509 1510 memset((void *)_va, 0, npages * PAGE_SIZE); 1511 1512 *pa = _pa; 1513 *va = _va; 1514 return 0; 1515 1516 error: 1517 for (i = 0; i < npages; i++) { 1518 uvm_pagefree(PHYS_TO_VM_PAGE(_pa + i * PAGE_SIZE)); 1519 } 1520 return ENOMEM; 1521 } 1522 1523 static void 1524 svm_memfree(paddr_t pa, vaddr_t va, size_t npages) 1525 { 1526 size_t i; 1527 1528 pmap_kremove(va, npages * PAGE_SIZE); 1529 pmap_update(pmap_kernel()); 1530 uvm_km_free(kernel_map, va, npages * PAGE_SIZE, UVM_KMF_VAONLY); 1531 for (i = 0; i < npages; i++) { 1532 uvm_pagefree(PHYS_TO_VM_PAGE(pa + i * PAGE_SIZE)); 1533 } 1534 } 1535 1536 /* -------------------------------------------------------------------------- */ 1537 1538 #define SVM_MSRBM_READ __BIT(0) 1539 #define SVM_MSRBM_WRITE __BIT(1) 1540 1541 static void 1542 svm_vcpu_msr_allow(uint8_t *bitmap, uint64_t msr, bool read, bool write) 1543 { 1544 uint64_t byte; 1545 uint8_t bitoff; 1546 1547 if (msr < 0x00002000) { 1548 /* Range 1 */ 1549 byte = ((msr - 0x00000000) >> 2UL) + 0x0000; 1550 } else if (msr >= 0xC0000000 && msr < 0xC0002000) { 1551 /* Range 2 */ 1552 byte = ((msr - 0xC0000000) >> 2UL) + 0x0800; 1553 } else if (msr >= 0xC0010000 && msr < 0xC0012000) { 1554 /* Range 3 */ 1555 byte = ((msr - 0xC0010000) >> 2UL) + 0x1000; 1556 } else { 1557 panic("%s: wrong range", __func__); 1558 } 1559 1560 bitoff = (msr & 0x3) << 1; 1561 1562 if (read) { 1563 bitmap[byte] &= ~(SVM_MSRBM_READ << bitoff); 1564 } 1565 if (write) { 1566 bitmap[byte] &= ~(SVM_MSRBM_WRITE << bitoff); 1567 } 1568 } 1569 1570 #define SVM_SEG_ATTRIB_TYPE __BITS(3,0) 1571 #define SVM_SEG_ATTRIB_S __BIT(4) 1572 #define SVM_SEG_ATTRIB_DPL __BITS(6,5) 1573 #define SVM_SEG_ATTRIB_P __BIT(7) 1574 #define SVM_SEG_ATTRIB_AVL __BIT(8) 1575 #define SVM_SEG_ATTRIB_L __BIT(9) 1576 #define SVM_SEG_ATTRIB_DEF __BIT(10) 1577 #define SVM_SEG_ATTRIB_G __BIT(11) 1578 1579 static void 1580 svm_vcpu_setstate_seg(const struct nvmm_x64_state_seg *seg, 1581 struct vmcb_segment *vseg) 1582 { 1583 vseg->selector = seg->selector; 1584 vseg->attrib = 1585 __SHIFTIN(seg->attrib.type, SVM_SEG_ATTRIB_TYPE) | 1586 __SHIFTIN(seg->attrib.s, SVM_SEG_ATTRIB_S) | 1587 __SHIFTIN(seg->attrib.dpl, SVM_SEG_ATTRIB_DPL) | 1588 __SHIFTIN(seg->attrib.p, SVM_SEG_ATTRIB_P) | 1589 __SHIFTIN(seg->attrib.avl, SVM_SEG_ATTRIB_AVL) | 1590 __SHIFTIN(seg->attrib.l, SVM_SEG_ATTRIB_L) | 1591 __SHIFTIN(seg->attrib.def, SVM_SEG_ATTRIB_DEF) | 1592 __SHIFTIN(seg->attrib.g, SVM_SEG_ATTRIB_G); 1593 vseg->limit = seg->limit; 1594 vseg->base = seg->base; 1595 } 1596 1597 static void 1598 svm_vcpu_getstate_seg(struct nvmm_x64_state_seg *seg, struct vmcb_segment *vseg) 1599 { 1600 seg->selector = vseg->selector; 1601 seg->attrib.type = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_TYPE); 1602 seg->attrib.s = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_S); 1603 seg->attrib.dpl = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_DPL); 1604 seg->attrib.p = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_P); 1605 seg->attrib.avl = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_AVL); 1606 seg->attrib.l = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_L); 1607 seg->attrib.def = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_DEF); 1608 seg->attrib.g = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_G); 1609 seg->limit = vseg->limit; 1610 seg->base = vseg->base; 1611 } 1612 1613 static inline bool 1614 svm_state_tlb_flush(const struct vmcb *vmcb, const struct nvmm_x64_state *state, 1615 uint64_t flags) 1616 { 1617 if (flags & NVMM_X64_STATE_CRS) { 1618 if ((vmcb->state.cr0 ^ 1619 state->crs[NVMM_X64_CR_CR0]) & CR0_TLB_FLUSH) { 1620 return true; 1621 } 1622 if (vmcb->state.cr3 != state->crs[NVMM_X64_CR_CR3]) { 1623 return true; 1624 } 1625 if ((vmcb->state.cr4 ^ 1626 state->crs[NVMM_X64_CR_CR4]) & CR4_TLB_FLUSH) { 1627 return true; 1628 } 1629 } 1630 1631 if (flags & NVMM_X64_STATE_MSRS) { 1632 if ((vmcb->state.efer ^ 1633 state->msrs[NVMM_X64_MSR_EFER]) & EFER_TLB_FLUSH) { 1634 return true; 1635 } 1636 } 1637 1638 return false; 1639 } 1640 1641 static void 1642 svm_vcpu_setstate(struct nvmm_cpu *vcpu) 1643 { 1644 struct nvmm_comm_page *comm = vcpu->comm; 1645 const struct nvmm_x64_state *state = &comm->state; 1646 struct svm_cpudata *cpudata = vcpu->cpudata; 1647 struct vmcb *vmcb = cpudata->vmcb; 1648 struct fxsave *fpustate; 1649 uint64_t flags; 1650 1651 flags = comm->state_wanted; 1652 1653 if (svm_state_tlb_flush(vmcb, state, flags)) { 1654 cpudata->gtlb_want_flush = true; 1655 } 1656 1657 if (flags & NVMM_X64_STATE_SEGS) { 1658 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_CS], 1659 &vmcb->state.cs); 1660 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_DS], 1661 &vmcb->state.ds); 1662 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_ES], 1663 &vmcb->state.es); 1664 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_FS], 1665 &vmcb->state.fs); 1666 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_GS], 1667 &vmcb->state.gs); 1668 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_SS], 1669 &vmcb->state.ss); 1670 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_GDT], 1671 &vmcb->state.gdt); 1672 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_IDT], 1673 &vmcb->state.idt); 1674 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_LDT], 1675 &vmcb->state.ldt); 1676 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_TR], 1677 &vmcb->state.tr); 1678 1679 vmcb->state.cpl = state->segs[NVMM_X64_SEG_SS].attrib.dpl; 1680 } 1681 1682 CTASSERT(sizeof(cpudata->gprs) == sizeof(state->gprs)); 1683 if (flags & NVMM_X64_STATE_GPRS) { 1684 memcpy(cpudata->gprs, state->gprs, sizeof(state->gprs)); 1685 1686 vmcb->state.rip = state->gprs[NVMM_X64_GPR_RIP]; 1687 vmcb->state.rsp = state->gprs[NVMM_X64_GPR_RSP]; 1688 vmcb->state.rax = state->gprs[NVMM_X64_GPR_RAX]; 1689 vmcb->state.rflags = state->gprs[NVMM_X64_GPR_RFLAGS]; 1690 } 1691 1692 if (flags & NVMM_X64_STATE_CRS) { 1693 vmcb->state.cr0 = state->crs[NVMM_X64_CR_CR0]; 1694 vmcb->state.cr2 = state->crs[NVMM_X64_CR_CR2]; 1695 vmcb->state.cr3 = state->crs[NVMM_X64_CR_CR3]; 1696 vmcb->state.cr4 = state->crs[NVMM_X64_CR_CR4]; 1697 1698 vmcb->ctrl.v &= ~VMCB_CTRL_V_TPR; 1699 vmcb->ctrl.v |= __SHIFTIN(state->crs[NVMM_X64_CR_CR8], 1700 VMCB_CTRL_V_TPR); 1701 1702 if (svm_xcr0_mask != 0) { 1703 /* Clear illegal XCR0 bits, set mandatory X87 bit. */ 1704 cpudata->gxcr0 = state->crs[NVMM_X64_CR_XCR0]; 1705 cpudata->gxcr0 &= svm_xcr0_mask; 1706 cpudata->gxcr0 |= XCR0_X87; 1707 } 1708 } 1709 1710 CTASSERT(sizeof(cpudata->drs) == sizeof(state->drs)); 1711 if (flags & NVMM_X64_STATE_DRS) { 1712 memcpy(cpudata->drs, state->drs, sizeof(state->drs)); 1713 1714 vmcb->state.dr6 = state->drs[NVMM_X64_DR_DR6]; 1715 vmcb->state.dr7 = state->drs[NVMM_X64_DR_DR7]; 1716 } 1717 1718 if (flags & NVMM_X64_STATE_MSRS) { 1719 /* 1720 * EFER_SVME is mandatory. 1721 */ 1722 vmcb->state.efer = state->msrs[NVMM_X64_MSR_EFER] | EFER_SVME; 1723 vmcb->state.star = state->msrs[NVMM_X64_MSR_STAR]; 1724 vmcb->state.lstar = state->msrs[NVMM_X64_MSR_LSTAR]; 1725 vmcb->state.cstar = state->msrs[NVMM_X64_MSR_CSTAR]; 1726 vmcb->state.sfmask = state->msrs[NVMM_X64_MSR_SFMASK]; 1727 vmcb->state.kernelgsbase = 1728 state->msrs[NVMM_X64_MSR_KERNELGSBASE]; 1729 vmcb->state.sysenter_cs = 1730 state->msrs[NVMM_X64_MSR_SYSENTER_CS]; 1731 vmcb->state.sysenter_esp = 1732 state->msrs[NVMM_X64_MSR_SYSENTER_ESP]; 1733 vmcb->state.sysenter_eip = 1734 state->msrs[NVMM_X64_MSR_SYSENTER_EIP]; 1735 vmcb->state.g_pat = state->msrs[NVMM_X64_MSR_PAT]; 1736 1737 cpudata->gtsc = state->msrs[NVMM_X64_MSR_TSC]; 1738 cpudata->gtsc_want_update = true; 1739 } 1740 1741 if (flags & NVMM_X64_STATE_INTR) { 1742 if (state->intr.int_shadow) { 1743 vmcb->ctrl.intr |= VMCB_CTRL_INTR_SHADOW; 1744 } else { 1745 vmcb->ctrl.intr &= ~VMCB_CTRL_INTR_SHADOW; 1746 } 1747 1748 if (state->intr.int_window_exiting) { 1749 svm_event_waitexit_enable(vcpu, false); 1750 } else { 1751 svm_event_waitexit_disable(vcpu, false); 1752 } 1753 1754 if (state->intr.nmi_window_exiting) { 1755 svm_event_waitexit_enable(vcpu, true); 1756 } else { 1757 svm_event_waitexit_disable(vcpu, true); 1758 } 1759 } 1760 1761 CTASSERT(sizeof(cpudata->gfpu.xsh_fxsave) == sizeof(state->fpu)); 1762 if (flags & NVMM_X64_STATE_FPU) { 1763 memcpy(cpudata->gfpu.xsh_fxsave, &state->fpu, 1764 sizeof(state->fpu)); 1765 1766 fpustate = (struct fxsave *)cpudata->gfpu.xsh_fxsave; 1767 fpustate->fx_mxcsr_mask &= x86_fpu_mxcsr_mask; 1768 fpustate->fx_mxcsr &= fpustate->fx_mxcsr_mask; 1769 1770 if (svm_xcr0_mask != 0) { 1771 /* Reset XSTATE_BV, to force a reload. */ 1772 cpudata->gfpu.xsh_xstate_bv = svm_xcr0_mask; 1773 } 1774 } 1775 1776 svm_vmcb_cache_update(vmcb, flags); 1777 1778 comm->state_wanted = 0; 1779 comm->state_cached |= flags; 1780 } 1781 1782 static void 1783 svm_vcpu_getstate(struct nvmm_cpu *vcpu) 1784 { 1785 struct nvmm_comm_page *comm = vcpu->comm; 1786 struct nvmm_x64_state *state = &comm->state; 1787 struct svm_cpudata *cpudata = vcpu->cpudata; 1788 struct vmcb *vmcb = cpudata->vmcb; 1789 uint64_t flags; 1790 1791 flags = comm->state_wanted; 1792 1793 if (flags & NVMM_X64_STATE_SEGS) { 1794 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_CS], 1795 &vmcb->state.cs); 1796 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_DS], 1797 &vmcb->state.ds); 1798 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_ES], 1799 &vmcb->state.es); 1800 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_FS], 1801 &vmcb->state.fs); 1802 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_GS], 1803 &vmcb->state.gs); 1804 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_SS], 1805 &vmcb->state.ss); 1806 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_GDT], 1807 &vmcb->state.gdt); 1808 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_IDT], 1809 &vmcb->state.idt); 1810 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_LDT], 1811 &vmcb->state.ldt); 1812 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_TR], 1813 &vmcb->state.tr); 1814 1815 state->segs[NVMM_X64_SEG_SS].attrib.dpl = vmcb->state.cpl; 1816 } 1817 1818 CTASSERT(sizeof(cpudata->gprs) == sizeof(state->gprs)); 1819 if (flags & NVMM_X64_STATE_GPRS) { 1820 memcpy(state->gprs, cpudata->gprs, sizeof(state->gprs)); 1821 1822 state->gprs[NVMM_X64_GPR_RIP] = vmcb->state.rip; 1823 state->gprs[NVMM_X64_GPR_RSP] = vmcb->state.rsp; 1824 state->gprs[NVMM_X64_GPR_RAX] = vmcb->state.rax; 1825 state->gprs[NVMM_X64_GPR_RFLAGS] = vmcb->state.rflags; 1826 } 1827 1828 if (flags & NVMM_X64_STATE_CRS) { 1829 state->crs[NVMM_X64_CR_CR0] = vmcb->state.cr0; 1830 state->crs[NVMM_X64_CR_CR2] = vmcb->state.cr2; 1831 state->crs[NVMM_X64_CR_CR3] = vmcb->state.cr3; 1832 state->crs[NVMM_X64_CR_CR4] = vmcb->state.cr4; 1833 state->crs[NVMM_X64_CR_CR8] = __SHIFTOUT(vmcb->ctrl.v, 1834 VMCB_CTRL_V_TPR); 1835 state->crs[NVMM_X64_CR_XCR0] = cpudata->gxcr0; 1836 } 1837 1838 CTASSERT(sizeof(cpudata->drs) == sizeof(state->drs)); 1839 if (flags & NVMM_X64_STATE_DRS) { 1840 memcpy(state->drs, cpudata->drs, sizeof(state->drs)); 1841 1842 state->drs[NVMM_X64_DR_DR6] = vmcb->state.dr6; 1843 state->drs[NVMM_X64_DR_DR7] = vmcb->state.dr7; 1844 } 1845 1846 if (flags & NVMM_X64_STATE_MSRS) { 1847 state->msrs[NVMM_X64_MSR_EFER] = vmcb->state.efer; 1848 state->msrs[NVMM_X64_MSR_STAR] = vmcb->state.star; 1849 state->msrs[NVMM_X64_MSR_LSTAR] = vmcb->state.lstar; 1850 state->msrs[NVMM_X64_MSR_CSTAR] = vmcb->state.cstar; 1851 state->msrs[NVMM_X64_MSR_SFMASK] = vmcb->state.sfmask; 1852 state->msrs[NVMM_X64_MSR_KERNELGSBASE] = 1853 vmcb->state.kernelgsbase; 1854 state->msrs[NVMM_X64_MSR_SYSENTER_CS] = 1855 vmcb->state.sysenter_cs; 1856 state->msrs[NVMM_X64_MSR_SYSENTER_ESP] = 1857 vmcb->state.sysenter_esp; 1858 state->msrs[NVMM_X64_MSR_SYSENTER_EIP] = 1859 vmcb->state.sysenter_eip; 1860 state->msrs[NVMM_X64_MSR_PAT] = vmcb->state.g_pat; 1861 state->msrs[NVMM_X64_MSR_TSC] = cpudata->gtsc; 1862 1863 /* Hide SVME. */ 1864 state->msrs[NVMM_X64_MSR_EFER] &= ~EFER_SVME; 1865 } 1866 1867 if (flags & NVMM_X64_STATE_INTR) { 1868 state->intr.int_shadow = 1869 (vmcb->ctrl.intr & VMCB_CTRL_INTR_SHADOW) != 0; 1870 state->intr.int_window_exiting = cpudata->int_window_exit; 1871 state->intr.nmi_window_exiting = cpudata->nmi_window_exit; 1872 state->intr.evt_pending = cpudata->evt_pending; 1873 } 1874 1875 CTASSERT(sizeof(cpudata->gfpu.xsh_fxsave) == sizeof(state->fpu)); 1876 if (flags & NVMM_X64_STATE_FPU) { 1877 memcpy(&state->fpu, cpudata->gfpu.xsh_fxsave, 1878 sizeof(state->fpu)); 1879 } 1880 1881 comm->state_wanted = 0; 1882 comm->state_cached |= flags; 1883 } 1884 1885 static void 1886 svm_vcpu_state_provide(struct nvmm_cpu *vcpu, uint64_t flags) 1887 { 1888 vcpu->comm->state_wanted = flags; 1889 svm_vcpu_getstate(vcpu); 1890 } 1891 1892 static void 1893 svm_vcpu_state_commit(struct nvmm_cpu *vcpu) 1894 { 1895 vcpu->comm->state_wanted = vcpu->comm->state_commit; 1896 vcpu->comm->state_commit = 0; 1897 svm_vcpu_setstate(vcpu); 1898 } 1899 1900 /* -------------------------------------------------------------------------- */ 1901 1902 static void 1903 svm_asid_alloc(struct nvmm_cpu *vcpu) 1904 { 1905 struct svm_cpudata *cpudata = vcpu->cpudata; 1906 struct vmcb *vmcb = cpudata->vmcb; 1907 size_t i, oct, bit; 1908 1909 mutex_enter(&svm_asidlock); 1910 1911 for (i = 0; i < svm_maxasid; i++) { 1912 oct = i / 8; 1913 bit = i % 8; 1914 1915 if (svm_asidmap[oct] & __BIT(bit)) { 1916 continue; 1917 } 1918 1919 svm_asidmap[oct] |= __BIT(bit); 1920 vmcb->ctrl.guest_asid = i; 1921 mutex_exit(&svm_asidlock); 1922 return; 1923 } 1924 1925 /* 1926 * No free ASID. Use the last one, which is shared and requires 1927 * special TLB handling. 1928 */ 1929 cpudata->shared_asid = true; 1930 vmcb->ctrl.guest_asid = svm_maxasid - 1; 1931 mutex_exit(&svm_asidlock); 1932 } 1933 1934 static void 1935 svm_asid_free(struct nvmm_cpu *vcpu) 1936 { 1937 struct svm_cpudata *cpudata = vcpu->cpudata; 1938 struct vmcb *vmcb = cpudata->vmcb; 1939 size_t oct, bit; 1940 1941 if (cpudata->shared_asid) { 1942 return; 1943 } 1944 1945 oct = vmcb->ctrl.guest_asid / 8; 1946 bit = vmcb->ctrl.guest_asid % 8; 1947 1948 mutex_enter(&svm_asidlock); 1949 svm_asidmap[oct] &= ~__BIT(bit); 1950 mutex_exit(&svm_asidlock); 1951 } 1952 1953 static void 1954 svm_vcpu_init(struct nvmm_machine *mach, struct nvmm_cpu *vcpu) 1955 { 1956 struct svm_cpudata *cpudata = vcpu->cpudata; 1957 struct vmcb *vmcb = cpudata->vmcb; 1958 1959 /* Allow reads/writes of Control Registers. */ 1960 vmcb->ctrl.intercept_cr = 0; 1961 1962 /* Allow reads/writes of Debug Registers. */ 1963 vmcb->ctrl.intercept_dr = 0; 1964 1965 /* Allow exceptions 0 to 31. */ 1966 vmcb->ctrl.intercept_vec = 0; 1967 1968 /* 1969 * Allow: 1970 * - SMI [smm interrupts] 1971 * - VINTR [virtual interrupts] 1972 * - CR0_SPEC [CR0 writes changing other fields than CR0.TS or CR0.MP] 1973 * - RIDTR [reads of IDTR] 1974 * - RGDTR [reads of GDTR] 1975 * - RLDTR [reads of LDTR] 1976 * - RTR [reads of TR] 1977 * - WIDTR [writes of IDTR] 1978 * - WGDTR [writes of GDTR] 1979 * - WLDTR [writes of LDTR] 1980 * - WTR [writes of TR] 1981 * - RDTSC [rdtsc instruction] 1982 * - PUSHF [pushf instruction] 1983 * - POPF [popf instruction] 1984 * - IRET [iret instruction] 1985 * - INTN [int $n instructions] 1986 * - INVD [invd instruction] 1987 * - PAUSE [pause instruction] 1988 * - INVLPG [invplg instruction] 1989 * - TASKSW [task switches] 1990 * 1991 * Intercept the rest below. 1992 */ 1993 vmcb->ctrl.intercept_misc1 = 1994 VMCB_CTRL_INTERCEPT_INTR | 1995 VMCB_CTRL_INTERCEPT_NMI | 1996 VMCB_CTRL_INTERCEPT_INIT | 1997 VMCB_CTRL_INTERCEPT_RDPMC | 1998 VMCB_CTRL_INTERCEPT_CPUID | 1999 VMCB_CTRL_INTERCEPT_RSM | 2000 VMCB_CTRL_INTERCEPT_HLT | 2001 VMCB_CTRL_INTERCEPT_INVLPGA | 2002 VMCB_CTRL_INTERCEPT_IOIO_PROT | 2003 VMCB_CTRL_INTERCEPT_MSR_PROT | 2004 VMCB_CTRL_INTERCEPT_FERR_FREEZE | 2005 VMCB_CTRL_INTERCEPT_SHUTDOWN; 2006 2007 /* 2008 * Allow: 2009 * - ICEBP [icebp instruction] 2010 * - WBINVD [wbinvd instruction] 2011 * - WCR_SPEC(0..15) [writes of CR0-15, received after instruction] 2012 * 2013 * Intercept the rest below. 2014 */ 2015 vmcb->ctrl.intercept_misc2 = 2016 VMCB_CTRL_INTERCEPT_VMRUN | 2017 VMCB_CTRL_INTERCEPT_VMMCALL | 2018 VMCB_CTRL_INTERCEPT_VMLOAD | 2019 VMCB_CTRL_INTERCEPT_VMSAVE | 2020 VMCB_CTRL_INTERCEPT_STGI | 2021 VMCB_CTRL_INTERCEPT_CLGI | 2022 VMCB_CTRL_INTERCEPT_SKINIT | 2023 VMCB_CTRL_INTERCEPT_RDTSCP | 2024 VMCB_CTRL_INTERCEPT_MONITOR | 2025 VMCB_CTRL_INTERCEPT_MWAIT | 2026 VMCB_CTRL_INTERCEPT_XSETBV; 2027 2028 /* Intercept all I/O accesses. */ 2029 memset(cpudata->iobm, 0xFF, IOBM_SIZE); 2030 vmcb->ctrl.iopm_base_pa = cpudata->iobm_pa; 2031 2032 /* Allow direct access to certain MSRs. */ 2033 memset(cpudata->msrbm, 0xFF, MSRBM_SIZE); 2034 svm_vcpu_msr_allow(cpudata->msrbm, MSR_EFER, true, false); 2035 svm_vcpu_msr_allow(cpudata->msrbm, MSR_STAR, true, true); 2036 svm_vcpu_msr_allow(cpudata->msrbm, MSR_LSTAR, true, true); 2037 svm_vcpu_msr_allow(cpudata->msrbm, MSR_CSTAR, true, true); 2038 svm_vcpu_msr_allow(cpudata->msrbm, MSR_SFMASK, true, true); 2039 svm_vcpu_msr_allow(cpudata->msrbm, MSR_KERNELGSBASE, true, true); 2040 svm_vcpu_msr_allow(cpudata->msrbm, MSR_SYSENTER_CS, true, true); 2041 svm_vcpu_msr_allow(cpudata->msrbm, MSR_SYSENTER_ESP, true, true); 2042 svm_vcpu_msr_allow(cpudata->msrbm, MSR_SYSENTER_EIP, true, true); 2043 svm_vcpu_msr_allow(cpudata->msrbm, MSR_FSBASE, true, true); 2044 svm_vcpu_msr_allow(cpudata->msrbm, MSR_GSBASE, true, true); 2045 svm_vcpu_msr_allow(cpudata->msrbm, MSR_CR_PAT, true, true); 2046 svm_vcpu_msr_allow(cpudata->msrbm, MSR_TSC, true, false); 2047 vmcb->ctrl.msrpm_base_pa = cpudata->msrbm_pa; 2048 2049 /* Generate ASID. */ 2050 svm_asid_alloc(vcpu); 2051 2052 /* Virtual TPR. */ 2053 vmcb->ctrl.v = VMCB_CTRL_V_INTR_MASKING; 2054 2055 /* Enable Nested Paging. */ 2056 vmcb->ctrl.enable1 = VMCB_CTRL_ENABLE_NP; 2057 vmcb->ctrl.n_cr3 = mach->vm->vm_map.pmap->pm_pdirpa[0]; 2058 2059 /* Init XSAVE header. */ 2060 cpudata->gfpu.xsh_xstate_bv = svm_xcr0_mask; 2061 cpudata->gfpu.xsh_xcomp_bv = 0; 2062 2063 /* These MSRs are static. */ 2064 cpudata->star = rdmsr(MSR_STAR); 2065 cpudata->lstar = rdmsr(MSR_LSTAR); 2066 cpudata->cstar = rdmsr(MSR_CSTAR); 2067 cpudata->sfmask = rdmsr(MSR_SFMASK); 2068 2069 /* Install the RESET state. */ 2070 memcpy(&vcpu->comm->state, &nvmm_x86_reset_state, 2071 sizeof(nvmm_x86_reset_state)); 2072 vcpu->comm->state_wanted = NVMM_X64_STATE_ALL; 2073 vcpu->comm->state_cached = 0; 2074 svm_vcpu_setstate(vcpu); 2075 } 2076 2077 static int 2078 svm_vcpu_create(struct nvmm_machine *mach, struct nvmm_cpu *vcpu) 2079 { 2080 struct svm_cpudata *cpudata; 2081 int error; 2082 2083 /* Allocate the SVM cpudata. */ 2084 cpudata = (struct svm_cpudata *)uvm_km_alloc(kernel_map, 2085 roundup(sizeof(*cpudata), PAGE_SIZE), 0, 2086 UVM_KMF_WIRED|UVM_KMF_ZERO); 2087 vcpu->cpudata = cpudata; 2088 2089 /* VMCB */ 2090 error = svm_memalloc(&cpudata->vmcb_pa, (vaddr_t *)&cpudata->vmcb, 2091 VMCB_NPAGES); 2092 if (error) 2093 goto error; 2094 2095 /* I/O Bitmap */ 2096 error = svm_memalloc(&cpudata->iobm_pa, (vaddr_t *)&cpudata->iobm, 2097 IOBM_NPAGES); 2098 if (error) 2099 goto error; 2100 2101 /* MSR Bitmap */ 2102 error = svm_memalloc(&cpudata->msrbm_pa, (vaddr_t *)&cpudata->msrbm, 2103 MSRBM_NPAGES); 2104 if (error) 2105 goto error; 2106 2107 /* Init the VCPU info. */ 2108 svm_vcpu_init(mach, vcpu); 2109 2110 return 0; 2111 2112 error: 2113 if (cpudata->vmcb_pa) { 2114 svm_memfree(cpudata->vmcb_pa, (vaddr_t)cpudata->vmcb, 2115 VMCB_NPAGES); 2116 } 2117 if (cpudata->iobm_pa) { 2118 svm_memfree(cpudata->iobm_pa, (vaddr_t)cpudata->iobm, 2119 IOBM_NPAGES); 2120 } 2121 if (cpudata->msrbm_pa) { 2122 svm_memfree(cpudata->msrbm_pa, (vaddr_t)cpudata->msrbm, 2123 MSRBM_NPAGES); 2124 } 2125 uvm_km_free(kernel_map, (vaddr_t)cpudata, 2126 roundup(sizeof(*cpudata), PAGE_SIZE), UVM_KMF_WIRED); 2127 return error; 2128 } 2129 2130 static void 2131 svm_vcpu_destroy(struct nvmm_machine *mach, struct nvmm_cpu *vcpu) 2132 { 2133 struct svm_cpudata *cpudata = vcpu->cpudata; 2134 2135 svm_asid_free(vcpu); 2136 2137 svm_memfree(cpudata->vmcb_pa, (vaddr_t)cpudata->vmcb, VMCB_NPAGES); 2138 svm_memfree(cpudata->iobm_pa, (vaddr_t)cpudata->iobm, IOBM_NPAGES); 2139 svm_memfree(cpudata->msrbm_pa, (vaddr_t)cpudata->msrbm, MSRBM_NPAGES); 2140 2141 uvm_km_free(kernel_map, (vaddr_t)cpudata, 2142 roundup(sizeof(*cpudata), PAGE_SIZE), UVM_KMF_WIRED); 2143 } 2144 2145 /* -------------------------------------------------------------------------- */ 2146 2147 static int 2148 svm_vcpu_configure_cpuid(struct svm_cpudata *cpudata, void *data) 2149 { 2150 struct nvmm_vcpu_conf_cpuid *cpuid = data; 2151 size_t i; 2152 2153 if (__predict_false(cpuid->mask && cpuid->exit)) { 2154 return EINVAL; 2155 } 2156 if (__predict_false(cpuid->mask && 2157 ((cpuid->u.mask.set.eax & cpuid->u.mask.del.eax) || 2158 (cpuid->u.mask.set.ebx & cpuid->u.mask.del.ebx) || 2159 (cpuid->u.mask.set.ecx & cpuid->u.mask.del.ecx) || 2160 (cpuid->u.mask.set.edx & cpuid->u.mask.del.edx)))) { 2161 return EINVAL; 2162 } 2163 2164 /* If unset, delete, to restore the default behavior. */ 2165 if (!cpuid->mask && !cpuid->exit) { 2166 for (i = 0; i < SVM_NCPUIDS; i++) { 2167 if (!cpudata->cpuidpresent[i]) { 2168 continue; 2169 } 2170 if (cpudata->cpuid[i].leaf == cpuid->leaf) { 2171 cpudata->cpuidpresent[i] = false; 2172 } 2173 } 2174 return 0; 2175 } 2176 2177 /* If already here, replace. */ 2178 for (i = 0; i < SVM_NCPUIDS; i++) { 2179 if (!cpudata->cpuidpresent[i]) { 2180 continue; 2181 } 2182 if (cpudata->cpuid[i].leaf == cpuid->leaf) { 2183 memcpy(&cpudata->cpuid[i], cpuid, 2184 sizeof(struct nvmm_vcpu_conf_cpuid)); 2185 return 0; 2186 } 2187 } 2188 2189 /* Not here, insert. */ 2190 for (i = 0; i < SVM_NCPUIDS; i++) { 2191 if (!cpudata->cpuidpresent[i]) { 2192 cpudata->cpuidpresent[i] = true; 2193 memcpy(&cpudata->cpuid[i], cpuid, 2194 sizeof(struct nvmm_vcpu_conf_cpuid)); 2195 return 0; 2196 } 2197 } 2198 2199 return ENOBUFS; 2200 } 2201 2202 static int 2203 svm_vcpu_configure(struct nvmm_cpu *vcpu, uint64_t op, void *data) 2204 { 2205 struct svm_cpudata *cpudata = vcpu->cpudata; 2206 2207 switch (op) { 2208 case NVMM_VCPU_CONF_MD(NVMM_VCPU_CONF_CPUID): 2209 return svm_vcpu_configure_cpuid(cpudata, data); 2210 default: 2211 return EINVAL; 2212 } 2213 } 2214 2215 /* -------------------------------------------------------------------------- */ 2216 2217 static void 2218 svm_tlb_flush(struct pmap *pm) 2219 { 2220 struct nvmm_machine *mach = pm->pm_data; 2221 struct svm_machdata *machdata = mach->machdata; 2222 2223 atomic_inc_64(&machdata->mach_htlb_gen); 2224 2225 /* Generates IPIs, which cause #VMEXITs. */ 2226 pmap_tlb_shootdown(pmap_kernel(), -1, PTE_G, TLBSHOOT_UPDATE); 2227 } 2228 2229 static void 2230 svm_machine_create(struct nvmm_machine *mach) 2231 { 2232 struct svm_machdata *machdata; 2233 2234 /* Fill in pmap info. */ 2235 mach->vm->vm_map.pmap->pm_data = (void *)mach; 2236 mach->vm->vm_map.pmap->pm_tlb_flush = svm_tlb_flush; 2237 2238 machdata = kmem_zalloc(sizeof(struct svm_machdata), KM_SLEEP); 2239 mach->machdata = machdata; 2240 2241 /* Start with an hTLB flush everywhere. */ 2242 machdata->mach_htlb_gen = 1; 2243 } 2244 2245 static void 2246 svm_machine_destroy(struct nvmm_machine *mach) 2247 { 2248 kmem_free(mach->machdata, sizeof(struct svm_machdata)); 2249 } 2250 2251 static int 2252 svm_machine_configure(struct nvmm_machine *mach, uint64_t op, void *data) 2253 { 2254 panic("%s: impossible", __func__); 2255 } 2256 2257 /* -------------------------------------------------------------------------- */ 2258 2259 static bool 2260 svm_ident(void) 2261 { 2262 u_int descs[4]; 2263 uint64_t msr; 2264 2265 if (cpu_vendor != CPUVENDOR_AMD) { 2266 return false; 2267 } 2268 if (!(cpu_feature[3] & CPUID_SVM)) { 2269 return false; 2270 } 2271 2272 if (curcpu()->ci_max_ext_cpuid < 0x8000000a) { 2273 return false; 2274 } 2275 x86_cpuid(0x8000000a, descs); 2276 2277 /* Want Nested Paging. */ 2278 if (!(descs[3] & CPUID_AMD_SVM_NP)) { 2279 return false; 2280 } 2281 2282 /* Want nRIP. */ 2283 if (!(descs[3] & CPUID_AMD_SVM_NRIPS)) { 2284 return false; 2285 } 2286 2287 svm_decode_assist = (descs[3] & CPUID_AMD_SVM_DecodeAssist) != 0; 2288 2289 msr = rdmsr(MSR_VMCR); 2290 if ((msr & VMCR_SVMED) && (msr & VMCR_LOCK)) { 2291 return false; 2292 } 2293 2294 return true; 2295 } 2296 2297 static void 2298 svm_init_asid(uint32_t maxasid) 2299 { 2300 size_t i, j, allocsz; 2301 2302 mutex_init(&svm_asidlock, MUTEX_DEFAULT, IPL_NONE); 2303 2304 /* Arbitrarily limit. */ 2305 maxasid = uimin(maxasid, 8192); 2306 2307 svm_maxasid = maxasid; 2308 allocsz = roundup(maxasid, 8) / 8; 2309 svm_asidmap = kmem_zalloc(allocsz, KM_SLEEP); 2310 2311 /* ASID 0 is reserved for the host. */ 2312 svm_asidmap[0] |= __BIT(0); 2313 2314 /* ASID n-1 is special, we share it. */ 2315 i = (maxasid - 1) / 8; 2316 j = (maxasid - 1) % 8; 2317 svm_asidmap[i] |= __BIT(j); 2318 } 2319 2320 static void 2321 svm_change_cpu(void *arg1, void *arg2) 2322 { 2323 bool enable = (bool)arg1; 2324 uint64_t msr; 2325 2326 msr = rdmsr(MSR_VMCR); 2327 if (msr & VMCR_SVMED) { 2328 wrmsr(MSR_VMCR, msr & ~VMCR_SVMED); 2329 } 2330 2331 if (!enable) { 2332 wrmsr(MSR_VM_HSAVE_PA, 0); 2333 } 2334 2335 msr = rdmsr(MSR_EFER); 2336 if (enable) { 2337 msr |= EFER_SVME; 2338 } else { 2339 msr &= ~EFER_SVME; 2340 } 2341 wrmsr(MSR_EFER, msr); 2342 2343 if (enable) { 2344 wrmsr(MSR_VM_HSAVE_PA, hsave[cpu_index(curcpu())].pa); 2345 } 2346 } 2347 2348 static void 2349 svm_init(void) 2350 { 2351 CPU_INFO_ITERATOR cii; 2352 struct cpu_info *ci; 2353 struct vm_page *pg; 2354 u_int descs[4]; 2355 uint64_t xc; 2356 2357 x86_cpuid(0x8000000a, descs); 2358 2359 /* The guest TLB flush command. */ 2360 if (descs[3] & CPUID_AMD_SVM_FlushByASID) { 2361 svm_ctrl_tlb_flush = VMCB_CTRL_TLB_CTRL_FLUSH_GUEST; 2362 } else { 2363 svm_ctrl_tlb_flush = VMCB_CTRL_TLB_CTRL_FLUSH_ALL; 2364 } 2365 2366 /* Init the ASID. */ 2367 svm_init_asid(descs[1]); 2368 2369 /* Init the XCR0 mask. */ 2370 svm_xcr0_mask = SVM_XCR0_MASK_DEFAULT & x86_xsave_features; 2371 2372 memset(hsave, 0, sizeof(hsave)); 2373 for (CPU_INFO_FOREACH(cii, ci)) { 2374 pg = uvm_pagealloc(NULL, 0, NULL, UVM_PGA_ZERO); 2375 hsave[cpu_index(ci)].pa = VM_PAGE_TO_PHYS(pg); 2376 } 2377 2378 xc = xc_broadcast(0, svm_change_cpu, (void *)true, NULL); 2379 xc_wait(xc); 2380 } 2381 2382 static void 2383 svm_fini_asid(void) 2384 { 2385 size_t allocsz; 2386 2387 allocsz = roundup(svm_maxasid, 8) / 8; 2388 kmem_free(svm_asidmap, allocsz); 2389 2390 mutex_destroy(&svm_asidlock); 2391 } 2392 2393 static void 2394 svm_fini(void) 2395 { 2396 uint64_t xc; 2397 size_t i; 2398 2399 xc = xc_broadcast(0, svm_change_cpu, (void *)false, NULL); 2400 xc_wait(xc); 2401 2402 for (i = 0; i < MAXCPUS; i++) { 2403 if (hsave[i].pa != 0) 2404 uvm_pagefree(PHYS_TO_VM_PAGE(hsave[i].pa)); 2405 } 2406 2407 svm_fini_asid(); 2408 } 2409 2410 static void 2411 svm_capability(struct nvmm_capability *cap) 2412 { 2413 cap->arch.mach_conf_support = 0; 2414 cap->arch.vcpu_conf_support = 2415 NVMM_CAP_ARCH_VCPU_CONF_CPUID; 2416 cap->arch.xcr0_mask = svm_xcr0_mask; 2417 cap->arch.mxcsr_mask = x86_fpu_mxcsr_mask; 2418 cap->arch.conf_cpuid_maxops = SVM_NCPUIDS; 2419 } 2420 2421 const struct nvmm_impl nvmm_x86_svm = { 2422 .ident = svm_ident, 2423 .init = svm_init, 2424 .fini = svm_fini, 2425 .capability = svm_capability, 2426 .mach_conf_max = NVMM_X86_MACH_NCONF, 2427 .mach_conf_sizes = NULL, 2428 .vcpu_conf_max = NVMM_X86_VCPU_NCONF, 2429 .vcpu_conf_sizes = svm_vcpu_conf_sizes, 2430 .state_size = sizeof(struct nvmm_x64_state), 2431 .machine_create = svm_machine_create, 2432 .machine_destroy = svm_machine_destroy, 2433 .machine_configure = svm_machine_configure, 2434 .vcpu_create = svm_vcpu_create, 2435 .vcpu_destroy = svm_vcpu_destroy, 2436 .vcpu_configure = svm_vcpu_configure, 2437 .vcpu_setstate = svm_vcpu_setstate, 2438 .vcpu_getstate = svm_vcpu_getstate, 2439 .vcpu_inject = svm_vcpu_inject, 2440 .vcpu_run = svm_vcpu_run 2441 }; 2442
Indexes created Mon Oct 27 20:09:55 GMT 2025