nvmm_x86_svm.c revision 1.49
1 /* $NetBSD: nvmm_x86_svm.c,v 1.49 2019/10/04 12:17:05 maxv Exp $ */ 2 3 /* 4 * Copyright (c) 2018 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Maxime Villard. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: nvmm_x86_svm.c,v 1.49 2019/10/04 12:17:05 maxv Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/kmem.h> 39 #include <sys/cpu.h> 40 #include <sys/xcall.h> 41 #include <sys/mman.h> 42 43 #include <uvm/uvm.h> 44 #include <uvm/uvm_page.h> 45 46 #include <x86/cputypes.h> 47 #include <x86/specialreg.h> 48 #include <x86/pmap.h> 49 #include <x86/dbregs.h> 50 #include <x86/cpu_counter.h> 51 #include <machine/cpuvar.h> 52 53 #include <dev/nvmm/nvmm.h> 54 #include <dev/nvmm/nvmm_internal.h> 55 #include <dev/nvmm/x86/nvmm_x86.h> 56 57 int svm_vmrun(paddr_t, uint64_t *); 58 59 #define MSR_VM_HSAVE_PA 0xC0010117 60 61 /* -------------------------------------------------------------------------- */ 62 63 #define VMCB_EXITCODE_CR0_READ 0x0000 64 #define VMCB_EXITCODE_CR1_READ 0x0001 65 #define VMCB_EXITCODE_CR2_READ 0x0002 66 #define VMCB_EXITCODE_CR3_READ 0x0003 67 #define VMCB_EXITCODE_CR4_READ 0x0004 68 #define VMCB_EXITCODE_CR5_READ 0x0005 69 #define VMCB_EXITCODE_CR6_READ 0x0006 70 #define VMCB_EXITCODE_CR7_READ 0x0007 71 #define VMCB_EXITCODE_CR8_READ 0x0008 72 #define VMCB_EXITCODE_CR9_READ 0x0009 73 #define VMCB_EXITCODE_CR10_READ 0x000A 74 #define VMCB_EXITCODE_CR11_READ 0x000B 75 #define VMCB_EXITCODE_CR12_READ 0x000C 76 #define VMCB_EXITCODE_CR13_READ 0x000D 77 #define VMCB_EXITCODE_CR14_READ 0x000E 78 #define VMCB_EXITCODE_CR15_READ 0x000F 79 #define VMCB_EXITCODE_CR0_WRITE 0x0010 80 #define VMCB_EXITCODE_CR1_WRITE 0x0011 81 #define VMCB_EXITCODE_CR2_WRITE 0x0012 82 #define VMCB_EXITCODE_CR3_WRITE 0x0013 83 #define VMCB_EXITCODE_CR4_WRITE 0x0014 84 #define VMCB_EXITCODE_CR5_WRITE 0x0015 85 #define VMCB_EXITCODE_CR6_WRITE 0x0016 86 #define VMCB_EXITCODE_CR7_WRITE 0x0017 87 #define VMCB_EXITCODE_CR8_WRITE 0x0018 88 #define VMCB_EXITCODE_CR9_WRITE 0x0019 89 #define VMCB_EXITCODE_CR10_WRITE 0x001A 90 #define VMCB_EXITCODE_CR11_WRITE 0x001B 91 #define VMCB_EXITCODE_CR12_WRITE 0x001C 92 #define VMCB_EXITCODE_CR13_WRITE 0x001D 93 #define VMCB_EXITCODE_CR14_WRITE 0x001E 94 #define VMCB_EXITCODE_CR15_WRITE 0x001F 95 #define VMCB_EXITCODE_DR0_READ 0x0020 96 #define VMCB_EXITCODE_DR1_READ 0x0021 97 #define VMCB_EXITCODE_DR2_READ 0x0022 98 #define VMCB_EXITCODE_DR3_READ 0x0023 99 #define VMCB_EXITCODE_DR4_READ 0x0024 100 #define VMCB_EXITCODE_DR5_READ 0x0025 101 #define VMCB_EXITCODE_DR6_READ 0x0026 102 #define VMCB_EXITCODE_DR7_READ 0x0027 103 #define VMCB_EXITCODE_DR8_READ 0x0028 104 #define VMCB_EXITCODE_DR9_READ 0x0029 105 #define VMCB_EXITCODE_DR10_READ 0x002A 106 #define VMCB_EXITCODE_DR11_READ 0x002B 107 #define VMCB_EXITCODE_DR12_READ 0x002C 108 #define VMCB_EXITCODE_DR13_READ 0x002D 109 #define VMCB_EXITCODE_DR14_READ 0x002E 110 #define VMCB_EXITCODE_DR15_READ 0x002F 111 #define VMCB_EXITCODE_DR0_WRITE 0x0030 112 #define VMCB_EXITCODE_DR1_WRITE 0x0031 113 #define VMCB_EXITCODE_DR2_WRITE 0x0032 114 #define VMCB_EXITCODE_DR3_WRITE 0x0033 115 #define VMCB_EXITCODE_DR4_WRITE 0x0034 116 #define VMCB_EXITCODE_DR5_WRITE 0x0035 117 #define VMCB_EXITCODE_DR6_WRITE 0x0036 118 #define VMCB_EXITCODE_DR7_WRITE 0x0037 119 #define VMCB_EXITCODE_DR8_WRITE 0x0038 120 #define VMCB_EXITCODE_DR9_WRITE 0x0039 121 #define VMCB_EXITCODE_DR10_WRITE 0x003A 122 #define VMCB_EXITCODE_DR11_WRITE 0x003B 123 #define VMCB_EXITCODE_DR12_WRITE 0x003C 124 #define VMCB_EXITCODE_DR13_WRITE 0x003D 125 #define VMCB_EXITCODE_DR14_WRITE 0x003E 126 #define VMCB_EXITCODE_DR15_WRITE 0x003F 127 #define VMCB_EXITCODE_EXCP0 0x0040 128 #define VMCB_EXITCODE_EXCP1 0x0041 129 #define VMCB_EXITCODE_EXCP2 0x0042 130 #define VMCB_EXITCODE_EXCP3 0x0043 131 #define VMCB_EXITCODE_EXCP4 0x0044 132 #define VMCB_EXITCODE_EXCP5 0x0045 133 #define VMCB_EXITCODE_EXCP6 0x0046 134 #define VMCB_EXITCODE_EXCP7 0x0047 135 #define VMCB_EXITCODE_EXCP8 0x0048 136 #define VMCB_EXITCODE_EXCP9 0x0049 137 #define VMCB_EXITCODE_EXCP10 0x004A 138 #define VMCB_EXITCODE_EXCP11 0x004B 139 #define VMCB_EXITCODE_EXCP12 0x004C 140 #define VMCB_EXITCODE_EXCP13 0x004D 141 #define VMCB_EXITCODE_EXCP14 0x004E 142 #define VMCB_EXITCODE_EXCP15 0x004F 143 #define VMCB_EXITCODE_EXCP16 0x0050 144 #define VMCB_EXITCODE_EXCP17 0x0051 145 #define VMCB_EXITCODE_EXCP18 0x0052 146 #define VMCB_EXITCODE_EXCP19 0x0053 147 #define VMCB_EXITCODE_EXCP20 0x0054 148 #define VMCB_EXITCODE_EXCP21 0x0055 149 #define VMCB_EXITCODE_EXCP22 0x0056 150 #define VMCB_EXITCODE_EXCP23 0x0057 151 #define VMCB_EXITCODE_EXCP24 0x0058 152 #define VMCB_EXITCODE_EXCP25 0x0059 153 #define VMCB_EXITCODE_EXCP26 0x005A 154 #define VMCB_EXITCODE_EXCP27 0x005B 155 #define VMCB_EXITCODE_EXCP28 0x005C 156 #define VMCB_EXITCODE_EXCP29 0x005D 157 #define VMCB_EXITCODE_EXCP30 0x005E 158 #define VMCB_EXITCODE_EXCP31 0x005F 159 #define VMCB_EXITCODE_INTR 0x0060 160 #define VMCB_EXITCODE_NMI 0x0061 161 #define VMCB_EXITCODE_SMI 0x0062 162 #define VMCB_EXITCODE_INIT 0x0063 163 #define VMCB_EXITCODE_VINTR 0x0064 164 #define VMCB_EXITCODE_CR0_SEL_WRITE 0x0065 165 #define VMCB_EXITCODE_IDTR_READ 0x0066 166 #define VMCB_EXITCODE_GDTR_READ 0x0067 167 #define VMCB_EXITCODE_LDTR_READ 0x0068 168 #define VMCB_EXITCODE_TR_READ 0x0069 169 #define VMCB_EXITCODE_IDTR_WRITE 0x006A 170 #define VMCB_EXITCODE_GDTR_WRITE 0x006B 171 #define VMCB_EXITCODE_LDTR_WRITE 0x006C 172 #define VMCB_EXITCODE_TR_WRITE 0x006D 173 #define VMCB_EXITCODE_RDTSC 0x006E 174 #define VMCB_EXITCODE_RDPMC 0x006F 175 #define VMCB_EXITCODE_PUSHF 0x0070 176 #define VMCB_EXITCODE_POPF 0x0071 177 #define VMCB_EXITCODE_CPUID 0x0072 178 #define VMCB_EXITCODE_RSM 0x0073 179 #define VMCB_EXITCODE_IRET 0x0074 180 #define VMCB_EXITCODE_SWINT 0x0075 181 #define VMCB_EXITCODE_INVD 0x0076 182 #define VMCB_EXITCODE_PAUSE 0x0077 183 #define VMCB_EXITCODE_HLT 0x0078 184 #define VMCB_EXITCODE_INVLPG 0x0079 185 #define VMCB_EXITCODE_INVLPGA 0x007A 186 #define VMCB_EXITCODE_IOIO 0x007B 187 #define VMCB_EXITCODE_MSR 0x007C 188 #define VMCB_EXITCODE_TASK_SWITCH 0x007D 189 #define VMCB_EXITCODE_FERR_FREEZE 0x007E 190 #define VMCB_EXITCODE_SHUTDOWN 0x007F 191 #define VMCB_EXITCODE_VMRUN 0x0080 192 #define VMCB_EXITCODE_VMMCALL 0x0081 193 #define VMCB_EXITCODE_VMLOAD 0x0082 194 #define VMCB_EXITCODE_VMSAVE 0x0083 195 #define VMCB_EXITCODE_STGI 0x0084 196 #define VMCB_EXITCODE_CLGI 0x0085 197 #define VMCB_EXITCODE_SKINIT 0x0086 198 #define VMCB_EXITCODE_RDTSCP 0x0087 199 #define VMCB_EXITCODE_ICEBP 0x0088 200 #define VMCB_EXITCODE_WBINVD 0x0089 201 #define VMCB_EXITCODE_MONITOR 0x008A 202 #define VMCB_EXITCODE_MWAIT 0x008B 203 #define VMCB_EXITCODE_MWAIT_CONDITIONAL 0x008C 204 #define VMCB_EXITCODE_XSETBV 0x008D 205 #define VMCB_EXITCODE_RDPRU 0x008E 206 #define VMCB_EXITCODE_EFER_WRITE_TRAP 0x008F 207 #define VMCB_EXITCODE_CR0_WRITE_TRAP 0x0090 208 #define VMCB_EXITCODE_CR1_WRITE_TRAP 0x0091 209 #define VMCB_EXITCODE_CR2_WRITE_TRAP 0x0092 210 #define VMCB_EXITCODE_CR3_WRITE_TRAP 0x0093 211 #define VMCB_EXITCODE_CR4_WRITE_TRAP 0x0094 212 #define VMCB_EXITCODE_CR5_WRITE_TRAP 0x0095 213 #define VMCB_EXITCODE_CR6_WRITE_TRAP 0x0096 214 #define VMCB_EXITCODE_CR7_WRITE_TRAP 0x0097 215 #define VMCB_EXITCODE_CR8_WRITE_TRAP 0x0098 216 #define VMCB_EXITCODE_CR9_WRITE_TRAP 0x0099 217 #define VMCB_EXITCODE_CR10_WRITE_TRAP 0x009A 218 #define VMCB_EXITCODE_CR11_WRITE_TRAP 0x009B 219 #define VMCB_EXITCODE_CR12_WRITE_TRAP 0x009C 220 #define VMCB_EXITCODE_CR13_WRITE_TRAP 0x009D 221 #define VMCB_EXITCODE_CR14_WRITE_TRAP 0x009E 222 #define VMCB_EXITCODE_CR15_WRITE_TRAP 0x009F 223 #define VMCB_EXITCODE_MCOMMIT 0x00A3 224 #define VMCB_EXITCODE_NPF 0x0400 225 #define VMCB_EXITCODE_AVIC_INCOMP_IPI 0x0401 226 #define VMCB_EXITCODE_AVIC_NOACCEL 0x0402 227 #define VMCB_EXITCODE_VMGEXIT 0x0403 228 #define VMCB_EXITCODE_INVALID -1 229 230 /* -------------------------------------------------------------------------- */ 231 232 struct vmcb_ctrl { 233 uint32_t intercept_cr; 234 #define VMCB_CTRL_INTERCEPT_RCR(x) __BIT( 0 + x) 235 #define VMCB_CTRL_INTERCEPT_WCR(x) __BIT(16 + x) 236 237 uint32_t intercept_dr; 238 #define VMCB_CTRL_INTERCEPT_RDR(x) __BIT( 0 + x) 239 #define VMCB_CTRL_INTERCEPT_WDR(x) __BIT(16 + x) 240 241 uint32_t intercept_vec; 242 #define VMCB_CTRL_INTERCEPT_VEC(x) __BIT(x) 243 244 uint32_t intercept_misc1; 245 #define VMCB_CTRL_INTERCEPT_INTR __BIT(0) 246 #define VMCB_CTRL_INTERCEPT_NMI __BIT(1) 247 #define VMCB_CTRL_INTERCEPT_SMI __BIT(2) 248 #define VMCB_CTRL_INTERCEPT_INIT __BIT(3) 249 #define VMCB_CTRL_INTERCEPT_VINTR __BIT(4) 250 #define VMCB_CTRL_INTERCEPT_CR0_SPEC __BIT(5) 251 #define VMCB_CTRL_INTERCEPT_RIDTR __BIT(6) 252 #define VMCB_CTRL_INTERCEPT_RGDTR __BIT(7) 253 #define VMCB_CTRL_INTERCEPT_RLDTR __BIT(8) 254 #define VMCB_CTRL_INTERCEPT_RTR __BIT(9) 255 #define VMCB_CTRL_INTERCEPT_WIDTR __BIT(10) 256 #define VMCB_CTRL_INTERCEPT_WGDTR __BIT(11) 257 #define VMCB_CTRL_INTERCEPT_WLDTR __BIT(12) 258 #define VMCB_CTRL_INTERCEPT_WTR __BIT(13) 259 #define VMCB_CTRL_INTERCEPT_RDTSC __BIT(14) 260 #define VMCB_CTRL_INTERCEPT_RDPMC __BIT(15) 261 #define VMCB_CTRL_INTERCEPT_PUSHF __BIT(16) 262 #define VMCB_CTRL_INTERCEPT_POPF __BIT(17) 263 #define VMCB_CTRL_INTERCEPT_CPUID __BIT(18) 264 #define VMCB_CTRL_INTERCEPT_RSM __BIT(19) 265 #define VMCB_CTRL_INTERCEPT_IRET __BIT(20) 266 #define VMCB_CTRL_INTERCEPT_INTN __BIT(21) 267 #define VMCB_CTRL_INTERCEPT_INVD __BIT(22) 268 #define VMCB_CTRL_INTERCEPT_PAUSE __BIT(23) 269 #define VMCB_CTRL_INTERCEPT_HLT __BIT(24) 270 #define VMCB_CTRL_INTERCEPT_INVLPG __BIT(25) 271 #define VMCB_CTRL_INTERCEPT_INVLPGA __BIT(26) 272 #define VMCB_CTRL_INTERCEPT_IOIO_PROT __BIT(27) 273 #define VMCB_CTRL_INTERCEPT_MSR_PROT __BIT(28) 274 #define VMCB_CTRL_INTERCEPT_TASKSW __BIT(29) 275 #define VMCB_CTRL_INTERCEPT_FERR_FREEZE __BIT(30) 276 #define VMCB_CTRL_INTERCEPT_SHUTDOWN __BIT(31) 277 278 uint32_t intercept_misc2; 279 #define VMCB_CTRL_INTERCEPT_VMRUN __BIT(0) 280 #define VMCB_CTRL_INTERCEPT_VMMCALL __BIT(1) 281 #define VMCB_CTRL_INTERCEPT_VMLOAD __BIT(2) 282 #define VMCB_CTRL_INTERCEPT_VMSAVE __BIT(3) 283 #define VMCB_CTRL_INTERCEPT_STGI __BIT(4) 284 #define VMCB_CTRL_INTERCEPT_CLGI __BIT(5) 285 #define VMCB_CTRL_INTERCEPT_SKINIT __BIT(6) 286 #define VMCB_CTRL_INTERCEPT_RDTSCP __BIT(7) 287 #define VMCB_CTRL_INTERCEPT_ICEBP __BIT(8) 288 #define VMCB_CTRL_INTERCEPT_WBINVD __BIT(9) 289 #define VMCB_CTRL_INTERCEPT_MONITOR __BIT(10) 290 #define VMCB_CTRL_INTERCEPT_MWAIT __BIT(11) 291 #define VMCB_CTRL_INTERCEPT_MWAIT_ARMED __BIT(12) 292 #define VMCB_CTRL_INTERCEPT_XSETBV __BIT(13) 293 #define VMCB_CTRL_INTERCEPT_RDPRU __BIT(14) 294 #define VMCB_CTRL_INTERCEPT_EFER_SPEC __BIT(15) 295 #define VMCB_CTRL_INTERCEPT_WCR_SPEC(x) __BIT(16 + x) 296 297 uint32_t intercept_misc3; 298 #define VMCB_CTRL_INTERCEPT_MCOMMIT __BIT(3) 299 300 uint8_t rsvd1[36]; 301 uint16_t pause_filt_thresh; 302 uint16_t pause_filt_cnt; 303 uint64_t iopm_base_pa; 304 uint64_t msrpm_base_pa; 305 uint64_t tsc_offset; 306 uint32_t guest_asid; 307 308 uint32_t tlb_ctrl; 309 #define VMCB_CTRL_TLB_CTRL_FLUSH_ALL 0x01 310 #define VMCB_CTRL_TLB_CTRL_FLUSH_GUEST 0x03 311 #define VMCB_CTRL_TLB_CTRL_FLUSH_GUEST_NONGLOBAL 0x07 312 313 uint64_t v; 314 #define VMCB_CTRL_V_TPR __BITS(3,0) 315 #define VMCB_CTRL_V_IRQ __BIT(8) 316 #define VMCB_CTRL_V_VGIF __BIT(9) 317 #define VMCB_CTRL_V_INTR_PRIO __BITS(19,16) 318 #define VMCB_CTRL_V_IGN_TPR __BIT(20) 319 #define VMCB_CTRL_V_INTR_MASKING __BIT(24) 320 #define VMCB_CTRL_V_GUEST_VGIF __BIT(25) 321 #define VMCB_CTRL_V_AVIC_EN __BIT(31) 322 #define VMCB_CTRL_V_INTR_VECTOR __BITS(39,32) 323 324 uint64_t intr; 325 #define VMCB_CTRL_INTR_SHADOW __BIT(0) 326 327 uint64_t exitcode; 328 uint64_t exitinfo1; 329 uint64_t exitinfo2; 330 331 uint64_t exitintinfo; 332 #define VMCB_CTRL_EXITINTINFO_VECTOR __BITS(7,0) 333 #define VMCB_CTRL_EXITINTINFO_TYPE __BITS(10,8) 334 #define VMCB_CTRL_EXITINTINFO_EV __BIT(11) 335 #define VMCB_CTRL_EXITINTINFO_V __BIT(31) 336 #define VMCB_CTRL_EXITINTINFO_ERRORCODE __BITS(63,32) 337 338 uint64_t enable1; 339 #define VMCB_CTRL_ENABLE_NP __BIT(0) 340 #define VMCB_CTRL_ENABLE_SEV __BIT(1) 341 #define VMCB_CTRL_ENABLE_ES_SEV __BIT(2) 342 #define VMCB_CTRL_ENABLE_GMET __BIT(3) 343 #define VMCB_CTRL_ENABLE_VTE __BIT(5) 344 345 uint64_t avic; 346 #define VMCB_CTRL_AVIC_APIC_BAR __BITS(51,0) 347 348 uint64_t ghcb; 349 350 uint64_t eventinj; 351 #define VMCB_CTRL_EVENTINJ_VECTOR __BITS(7,0) 352 #define VMCB_CTRL_EVENTINJ_TYPE __BITS(10,8) 353 #define VMCB_CTRL_EVENTINJ_EV __BIT(11) 354 #define VMCB_CTRL_EVENTINJ_V __BIT(31) 355 #define VMCB_CTRL_EVENTINJ_ERRORCODE __BITS(63,32) 356 357 uint64_t n_cr3; 358 359 uint64_t enable2; 360 #define VMCB_CTRL_ENABLE_LBR __BIT(0) 361 #define VMCB_CTRL_ENABLE_VVMSAVE __BIT(1) 362 363 uint32_t vmcb_clean; 364 #define VMCB_CTRL_VMCB_CLEAN_I __BIT(0) 365 #define VMCB_CTRL_VMCB_CLEAN_IOPM __BIT(1) 366 #define VMCB_CTRL_VMCB_CLEAN_ASID __BIT(2) 367 #define VMCB_CTRL_VMCB_CLEAN_TPR __BIT(3) 368 #define VMCB_CTRL_VMCB_CLEAN_NP __BIT(4) 369 #define VMCB_CTRL_VMCB_CLEAN_CR __BIT(5) 370 #define VMCB_CTRL_VMCB_CLEAN_DR __BIT(6) 371 #define VMCB_CTRL_VMCB_CLEAN_DT __BIT(7) 372 #define VMCB_CTRL_VMCB_CLEAN_SEG __BIT(8) 373 #define VMCB_CTRL_VMCB_CLEAN_CR2 __BIT(9) 374 #define VMCB_CTRL_VMCB_CLEAN_LBR __BIT(10) 375 #define VMCB_CTRL_VMCB_CLEAN_AVIC __BIT(11) 376 377 uint32_t rsvd2; 378 uint64_t nrip; 379 uint8_t inst_len; 380 uint8_t inst_bytes[15]; 381 uint64_t avic_abpp; 382 uint64_t rsvd3; 383 uint64_t avic_ltp; 384 385 uint64_t avic_phys; 386 #define VMCB_CTRL_AVIC_PHYS_TABLE_PTR __BITS(51,12) 387 #define VMCB_CTRL_AVIC_PHYS_MAX_INDEX __BITS(7,0) 388 389 uint64_t rsvd4; 390 uint64_t vmcb_ptr; 391 392 uint8_t pad[752]; 393 } __packed; 394 395 CTASSERT(sizeof(struct vmcb_ctrl) == 1024); 396 397 struct vmcb_segment { 398 uint16_t selector; 399 uint16_t attrib; /* hidden */ 400 uint32_t limit; /* hidden */ 401 uint64_t base; /* hidden */ 402 } __packed; 403 404 CTASSERT(sizeof(struct vmcb_segment) == 16); 405 406 struct vmcb_state { 407 struct vmcb_segment es; 408 struct vmcb_segment cs; 409 struct vmcb_segment ss; 410 struct vmcb_segment ds; 411 struct vmcb_segment fs; 412 struct vmcb_segment gs; 413 struct vmcb_segment gdt; 414 struct vmcb_segment ldt; 415 struct vmcb_segment idt; 416 struct vmcb_segment tr; 417 uint8_t rsvd1[43]; 418 uint8_t cpl; 419 uint8_t rsvd2[4]; 420 uint64_t efer; 421 uint8_t rsvd3[112]; 422 uint64_t cr4; 423 uint64_t cr3; 424 uint64_t cr0; 425 uint64_t dr7; 426 uint64_t dr6; 427 uint64_t rflags; 428 uint64_t rip; 429 uint8_t rsvd4[88]; 430 uint64_t rsp; 431 uint8_t rsvd5[24]; 432 uint64_t rax; 433 uint64_t star; 434 uint64_t lstar; 435 uint64_t cstar; 436 uint64_t sfmask; 437 uint64_t kernelgsbase; 438 uint64_t sysenter_cs; 439 uint64_t sysenter_esp; 440 uint64_t sysenter_eip; 441 uint64_t cr2; 442 uint8_t rsvd6[32]; 443 uint64_t g_pat; 444 uint64_t dbgctl; 445 uint64_t br_from; 446 uint64_t br_to; 447 uint64_t int_from; 448 uint64_t int_to; 449 uint8_t pad[2408]; 450 } __packed; 451 452 CTASSERT(sizeof(struct vmcb_state) == 0xC00); 453 454 struct vmcb { 455 struct vmcb_ctrl ctrl; 456 struct vmcb_state state; 457 } __packed; 458 459 CTASSERT(sizeof(struct vmcb) == PAGE_SIZE); 460 CTASSERT(offsetof(struct vmcb, state) == 0x400); 461 462 /* -------------------------------------------------------------------------- */ 463 464 static void svm_vcpu_state_provide(struct nvmm_cpu *, uint64_t); 465 static void svm_vcpu_state_commit(struct nvmm_cpu *); 466 467 struct svm_hsave { 468 paddr_t pa; 469 }; 470 471 static struct svm_hsave hsave[MAXCPUS]; 472 473 static uint8_t *svm_asidmap __read_mostly; 474 static uint32_t svm_maxasid __read_mostly; 475 static kmutex_t svm_asidlock __cacheline_aligned; 476 477 static bool svm_decode_assist __read_mostly; 478 static uint32_t svm_ctrl_tlb_flush __read_mostly; 479 480 #define SVM_XCR0_MASK_DEFAULT (XCR0_X87|XCR0_SSE) 481 static uint64_t svm_xcr0_mask __read_mostly; 482 483 #define SVM_NCPUIDS 32 484 485 #define VMCB_NPAGES 1 486 487 #define MSRBM_NPAGES 2 488 #define MSRBM_SIZE (MSRBM_NPAGES * PAGE_SIZE) 489 490 #define IOBM_NPAGES 3 491 #define IOBM_SIZE (IOBM_NPAGES * PAGE_SIZE) 492 493 /* Does not include EFER_LMSLE. */ 494 #define EFER_VALID \ 495 (EFER_SCE|EFER_LME|EFER_LMA|EFER_NXE|EFER_SVME|EFER_FFXSR|EFER_TCE) 496 497 #define EFER_TLB_FLUSH \ 498 (EFER_NXE|EFER_LMA|EFER_LME) 499 #define CR0_TLB_FLUSH \ 500 (CR0_PG|CR0_WP|CR0_CD|CR0_NW) 501 #define CR4_TLB_FLUSH \ 502 (CR4_PGE|CR4_PAE|CR4_PSE) 503 504 /* -------------------------------------------------------------------------- */ 505 506 struct svm_machdata { 507 bool cpuidpresent[SVM_NCPUIDS]; 508 struct nvmm_mach_conf_x86_cpuid cpuid[SVM_NCPUIDS]; 509 volatile uint64_t mach_htlb_gen; 510 }; 511 512 static const size_t svm_conf_sizes[NVMM_X86_NCONF] = { 513 [NVMM_MACH_CONF_MD(NVMM_MACH_CONF_X86_CPUID)] = 514 sizeof(struct nvmm_mach_conf_x86_cpuid) 515 }; 516 517 struct svm_cpudata { 518 /* General */ 519 bool shared_asid; 520 bool gtlb_want_flush; 521 bool gtsc_want_update; 522 uint64_t vcpu_htlb_gen; 523 524 /* VMCB */ 525 struct vmcb *vmcb; 526 paddr_t vmcb_pa; 527 528 /* I/O bitmap */ 529 uint8_t *iobm; 530 paddr_t iobm_pa; 531 532 /* MSR bitmap */ 533 uint8_t *msrbm; 534 paddr_t msrbm_pa; 535 536 /* Host state */ 537 uint64_t hxcr0; 538 uint64_t star; 539 uint64_t lstar; 540 uint64_t cstar; 541 uint64_t sfmask; 542 uint64_t fsbase; 543 uint64_t kernelgsbase; 544 bool ts_set; 545 struct xsave_header hfpu __aligned(64); 546 547 /* Intr state */ 548 bool int_window_exit; 549 bool nmi_window_exit; 550 bool evt_pending; 551 552 /* Guest state */ 553 uint64_t gxcr0; 554 uint64_t gprs[NVMM_X64_NGPR]; 555 uint64_t drs[NVMM_X64_NDR]; 556 uint64_t gtsc; 557 struct xsave_header gfpu __aligned(64); 558 }; 559 560 static void 561 svm_vmcb_cache_default(struct vmcb *vmcb) 562 { 563 vmcb->ctrl.vmcb_clean = 564 VMCB_CTRL_VMCB_CLEAN_I | 565 VMCB_CTRL_VMCB_CLEAN_IOPM | 566 VMCB_CTRL_VMCB_CLEAN_ASID | 567 VMCB_CTRL_VMCB_CLEAN_TPR | 568 VMCB_CTRL_VMCB_CLEAN_NP | 569 VMCB_CTRL_VMCB_CLEAN_CR | 570 VMCB_CTRL_VMCB_CLEAN_DR | 571 VMCB_CTRL_VMCB_CLEAN_DT | 572 VMCB_CTRL_VMCB_CLEAN_SEG | 573 VMCB_CTRL_VMCB_CLEAN_CR2 | 574 VMCB_CTRL_VMCB_CLEAN_LBR | 575 VMCB_CTRL_VMCB_CLEAN_AVIC; 576 } 577 578 static void 579 svm_vmcb_cache_update(struct vmcb *vmcb, uint64_t flags) 580 { 581 if (flags & NVMM_X64_STATE_SEGS) { 582 vmcb->ctrl.vmcb_clean &= 583 ~(VMCB_CTRL_VMCB_CLEAN_SEG | VMCB_CTRL_VMCB_CLEAN_DT); 584 } 585 if (flags & NVMM_X64_STATE_CRS) { 586 vmcb->ctrl.vmcb_clean &= 587 ~(VMCB_CTRL_VMCB_CLEAN_CR | VMCB_CTRL_VMCB_CLEAN_CR2 | 588 VMCB_CTRL_VMCB_CLEAN_TPR); 589 } 590 if (flags & NVMM_X64_STATE_DRS) { 591 vmcb->ctrl.vmcb_clean &= ~VMCB_CTRL_VMCB_CLEAN_DR; 592 } 593 if (flags & NVMM_X64_STATE_MSRS) { 594 /* CR for EFER, NP for PAT. */ 595 vmcb->ctrl.vmcb_clean &= 596 ~(VMCB_CTRL_VMCB_CLEAN_CR | VMCB_CTRL_VMCB_CLEAN_NP); 597 } 598 } 599 600 static inline void 601 svm_vmcb_cache_flush(struct vmcb *vmcb, uint64_t flags) 602 { 603 vmcb->ctrl.vmcb_clean &= ~flags; 604 } 605 606 static inline void 607 svm_vmcb_cache_flush_all(struct vmcb *vmcb) 608 { 609 vmcb->ctrl.vmcb_clean = 0; 610 } 611 612 #define SVM_EVENT_TYPE_HW_INT 0 613 #define SVM_EVENT_TYPE_NMI 2 614 #define SVM_EVENT_TYPE_EXC 3 615 #define SVM_EVENT_TYPE_SW_INT 4 616 617 static void 618 svm_event_waitexit_enable(struct nvmm_cpu *vcpu, bool nmi) 619 { 620 struct svm_cpudata *cpudata = vcpu->cpudata; 621 struct vmcb *vmcb = cpudata->vmcb; 622 623 if (nmi) { 624 vmcb->ctrl.intercept_misc1 |= VMCB_CTRL_INTERCEPT_IRET; 625 cpudata->nmi_window_exit = true; 626 } else { 627 vmcb->ctrl.intercept_misc1 |= VMCB_CTRL_INTERCEPT_VINTR; 628 vmcb->ctrl.v |= (VMCB_CTRL_V_IRQ | VMCB_CTRL_V_IGN_TPR); 629 svm_vmcb_cache_flush(vmcb, VMCB_CTRL_VMCB_CLEAN_TPR); 630 cpudata->int_window_exit = true; 631 } 632 633 svm_vmcb_cache_flush(vmcb, VMCB_CTRL_VMCB_CLEAN_I); 634 } 635 636 static void 637 svm_event_waitexit_disable(struct nvmm_cpu *vcpu, bool nmi) 638 { 639 struct svm_cpudata *cpudata = vcpu->cpudata; 640 struct vmcb *vmcb = cpudata->vmcb; 641 642 if (nmi) { 643 vmcb->ctrl.intercept_misc1 &= ~VMCB_CTRL_INTERCEPT_IRET; 644 cpudata->nmi_window_exit = false; 645 } else { 646 vmcb->ctrl.intercept_misc1 &= ~VMCB_CTRL_INTERCEPT_VINTR; 647 vmcb->ctrl.v &= ~(VMCB_CTRL_V_IRQ | VMCB_CTRL_V_IGN_TPR); 648 svm_vmcb_cache_flush(vmcb, VMCB_CTRL_VMCB_CLEAN_TPR); 649 cpudata->int_window_exit = false; 650 } 651 652 svm_vmcb_cache_flush(vmcb, VMCB_CTRL_VMCB_CLEAN_I); 653 } 654 655 static inline int 656 svm_event_has_error(uint64_t vector) 657 { 658 switch (vector) { 659 case 8: /* #DF */ 660 case 10: /* #TS */ 661 case 11: /* #NP */ 662 case 12: /* #SS */ 663 case 13: /* #GP */ 664 case 14: /* #PF */ 665 case 17: /* #AC */ 666 case 30: /* #SX */ 667 return 1; 668 default: 669 return 0; 670 } 671 } 672 673 static int 674 svm_vcpu_inject(struct nvmm_cpu *vcpu) 675 { 676 struct nvmm_comm_page *comm = vcpu->comm; 677 struct svm_cpudata *cpudata = vcpu->cpudata; 678 struct vmcb *vmcb = cpudata->vmcb; 679 enum nvmm_event_type evtype; 680 uint64_t vector, error; 681 int type = 0, err = 0; 682 683 evtype = comm->event.type; 684 vector = comm->event.vector; 685 error = comm->event.u.error; 686 __insn_barrier(); 687 688 if (__predict_false(vector >= 256)) { 689 return EINVAL; 690 } 691 692 switch (evtype) { 693 case NVMM_EVENT_INTERRUPT_HW: 694 type = SVM_EVENT_TYPE_HW_INT; 695 if (vector == 2) { 696 type = SVM_EVENT_TYPE_NMI; 697 svm_event_waitexit_enable(vcpu, true); 698 } 699 err = 0; 700 break; 701 case NVMM_EVENT_EXCEPTION: 702 type = SVM_EVENT_TYPE_EXC; 703 if (vector == 2 || vector >= 32) 704 return EINVAL; 705 if (vector == 3 || vector == 0) 706 return EINVAL; 707 err = svm_event_has_error(vector); 708 break; 709 default: 710 return EINVAL; 711 } 712 713 vmcb->ctrl.eventinj = 714 __SHIFTIN(vector, VMCB_CTRL_EVENTINJ_VECTOR) | 715 __SHIFTIN(type, VMCB_CTRL_EVENTINJ_TYPE) | 716 __SHIFTIN(err, VMCB_CTRL_EVENTINJ_EV) | 717 __SHIFTIN(1, VMCB_CTRL_EVENTINJ_V) | 718 __SHIFTIN(error, VMCB_CTRL_EVENTINJ_ERRORCODE); 719 720 cpudata->evt_pending = true; 721 722 return 0; 723 } 724 725 static void 726 svm_inject_ud(struct nvmm_cpu *vcpu) 727 { 728 struct nvmm_comm_page *comm = vcpu->comm; 729 int ret __diagused; 730 731 comm->event.type = NVMM_EVENT_EXCEPTION; 732 comm->event.vector = 6; 733 comm->event.u.error = 0; 734 735 ret = svm_vcpu_inject(vcpu); 736 KASSERT(ret == 0); 737 } 738 739 static void 740 svm_inject_gp(struct nvmm_cpu *vcpu) 741 { 742 struct nvmm_comm_page *comm = vcpu->comm; 743 int ret __diagused; 744 745 comm->event.type = NVMM_EVENT_EXCEPTION; 746 comm->event.vector = 13; 747 comm->event.u.error = 0; 748 749 ret = svm_vcpu_inject(vcpu); 750 KASSERT(ret == 0); 751 } 752 753 static inline int 754 svm_vcpu_event_commit(struct nvmm_cpu *vcpu) 755 { 756 if (__predict_true(!vcpu->comm->event_commit)) { 757 return 0; 758 } 759 vcpu->comm->event_commit = false; 760 return svm_vcpu_inject(vcpu); 761 } 762 763 static inline void 764 svm_inkernel_advance(struct vmcb *vmcb) 765 { 766 /* 767 * Maybe we should also apply single-stepping and debug exceptions. 768 * Matters for guest-ring3, because it can execute 'cpuid' under a 769 * debugger. 770 */ 771 vmcb->state.rip = vmcb->ctrl.nrip; 772 vmcb->ctrl.intr &= ~VMCB_CTRL_INTR_SHADOW; 773 } 774 775 static void 776 svm_inkernel_handle_cpuid(struct nvmm_cpu *vcpu, uint64_t eax, uint64_t ecx) 777 { 778 struct svm_cpudata *cpudata = vcpu->cpudata; 779 uint64_t cr4; 780 781 switch (eax) { 782 case 0x00000001: 783 cpudata->vmcb->state.rax &= nvmm_cpuid_00000001.eax; 784 785 cpudata->gprs[NVMM_X64_GPR_RBX] &= ~CPUID_LOCAL_APIC_ID; 786 cpudata->gprs[NVMM_X64_GPR_RBX] |= __SHIFTIN(vcpu->cpuid, 787 CPUID_LOCAL_APIC_ID); 788 789 cpudata->gprs[NVMM_X64_GPR_RCX] &= nvmm_cpuid_00000001.ecx; 790 cpudata->gprs[NVMM_X64_GPR_RCX] |= CPUID2_RAZ; 791 792 cpudata->gprs[NVMM_X64_GPR_RDX] &= nvmm_cpuid_00000001.edx; 793 794 /* CPUID2_OSXSAVE depends on CR4. */ 795 cr4 = cpudata->vmcb->state.cr4; 796 if (!(cr4 & CR4_OSXSAVE)) { 797 cpudata->gprs[NVMM_X64_GPR_RCX] &= ~CPUID2_OSXSAVE; 798 } 799 break; 800 case 0x00000005: 801 case 0x00000006: 802 cpudata->vmcb->state.rax = 0; 803 cpudata->gprs[NVMM_X64_GPR_RBX] = 0; 804 cpudata->gprs[NVMM_X64_GPR_RCX] = 0; 805 cpudata->gprs[NVMM_X64_GPR_RDX] = 0; 806 break; 807 case 0x00000007: 808 cpudata->vmcb->state.rax &= nvmm_cpuid_00000007.eax; 809 cpudata->gprs[NVMM_X64_GPR_RBX] &= nvmm_cpuid_00000007.ebx; 810 cpudata->gprs[NVMM_X64_GPR_RCX] &= nvmm_cpuid_00000007.ecx; 811 cpudata->gprs[NVMM_X64_GPR_RDX] &= nvmm_cpuid_00000007.edx; 812 break; 813 case 0x0000000D: 814 if (svm_xcr0_mask == 0) { 815 break; 816 } 817 switch (ecx) { 818 case 0: 819 cpudata->vmcb->state.rax = svm_xcr0_mask & 0xFFFFFFFF; 820 if (cpudata->gxcr0 & XCR0_SSE) { 821 cpudata->gprs[NVMM_X64_GPR_RBX] = sizeof(struct fxsave); 822 } else { 823 cpudata->gprs[NVMM_X64_GPR_RBX] = sizeof(struct save87); 824 } 825 cpudata->gprs[NVMM_X64_GPR_RBX] += 64; /* XSAVE header */ 826 cpudata->gprs[NVMM_X64_GPR_RCX] = sizeof(struct fxsave) + 64; 827 cpudata->gprs[NVMM_X64_GPR_RDX] = svm_xcr0_mask >> 32; 828 break; 829 case 1: 830 cpudata->vmcb->state.rax &= ~CPUID_PES1_XSAVES; 831 break; 832 } 833 break; 834 case 0x40000000: 835 cpudata->gprs[NVMM_X64_GPR_RBX] = 0; 836 cpudata->gprs[NVMM_X64_GPR_RCX] = 0; 837 cpudata->gprs[NVMM_X64_GPR_RDX] = 0; 838 memcpy(&cpudata->gprs[NVMM_X64_GPR_RBX], "___ ", 4); 839 memcpy(&cpudata->gprs[NVMM_X64_GPR_RCX], "NVMM", 4); 840 memcpy(&cpudata->gprs[NVMM_X64_GPR_RDX], " ___", 4); 841 break; 842 case 0x80000001: 843 cpudata->vmcb->state.rax &= nvmm_cpuid_80000001.eax; 844 cpudata->gprs[NVMM_X64_GPR_RBX] &= nvmm_cpuid_80000001.ebx; 845 cpudata->gprs[NVMM_X64_GPR_RCX] &= nvmm_cpuid_80000001.ecx; 846 cpudata->gprs[NVMM_X64_GPR_RDX] &= nvmm_cpuid_80000001.edx; 847 break; 848 default: 849 break; 850 } 851 } 852 853 static void 854 svm_exit_cpuid(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 855 struct nvmm_exit *exit) 856 { 857 struct svm_machdata *machdata = mach->machdata; 858 struct svm_cpudata *cpudata = vcpu->cpudata; 859 struct nvmm_mach_conf_x86_cpuid *cpuid; 860 uint64_t eax, ecx; 861 u_int descs[4]; 862 size_t i; 863 864 eax = cpudata->vmcb->state.rax; 865 ecx = cpudata->gprs[NVMM_X64_GPR_RCX]; 866 x86_cpuid2(eax, ecx, descs); 867 868 cpudata->vmcb->state.rax = descs[0]; 869 cpudata->gprs[NVMM_X64_GPR_RBX] = descs[1]; 870 cpudata->gprs[NVMM_X64_GPR_RCX] = descs[2]; 871 cpudata->gprs[NVMM_X64_GPR_RDX] = descs[3]; 872 873 svm_inkernel_handle_cpuid(vcpu, eax, ecx); 874 875 for (i = 0; i < SVM_NCPUIDS; i++) { 876 cpuid = &machdata->cpuid[i]; 877 if (!machdata->cpuidpresent[i]) { 878 continue; 879 } 880 if (cpuid->leaf != eax) { 881 continue; 882 } 883 884 /* del */ 885 cpudata->vmcb->state.rax &= ~cpuid->del.eax; 886 cpudata->gprs[NVMM_X64_GPR_RBX] &= ~cpuid->del.ebx; 887 cpudata->gprs[NVMM_X64_GPR_RCX] &= ~cpuid->del.ecx; 888 cpudata->gprs[NVMM_X64_GPR_RDX] &= ~cpuid->del.edx; 889 890 /* set */ 891 cpudata->vmcb->state.rax |= cpuid->set.eax; 892 cpudata->gprs[NVMM_X64_GPR_RBX] |= cpuid->set.ebx; 893 cpudata->gprs[NVMM_X64_GPR_RCX] |= cpuid->set.ecx; 894 cpudata->gprs[NVMM_X64_GPR_RDX] |= cpuid->set.edx; 895 896 break; 897 } 898 899 svm_inkernel_advance(cpudata->vmcb); 900 exit->reason = NVMM_EXIT_NONE; 901 } 902 903 static void 904 svm_exit_hlt(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 905 struct nvmm_exit *exit) 906 { 907 struct svm_cpudata *cpudata = vcpu->cpudata; 908 struct vmcb *vmcb = cpudata->vmcb; 909 910 if (cpudata->int_window_exit && (vmcb->state.rflags & PSL_I)) { 911 svm_event_waitexit_disable(vcpu, false); 912 } 913 914 svm_inkernel_advance(cpudata->vmcb); 915 exit->reason = NVMM_EXIT_HALTED; 916 } 917 918 #define SVM_EXIT_IO_PORT __BITS(31,16) 919 #define SVM_EXIT_IO_SEG __BITS(12,10) 920 #define SVM_EXIT_IO_A64 __BIT(9) 921 #define SVM_EXIT_IO_A32 __BIT(8) 922 #define SVM_EXIT_IO_A16 __BIT(7) 923 #define SVM_EXIT_IO_SZ32 __BIT(6) 924 #define SVM_EXIT_IO_SZ16 __BIT(5) 925 #define SVM_EXIT_IO_SZ8 __BIT(4) 926 #define SVM_EXIT_IO_REP __BIT(3) 927 #define SVM_EXIT_IO_STR __BIT(2) 928 #define SVM_EXIT_IO_IN __BIT(0) 929 930 static void 931 svm_exit_io(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 932 struct nvmm_exit *exit) 933 { 934 struct svm_cpudata *cpudata = vcpu->cpudata; 935 uint64_t info = cpudata->vmcb->ctrl.exitinfo1; 936 uint64_t nextpc = cpudata->vmcb->ctrl.exitinfo2; 937 938 exit->reason = NVMM_EXIT_IO; 939 940 if (info & SVM_EXIT_IO_IN) { 941 exit->u.io.type = NVMM_EXIT_IO_IN; 942 } else { 943 exit->u.io.type = NVMM_EXIT_IO_OUT; 944 } 945 946 exit->u.io.port = __SHIFTOUT(info, SVM_EXIT_IO_PORT); 947 948 if (svm_decode_assist) { 949 KASSERT(__SHIFTOUT(info, SVM_EXIT_IO_SEG) < 6); 950 exit->u.io.seg = __SHIFTOUT(info, SVM_EXIT_IO_SEG); 951 } else { 952 exit->u.io.seg = -1; 953 } 954 955 if (info & SVM_EXIT_IO_A64) { 956 exit->u.io.address_size = 8; 957 } else if (info & SVM_EXIT_IO_A32) { 958 exit->u.io.address_size = 4; 959 } else if (info & SVM_EXIT_IO_A16) { 960 exit->u.io.address_size = 2; 961 } 962 963 if (info & SVM_EXIT_IO_SZ32) { 964 exit->u.io.operand_size = 4; 965 } else if (info & SVM_EXIT_IO_SZ16) { 966 exit->u.io.operand_size = 2; 967 } else if (info & SVM_EXIT_IO_SZ8) { 968 exit->u.io.operand_size = 1; 969 } 970 971 exit->u.io.rep = (info & SVM_EXIT_IO_REP) != 0; 972 exit->u.io.str = (info & SVM_EXIT_IO_STR) != 0; 973 exit->u.io.npc = nextpc; 974 975 svm_vcpu_state_provide(vcpu, 976 NVMM_X64_STATE_GPRS | NVMM_X64_STATE_SEGS | 977 NVMM_X64_STATE_CRS | NVMM_X64_STATE_MSRS); 978 } 979 980 static const uint64_t msr_ignore_list[] = { 981 0xc0010055, /* MSR_CMPHALT */ 982 MSR_DE_CFG, 983 MSR_IC_CFG, 984 MSR_UCODE_AMD_PATCHLEVEL 985 }; 986 987 static bool 988 svm_inkernel_handle_msr(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 989 struct nvmm_exit *exit) 990 { 991 struct svm_cpudata *cpudata = vcpu->cpudata; 992 struct vmcb *vmcb = cpudata->vmcb; 993 uint64_t val; 994 size_t i; 995 996 switch (exit->u.msr.type) { 997 case NVMM_EXIT_MSR_RDMSR: 998 if (exit->u.msr.msr == MSR_NB_CFG) { 999 val = NB_CFG_INITAPICCPUIDLO; 1000 vmcb->state.rax = (val & 0xFFFFFFFF); 1001 cpudata->gprs[NVMM_X64_GPR_RDX] = (val >> 32); 1002 goto handled; 1003 } 1004 for (i = 0; i < __arraycount(msr_ignore_list); i++) { 1005 if (msr_ignore_list[i] != exit->u.msr.msr) 1006 continue; 1007 val = 0; 1008 vmcb->state.rax = (val & 0xFFFFFFFF); 1009 cpudata->gprs[NVMM_X64_GPR_RDX] = (val >> 32); 1010 goto handled; 1011 } 1012 break; 1013 case NVMM_EXIT_MSR_WRMSR: 1014 if (exit->u.msr.msr == MSR_EFER) { 1015 if (__predict_false(exit->u.msr.val & ~EFER_VALID)) { 1016 goto error; 1017 } 1018 if ((vmcb->state.efer ^ exit->u.msr.val) & 1019 EFER_TLB_FLUSH) { 1020 cpudata->gtlb_want_flush = true; 1021 } 1022 vmcb->state.efer = exit->u.msr.val | EFER_SVME; 1023 svm_vmcb_cache_flush(vmcb, VMCB_CTRL_VMCB_CLEAN_CR); 1024 goto handled; 1025 } 1026 if (exit->u.msr.msr == MSR_TSC) { 1027 cpudata->gtsc = exit->u.msr.val; 1028 cpudata->gtsc_want_update = true; 1029 goto handled; 1030 } 1031 for (i = 0; i < __arraycount(msr_ignore_list); i++) { 1032 if (msr_ignore_list[i] != exit->u.msr.msr) 1033 continue; 1034 goto handled; 1035 } 1036 break; 1037 } 1038 1039 return false; 1040 1041 handled: 1042 svm_inkernel_advance(cpudata->vmcb); 1043 return true; 1044 1045 error: 1046 svm_inject_gp(vcpu); 1047 return true; 1048 } 1049 1050 static void 1051 svm_exit_msr(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 1052 struct nvmm_exit *exit) 1053 { 1054 struct svm_cpudata *cpudata = vcpu->cpudata; 1055 uint64_t info = cpudata->vmcb->ctrl.exitinfo1; 1056 1057 if (info == 0) { 1058 exit->u.msr.type = NVMM_EXIT_MSR_RDMSR; 1059 } else { 1060 exit->u.msr.type = NVMM_EXIT_MSR_WRMSR; 1061 } 1062 1063 exit->u.msr.msr = (cpudata->gprs[NVMM_X64_GPR_RCX] & 0xFFFFFFFF); 1064 1065 if (info == 1) { 1066 uint64_t rdx, rax; 1067 rdx = cpudata->gprs[NVMM_X64_GPR_RDX]; 1068 rax = cpudata->vmcb->state.rax; 1069 exit->u.msr.val = (rdx << 32) | (rax & 0xFFFFFFFF); 1070 } else { 1071 exit->u.msr.val = 0; 1072 } 1073 1074 if (svm_inkernel_handle_msr(mach, vcpu, exit)) { 1075 exit->reason = NVMM_EXIT_NONE; 1076 return; 1077 } 1078 1079 exit->reason = NVMM_EXIT_MSR; 1080 exit->u.msr.npc = cpudata->vmcb->ctrl.nrip; 1081 1082 svm_vcpu_state_provide(vcpu, NVMM_X64_STATE_GPRS); 1083 } 1084 1085 static void 1086 svm_exit_npf(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 1087 struct nvmm_exit *exit) 1088 { 1089 struct svm_cpudata *cpudata = vcpu->cpudata; 1090 gpaddr_t gpa = cpudata->vmcb->ctrl.exitinfo2; 1091 1092 exit->reason = NVMM_EXIT_MEMORY; 1093 if (cpudata->vmcb->ctrl.exitinfo1 & PGEX_W) 1094 exit->u.mem.prot = PROT_WRITE; 1095 else if (cpudata->vmcb->ctrl.exitinfo1 & PGEX_X) 1096 exit->u.mem.prot = PROT_EXEC; 1097 else 1098 exit->u.mem.prot = PROT_READ; 1099 exit->u.mem.gpa = gpa; 1100 exit->u.mem.inst_len = cpudata->vmcb->ctrl.inst_len; 1101 memcpy(exit->u.mem.inst_bytes, cpudata->vmcb->ctrl.inst_bytes, 1102 sizeof(exit->u.mem.inst_bytes)); 1103 1104 svm_vcpu_state_provide(vcpu, 1105 NVMM_X64_STATE_GPRS | NVMM_X64_STATE_SEGS | 1106 NVMM_X64_STATE_CRS | NVMM_X64_STATE_MSRS); 1107 } 1108 1109 static void 1110 svm_exit_insn(struct vmcb *vmcb, struct nvmm_exit *exit, uint64_t reason) 1111 { 1112 exit->u.insn.npc = vmcb->ctrl.nrip; 1113 exit->reason = reason; 1114 } 1115 1116 static void 1117 svm_exit_xsetbv(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 1118 struct nvmm_exit *exit) 1119 { 1120 struct svm_cpudata *cpudata = vcpu->cpudata; 1121 struct vmcb *vmcb = cpudata->vmcb; 1122 uint64_t val; 1123 1124 exit->reason = NVMM_EXIT_NONE; 1125 1126 val = (cpudata->gprs[NVMM_X64_GPR_RDX] << 32) | 1127 (vmcb->state.rax & 0xFFFFFFFF); 1128 1129 if (__predict_false(cpudata->gprs[NVMM_X64_GPR_RCX] != 0)) { 1130 goto error; 1131 } else if (__predict_false(vmcb->state.cpl != 0)) { 1132 goto error; 1133 } else if (__predict_false((val & ~svm_xcr0_mask) != 0)) { 1134 goto error; 1135 } else if (__predict_false((val & XCR0_X87) == 0)) { 1136 goto error; 1137 } 1138 1139 cpudata->gxcr0 = val; 1140 1141 svm_inkernel_advance(cpudata->vmcb); 1142 return; 1143 1144 error: 1145 svm_inject_gp(vcpu); 1146 } 1147 1148 static void 1149 svm_exit_invalid(struct nvmm_exit *exit, uint64_t code) 1150 { 1151 exit->u.inv.hwcode = code; 1152 exit->reason = NVMM_EXIT_INVALID; 1153 } 1154 1155 /* -------------------------------------------------------------------------- */ 1156 1157 static void 1158 svm_vcpu_guest_fpu_enter(struct nvmm_cpu *vcpu) 1159 { 1160 struct svm_cpudata *cpudata = vcpu->cpudata; 1161 1162 cpudata->ts_set = (rcr0() & CR0_TS) != 0; 1163 1164 fpu_area_save(&cpudata->hfpu, svm_xcr0_mask); 1165 fpu_area_restore(&cpudata->gfpu, svm_xcr0_mask); 1166 1167 if (svm_xcr0_mask != 0) { 1168 cpudata->hxcr0 = rdxcr(0); 1169 wrxcr(0, cpudata->gxcr0); 1170 } 1171 } 1172 1173 static void 1174 svm_vcpu_guest_fpu_leave(struct nvmm_cpu *vcpu) 1175 { 1176 struct svm_cpudata *cpudata = vcpu->cpudata; 1177 1178 if (svm_xcr0_mask != 0) { 1179 cpudata->gxcr0 = rdxcr(0); 1180 wrxcr(0, cpudata->hxcr0); 1181 } 1182 1183 fpu_area_save(&cpudata->gfpu, svm_xcr0_mask); 1184 fpu_area_restore(&cpudata->hfpu, svm_xcr0_mask); 1185 1186 if (cpudata->ts_set) { 1187 stts(); 1188 } 1189 } 1190 1191 static void 1192 svm_vcpu_guest_dbregs_enter(struct nvmm_cpu *vcpu) 1193 { 1194 struct svm_cpudata *cpudata = vcpu->cpudata; 1195 1196 x86_dbregs_save(curlwp); 1197 1198 ldr7(0); 1199 1200 ldr0(cpudata->drs[NVMM_X64_DR_DR0]); 1201 ldr1(cpudata->drs[NVMM_X64_DR_DR1]); 1202 ldr2(cpudata->drs[NVMM_X64_DR_DR2]); 1203 ldr3(cpudata->drs[NVMM_X64_DR_DR3]); 1204 } 1205 1206 static void 1207 svm_vcpu_guest_dbregs_leave(struct nvmm_cpu *vcpu) 1208 { 1209 struct svm_cpudata *cpudata = vcpu->cpudata; 1210 1211 cpudata->drs[NVMM_X64_DR_DR0] = rdr0(); 1212 cpudata->drs[NVMM_X64_DR_DR1] = rdr1(); 1213 cpudata->drs[NVMM_X64_DR_DR2] = rdr2(); 1214 cpudata->drs[NVMM_X64_DR_DR3] = rdr3(); 1215 1216 x86_dbregs_restore(curlwp); 1217 } 1218 1219 static void 1220 svm_vcpu_guest_misc_enter(struct nvmm_cpu *vcpu) 1221 { 1222 struct svm_cpudata *cpudata = vcpu->cpudata; 1223 1224 cpudata->fsbase = rdmsr(MSR_FSBASE); 1225 cpudata->kernelgsbase = rdmsr(MSR_KERNELGSBASE); 1226 } 1227 1228 static void 1229 svm_vcpu_guest_misc_leave(struct nvmm_cpu *vcpu) 1230 { 1231 struct svm_cpudata *cpudata = vcpu->cpudata; 1232 1233 wrmsr(MSR_STAR, cpudata->star); 1234 wrmsr(MSR_LSTAR, cpudata->lstar); 1235 wrmsr(MSR_CSTAR, cpudata->cstar); 1236 wrmsr(MSR_SFMASK, cpudata->sfmask); 1237 wrmsr(MSR_FSBASE, cpudata->fsbase); 1238 wrmsr(MSR_KERNELGSBASE, cpudata->kernelgsbase); 1239 } 1240 1241 /* -------------------------------------------------------------------------- */ 1242 1243 static inline void 1244 svm_gtlb_catchup(struct nvmm_cpu *vcpu, int hcpu) 1245 { 1246 struct svm_cpudata *cpudata = vcpu->cpudata; 1247 1248 if (vcpu->hcpu_last != hcpu || cpudata->shared_asid) { 1249 cpudata->gtlb_want_flush = true; 1250 } 1251 } 1252 1253 static inline void 1254 svm_htlb_catchup(struct nvmm_cpu *vcpu, int hcpu) 1255 { 1256 /* 1257 * Nothing to do. If an hTLB flush was needed, either the VCPU was 1258 * executing on this hCPU and the hTLB already got flushed, or it 1259 * was executing on another hCPU in which case the catchup is done 1260 * in svm_gtlb_catchup(). 1261 */ 1262 } 1263 1264 static inline uint64_t 1265 svm_htlb_flush(struct svm_machdata *machdata, struct svm_cpudata *cpudata) 1266 { 1267 struct vmcb *vmcb = cpudata->vmcb; 1268 uint64_t machgen; 1269 1270 machgen = machdata->mach_htlb_gen; 1271 if (__predict_true(machgen == cpudata->vcpu_htlb_gen)) { 1272 return machgen; 1273 } 1274 1275 vmcb->ctrl.tlb_ctrl = svm_ctrl_tlb_flush; 1276 return machgen; 1277 } 1278 1279 static inline void 1280 svm_htlb_flush_ack(struct svm_cpudata *cpudata, uint64_t machgen) 1281 { 1282 struct vmcb *vmcb = cpudata->vmcb; 1283 1284 if (__predict_true(vmcb->ctrl.exitcode != VMCB_EXITCODE_INVALID)) { 1285 cpudata->vcpu_htlb_gen = machgen; 1286 } 1287 } 1288 1289 static inline void 1290 svm_exit_evt(struct svm_cpudata *cpudata, struct vmcb *vmcb) 1291 { 1292 cpudata->evt_pending = false; 1293 1294 if (__predict_false(vmcb->ctrl.exitintinfo & VMCB_CTRL_EXITINTINFO_V)) { 1295 vmcb->ctrl.eventinj = vmcb->ctrl.exitintinfo; 1296 cpudata->evt_pending = true; 1297 } 1298 } 1299 1300 static int 1301 svm_vcpu_run(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 1302 struct nvmm_exit *exit) 1303 { 1304 struct nvmm_comm_page *comm = vcpu->comm; 1305 struct svm_machdata *machdata = mach->machdata; 1306 struct svm_cpudata *cpudata = vcpu->cpudata; 1307 struct vmcb *vmcb = cpudata->vmcb; 1308 uint64_t machgen; 1309 int hcpu, s; 1310 1311 if (__predict_false(svm_vcpu_event_commit(vcpu) != 0)) { 1312 return EINVAL; 1313 } 1314 svm_vcpu_state_commit(vcpu); 1315 comm->state_cached = 0; 1316 1317 kpreempt_disable(); 1318 hcpu = cpu_number(); 1319 1320 svm_gtlb_catchup(vcpu, hcpu); 1321 svm_htlb_catchup(vcpu, hcpu); 1322 1323 if (vcpu->hcpu_last != hcpu) { 1324 svm_vmcb_cache_flush_all(vmcb); 1325 cpudata->gtsc_want_update = true; 1326 } 1327 1328 svm_vcpu_guest_dbregs_enter(vcpu); 1329 svm_vcpu_guest_misc_enter(vcpu); 1330 1331 while (1) { 1332 if (cpudata->gtlb_want_flush) { 1333 vmcb->ctrl.tlb_ctrl = svm_ctrl_tlb_flush; 1334 } else { 1335 vmcb->ctrl.tlb_ctrl = 0; 1336 } 1337 1338 if (__predict_false(cpudata->gtsc_want_update)) { 1339 vmcb->ctrl.tsc_offset = cpudata->gtsc - rdtsc(); 1340 svm_vmcb_cache_flush(vmcb, VMCB_CTRL_VMCB_CLEAN_I); 1341 } 1342 1343 s = splhigh(); 1344 machgen = svm_htlb_flush(machdata, cpudata); 1345 svm_vcpu_guest_fpu_enter(vcpu); 1346 svm_vmrun(cpudata->vmcb_pa, cpudata->gprs); 1347 svm_vcpu_guest_fpu_leave(vcpu); 1348 svm_htlb_flush_ack(cpudata, machgen); 1349 splx(s); 1350 1351 svm_vmcb_cache_default(vmcb); 1352 1353 if (vmcb->ctrl.exitcode != VMCB_EXITCODE_INVALID) { 1354 cpudata->gtlb_want_flush = false; 1355 cpudata->gtsc_want_update = false; 1356 vcpu->hcpu_last = hcpu; 1357 } 1358 svm_exit_evt(cpudata, vmcb); 1359 1360 switch (vmcb->ctrl.exitcode) { 1361 case VMCB_EXITCODE_INTR: 1362 case VMCB_EXITCODE_NMI: 1363 exit->reason = NVMM_EXIT_NONE; 1364 break; 1365 case VMCB_EXITCODE_VINTR: 1366 svm_event_waitexit_disable(vcpu, false); 1367 exit->reason = NVMM_EXIT_INT_READY; 1368 break; 1369 case VMCB_EXITCODE_IRET: 1370 svm_event_waitexit_disable(vcpu, true); 1371 exit->reason = NVMM_EXIT_NMI_READY; 1372 break; 1373 case VMCB_EXITCODE_CPUID: 1374 svm_exit_cpuid(mach, vcpu, exit); 1375 break; 1376 case VMCB_EXITCODE_HLT: 1377 svm_exit_hlt(mach, vcpu, exit); 1378 break; 1379 case VMCB_EXITCODE_IOIO: 1380 svm_exit_io(mach, vcpu, exit); 1381 break; 1382 case VMCB_EXITCODE_MSR: 1383 svm_exit_msr(mach, vcpu, exit); 1384 break; 1385 case VMCB_EXITCODE_SHUTDOWN: 1386 exit->reason = NVMM_EXIT_SHUTDOWN; 1387 break; 1388 case VMCB_EXITCODE_RDPMC: 1389 case VMCB_EXITCODE_RSM: 1390 case VMCB_EXITCODE_INVLPGA: 1391 case VMCB_EXITCODE_VMRUN: 1392 case VMCB_EXITCODE_VMMCALL: 1393 case VMCB_EXITCODE_VMLOAD: 1394 case VMCB_EXITCODE_VMSAVE: 1395 case VMCB_EXITCODE_STGI: 1396 case VMCB_EXITCODE_CLGI: 1397 case VMCB_EXITCODE_SKINIT: 1398 case VMCB_EXITCODE_RDTSCP: 1399 svm_inject_ud(vcpu); 1400 exit->reason = NVMM_EXIT_NONE; 1401 break; 1402 case VMCB_EXITCODE_MONITOR: 1403 svm_exit_insn(vmcb, exit, NVMM_EXIT_MONITOR); 1404 break; 1405 case VMCB_EXITCODE_MWAIT: 1406 svm_exit_insn(vmcb, exit, NVMM_EXIT_MWAIT); 1407 break; 1408 case VMCB_EXITCODE_MWAIT_CONDITIONAL: 1409 svm_exit_insn(vmcb, exit, NVMM_EXIT_MWAIT_COND); 1410 break; 1411 case VMCB_EXITCODE_XSETBV: 1412 svm_exit_xsetbv(mach, vcpu, exit); 1413 break; 1414 case VMCB_EXITCODE_NPF: 1415 svm_exit_npf(mach, vcpu, exit); 1416 break; 1417 case VMCB_EXITCODE_FERR_FREEZE: /* ? */ 1418 default: 1419 svm_exit_invalid(exit, vmcb->ctrl.exitcode); 1420 break; 1421 } 1422 1423 /* If no reason to return to userland, keep rolling. */ 1424 if (curcpu()->ci_schedstate.spc_flags & SPCF_SHOULDYIELD) { 1425 break; 1426 } 1427 if (curcpu()->ci_data.cpu_softints != 0) { 1428 break; 1429 } 1430 if (curlwp->l_flag & LW_USERRET) { 1431 break; 1432 } 1433 if (exit->reason != NVMM_EXIT_NONE) { 1434 break; 1435 } 1436 } 1437 1438 cpudata->gtsc = rdtsc() + vmcb->ctrl.tsc_offset; 1439 1440 svm_vcpu_guest_misc_leave(vcpu); 1441 svm_vcpu_guest_dbregs_leave(vcpu); 1442 1443 kpreempt_enable(); 1444 1445 exit->exitstate[NVMM_X64_EXITSTATE_CR8] = __SHIFTOUT(vmcb->ctrl.v, 1446 VMCB_CTRL_V_TPR); 1447 exit->exitstate[NVMM_X64_EXITSTATE_RFLAGS] = vmcb->state.rflags; 1448 1449 exit->exitstate[NVMM_X64_EXITSTATE_INT_SHADOW] = 1450 ((vmcb->ctrl.intr & VMCB_CTRL_INTR_SHADOW) != 0); 1451 exit->exitstate[NVMM_X64_EXITSTATE_INT_WINDOW_EXIT] = 1452 cpudata->int_window_exit; 1453 exit->exitstate[NVMM_X64_EXITSTATE_NMI_WINDOW_EXIT] = 1454 cpudata->nmi_window_exit; 1455 exit->exitstate[NVMM_X64_EXITSTATE_EVT_PENDING] = 1456 cpudata->evt_pending; 1457 1458 return 0; 1459 } 1460 1461 /* -------------------------------------------------------------------------- */ 1462 1463 static int 1464 svm_memalloc(paddr_t *pa, vaddr_t *va, size_t npages) 1465 { 1466 struct pglist pglist; 1467 paddr_t _pa; 1468 vaddr_t _va; 1469 size_t i; 1470 int ret; 1471 1472 ret = uvm_pglistalloc(npages * PAGE_SIZE, 0, ~0UL, PAGE_SIZE, 0, 1473 &pglist, 1, 0); 1474 if (ret != 0) 1475 return ENOMEM; 1476 _pa = TAILQ_FIRST(&pglist)->phys_addr; 1477 _va = uvm_km_alloc(kernel_map, npages * PAGE_SIZE, 0, 1478 UVM_KMF_VAONLY | UVM_KMF_NOWAIT); 1479 if (_va == 0) 1480 goto error; 1481 1482 for (i = 0; i < npages; i++) { 1483 pmap_kenter_pa(_va + i * PAGE_SIZE, _pa + i * PAGE_SIZE, 1484 VM_PROT_READ | VM_PROT_WRITE, PMAP_WRITE_BACK); 1485 } 1486 pmap_update(pmap_kernel()); 1487 1488 memset((void *)_va, 0, npages * PAGE_SIZE); 1489 1490 *pa = _pa; 1491 *va = _va; 1492 return 0; 1493 1494 error: 1495 for (i = 0; i < npages; i++) { 1496 uvm_pagefree(PHYS_TO_VM_PAGE(_pa + i * PAGE_SIZE)); 1497 } 1498 return ENOMEM; 1499 } 1500 1501 static void 1502 svm_memfree(paddr_t pa, vaddr_t va, size_t npages) 1503 { 1504 size_t i; 1505 1506 pmap_kremove(va, npages * PAGE_SIZE); 1507 pmap_update(pmap_kernel()); 1508 uvm_km_free(kernel_map, va, npages * PAGE_SIZE, UVM_KMF_VAONLY); 1509 for (i = 0; i < npages; i++) { 1510 uvm_pagefree(PHYS_TO_VM_PAGE(pa + i * PAGE_SIZE)); 1511 } 1512 } 1513 1514 /* -------------------------------------------------------------------------- */ 1515 1516 #define SVM_MSRBM_READ __BIT(0) 1517 #define SVM_MSRBM_WRITE __BIT(1) 1518 1519 static void 1520 svm_vcpu_msr_allow(uint8_t *bitmap, uint64_t msr, bool read, bool write) 1521 { 1522 uint64_t byte; 1523 uint8_t bitoff; 1524 1525 if (msr < 0x00002000) { 1526 /* Range 1 */ 1527 byte = ((msr - 0x00000000) >> 2UL) + 0x0000; 1528 } else if (msr >= 0xC0000000 && msr < 0xC0002000) { 1529 /* Range 2 */ 1530 byte = ((msr - 0xC0000000) >> 2UL) + 0x0800; 1531 } else if (msr >= 0xC0010000 && msr < 0xC0012000) { 1532 /* Range 3 */ 1533 byte = ((msr - 0xC0010000) >> 2UL) + 0x1000; 1534 } else { 1535 panic("%s: wrong range", __func__); 1536 } 1537 1538 bitoff = (msr & 0x3) << 1; 1539 1540 if (read) { 1541 bitmap[byte] &= ~(SVM_MSRBM_READ << bitoff); 1542 } 1543 if (write) { 1544 bitmap[byte] &= ~(SVM_MSRBM_WRITE << bitoff); 1545 } 1546 } 1547 1548 #define SVM_SEG_ATTRIB_TYPE __BITS(3,0) 1549 #define SVM_SEG_ATTRIB_S __BIT(4) 1550 #define SVM_SEG_ATTRIB_DPL __BITS(6,5) 1551 #define SVM_SEG_ATTRIB_P __BIT(7) 1552 #define SVM_SEG_ATTRIB_AVL __BIT(8) 1553 #define SVM_SEG_ATTRIB_L __BIT(9) 1554 #define SVM_SEG_ATTRIB_DEF __BIT(10) 1555 #define SVM_SEG_ATTRIB_G __BIT(11) 1556 1557 static void 1558 svm_vcpu_setstate_seg(const struct nvmm_x64_state_seg *seg, 1559 struct vmcb_segment *vseg) 1560 { 1561 vseg->selector = seg->selector; 1562 vseg->attrib = 1563 __SHIFTIN(seg->attrib.type, SVM_SEG_ATTRIB_TYPE) | 1564 __SHIFTIN(seg->attrib.s, SVM_SEG_ATTRIB_S) | 1565 __SHIFTIN(seg->attrib.dpl, SVM_SEG_ATTRIB_DPL) | 1566 __SHIFTIN(seg->attrib.p, SVM_SEG_ATTRIB_P) | 1567 __SHIFTIN(seg->attrib.avl, SVM_SEG_ATTRIB_AVL) | 1568 __SHIFTIN(seg->attrib.l, SVM_SEG_ATTRIB_L) | 1569 __SHIFTIN(seg->attrib.def, SVM_SEG_ATTRIB_DEF) | 1570 __SHIFTIN(seg->attrib.g, SVM_SEG_ATTRIB_G); 1571 vseg->limit = seg->limit; 1572 vseg->base = seg->base; 1573 } 1574 1575 static void 1576 svm_vcpu_getstate_seg(struct nvmm_x64_state_seg *seg, struct vmcb_segment *vseg) 1577 { 1578 seg->selector = vseg->selector; 1579 seg->attrib.type = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_TYPE); 1580 seg->attrib.s = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_S); 1581 seg->attrib.dpl = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_DPL); 1582 seg->attrib.p = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_P); 1583 seg->attrib.avl = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_AVL); 1584 seg->attrib.l = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_L); 1585 seg->attrib.def = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_DEF); 1586 seg->attrib.g = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_G); 1587 seg->limit = vseg->limit; 1588 seg->base = vseg->base; 1589 } 1590 1591 static inline bool 1592 svm_state_tlb_flush(const struct vmcb *vmcb, const struct nvmm_x64_state *state, 1593 uint64_t flags) 1594 { 1595 if (flags & NVMM_X64_STATE_CRS) { 1596 if ((vmcb->state.cr0 ^ 1597 state->crs[NVMM_X64_CR_CR0]) & CR0_TLB_FLUSH) { 1598 return true; 1599 } 1600 if (vmcb->state.cr3 != state->crs[NVMM_X64_CR_CR3]) { 1601 return true; 1602 } 1603 if ((vmcb->state.cr4 ^ 1604 state->crs[NVMM_X64_CR_CR4]) & CR4_TLB_FLUSH) { 1605 return true; 1606 } 1607 } 1608 1609 if (flags & NVMM_X64_STATE_MSRS) { 1610 if ((vmcb->state.efer ^ 1611 state->msrs[NVMM_X64_MSR_EFER]) & EFER_TLB_FLUSH) { 1612 return true; 1613 } 1614 } 1615 1616 return false; 1617 } 1618 1619 static void 1620 svm_vcpu_setstate(struct nvmm_cpu *vcpu) 1621 { 1622 struct nvmm_comm_page *comm = vcpu->comm; 1623 const struct nvmm_x64_state *state = &comm->state; 1624 struct svm_cpudata *cpudata = vcpu->cpudata; 1625 struct vmcb *vmcb = cpudata->vmcb; 1626 struct fxsave *fpustate; 1627 uint64_t flags; 1628 1629 flags = comm->state_wanted; 1630 1631 if (svm_state_tlb_flush(vmcb, state, flags)) { 1632 cpudata->gtlb_want_flush = true; 1633 } 1634 1635 if (flags & NVMM_X64_STATE_SEGS) { 1636 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_CS], 1637 &vmcb->state.cs); 1638 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_DS], 1639 &vmcb->state.ds); 1640 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_ES], 1641 &vmcb->state.es); 1642 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_FS], 1643 &vmcb->state.fs); 1644 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_GS], 1645 &vmcb->state.gs); 1646 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_SS], 1647 &vmcb->state.ss); 1648 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_GDT], 1649 &vmcb->state.gdt); 1650 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_IDT], 1651 &vmcb->state.idt); 1652 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_LDT], 1653 &vmcb->state.ldt); 1654 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_TR], 1655 &vmcb->state.tr); 1656 1657 vmcb->state.cpl = state->segs[NVMM_X64_SEG_SS].attrib.dpl; 1658 } 1659 1660 CTASSERT(sizeof(cpudata->gprs) == sizeof(state->gprs)); 1661 if (flags & NVMM_X64_STATE_GPRS) { 1662 memcpy(cpudata->gprs, state->gprs, sizeof(state->gprs)); 1663 1664 vmcb->state.rip = state->gprs[NVMM_X64_GPR_RIP]; 1665 vmcb->state.rsp = state->gprs[NVMM_X64_GPR_RSP]; 1666 vmcb->state.rax = state->gprs[NVMM_X64_GPR_RAX]; 1667 vmcb->state.rflags = state->gprs[NVMM_X64_GPR_RFLAGS]; 1668 } 1669 1670 if (flags & NVMM_X64_STATE_CRS) { 1671 vmcb->state.cr0 = state->crs[NVMM_X64_CR_CR0]; 1672 vmcb->state.cr2 = state->crs[NVMM_X64_CR_CR2]; 1673 vmcb->state.cr3 = state->crs[NVMM_X64_CR_CR3]; 1674 vmcb->state.cr4 = state->crs[NVMM_X64_CR_CR4]; 1675 1676 vmcb->ctrl.v &= ~VMCB_CTRL_V_TPR; 1677 vmcb->ctrl.v |= __SHIFTIN(state->crs[NVMM_X64_CR_CR8], 1678 VMCB_CTRL_V_TPR); 1679 1680 if (svm_xcr0_mask != 0) { 1681 /* Clear illegal XCR0 bits, set mandatory X87 bit. */ 1682 cpudata->gxcr0 = state->crs[NVMM_X64_CR_XCR0]; 1683 cpudata->gxcr0 &= svm_xcr0_mask; 1684 cpudata->gxcr0 |= XCR0_X87; 1685 } 1686 } 1687 1688 CTASSERT(sizeof(cpudata->drs) == sizeof(state->drs)); 1689 if (flags & NVMM_X64_STATE_DRS) { 1690 memcpy(cpudata->drs, state->drs, sizeof(state->drs)); 1691 1692 vmcb->state.dr6 = state->drs[NVMM_X64_DR_DR6]; 1693 vmcb->state.dr7 = state->drs[NVMM_X64_DR_DR7]; 1694 } 1695 1696 if (flags & NVMM_X64_STATE_MSRS) { 1697 /* 1698 * EFER_SVME is mandatory. 1699 */ 1700 vmcb->state.efer = state->msrs[NVMM_X64_MSR_EFER] | EFER_SVME; 1701 vmcb->state.star = state->msrs[NVMM_X64_MSR_STAR]; 1702 vmcb->state.lstar = state->msrs[NVMM_X64_MSR_LSTAR]; 1703 vmcb->state.cstar = state->msrs[NVMM_X64_MSR_CSTAR]; 1704 vmcb->state.sfmask = state->msrs[NVMM_X64_MSR_SFMASK]; 1705 vmcb->state.kernelgsbase = 1706 state->msrs[NVMM_X64_MSR_KERNELGSBASE]; 1707 vmcb->state.sysenter_cs = 1708 state->msrs[NVMM_X64_MSR_SYSENTER_CS]; 1709 vmcb->state.sysenter_esp = 1710 state->msrs[NVMM_X64_MSR_SYSENTER_ESP]; 1711 vmcb->state.sysenter_eip = 1712 state->msrs[NVMM_X64_MSR_SYSENTER_EIP]; 1713 vmcb->state.g_pat = state->msrs[NVMM_X64_MSR_PAT]; 1714 1715 cpudata->gtsc = state->msrs[NVMM_X64_MSR_TSC]; 1716 cpudata->gtsc_want_update = true; 1717 } 1718 1719 if (flags & NVMM_X64_STATE_INTR) { 1720 if (state->intr.int_shadow) { 1721 vmcb->ctrl.intr |= VMCB_CTRL_INTR_SHADOW; 1722 } else { 1723 vmcb->ctrl.intr &= ~VMCB_CTRL_INTR_SHADOW; 1724 } 1725 1726 if (state->intr.int_window_exiting) { 1727 svm_event_waitexit_enable(vcpu, false); 1728 } else { 1729 svm_event_waitexit_disable(vcpu, false); 1730 } 1731 1732 if (state->intr.nmi_window_exiting) { 1733 svm_event_waitexit_enable(vcpu, true); 1734 } else { 1735 svm_event_waitexit_disable(vcpu, true); 1736 } 1737 } 1738 1739 CTASSERT(sizeof(cpudata->gfpu.xsh_fxsave) == sizeof(state->fpu)); 1740 if (flags & NVMM_X64_STATE_FPU) { 1741 memcpy(cpudata->gfpu.xsh_fxsave, &state->fpu, 1742 sizeof(state->fpu)); 1743 1744 fpustate = (struct fxsave *)cpudata->gfpu.xsh_fxsave; 1745 fpustate->fx_mxcsr_mask &= x86_fpu_mxcsr_mask; 1746 fpustate->fx_mxcsr &= fpustate->fx_mxcsr_mask; 1747 1748 if (svm_xcr0_mask != 0) { 1749 /* Reset XSTATE_BV, to force a reload. */ 1750 cpudata->gfpu.xsh_xstate_bv = svm_xcr0_mask; 1751 } 1752 } 1753 1754 svm_vmcb_cache_update(vmcb, flags); 1755 1756 comm->state_wanted = 0; 1757 comm->state_cached |= flags; 1758 } 1759 1760 static void 1761 svm_vcpu_getstate(struct nvmm_cpu *vcpu) 1762 { 1763 struct nvmm_comm_page *comm = vcpu->comm; 1764 struct nvmm_x64_state *state = &comm->state; 1765 struct svm_cpudata *cpudata = vcpu->cpudata; 1766 struct vmcb *vmcb = cpudata->vmcb; 1767 uint64_t flags; 1768 1769 flags = comm->state_wanted; 1770 1771 if (flags & NVMM_X64_STATE_SEGS) { 1772 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_CS], 1773 &vmcb->state.cs); 1774 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_DS], 1775 &vmcb->state.ds); 1776 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_ES], 1777 &vmcb->state.es); 1778 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_FS], 1779 &vmcb->state.fs); 1780 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_GS], 1781 &vmcb->state.gs); 1782 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_SS], 1783 &vmcb->state.ss); 1784 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_GDT], 1785 &vmcb->state.gdt); 1786 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_IDT], 1787 &vmcb->state.idt); 1788 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_LDT], 1789 &vmcb->state.ldt); 1790 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_TR], 1791 &vmcb->state.tr); 1792 1793 state->segs[NVMM_X64_SEG_SS].attrib.dpl = vmcb->state.cpl; 1794 } 1795 1796 CTASSERT(sizeof(cpudata->gprs) == sizeof(state->gprs)); 1797 if (flags & NVMM_X64_STATE_GPRS) { 1798 memcpy(state->gprs, cpudata->gprs, sizeof(state->gprs)); 1799 1800 state->gprs[NVMM_X64_GPR_RIP] = vmcb->state.rip; 1801 state->gprs[NVMM_X64_GPR_RSP] = vmcb->state.rsp; 1802 state->gprs[NVMM_X64_GPR_RAX] = vmcb->state.rax; 1803 state->gprs[NVMM_X64_GPR_RFLAGS] = vmcb->state.rflags; 1804 } 1805 1806 if (flags & NVMM_X64_STATE_CRS) { 1807 state->crs[NVMM_X64_CR_CR0] = vmcb->state.cr0; 1808 state->crs[NVMM_X64_CR_CR2] = vmcb->state.cr2; 1809 state->crs[NVMM_X64_CR_CR3] = vmcb->state.cr3; 1810 state->crs[NVMM_X64_CR_CR4] = vmcb->state.cr4; 1811 state->crs[NVMM_X64_CR_CR8] = __SHIFTOUT(vmcb->ctrl.v, 1812 VMCB_CTRL_V_TPR); 1813 state->crs[NVMM_X64_CR_XCR0] = cpudata->gxcr0; 1814 } 1815 1816 CTASSERT(sizeof(cpudata->drs) == sizeof(state->drs)); 1817 if (flags & NVMM_X64_STATE_DRS) { 1818 memcpy(state->drs, cpudata->drs, sizeof(state->drs)); 1819 1820 state->drs[NVMM_X64_DR_DR6] = vmcb->state.dr6; 1821 state->drs[NVMM_X64_DR_DR7] = vmcb->state.dr7; 1822 } 1823 1824 if (flags & NVMM_X64_STATE_MSRS) { 1825 state->msrs[NVMM_X64_MSR_EFER] = vmcb->state.efer; 1826 state->msrs[NVMM_X64_MSR_STAR] = vmcb->state.star; 1827 state->msrs[NVMM_X64_MSR_LSTAR] = vmcb->state.lstar; 1828 state->msrs[NVMM_X64_MSR_CSTAR] = vmcb->state.cstar; 1829 state->msrs[NVMM_X64_MSR_SFMASK] = vmcb->state.sfmask; 1830 state->msrs[NVMM_X64_MSR_KERNELGSBASE] = 1831 vmcb->state.kernelgsbase; 1832 state->msrs[NVMM_X64_MSR_SYSENTER_CS] = 1833 vmcb->state.sysenter_cs; 1834 state->msrs[NVMM_X64_MSR_SYSENTER_ESP] = 1835 vmcb->state.sysenter_esp; 1836 state->msrs[NVMM_X64_MSR_SYSENTER_EIP] = 1837 vmcb->state.sysenter_eip; 1838 state->msrs[NVMM_X64_MSR_PAT] = vmcb->state.g_pat; 1839 state->msrs[NVMM_X64_MSR_TSC] = cpudata->gtsc; 1840 1841 /* Hide SVME. */ 1842 state->msrs[NVMM_X64_MSR_EFER] &= ~EFER_SVME; 1843 } 1844 1845 if (flags & NVMM_X64_STATE_INTR) { 1846 state->intr.int_shadow = 1847 (vmcb->ctrl.intr & VMCB_CTRL_INTR_SHADOW) != 0; 1848 state->intr.int_window_exiting = cpudata->int_window_exit; 1849 state->intr.nmi_window_exiting = cpudata->nmi_window_exit; 1850 state->intr.evt_pending = cpudata->evt_pending; 1851 } 1852 1853 CTASSERT(sizeof(cpudata->gfpu.xsh_fxsave) == sizeof(state->fpu)); 1854 if (flags & NVMM_X64_STATE_FPU) { 1855 memcpy(&state->fpu, cpudata->gfpu.xsh_fxsave, 1856 sizeof(state->fpu)); 1857 } 1858 1859 comm->state_wanted = 0; 1860 comm->state_cached |= flags; 1861 } 1862 1863 static void 1864 svm_vcpu_state_provide(struct nvmm_cpu *vcpu, uint64_t flags) 1865 { 1866 vcpu->comm->state_wanted = flags; 1867 svm_vcpu_getstate(vcpu); 1868 } 1869 1870 static void 1871 svm_vcpu_state_commit(struct nvmm_cpu *vcpu) 1872 { 1873 vcpu->comm->state_wanted = vcpu->comm->state_commit; 1874 vcpu->comm->state_commit = 0; 1875 svm_vcpu_setstate(vcpu); 1876 } 1877 1878 /* -------------------------------------------------------------------------- */ 1879 1880 static void 1881 svm_asid_alloc(struct nvmm_cpu *vcpu) 1882 { 1883 struct svm_cpudata *cpudata = vcpu->cpudata; 1884 struct vmcb *vmcb = cpudata->vmcb; 1885 size_t i, oct, bit; 1886 1887 mutex_enter(&svm_asidlock); 1888 1889 for (i = 0; i < svm_maxasid; i++) { 1890 oct = i / 8; 1891 bit = i % 8; 1892 1893 if (svm_asidmap[oct] & __BIT(bit)) { 1894 continue; 1895 } 1896 1897 svm_asidmap[oct] |= __BIT(bit); 1898 vmcb->ctrl.guest_asid = i; 1899 mutex_exit(&svm_asidlock); 1900 return; 1901 } 1902 1903 /* 1904 * No free ASID. Use the last one, which is shared and requires 1905 * special TLB handling. 1906 */ 1907 cpudata->shared_asid = true; 1908 vmcb->ctrl.guest_asid = svm_maxasid - 1; 1909 mutex_exit(&svm_asidlock); 1910 } 1911 1912 static void 1913 svm_asid_free(struct nvmm_cpu *vcpu) 1914 { 1915 struct svm_cpudata *cpudata = vcpu->cpudata; 1916 struct vmcb *vmcb = cpudata->vmcb; 1917 size_t oct, bit; 1918 1919 if (cpudata->shared_asid) { 1920 return; 1921 } 1922 1923 oct = vmcb->ctrl.guest_asid / 8; 1924 bit = vmcb->ctrl.guest_asid % 8; 1925 1926 mutex_enter(&svm_asidlock); 1927 svm_asidmap[oct] &= ~__BIT(bit); 1928 mutex_exit(&svm_asidlock); 1929 } 1930 1931 static void 1932 svm_vcpu_init(struct nvmm_machine *mach, struct nvmm_cpu *vcpu) 1933 { 1934 struct svm_cpudata *cpudata = vcpu->cpudata; 1935 struct vmcb *vmcb = cpudata->vmcb; 1936 1937 /* Allow reads/writes of Control Registers. */ 1938 vmcb->ctrl.intercept_cr = 0; 1939 1940 /* Allow reads/writes of Debug Registers. */ 1941 vmcb->ctrl.intercept_dr = 0; 1942 1943 /* Allow exceptions 0 to 31. */ 1944 vmcb->ctrl.intercept_vec = 0; 1945 1946 /* 1947 * Allow: 1948 * - SMI [smm interrupts] 1949 * - VINTR [virtual interrupts] 1950 * - CR0_SPEC [CR0 writes changing other fields than CR0.TS or CR0.MP] 1951 * - RIDTR [reads of IDTR] 1952 * - RGDTR [reads of GDTR] 1953 * - RLDTR [reads of LDTR] 1954 * - RTR [reads of TR] 1955 * - WIDTR [writes of IDTR] 1956 * - WGDTR [writes of GDTR] 1957 * - WLDTR [writes of LDTR] 1958 * - WTR [writes of TR] 1959 * - RDTSC [rdtsc instruction] 1960 * - PUSHF [pushf instruction] 1961 * - POPF [popf instruction] 1962 * - IRET [iret instruction] 1963 * - INTN [int $n instructions] 1964 * - INVD [invd instruction] 1965 * - PAUSE [pause instruction] 1966 * - INVLPG [invplg instruction] 1967 * - TASKSW [task switches] 1968 * 1969 * Intercept the rest below. 1970 */ 1971 vmcb->ctrl.intercept_misc1 = 1972 VMCB_CTRL_INTERCEPT_INTR | 1973 VMCB_CTRL_INTERCEPT_NMI | 1974 VMCB_CTRL_INTERCEPT_INIT | 1975 VMCB_CTRL_INTERCEPT_RDPMC | 1976 VMCB_CTRL_INTERCEPT_CPUID | 1977 VMCB_CTRL_INTERCEPT_RSM | 1978 VMCB_CTRL_INTERCEPT_HLT | 1979 VMCB_CTRL_INTERCEPT_INVLPGA | 1980 VMCB_CTRL_INTERCEPT_IOIO_PROT | 1981 VMCB_CTRL_INTERCEPT_MSR_PROT | 1982 VMCB_CTRL_INTERCEPT_FERR_FREEZE | 1983 VMCB_CTRL_INTERCEPT_SHUTDOWN; 1984 1985 /* 1986 * Allow: 1987 * - ICEBP [icebp instruction] 1988 * - WBINVD [wbinvd instruction] 1989 * - WCR_SPEC(0..15) [writes of CR0-15, received after instruction] 1990 * 1991 * Intercept the rest below. 1992 */ 1993 vmcb->ctrl.intercept_misc2 = 1994 VMCB_CTRL_INTERCEPT_VMRUN | 1995 VMCB_CTRL_INTERCEPT_VMMCALL | 1996 VMCB_CTRL_INTERCEPT_VMLOAD | 1997 VMCB_CTRL_INTERCEPT_VMSAVE | 1998 VMCB_CTRL_INTERCEPT_STGI | 1999 VMCB_CTRL_INTERCEPT_CLGI | 2000 VMCB_CTRL_INTERCEPT_SKINIT | 2001 VMCB_CTRL_INTERCEPT_RDTSCP | 2002 VMCB_CTRL_INTERCEPT_MONITOR | 2003 VMCB_CTRL_INTERCEPT_MWAIT | 2004 VMCB_CTRL_INTERCEPT_XSETBV; 2005 2006 /* Intercept all I/O accesses. */ 2007 memset(cpudata->iobm, 0xFF, IOBM_SIZE); 2008 vmcb->ctrl.iopm_base_pa = cpudata->iobm_pa; 2009 2010 /* Allow direct access to certain MSRs. */ 2011 memset(cpudata->msrbm, 0xFF, MSRBM_SIZE); 2012 svm_vcpu_msr_allow(cpudata->msrbm, MSR_EFER, true, false); 2013 svm_vcpu_msr_allow(cpudata->msrbm, MSR_STAR, true, true); 2014 svm_vcpu_msr_allow(cpudata->msrbm, MSR_LSTAR, true, true); 2015 svm_vcpu_msr_allow(cpudata->msrbm, MSR_CSTAR, true, true); 2016 svm_vcpu_msr_allow(cpudata->msrbm, MSR_SFMASK, true, true); 2017 svm_vcpu_msr_allow(cpudata->msrbm, MSR_KERNELGSBASE, true, true); 2018 svm_vcpu_msr_allow(cpudata->msrbm, MSR_SYSENTER_CS, true, true); 2019 svm_vcpu_msr_allow(cpudata->msrbm, MSR_SYSENTER_ESP, true, true); 2020 svm_vcpu_msr_allow(cpudata->msrbm, MSR_SYSENTER_EIP, true, true); 2021 svm_vcpu_msr_allow(cpudata->msrbm, MSR_FSBASE, true, true); 2022 svm_vcpu_msr_allow(cpudata->msrbm, MSR_GSBASE, true, true); 2023 svm_vcpu_msr_allow(cpudata->msrbm, MSR_CR_PAT, true, true); 2024 svm_vcpu_msr_allow(cpudata->msrbm, MSR_TSC, true, false); 2025 vmcb->ctrl.msrpm_base_pa = cpudata->msrbm_pa; 2026 2027 /* Generate ASID. */ 2028 svm_asid_alloc(vcpu); 2029 2030 /* Virtual TPR. */ 2031 vmcb->ctrl.v = VMCB_CTRL_V_INTR_MASKING; 2032 2033 /* Enable Nested Paging. */ 2034 vmcb->ctrl.enable1 = VMCB_CTRL_ENABLE_NP; 2035 vmcb->ctrl.n_cr3 = mach->vm->vm_map.pmap->pm_pdirpa[0]; 2036 2037 /* Init XSAVE header. */ 2038 cpudata->gfpu.xsh_xstate_bv = svm_xcr0_mask; 2039 cpudata->gfpu.xsh_xcomp_bv = 0; 2040 2041 /* These MSRs are static. */ 2042 cpudata->star = rdmsr(MSR_STAR); 2043 cpudata->lstar = rdmsr(MSR_LSTAR); 2044 cpudata->cstar = rdmsr(MSR_CSTAR); 2045 cpudata->sfmask = rdmsr(MSR_SFMASK); 2046 2047 /* Install the RESET state. */ 2048 memcpy(&vcpu->comm->state, &nvmm_x86_reset_state, 2049 sizeof(nvmm_x86_reset_state)); 2050 vcpu->comm->state_wanted = NVMM_X64_STATE_ALL; 2051 vcpu->comm->state_cached = 0; 2052 svm_vcpu_setstate(vcpu); 2053 } 2054 2055 static int 2056 svm_vcpu_create(struct nvmm_machine *mach, struct nvmm_cpu *vcpu) 2057 { 2058 struct svm_cpudata *cpudata; 2059 int error; 2060 2061 /* Allocate the SVM cpudata. */ 2062 cpudata = (struct svm_cpudata *)uvm_km_alloc(kernel_map, 2063 roundup(sizeof(*cpudata), PAGE_SIZE), 0, 2064 UVM_KMF_WIRED|UVM_KMF_ZERO); 2065 vcpu->cpudata = cpudata; 2066 2067 /* VMCB */ 2068 error = svm_memalloc(&cpudata->vmcb_pa, (vaddr_t *)&cpudata->vmcb, 2069 VMCB_NPAGES); 2070 if (error) 2071 goto error; 2072 2073 /* I/O Bitmap */ 2074 error = svm_memalloc(&cpudata->iobm_pa, (vaddr_t *)&cpudata->iobm, 2075 IOBM_NPAGES); 2076 if (error) 2077 goto error; 2078 2079 /* MSR Bitmap */ 2080 error = svm_memalloc(&cpudata->msrbm_pa, (vaddr_t *)&cpudata->msrbm, 2081 MSRBM_NPAGES); 2082 if (error) 2083 goto error; 2084 2085 /* Init the VCPU info. */ 2086 svm_vcpu_init(mach, vcpu); 2087 2088 return 0; 2089 2090 error: 2091 if (cpudata->vmcb_pa) { 2092 svm_memfree(cpudata->vmcb_pa, (vaddr_t)cpudata->vmcb, 2093 VMCB_NPAGES); 2094 } 2095 if (cpudata->iobm_pa) { 2096 svm_memfree(cpudata->iobm_pa, (vaddr_t)cpudata->iobm, 2097 IOBM_NPAGES); 2098 } 2099 if (cpudata->msrbm_pa) { 2100 svm_memfree(cpudata->msrbm_pa, (vaddr_t)cpudata->msrbm, 2101 MSRBM_NPAGES); 2102 } 2103 uvm_km_free(kernel_map, (vaddr_t)cpudata, 2104 roundup(sizeof(*cpudata), PAGE_SIZE), UVM_KMF_WIRED); 2105 return error; 2106 } 2107 2108 static void 2109 svm_vcpu_destroy(struct nvmm_machine *mach, struct nvmm_cpu *vcpu) 2110 { 2111 struct svm_cpudata *cpudata = vcpu->cpudata; 2112 2113 svm_asid_free(vcpu); 2114 2115 svm_memfree(cpudata->vmcb_pa, (vaddr_t)cpudata->vmcb, VMCB_NPAGES); 2116 svm_memfree(cpudata->iobm_pa, (vaddr_t)cpudata->iobm, IOBM_NPAGES); 2117 svm_memfree(cpudata->msrbm_pa, (vaddr_t)cpudata->msrbm, MSRBM_NPAGES); 2118 2119 uvm_km_free(kernel_map, (vaddr_t)cpudata, 2120 roundup(sizeof(*cpudata), PAGE_SIZE), UVM_KMF_WIRED); 2121 } 2122 2123 /* -------------------------------------------------------------------------- */ 2124 2125 static void 2126 svm_tlb_flush(struct pmap *pm) 2127 { 2128 struct nvmm_machine *mach = pm->pm_data; 2129 struct svm_machdata *machdata = mach->machdata; 2130 2131 atomic_inc_64(&machdata->mach_htlb_gen); 2132 2133 /* Generates IPIs, which cause #VMEXITs. */ 2134 pmap_tlb_shootdown(pmap_kernel(), -1, PTE_G, TLBSHOOT_UPDATE); 2135 } 2136 2137 static void 2138 svm_machine_create(struct nvmm_machine *mach) 2139 { 2140 struct svm_machdata *machdata; 2141 2142 /* Fill in pmap info. */ 2143 mach->vm->vm_map.pmap->pm_data = (void *)mach; 2144 mach->vm->vm_map.pmap->pm_tlb_flush = svm_tlb_flush; 2145 2146 machdata = kmem_zalloc(sizeof(struct svm_machdata), KM_SLEEP); 2147 mach->machdata = machdata; 2148 2149 /* Start with an hTLB flush everywhere. */ 2150 machdata->mach_htlb_gen = 1; 2151 } 2152 2153 static void 2154 svm_machine_destroy(struct nvmm_machine *mach) 2155 { 2156 kmem_free(mach->machdata, sizeof(struct svm_machdata)); 2157 } 2158 2159 static int 2160 svm_machine_configure(struct nvmm_machine *mach, uint64_t op, void *data) 2161 { 2162 struct nvmm_mach_conf_x86_cpuid *cpuid = data; 2163 struct svm_machdata *machdata = (struct svm_machdata *)mach->machdata; 2164 size_t i; 2165 2166 if (__predict_false(op != NVMM_MACH_CONF_MD(NVMM_MACH_CONF_X86_CPUID))) { 2167 return EINVAL; 2168 } 2169 2170 if (__predict_false((cpuid->set.eax & cpuid->del.eax) || 2171 (cpuid->set.ebx & cpuid->del.ebx) || 2172 (cpuid->set.ecx & cpuid->del.ecx) || 2173 (cpuid->set.edx & cpuid->del.edx))) { 2174 return EINVAL; 2175 } 2176 2177 /* If already here, replace. */ 2178 for (i = 0; i < SVM_NCPUIDS; i++) { 2179 if (!machdata->cpuidpresent[i]) { 2180 continue; 2181 } 2182 if (machdata->cpuid[i].leaf == cpuid->leaf) { 2183 memcpy(&machdata->cpuid[i], cpuid, 2184 sizeof(struct nvmm_mach_conf_x86_cpuid)); 2185 return 0; 2186 } 2187 } 2188 2189 /* Not here, insert. */ 2190 for (i = 0; i < SVM_NCPUIDS; i++) { 2191 if (!machdata->cpuidpresent[i]) { 2192 machdata->cpuidpresent[i] = true; 2193 memcpy(&machdata->cpuid[i], cpuid, 2194 sizeof(struct nvmm_mach_conf_x86_cpuid)); 2195 return 0; 2196 } 2197 } 2198 2199 return ENOBUFS; 2200 } 2201 2202 /* -------------------------------------------------------------------------- */ 2203 2204 static bool 2205 svm_ident(void) 2206 { 2207 u_int descs[4]; 2208 uint64_t msr; 2209 2210 if (cpu_vendor != CPUVENDOR_AMD) { 2211 return false; 2212 } 2213 if (!(cpu_feature[3] & CPUID_SVM)) { 2214 return false; 2215 } 2216 2217 if (curcpu()->ci_max_ext_cpuid < 0x8000000a) { 2218 return false; 2219 } 2220 x86_cpuid(0x8000000a, descs); 2221 2222 /* Want Nested Paging. */ 2223 if (!(descs[3] & CPUID_AMD_SVM_NP)) { 2224 return false; 2225 } 2226 2227 /* Want nRIP. */ 2228 if (!(descs[3] & CPUID_AMD_SVM_NRIPS)) { 2229 return false; 2230 } 2231 2232 svm_decode_assist = (descs[3] & CPUID_AMD_SVM_DecodeAssist) != 0; 2233 2234 msr = rdmsr(MSR_VMCR); 2235 if ((msr & VMCR_SVMED) && (msr & VMCR_LOCK)) { 2236 return false; 2237 } 2238 2239 return true; 2240 } 2241 2242 static void 2243 svm_init_asid(uint32_t maxasid) 2244 { 2245 size_t i, j, allocsz; 2246 2247 mutex_init(&svm_asidlock, MUTEX_DEFAULT, IPL_NONE); 2248 2249 /* Arbitrarily limit. */ 2250 maxasid = uimin(maxasid, 8192); 2251 2252 svm_maxasid = maxasid; 2253 allocsz = roundup(maxasid, 8) / 8; 2254 svm_asidmap = kmem_zalloc(allocsz, KM_SLEEP); 2255 2256 /* ASID 0 is reserved for the host. */ 2257 svm_asidmap[0] |= __BIT(0); 2258 2259 /* ASID n-1 is special, we share it. */ 2260 i = (maxasid - 1) / 8; 2261 j = (maxasid - 1) % 8; 2262 svm_asidmap[i] |= __BIT(j); 2263 } 2264 2265 static void 2266 svm_change_cpu(void *arg1, void *arg2) 2267 { 2268 bool enable = (bool)arg1; 2269 uint64_t msr; 2270 2271 msr = rdmsr(MSR_VMCR); 2272 if (msr & VMCR_SVMED) { 2273 wrmsr(MSR_VMCR, msr & ~VMCR_SVMED); 2274 } 2275 2276 if (!enable) { 2277 wrmsr(MSR_VM_HSAVE_PA, 0); 2278 } 2279 2280 msr = rdmsr(MSR_EFER); 2281 if (enable) { 2282 msr |= EFER_SVME; 2283 } else { 2284 msr &= ~EFER_SVME; 2285 } 2286 wrmsr(MSR_EFER, msr); 2287 2288 if (enable) { 2289 wrmsr(MSR_VM_HSAVE_PA, hsave[cpu_index(curcpu())].pa); 2290 } 2291 } 2292 2293 static void 2294 svm_init(void) 2295 { 2296 CPU_INFO_ITERATOR cii; 2297 struct cpu_info *ci; 2298 struct vm_page *pg; 2299 u_int descs[4]; 2300 uint64_t xc; 2301 2302 x86_cpuid(0x8000000a, descs); 2303 2304 /* The guest TLB flush command. */ 2305 if (descs[3] & CPUID_AMD_SVM_FlushByASID) { 2306 svm_ctrl_tlb_flush = VMCB_CTRL_TLB_CTRL_FLUSH_GUEST; 2307 } else { 2308 svm_ctrl_tlb_flush = VMCB_CTRL_TLB_CTRL_FLUSH_ALL; 2309 } 2310 2311 /* Init the ASID. */ 2312 svm_init_asid(descs[1]); 2313 2314 /* Init the XCR0 mask. */ 2315 svm_xcr0_mask = SVM_XCR0_MASK_DEFAULT & x86_xsave_features; 2316 2317 memset(hsave, 0, sizeof(hsave)); 2318 for (CPU_INFO_FOREACH(cii, ci)) { 2319 pg = uvm_pagealloc(NULL, 0, NULL, UVM_PGA_ZERO); 2320 hsave[cpu_index(ci)].pa = VM_PAGE_TO_PHYS(pg); 2321 } 2322 2323 xc = xc_broadcast(0, svm_change_cpu, (void *)true, NULL); 2324 xc_wait(xc); 2325 } 2326 2327 static void 2328 svm_fini_asid(void) 2329 { 2330 size_t allocsz; 2331 2332 allocsz = roundup(svm_maxasid, 8) / 8; 2333 kmem_free(svm_asidmap, allocsz); 2334 2335 mutex_destroy(&svm_asidlock); 2336 } 2337 2338 static void 2339 svm_fini(void) 2340 { 2341 uint64_t xc; 2342 size_t i; 2343 2344 xc = xc_broadcast(0, svm_change_cpu, (void *)false, NULL); 2345 xc_wait(xc); 2346 2347 for (i = 0; i < MAXCPUS; i++) { 2348 if (hsave[i].pa != 0) 2349 uvm_pagefree(PHYS_TO_VM_PAGE(hsave[i].pa)); 2350 } 2351 2352 svm_fini_asid(); 2353 } 2354 2355 static void 2356 svm_capability(struct nvmm_capability *cap) 2357 { 2358 cap->arch.xcr0_mask = svm_xcr0_mask; 2359 cap->arch.mxcsr_mask = x86_fpu_mxcsr_mask; 2360 cap->arch.conf_cpuid_maxops = SVM_NCPUIDS; 2361 } 2362 2363 const struct nvmm_impl nvmm_x86_svm = { 2364 .ident = svm_ident, 2365 .init = svm_init, 2366 .fini = svm_fini, 2367 .capability = svm_capability, 2368 .conf_max = NVMM_X86_NCONF, 2369 .conf_sizes = svm_conf_sizes, 2370 .state_size = sizeof(struct nvmm_x64_state), 2371 .machine_create = svm_machine_create, 2372 .machine_destroy = svm_machine_destroy, 2373 .machine_configure = svm_machine_configure, 2374 .vcpu_create = svm_vcpu_create, 2375 .vcpu_destroy = svm_vcpu_destroy, 2376 .vcpu_setstate = svm_vcpu_setstate, 2377 .vcpu_getstate = svm_vcpu_getstate, 2378 .vcpu_inject = svm_vcpu_inject, 2379 .vcpu_run = svm_vcpu_run 2380 }; 2381
Indexes created Tue Sep 30 20:09:53 GMT 2025