nvmm_x86_svm.c revision 1.50
1 /* $NetBSD: nvmm_x86_svm.c,v 1.50 2019/10/12 06:31:04 maxv Exp $ */ 2 3 /* 4 * Copyright (c) 2018 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Maxime Villard. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: nvmm_x86_svm.c,v 1.50 2019/10/12 06:31:04 maxv Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/kmem.h> 39 #include <sys/cpu.h> 40 #include <sys/xcall.h> 41 #include <sys/mman.h> 42 43 #include <uvm/uvm.h> 44 #include <uvm/uvm_page.h> 45 46 #include <x86/cputypes.h> 47 #include <x86/specialreg.h> 48 #include <x86/pmap.h> 49 #include <x86/dbregs.h> 50 #include <x86/cpu_counter.h> 51 #include <machine/cpuvar.h> 52 53 #include <dev/nvmm/nvmm.h> 54 #include <dev/nvmm/nvmm_internal.h> 55 #include <dev/nvmm/x86/nvmm_x86.h> 56 57 int svm_vmrun(paddr_t, uint64_t *); 58 59 #define MSR_VM_HSAVE_PA 0xC0010117 60 61 /* -------------------------------------------------------------------------- */ 62 63 #define VMCB_EXITCODE_CR0_READ 0x0000 64 #define VMCB_EXITCODE_CR1_READ 0x0001 65 #define VMCB_EXITCODE_CR2_READ 0x0002 66 #define VMCB_EXITCODE_CR3_READ 0x0003 67 #define VMCB_EXITCODE_CR4_READ 0x0004 68 #define VMCB_EXITCODE_CR5_READ 0x0005 69 #define VMCB_EXITCODE_CR6_READ 0x0006 70 #define VMCB_EXITCODE_CR7_READ 0x0007 71 #define VMCB_EXITCODE_CR8_READ 0x0008 72 #define VMCB_EXITCODE_CR9_READ 0x0009 73 #define VMCB_EXITCODE_CR10_READ 0x000A 74 #define VMCB_EXITCODE_CR11_READ 0x000B 75 #define VMCB_EXITCODE_CR12_READ 0x000C 76 #define VMCB_EXITCODE_CR13_READ 0x000D 77 #define VMCB_EXITCODE_CR14_READ 0x000E 78 #define VMCB_EXITCODE_CR15_READ 0x000F 79 #define VMCB_EXITCODE_CR0_WRITE 0x0010 80 #define VMCB_EXITCODE_CR1_WRITE 0x0011 81 #define VMCB_EXITCODE_CR2_WRITE 0x0012 82 #define VMCB_EXITCODE_CR3_WRITE 0x0013 83 #define VMCB_EXITCODE_CR4_WRITE 0x0014 84 #define VMCB_EXITCODE_CR5_WRITE 0x0015 85 #define VMCB_EXITCODE_CR6_WRITE 0x0016 86 #define VMCB_EXITCODE_CR7_WRITE 0x0017 87 #define VMCB_EXITCODE_CR8_WRITE 0x0018 88 #define VMCB_EXITCODE_CR9_WRITE 0x0019 89 #define VMCB_EXITCODE_CR10_WRITE 0x001A 90 #define VMCB_EXITCODE_CR11_WRITE 0x001B 91 #define VMCB_EXITCODE_CR12_WRITE 0x001C 92 #define VMCB_EXITCODE_CR13_WRITE 0x001D 93 #define VMCB_EXITCODE_CR14_WRITE 0x001E 94 #define VMCB_EXITCODE_CR15_WRITE 0x001F 95 #define VMCB_EXITCODE_DR0_READ 0x0020 96 #define VMCB_EXITCODE_DR1_READ 0x0021 97 #define VMCB_EXITCODE_DR2_READ 0x0022 98 #define VMCB_EXITCODE_DR3_READ 0x0023 99 #define VMCB_EXITCODE_DR4_READ 0x0024 100 #define VMCB_EXITCODE_DR5_READ 0x0025 101 #define VMCB_EXITCODE_DR6_READ 0x0026 102 #define VMCB_EXITCODE_DR7_READ 0x0027 103 #define VMCB_EXITCODE_DR8_READ 0x0028 104 #define VMCB_EXITCODE_DR9_READ 0x0029 105 #define VMCB_EXITCODE_DR10_READ 0x002A 106 #define VMCB_EXITCODE_DR11_READ 0x002B 107 #define VMCB_EXITCODE_DR12_READ 0x002C 108 #define VMCB_EXITCODE_DR13_READ 0x002D 109 #define VMCB_EXITCODE_DR14_READ 0x002E 110 #define VMCB_EXITCODE_DR15_READ 0x002F 111 #define VMCB_EXITCODE_DR0_WRITE 0x0030 112 #define VMCB_EXITCODE_DR1_WRITE 0x0031 113 #define VMCB_EXITCODE_DR2_WRITE 0x0032 114 #define VMCB_EXITCODE_DR3_WRITE 0x0033 115 #define VMCB_EXITCODE_DR4_WRITE 0x0034 116 #define VMCB_EXITCODE_DR5_WRITE 0x0035 117 #define VMCB_EXITCODE_DR6_WRITE 0x0036 118 #define VMCB_EXITCODE_DR7_WRITE 0x0037 119 #define VMCB_EXITCODE_DR8_WRITE 0x0038 120 #define VMCB_EXITCODE_DR9_WRITE 0x0039 121 #define VMCB_EXITCODE_DR10_WRITE 0x003A 122 #define VMCB_EXITCODE_DR11_WRITE 0x003B 123 #define VMCB_EXITCODE_DR12_WRITE 0x003C 124 #define VMCB_EXITCODE_DR13_WRITE 0x003D 125 #define VMCB_EXITCODE_DR14_WRITE 0x003E 126 #define VMCB_EXITCODE_DR15_WRITE 0x003F 127 #define VMCB_EXITCODE_EXCP0 0x0040 128 #define VMCB_EXITCODE_EXCP1 0x0041 129 #define VMCB_EXITCODE_EXCP2 0x0042 130 #define VMCB_EXITCODE_EXCP3 0x0043 131 #define VMCB_EXITCODE_EXCP4 0x0044 132 #define VMCB_EXITCODE_EXCP5 0x0045 133 #define VMCB_EXITCODE_EXCP6 0x0046 134 #define VMCB_EXITCODE_EXCP7 0x0047 135 #define VMCB_EXITCODE_EXCP8 0x0048 136 #define VMCB_EXITCODE_EXCP9 0x0049 137 #define VMCB_EXITCODE_EXCP10 0x004A 138 #define VMCB_EXITCODE_EXCP11 0x004B 139 #define VMCB_EXITCODE_EXCP12 0x004C 140 #define VMCB_EXITCODE_EXCP13 0x004D 141 #define VMCB_EXITCODE_EXCP14 0x004E 142 #define VMCB_EXITCODE_EXCP15 0x004F 143 #define VMCB_EXITCODE_EXCP16 0x0050 144 #define VMCB_EXITCODE_EXCP17 0x0051 145 #define VMCB_EXITCODE_EXCP18 0x0052 146 #define VMCB_EXITCODE_EXCP19 0x0053 147 #define VMCB_EXITCODE_EXCP20 0x0054 148 #define VMCB_EXITCODE_EXCP21 0x0055 149 #define VMCB_EXITCODE_EXCP22 0x0056 150 #define VMCB_EXITCODE_EXCP23 0x0057 151 #define VMCB_EXITCODE_EXCP24 0x0058 152 #define VMCB_EXITCODE_EXCP25 0x0059 153 #define VMCB_EXITCODE_EXCP26 0x005A 154 #define VMCB_EXITCODE_EXCP27 0x005B 155 #define VMCB_EXITCODE_EXCP28 0x005C 156 #define VMCB_EXITCODE_EXCP29 0x005D 157 #define VMCB_EXITCODE_EXCP30 0x005E 158 #define VMCB_EXITCODE_EXCP31 0x005F 159 #define VMCB_EXITCODE_INTR 0x0060 160 #define VMCB_EXITCODE_NMI 0x0061 161 #define VMCB_EXITCODE_SMI 0x0062 162 #define VMCB_EXITCODE_INIT 0x0063 163 #define VMCB_EXITCODE_VINTR 0x0064 164 #define VMCB_EXITCODE_CR0_SEL_WRITE 0x0065 165 #define VMCB_EXITCODE_IDTR_READ 0x0066 166 #define VMCB_EXITCODE_GDTR_READ 0x0067 167 #define VMCB_EXITCODE_LDTR_READ 0x0068 168 #define VMCB_EXITCODE_TR_READ 0x0069 169 #define VMCB_EXITCODE_IDTR_WRITE 0x006A 170 #define VMCB_EXITCODE_GDTR_WRITE 0x006B 171 #define VMCB_EXITCODE_LDTR_WRITE 0x006C 172 #define VMCB_EXITCODE_TR_WRITE 0x006D 173 #define VMCB_EXITCODE_RDTSC 0x006E 174 #define VMCB_EXITCODE_RDPMC 0x006F 175 #define VMCB_EXITCODE_PUSHF 0x0070 176 #define VMCB_EXITCODE_POPF 0x0071 177 #define VMCB_EXITCODE_CPUID 0x0072 178 #define VMCB_EXITCODE_RSM 0x0073 179 #define VMCB_EXITCODE_IRET 0x0074 180 #define VMCB_EXITCODE_SWINT 0x0075 181 #define VMCB_EXITCODE_INVD 0x0076 182 #define VMCB_EXITCODE_PAUSE 0x0077 183 #define VMCB_EXITCODE_HLT 0x0078 184 #define VMCB_EXITCODE_INVLPG 0x0079 185 #define VMCB_EXITCODE_INVLPGA 0x007A 186 #define VMCB_EXITCODE_IOIO 0x007B 187 #define VMCB_EXITCODE_MSR 0x007C 188 #define VMCB_EXITCODE_TASK_SWITCH 0x007D 189 #define VMCB_EXITCODE_FERR_FREEZE 0x007E 190 #define VMCB_EXITCODE_SHUTDOWN 0x007F 191 #define VMCB_EXITCODE_VMRUN 0x0080 192 #define VMCB_EXITCODE_VMMCALL 0x0081 193 #define VMCB_EXITCODE_VMLOAD 0x0082 194 #define VMCB_EXITCODE_VMSAVE 0x0083 195 #define VMCB_EXITCODE_STGI 0x0084 196 #define VMCB_EXITCODE_CLGI 0x0085 197 #define VMCB_EXITCODE_SKINIT 0x0086 198 #define VMCB_EXITCODE_RDTSCP 0x0087 199 #define VMCB_EXITCODE_ICEBP 0x0088 200 #define VMCB_EXITCODE_WBINVD 0x0089 201 #define VMCB_EXITCODE_MONITOR 0x008A 202 #define VMCB_EXITCODE_MWAIT 0x008B 203 #define VMCB_EXITCODE_MWAIT_CONDITIONAL 0x008C 204 #define VMCB_EXITCODE_XSETBV 0x008D 205 #define VMCB_EXITCODE_RDPRU 0x008E 206 #define VMCB_EXITCODE_EFER_WRITE_TRAP 0x008F 207 #define VMCB_EXITCODE_CR0_WRITE_TRAP 0x0090 208 #define VMCB_EXITCODE_CR1_WRITE_TRAP 0x0091 209 #define VMCB_EXITCODE_CR2_WRITE_TRAP 0x0092 210 #define VMCB_EXITCODE_CR3_WRITE_TRAP 0x0093 211 #define VMCB_EXITCODE_CR4_WRITE_TRAP 0x0094 212 #define VMCB_EXITCODE_CR5_WRITE_TRAP 0x0095 213 #define VMCB_EXITCODE_CR6_WRITE_TRAP 0x0096 214 #define VMCB_EXITCODE_CR7_WRITE_TRAP 0x0097 215 #define VMCB_EXITCODE_CR8_WRITE_TRAP 0x0098 216 #define VMCB_EXITCODE_CR9_WRITE_TRAP 0x0099 217 #define VMCB_EXITCODE_CR10_WRITE_TRAP 0x009A 218 #define VMCB_EXITCODE_CR11_WRITE_TRAP 0x009B 219 #define VMCB_EXITCODE_CR12_WRITE_TRAP 0x009C 220 #define VMCB_EXITCODE_CR13_WRITE_TRAP 0x009D 221 #define VMCB_EXITCODE_CR14_WRITE_TRAP 0x009E 222 #define VMCB_EXITCODE_CR15_WRITE_TRAP 0x009F 223 #define VMCB_EXITCODE_MCOMMIT 0x00A3 224 #define VMCB_EXITCODE_NPF 0x0400 225 #define VMCB_EXITCODE_AVIC_INCOMP_IPI 0x0401 226 #define VMCB_EXITCODE_AVIC_NOACCEL 0x0402 227 #define VMCB_EXITCODE_VMGEXIT 0x0403 228 #define VMCB_EXITCODE_INVALID -1 229 230 /* -------------------------------------------------------------------------- */ 231 232 struct vmcb_ctrl { 233 uint32_t intercept_cr; 234 #define VMCB_CTRL_INTERCEPT_RCR(x) __BIT( 0 + x) 235 #define VMCB_CTRL_INTERCEPT_WCR(x) __BIT(16 + x) 236 237 uint32_t intercept_dr; 238 #define VMCB_CTRL_INTERCEPT_RDR(x) __BIT( 0 + x) 239 #define VMCB_CTRL_INTERCEPT_WDR(x) __BIT(16 + x) 240 241 uint32_t intercept_vec; 242 #define VMCB_CTRL_INTERCEPT_VEC(x) __BIT(x) 243 244 uint32_t intercept_misc1; 245 #define VMCB_CTRL_INTERCEPT_INTR __BIT(0) 246 #define VMCB_CTRL_INTERCEPT_NMI __BIT(1) 247 #define VMCB_CTRL_INTERCEPT_SMI __BIT(2) 248 #define VMCB_CTRL_INTERCEPT_INIT __BIT(3) 249 #define VMCB_CTRL_INTERCEPT_VINTR __BIT(4) 250 #define VMCB_CTRL_INTERCEPT_CR0_SPEC __BIT(5) 251 #define VMCB_CTRL_INTERCEPT_RIDTR __BIT(6) 252 #define VMCB_CTRL_INTERCEPT_RGDTR __BIT(7) 253 #define VMCB_CTRL_INTERCEPT_RLDTR __BIT(8) 254 #define VMCB_CTRL_INTERCEPT_RTR __BIT(9) 255 #define VMCB_CTRL_INTERCEPT_WIDTR __BIT(10) 256 #define VMCB_CTRL_INTERCEPT_WGDTR __BIT(11) 257 #define VMCB_CTRL_INTERCEPT_WLDTR __BIT(12) 258 #define VMCB_CTRL_INTERCEPT_WTR __BIT(13) 259 #define VMCB_CTRL_INTERCEPT_RDTSC __BIT(14) 260 #define VMCB_CTRL_INTERCEPT_RDPMC __BIT(15) 261 #define VMCB_CTRL_INTERCEPT_PUSHF __BIT(16) 262 #define VMCB_CTRL_INTERCEPT_POPF __BIT(17) 263 #define VMCB_CTRL_INTERCEPT_CPUID __BIT(18) 264 #define VMCB_CTRL_INTERCEPT_RSM __BIT(19) 265 #define VMCB_CTRL_INTERCEPT_IRET __BIT(20) 266 #define VMCB_CTRL_INTERCEPT_INTN __BIT(21) 267 #define VMCB_CTRL_INTERCEPT_INVD __BIT(22) 268 #define VMCB_CTRL_INTERCEPT_PAUSE __BIT(23) 269 #define VMCB_CTRL_INTERCEPT_HLT __BIT(24) 270 #define VMCB_CTRL_INTERCEPT_INVLPG __BIT(25) 271 #define VMCB_CTRL_INTERCEPT_INVLPGA __BIT(26) 272 #define VMCB_CTRL_INTERCEPT_IOIO_PROT __BIT(27) 273 #define VMCB_CTRL_INTERCEPT_MSR_PROT __BIT(28) 274 #define VMCB_CTRL_INTERCEPT_TASKSW __BIT(29) 275 #define VMCB_CTRL_INTERCEPT_FERR_FREEZE __BIT(30) 276 #define VMCB_CTRL_INTERCEPT_SHUTDOWN __BIT(31) 277 278 uint32_t intercept_misc2; 279 #define VMCB_CTRL_INTERCEPT_VMRUN __BIT(0) 280 #define VMCB_CTRL_INTERCEPT_VMMCALL __BIT(1) 281 #define VMCB_CTRL_INTERCEPT_VMLOAD __BIT(2) 282 #define VMCB_CTRL_INTERCEPT_VMSAVE __BIT(3) 283 #define VMCB_CTRL_INTERCEPT_STGI __BIT(4) 284 #define VMCB_CTRL_INTERCEPT_CLGI __BIT(5) 285 #define VMCB_CTRL_INTERCEPT_SKINIT __BIT(6) 286 #define VMCB_CTRL_INTERCEPT_RDTSCP __BIT(7) 287 #define VMCB_CTRL_INTERCEPT_ICEBP __BIT(8) 288 #define VMCB_CTRL_INTERCEPT_WBINVD __BIT(9) 289 #define VMCB_CTRL_INTERCEPT_MONITOR __BIT(10) 290 #define VMCB_CTRL_INTERCEPT_MWAIT __BIT(11) 291 #define VMCB_CTRL_INTERCEPT_MWAIT_ARMED __BIT(12) 292 #define VMCB_CTRL_INTERCEPT_XSETBV __BIT(13) 293 #define VMCB_CTRL_INTERCEPT_RDPRU __BIT(14) 294 #define VMCB_CTRL_INTERCEPT_EFER_SPEC __BIT(15) 295 #define VMCB_CTRL_INTERCEPT_WCR_SPEC(x) __BIT(16 + x) 296 297 uint32_t intercept_misc3; 298 #define VMCB_CTRL_INTERCEPT_MCOMMIT __BIT(3) 299 300 uint8_t rsvd1[36]; 301 uint16_t pause_filt_thresh; 302 uint16_t pause_filt_cnt; 303 uint64_t iopm_base_pa; 304 uint64_t msrpm_base_pa; 305 uint64_t tsc_offset; 306 uint32_t guest_asid; 307 308 uint32_t tlb_ctrl; 309 #define VMCB_CTRL_TLB_CTRL_FLUSH_ALL 0x01 310 #define VMCB_CTRL_TLB_CTRL_FLUSH_GUEST 0x03 311 #define VMCB_CTRL_TLB_CTRL_FLUSH_GUEST_NONGLOBAL 0x07 312 313 uint64_t v; 314 #define VMCB_CTRL_V_TPR __BITS(3,0) 315 #define VMCB_CTRL_V_IRQ __BIT(8) 316 #define VMCB_CTRL_V_VGIF __BIT(9) 317 #define VMCB_CTRL_V_INTR_PRIO __BITS(19,16) 318 #define VMCB_CTRL_V_IGN_TPR __BIT(20) 319 #define VMCB_CTRL_V_INTR_MASKING __BIT(24) 320 #define VMCB_CTRL_V_GUEST_VGIF __BIT(25) 321 #define VMCB_CTRL_V_AVIC_EN __BIT(31) 322 #define VMCB_CTRL_V_INTR_VECTOR __BITS(39,32) 323 324 uint64_t intr; 325 #define VMCB_CTRL_INTR_SHADOW __BIT(0) 326 327 uint64_t exitcode; 328 uint64_t exitinfo1; 329 uint64_t exitinfo2; 330 331 uint64_t exitintinfo; 332 #define VMCB_CTRL_EXITINTINFO_VECTOR __BITS(7,0) 333 #define VMCB_CTRL_EXITINTINFO_TYPE __BITS(10,8) 334 #define VMCB_CTRL_EXITINTINFO_EV __BIT(11) 335 #define VMCB_CTRL_EXITINTINFO_V __BIT(31) 336 #define VMCB_CTRL_EXITINTINFO_ERRORCODE __BITS(63,32) 337 338 uint64_t enable1; 339 #define VMCB_CTRL_ENABLE_NP __BIT(0) 340 #define VMCB_CTRL_ENABLE_SEV __BIT(1) 341 #define VMCB_CTRL_ENABLE_ES_SEV __BIT(2) 342 #define VMCB_CTRL_ENABLE_GMET __BIT(3) 343 #define VMCB_CTRL_ENABLE_VTE __BIT(5) 344 345 uint64_t avic; 346 #define VMCB_CTRL_AVIC_APIC_BAR __BITS(51,0) 347 348 uint64_t ghcb; 349 350 uint64_t eventinj; 351 #define VMCB_CTRL_EVENTINJ_VECTOR __BITS(7,0) 352 #define VMCB_CTRL_EVENTINJ_TYPE __BITS(10,8) 353 #define VMCB_CTRL_EVENTINJ_EV __BIT(11) 354 #define VMCB_CTRL_EVENTINJ_V __BIT(31) 355 #define VMCB_CTRL_EVENTINJ_ERRORCODE __BITS(63,32) 356 357 uint64_t n_cr3; 358 359 uint64_t enable2; 360 #define VMCB_CTRL_ENABLE_LBR __BIT(0) 361 #define VMCB_CTRL_ENABLE_VVMSAVE __BIT(1) 362 363 uint32_t vmcb_clean; 364 #define VMCB_CTRL_VMCB_CLEAN_I __BIT(0) 365 #define VMCB_CTRL_VMCB_CLEAN_IOPM __BIT(1) 366 #define VMCB_CTRL_VMCB_CLEAN_ASID __BIT(2) 367 #define VMCB_CTRL_VMCB_CLEAN_TPR __BIT(3) 368 #define VMCB_CTRL_VMCB_CLEAN_NP __BIT(4) 369 #define VMCB_CTRL_VMCB_CLEAN_CR __BIT(5) 370 #define VMCB_CTRL_VMCB_CLEAN_DR __BIT(6) 371 #define VMCB_CTRL_VMCB_CLEAN_DT __BIT(7) 372 #define VMCB_CTRL_VMCB_CLEAN_SEG __BIT(8) 373 #define VMCB_CTRL_VMCB_CLEAN_CR2 __BIT(9) 374 #define VMCB_CTRL_VMCB_CLEAN_LBR __BIT(10) 375 #define VMCB_CTRL_VMCB_CLEAN_AVIC __BIT(11) 376 377 uint32_t rsvd2; 378 uint64_t nrip; 379 uint8_t inst_len; 380 uint8_t inst_bytes[15]; 381 uint64_t avic_abpp; 382 uint64_t rsvd3; 383 uint64_t avic_ltp; 384 385 uint64_t avic_phys; 386 #define VMCB_CTRL_AVIC_PHYS_TABLE_PTR __BITS(51,12) 387 #define VMCB_CTRL_AVIC_PHYS_MAX_INDEX __BITS(7,0) 388 389 uint64_t rsvd4; 390 uint64_t vmcb_ptr; 391 392 uint8_t pad[752]; 393 } __packed; 394 395 CTASSERT(sizeof(struct vmcb_ctrl) == 1024); 396 397 struct vmcb_segment { 398 uint16_t selector; 399 uint16_t attrib; /* hidden */ 400 uint32_t limit; /* hidden */ 401 uint64_t base; /* hidden */ 402 } __packed; 403 404 CTASSERT(sizeof(struct vmcb_segment) == 16); 405 406 struct vmcb_state { 407 struct vmcb_segment es; 408 struct vmcb_segment cs; 409 struct vmcb_segment ss; 410 struct vmcb_segment ds; 411 struct vmcb_segment fs; 412 struct vmcb_segment gs; 413 struct vmcb_segment gdt; 414 struct vmcb_segment ldt; 415 struct vmcb_segment idt; 416 struct vmcb_segment tr; 417 uint8_t rsvd1[43]; 418 uint8_t cpl; 419 uint8_t rsvd2[4]; 420 uint64_t efer; 421 uint8_t rsvd3[112]; 422 uint64_t cr4; 423 uint64_t cr3; 424 uint64_t cr0; 425 uint64_t dr7; 426 uint64_t dr6; 427 uint64_t rflags; 428 uint64_t rip; 429 uint8_t rsvd4[88]; 430 uint64_t rsp; 431 uint8_t rsvd5[24]; 432 uint64_t rax; 433 uint64_t star; 434 uint64_t lstar; 435 uint64_t cstar; 436 uint64_t sfmask; 437 uint64_t kernelgsbase; 438 uint64_t sysenter_cs; 439 uint64_t sysenter_esp; 440 uint64_t sysenter_eip; 441 uint64_t cr2; 442 uint8_t rsvd6[32]; 443 uint64_t g_pat; 444 uint64_t dbgctl; 445 uint64_t br_from; 446 uint64_t br_to; 447 uint64_t int_from; 448 uint64_t int_to; 449 uint8_t pad[2408]; 450 } __packed; 451 452 CTASSERT(sizeof(struct vmcb_state) == 0xC00); 453 454 struct vmcb { 455 struct vmcb_ctrl ctrl; 456 struct vmcb_state state; 457 } __packed; 458 459 CTASSERT(sizeof(struct vmcb) == PAGE_SIZE); 460 CTASSERT(offsetof(struct vmcb, state) == 0x400); 461 462 /* -------------------------------------------------------------------------- */ 463 464 static void svm_vcpu_state_provide(struct nvmm_cpu *, uint64_t); 465 static void svm_vcpu_state_commit(struct nvmm_cpu *); 466 467 struct svm_hsave { 468 paddr_t pa; 469 }; 470 471 static struct svm_hsave hsave[MAXCPUS]; 472 473 static uint8_t *svm_asidmap __read_mostly; 474 static uint32_t svm_maxasid __read_mostly; 475 static kmutex_t svm_asidlock __cacheline_aligned; 476 477 static bool svm_decode_assist __read_mostly; 478 static uint32_t svm_ctrl_tlb_flush __read_mostly; 479 480 #define SVM_XCR0_MASK_DEFAULT (XCR0_X87|XCR0_SSE) 481 static uint64_t svm_xcr0_mask __read_mostly; 482 483 #define SVM_NCPUIDS 32 484 485 #define VMCB_NPAGES 1 486 487 #define MSRBM_NPAGES 2 488 #define MSRBM_SIZE (MSRBM_NPAGES * PAGE_SIZE) 489 490 #define IOBM_NPAGES 3 491 #define IOBM_SIZE (IOBM_NPAGES * PAGE_SIZE) 492 493 /* Does not include EFER_LMSLE. */ 494 #define EFER_VALID \ 495 (EFER_SCE|EFER_LME|EFER_LMA|EFER_NXE|EFER_SVME|EFER_FFXSR|EFER_TCE) 496 497 #define EFER_TLB_FLUSH \ 498 (EFER_NXE|EFER_LMA|EFER_LME) 499 #define CR0_TLB_FLUSH \ 500 (CR0_PG|CR0_WP|CR0_CD|CR0_NW) 501 #define CR4_TLB_FLUSH \ 502 (CR4_PGE|CR4_PAE|CR4_PSE) 503 504 /* -------------------------------------------------------------------------- */ 505 506 struct svm_machdata { 507 bool cpuidpresent[SVM_NCPUIDS]; 508 struct nvmm_mach_conf_x86_cpuid cpuid[SVM_NCPUIDS]; 509 volatile uint64_t mach_htlb_gen; 510 }; 511 512 static const size_t svm_conf_sizes[NVMM_X86_NCONF] = { 513 [NVMM_MACH_CONF_MD(NVMM_MACH_CONF_X86_CPUID)] = 514 sizeof(struct nvmm_mach_conf_x86_cpuid) 515 }; 516 517 struct svm_cpudata { 518 /* General */ 519 bool shared_asid; 520 bool gtlb_want_flush; 521 bool gtsc_want_update; 522 uint64_t vcpu_htlb_gen; 523 524 /* VMCB */ 525 struct vmcb *vmcb; 526 paddr_t vmcb_pa; 527 528 /* I/O bitmap */ 529 uint8_t *iobm; 530 paddr_t iobm_pa; 531 532 /* MSR bitmap */ 533 uint8_t *msrbm; 534 paddr_t msrbm_pa; 535 536 /* Host state */ 537 uint64_t hxcr0; 538 uint64_t star; 539 uint64_t lstar; 540 uint64_t cstar; 541 uint64_t sfmask; 542 uint64_t fsbase; 543 uint64_t kernelgsbase; 544 545 /* Intr state */ 546 bool int_window_exit; 547 bool nmi_window_exit; 548 bool evt_pending; 549 550 /* Guest state */ 551 uint64_t gxcr0; 552 uint64_t gprs[NVMM_X64_NGPR]; 553 uint64_t drs[NVMM_X64_NDR]; 554 uint64_t gtsc; 555 struct xsave_header gfpu __aligned(64); 556 }; 557 558 static void 559 svm_vmcb_cache_default(struct vmcb *vmcb) 560 { 561 vmcb->ctrl.vmcb_clean = 562 VMCB_CTRL_VMCB_CLEAN_I | 563 VMCB_CTRL_VMCB_CLEAN_IOPM | 564 VMCB_CTRL_VMCB_CLEAN_ASID | 565 VMCB_CTRL_VMCB_CLEAN_TPR | 566 VMCB_CTRL_VMCB_CLEAN_NP | 567 VMCB_CTRL_VMCB_CLEAN_CR | 568 VMCB_CTRL_VMCB_CLEAN_DR | 569 VMCB_CTRL_VMCB_CLEAN_DT | 570 VMCB_CTRL_VMCB_CLEAN_SEG | 571 VMCB_CTRL_VMCB_CLEAN_CR2 | 572 VMCB_CTRL_VMCB_CLEAN_LBR | 573 VMCB_CTRL_VMCB_CLEAN_AVIC; 574 } 575 576 static void 577 svm_vmcb_cache_update(struct vmcb *vmcb, uint64_t flags) 578 { 579 if (flags & NVMM_X64_STATE_SEGS) { 580 vmcb->ctrl.vmcb_clean &= 581 ~(VMCB_CTRL_VMCB_CLEAN_SEG | VMCB_CTRL_VMCB_CLEAN_DT); 582 } 583 if (flags & NVMM_X64_STATE_CRS) { 584 vmcb->ctrl.vmcb_clean &= 585 ~(VMCB_CTRL_VMCB_CLEAN_CR | VMCB_CTRL_VMCB_CLEAN_CR2 | 586 VMCB_CTRL_VMCB_CLEAN_TPR); 587 } 588 if (flags & NVMM_X64_STATE_DRS) { 589 vmcb->ctrl.vmcb_clean &= ~VMCB_CTRL_VMCB_CLEAN_DR; 590 } 591 if (flags & NVMM_X64_STATE_MSRS) { 592 /* CR for EFER, NP for PAT. */ 593 vmcb->ctrl.vmcb_clean &= 594 ~(VMCB_CTRL_VMCB_CLEAN_CR | VMCB_CTRL_VMCB_CLEAN_NP); 595 } 596 } 597 598 static inline void 599 svm_vmcb_cache_flush(struct vmcb *vmcb, uint64_t flags) 600 { 601 vmcb->ctrl.vmcb_clean &= ~flags; 602 } 603 604 static inline void 605 svm_vmcb_cache_flush_all(struct vmcb *vmcb) 606 { 607 vmcb->ctrl.vmcb_clean = 0; 608 } 609 610 #define SVM_EVENT_TYPE_HW_INT 0 611 #define SVM_EVENT_TYPE_NMI 2 612 #define SVM_EVENT_TYPE_EXC 3 613 #define SVM_EVENT_TYPE_SW_INT 4 614 615 static void 616 svm_event_waitexit_enable(struct nvmm_cpu *vcpu, bool nmi) 617 { 618 struct svm_cpudata *cpudata = vcpu->cpudata; 619 struct vmcb *vmcb = cpudata->vmcb; 620 621 if (nmi) { 622 vmcb->ctrl.intercept_misc1 |= VMCB_CTRL_INTERCEPT_IRET; 623 cpudata->nmi_window_exit = true; 624 } else { 625 vmcb->ctrl.intercept_misc1 |= VMCB_CTRL_INTERCEPT_VINTR; 626 vmcb->ctrl.v |= (VMCB_CTRL_V_IRQ | VMCB_CTRL_V_IGN_TPR); 627 svm_vmcb_cache_flush(vmcb, VMCB_CTRL_VMCB_CLEAN_TPR); 628 cpudata->int_window_exit = true; 629 } 630 631 svm_vmcb_cache_flush(vmcb, VMCB_CTRL_VMCB_CLEAN_I); 632 } 633 634 static void 635 svm_event_waitexit_disable(struct nvmm_cpu *vcpu, bool nmi) 636 { 637 struct svm_cpudata *cpudata = vcpu->cpudata; 638 struct vmcb *vmcb = cpudata->vmcb; 639 640 if (nmi) { 641 vmcb->ctrl.intercept_misc1 &= ~VMCB_CTRL_INTERCEPT_IRET; 642 cpudata->nmi_window_exit = false; 643 } else { 644 vmcb->ctrl.intercept_misc1 &= ~VMCB_CTRL_INTERCEPT_VINTR; 645 vmcb->ctrl.v &= ~(VMCB_CTRL_V_IRQ | VMCB_CTRL_V_IGN_TPR); 646 svm_vmcb_cache_flush(vmcb, VMCB_CTRL_VMCB_CLEAN_TPR); 647 cpudata->int_window_exit = false; 648 } 649 650 svm_vmcb_cache_flush(vmcb, VMCB_CTRL_VMCB_CLEAN_I); 651 } 652 653 static inline int 654 svm_event_has_error(uint64_t vector) 655 { 656 switch (vector) { 657 case 8: /* #DF */ 658 case 10: /* #TS */ 659 case 11: /* #NP */ 660 case 12: /* #SS */ 661 case 13: /* #GP */ 662 case 14: /* #PF */ 663 case 17: /* #AC */ 664 case 30: /* #SX */ 665 return 1; 666 default: 667 return 0; 668 } 669 } 670 671 static int 672 svm_vcpu_inject(struct nvmm_cpu *vcpu) 673 { 674 struct nvmm_comm_page *comm = vcpu->comm; 675 struct svm_cpudata *cpudata = vcpu->cpudata; 676 struct vmcb *vmcb = cpudata->vmcb; 677 enum nvmm_event_type evtype; 678 uint64_t vector, error; 679 int type = 0, err = 0; 680 681 evtype = comm->event.type; 682 vector = comm->event.vector; 683 error = comm->event.u.error; 684 __insn_barrier(); 685 686 if (__predict_false(vector >= 256)) { 687 return EINVAL; 688 } 689 690 switch (evtype) { 691 case NVMM_EVENT_INTERRUPT_HW: 692 type = SVM_EVENT_TYPE_HW_INT; 693 if (vector == 2) { 694 type = SVM_EVENT_TYPE_NMI; 695 svm_event_waitexit_enable(vcpu, true); 696 } 697 err = 0; 698 break; 699 case NVMM_EVENT_EXCEPTION: 700 type = SVM_EVENT_TYPE_EXC; 701 if (vector == 2 || vector >= 32) 702 return EINVAL; 703 if (vector == 3 || vector == 0) 704 return EINVAL; 705 err = svm_event_has_error(vector); 706 break; 707 default: 708 return EINVAL; 709 } 710 711 vmcb->ctrl.eventinj = 712 __SHIFTIN(vector, VMCB_CTRL_EVENTINJ_VECTOR) | 713 __SHIFTIN(type, VMCB_CTRL_EVENTINJ_TYPE) | 714 __SHIFTIN(err, VMCB_CTRL_EVENTINJ_EV) | 715 __SHIFTIN(1, VMCB_CTRL_EVENTINJ_V) | 716 __SHIFTIN(error, VMCB_CTRL_EVENTINJ_ERRORCODE); 717 718 cpudata->evt_pending = true; 719 720 return 0; 721 } 722 723 static void 724 svm_inject_ud(struct nvmm_cpu *vcpu) 725 { 726 struct nvmm_comm_page *comm = vcpu->comm; 727 int ret __diagused; 728 729 comm->event.type = NVMM_EVENT_EXCEPTION; 730 comm->event.vector = 6; 731 comm->event.u.error = 0; 732 733 ret = svm_vcpu_inject(vcpu); 734 KASSERT(ret == 0); 735 } 736 737 static void 738 svm_inject_gp(struct nvmm_cpu *vcpu) 739 { 740 struct nvmm_comm_page *comm = vcpu->comm; 741 int ret __diagused; 742 743 comm->event.type = NVMM_EVENT_EXCEPTION; 744 comm->event.vector = 13; 745 comm->event.u.error = 0; 746 747 ret = svm_vcpu_inject(vcpu); 748 KASSERT(ret == 0); 749 } 750 751 static inline int 752 svm_vcpu_event_commit(struct nvmm_cpu *vcpu) 753 { 754 if (__predict_true(!vcpu->comm->event_commit)) { 755 return 0; 756 } 757 vcpu->comm->event_commit = false; 758 return svm_vcpu_inject(vcpu); 759 } 760 761 static inline void 762 svm_inkernel_advance(struct vmcb *vmcb) 763 { 764 /* 765 * Maybe we should also apply single-stepping and debug exceptions. 766 * Matters for guest-ring3, because it can execute 'cpuid' under a 767 * debugger. 768 */ 769 vmcb->state.rip = vmcb->ctrl.nrip; 770 vmcb->ctrl.intr &= ~VMCB_CTRL_INTR_SHADOW; 771 } 772 773 static void 774 svm_inkernel_handle_cpuid(struct nvmm_cpu *vcpu, uint64_t eax, uint64_t ecx) 775 { 776 struct svm_cpudata *cpudata = vcpu->cpudata; 777 uint64_t cr4; 778 779 switch (eax) { 780 case 0x00000001: 781 cpudata->vmcb->state.rax &= nvmm_cpuid_00000001.eax; 782 783 cpudata->gprs[NVMM_X64_GPR_RBX] &= ~CPUID_LOCAL_APIC_ID; 784 cpudata->gprs[NVMM_X64_GPR_RBX] |= __SHIFTIN(vcpu->cpuid, 785 CPUID_LOCAL_APIC_ID); 786 787 cpudata->gprs[NVMM_X64_GPR_RCX] &= nvmm_cpuid_00000001.ecx; 788 cpudata->gprs[NVMM_X64_GPR_RCX] |= CPUID2_RAZ; 789 790 cpudata->gprs[NVMM_X64_GPR_RDX] &= nvmm_cpuid_00000001.edx; 791 792 /* CPUID2_OSXSAVE depends on CR4. */ 793 cr4 = cpudata->vmcb->state.cr4; 794 if (!(cr4 & CR4_OSXSAVE)) { 795 cpudata->gprs[NVMM_X64_GPR_RCX] &= ~CPUID2_OSXSAVE; 796 } 797 break; 798 case 0x00000005: 799 case 0x00000006: 800 cpudata->vmcb->state.rax = 0; 801 cpudata->gprs[NVMM_X64_GPR_RBX] = 0; 802 cpudata->gprs[NVMM_X64_GPR_RCX] = 0; 803 cpudata->gprs[NVMM_X64_GPR_RDX] = 0; 804 break; 805 case 0x00000007: 806 cpudata->vmcb->state.rax &= nvmm_cpuid_00000007.eax; 807 cpudata->gprs[NVMM_X64_GPR_RBX] &= nvmm_cpuid_00000007.ebx; 808 cpudata->gprs[NVMM_X64_GPR_RCX] &= nvmm_cpuid_00000007.ecx; 809 cpudata->gprs[NVMM_X64_GPR_RDX] &= nvmm_cpuid_00000007.edx; 810 break; 811 case 0x0000000D: 812 if (svm_xcr0_mask == 0) { 813 break; 814 } 815 switch (ecx) { 816 case 0: 817 cpudata->vmcb->state.rax = svm_xcr0_mask & 0xFFFFFFFF; 818 if (cpudata->gxcr0 & XCR0_SSE) { 819 cpudata->gprs[NVMM_X64_GPR_RBX] = sizeof(struct fxsave); 820 } else { 821 cpudata->gprs[NVMM_X64_GPR_RBX] = sizeof(struct save87); 822 } 823 cpudata->gprs[NVMM_X64_GPR_RBX] += 64; /* XSAVE header */ 824 cpudata->gprs[NVMM_X64_GPR_RCX] = sizeof(struct fxsave) + 64; 825 cpudata->gprs[NVMM_X64_GPR_RDX] = svm_xcr0_mask >> 32; 826 break; 827 case 1: 828 cpudata->vmcb->state.rax &= ~CPUID_PES1_XSAVES; 829 break; 830 } 831 break; 832 case 0x40000000: 833 cpudata->gprs[NVMM_X64_GPR_RBX] = 0; 834 cpudata->gprs[NVMM_X64_GPR_RCX] = 0; 835 cpudata->gprs[NVMM_X64_GPR_RDX] = 0; 836 memcpy(&cpudata->gprs[NVMM_X64_GPR_RBX], "___ ", 4); 837 memcpy(&cpudata->gprs[NVMM_X64_GPR_RCX], "NVMM", 4); 838 memcpy(&cpudata->gprs[NVMM_X64_GPR_RDX], " ___", 4); 839 break; 840 case 0x80000001: 841 cpudata->vmcb->state.rax &= nvmm_cpuid_80000001.eax; 842 cpudata->gprs[NVMM_X64_GPR_RBX] &= nvmm_cpuid_80000001.ebx; 843 cpudata->gprs[NVMM_X64_GPR_RCX] &= nvmm_cpuid_80000001.ecx; 844 cpudata->gprs[NVMM_X64_GPR_RDX] &= nvmm_cpuid_80000001.edx; 845 break; 846 default: 847 break; 848 } 849 } 850 851 static void 852 svm_exit_cpuid(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 853 struct nvmm_exit *exit) 854 { 855 struct svm_machdata *machdata = mach->machdata; 856 struct svm_cpudata *cpudata = vcpu->cpudata; 857 struct nvmm_mach_conf_x86_cpuid *cpuid; 858 uint64_t eax, ecx; 859 u_int descs[4]; 860 size_t i; 861 862 eax = cpudata->vmcb->state.rax; 863 ecx = cpudata->gprs[NVMM_X64_GPR_RCX]; 864 x86_cpuid2(eax, ecx, descs); 865 866 cpudata->vmcb->state.rax = descs[0]; 867 cpudata->gprs[NVMM_X64_GPR_RBX] = descs[1]; 868 cpudata->gprs[NVMM_X64_GPR_RCX] = descs[2]; 869 cpudata->gprs[NVMM_X64_GPR_RDX] = descs[3]; 870 871 svm_inkernel_handle_cpuid(vcpu, eax, ecx); 872 873 for (i = 0; i < SVM_NCPUIDS; i++) { 874 cpuid = &machdata->cpuid[i]; 875 if (!machdata->cpuidpresent[i]) { 876 continue; 877 } 878 if (cpuid->leaf != eax) { 879 continue; 880 } 881 882 /* del */ 883 cpudata->vmcb->state.rax &= ~cpuid->del.eax; 884 cpudata->gprs[NVMM_X64_GPR_RBX] &= ~cpuid->del.ebx; 885 cpudata->gprs[NVMM_X64_GPR_RCX] &= ~cpuid->del.ecx; 886 cpudata->gprs[NVMM_X64_GPR_RDX] &= ~cpuid->del.edx; 887 888 /* set */ 889 cpudata->vmcb->state.rax |= cpuid->set.eax; 890 cpudata->gprs[NVMM_X64_GPR_RBX] |= cpuid->set.ebx; 891 cpudata->gprs[NVMM_X64_GPR_RCX] |= cpuid->set.ecx; 892 cpudata->gprs[NVMM_X64_GPR_RDX] |= cpuid->set.edx; 893 894 break; 895 } 896 897 svm_inkernel_advance(cpudata->vmcb); 898 exit->reason = NVMM_EXIT_NONE; 899 } 900 901 static void 902 svm_exit_hlt(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 903 struct nvmm_exit *exit) 904 { 905 struct svm_cpudata *cpudata = vcpu->cpudata; 906 struct vmcb *vmcb = cpudata->vmcb; 907 908 if (cpudata->int_window_exit && (vmcb->state.rflags & PSL_I)) { 909 svm_event_waitexit_disable(vcpu, false); 910 } 911 912 svm_inkernel_advance(cpudata->vmcb); 913 exit->reason = NVMM_EXIT_HALTED; 914 } 915 916 #define SVM_EXIT_IO_PORT __BITS(31,16) 917 #define SVM_EXIT_IO_SEG __BITS(12,10) 918 #define SVM_EXIT_IO_A64 __BIT(9) 919 #define SVM_EXIT_IO_A32 __BIT(8) 920 #define SVM_EXIT_IO_A16 __BIT(7) 921 #define SVM_EXIT_IO_SZ32 __BIT(6) 922 #define SVM_EXIT_IO_SZ16 __BIT(5) 923 #define SVM_EXIT_IO_SZ8 __BIT(4) 924 #define SVM_EXIT_IO_REP __BIT(3) 925 #define SVM_EXIT_IO_STR __BIT(2) 926 #define SVM_EXIT_IO_IN __BIT(0) 927 928 static void 929 svm_exit_io(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 930 struct nvmm_exit *exit) 931 { 932 struct svm_cpudata *cpudata = vcpu->cpudata; 933 uint64_t info = cpudata->vmcb->ctrl.exitinfo1; 934 uint64_t nextpc = cpudata->vmcb->ctrl.exitinfo2; 935 936 exit->reason = NVMM_EXIT_IO; 937 938 if (info & SVM_EXIT_IO_IN) { 939 exit->u.io.type = NVMM_EXIT_IO_IN; 940 } else { 941 exit->u.io.type = NVMM_EXIT_IO_OUT; 942 } 943 944 exit->u.io.port = __SHIFTOUT(info, SVM_EXIT_IO_PORT); 945 946 if (svm_decode_assist) { 947 KASSERT(__SHIFTOUT(info, SVM_EXIT_IO_SEG) < 6); 948 exit->u.io.seg = __SHIFTOUT(info, SVM_EXIT_IO_SEG); 949 } else { 950 exit->u.io.seg = -1; 951 } 952 953 if (info & SVM_EXIT_IO_A64) { 954 exit->u.io.address_size = 8; 955 } else if (info & SVM_EXIT_IO_A32) { 956 exit->u.io.address_size = 4; 957 } else if (info & SVM_EXIT_IO_A16) { 958 exit->u.io.address_size = 2; 959 } 960 961 if (info & SVM_EXIT_IO_SZ32) { 962 exit->u.io.operand_size = 4; 963 } else if (info & SVM_EXIT_IO_SZ16) { 964 exit->u.io.operand_size = 2; 965 } else if (info & SVM_EXIT_IO_SZ8) { 966 exit->u.io.operand_size = 1; 967 } 968 969 exit->u.io.rep = (info & SVM_EXIT_IO_REP) != 0; 970 exit->u.io.str = (info & SVM_EXIT_IO_STR) != 0; 971 exit->u.io.npc = nextpc; 972 973 svm_vcpu_state_provide(vcpu, 974 NVMM_X64_STATE_GPRS | NVMM_X64_STATE_SEGS | 975 NVMM_X64_STATE_CRS | NVMM_X64_STATE_MSRS); 976 } 977 978 static const uint64_t msr_ignore_list[] = { 979 0xc0010055, /* MSR_CMPHALT */ 980 MSR_DE_CFG, 981 MSR_IC_CFG, 982 MSR_UCODE_AMD_PATCHLEVEL 983 }; 984 985 static bool 986 svm_inkernel_handle_msr(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 987 struct nvmm_exit *exit) 988 { 989 struct svm_cpudata *cpudata = vcpu->cpudata; 990 struct vmcb *vmcb = cpudata->vmcb; 991 uint64_t val; 992 size_t i; 993 994 switch (exit->u.msr.type) { 995 case NVMM_EXIT_MSR_RDMSR: 996 if (exit->u.msr.msr == MSR_NB_CFG) { 997 val = NB_CFG_INITAPICCPUIDLO; 998 vmcb->state.rax = (val & 0xFFFFFFFF); 999 cpudata->gprs[NVMM_X64_GPR_RDX] = (val >> 32); 1000 goto handled; 1001 } 1002 for (i = 0; i < __arraycount(msr_ignore_list); i++) { 1003 if (msr_ignore_list[i] != exit->u.msr.msr) 1004 continue; 1005 val = 0; 1006 vmcb->state.rax = (val & 0xFFFFFFFF); 1007 cpudata->gprs[NVMM_X64_GPR_RDX] = (val >> 32); 1008 goto handled; 1009 } 1010 break; 1011 case NVMM_EXIT_MSR_WRMSR: 1012 if (exit->u.msr.msr == MSR_EFER) { 1013 if (__predict_false(exit->u.msr.val & ~EFER_VALID)) { 1014 goto error; 1015 } 1016 if ((vmcb->state.efer ^ exit->u.msr.val) & 1017 EFER_TLB_FLUSH) { 1018 cpudata->gtlb_want_flush = true; 1019 } 1020 vmcb->state.efer = exit->u.msr.val | EFER_SVME; 1021 svm_vmcb_cache_flush(vmcb, VMCB_CTRL_VMCB_CLEAN_CR); 1022 goto handled; 1023 } 1024 if (exit->u.msr.msr == MSR_TSC) { 1025 cpudata->gtsc = exit->u.msr.val; 1026 cpudata->gtsc_want_update = true; 1027 goto handled; 1028 } 1029 for (i = 0; i < __arraycount(msr_ignore_list); i++) { 1030 if (msr_ignore_list[i] != exit->u.msr.msr) 1031 continue; 1032 goto handled; 1033 } 1034 break; 1035 } 1036 1037 return false; 1038 1039 handled: 1040 svm_inkernel_advance(cpudata->vmcb); 1041 return true; 1042 1043 error: 1044 svm_inject_gp(vcpu); 1045 return true; 1046 } 1047 1048 static void 1049 svm_exit_msr(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 1050 struct nvmm_exit *exit) 1051 { 1052 struct svm_cpudata *cpudata = vcpu->cpudata; 1053 uint64_t info = cpudata->vmcb->ctrl.exitinfo1; 1054 1055 if (info == 0) { 1056 exit->u.msr.type = NVMM_EXIT_MSR_RDMSR; 1057 } else { 1058 exit->u.msr.type = NVMM_EXIT_MSR_WRMSR; 1059 } 1060 1061 exit->u.msr.msr = (cpudata->gprs[NVMM_X64_GPR_RCX] & 0xFFFFFFFF); 1062 1063 if (info == 1) { 1064 uint64_t rdx, rax; 1065 rdx = cpudata->gprs[NVMM_X64_GPR_RDX]; 1066 rax = cpudata->vmcb->state.rax; 1067 exit->u.msr.val = (rdx << 32) | (rax & 0xFFFFFFFF); 1068 } else { 1069 exit->u.msr.val = 0; 1070 } 1071 1072 if (svm_inkernel_handle_msr(mach, vcpu, exit)) { 1073 exit->reason = NVMM_EXIT_NONE; 1074 return; 1075 } 1076 1077 exit->reason = NVMM_EXIT_MSR; 1078 exit->u.msr.npc = cpudata->vmcb->ctrl.nrip; 1079 1080 svm_vcpu_state_provide(vcpu, NVMM_X64_STATE_GPRS); 1081 } 1082 1083 static void 1084 svm_exit_npf(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 1085 struct nvmm_exit *exit) 1086 { 1087 struct svm_cpudata *cpudata = vcpu->cpudata; 1088 gpaddr_t gpa = cpudata->vmcb->ctrl.exitinfo2; 1089 1090 exit->reason = NVMM_EXIT_MEMORY; 1091 if (cpudata->vmcb->ctrl.exitinfo1 & PGEX_W) 1092 exit->u.mem.prot = PROT_WRITE; 1093 else if (cpudata->vmcb->ctrl.exitinfo1 & PGEX_X) 1094 exit->u.mem.prot = PROT_EXEC; 1095 else 1096 exit->u.mem.prot = PROT_READ; 1097 exit->u.mem.gpa = gpa; 1098 exit->u.mem.inst_len = cpudata->vmcb->ctrl.inst_len; 1099 memcpy(exit->u.mem.inst_bytes, cpudata->vmcb->ctrl.inst_bytes, 1100 sizeof(exit->u.mem.inst_bytes)); 1101 1102 svm_vcpu_state_provide(vcpu, 1103 NVMM_X64_STATE_GPRS | NVMM_X64_STATE_SEGS | 1104 NVMM_X64_STATE_CRS | NVMM_X64_STATE_MSRS); 1105 } 1106 1107 static void 1108 svm_exit_insn(struct vmcb *vmcb, struct nvmm_exit *exit, uint64_t reason) 1109 { 1110 exit->u.insn.npc = vmcb->ctrl.nrip; 1111 exit->reason = reason; 1112 } 1113 1114 static void 1115 svm_exit_xsetbv(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 1116 struct nvmm_exit *exit) 1117 { 1118 struct svm_cpudata *cpudata = vcpu->cpudata; 1119 struct vmcb *vmcb = cpudata->vmcb; 1120 uint64_t val; 1121 1122 exit->reason = NVMM_EXIT_NONE; 1123 1124 val = (cpudata->gprs[NVMM_X64_GPR_RDX] << 32) | 1125 (vmcb->state.rax & 0xFFFFFFFF); 1126 1127 if (__predict_false(cpudata->gprs[NVMM_X64_GPR_RCX] != 0)) { 1128 goto error; 1129 } else if (__predict_false(vmcb->state.cpl != 0)) { 1130 goto error; 1131 } else if (__predict_false((val & ~svm_xcr0_mask) != 0)) { 1132 goto error; 1133 } else if (__predict_false((val & XCR0_X87) == 0)) { 1134 goto error; 1135 } 1136 1137 cpudata->gxcr0 = val; 1138 if (svm_xcr0_mask != 0) { 1139 wrxcr(0, cpudata->gxcr0); 1140 } 1141 1142 svm_inkernel_advance(cpudata->vmcb); 1143 return; 1144 1145 error: 1146 svm_inject_gp(vcpu); 1147 } 1148 1149 static void 1150 svm_exit_invalid(struct nvmm_exit *exit, uint64_t code) 1151 { 1152 exit->u.inv.hwcode = code; 1153 exit->reason = NVMM_EXIT_INVALID; 1154 } 1155 1156 /* -------------------------------------------------------------------------- */ 1157 1158 static void 1159 svm_vcpu_guest_fpu_enter(struct nvmm_cpu *vcpu) 1160 { 1161 struct svm_cpudata *cpudata = vcpu->cpudata; 1162 1163 fpu_save(); 1164 fpu_area_restore(&cpudata->gfpu, svm_xcr0_mask); 1165 1166 if (svm_xcr0_mask != 0) { 1167 cpudata->hxcr0 = rdxcr(0); 1168 wrxcr(0, cpudata->gxcr0); 1169 } 1170 } 1171 1172 static void 1173 svm_vcpu_guest_fpu_leave(struct nvmm_cpu *vcpu) 1174 { 1175 struct svm_cpudata *cpudata = vcpu->cpudata; 1176 1177 if (svm_xcr0_mask != 0) { 1178 cpudata->gxcr0 = rdxcr(0); 1179 wrxcr(0, cpudata->hxcr0); 1180 } 1181 1182 fpu_area_save(&cpudata->gfpu, svm_xcr0_mask); 1183 } 1184 1185 static void 1186 svm_vcpu_guest_dbregs_enter(struct nvmm_cpu *vcpu) 1187 { 1188 struct svm_cpudata *cpudata = vcpu->cpudata; 1189 1190 x86_dbregs_save(curlwp); 1191 1192 ldr7(0); 1193 1194 ldr0(cpudata->drs[NVMM_X64_DR_DR0]); 1195 ldr1(cpudata->drs[NVMM_X64_DR_DR1]); 1196 ldr2(cpudata->drs[NVMM_X64_DR_DR2]); 1197 ldr3(cpudata->drs[NVMM_X64_DR_DR3]); 1198 } 1199 1200 static void 1201 svm_vcpu_guest_dbregs_leave(struct nvmm_cpu *vcpu) 1202 { 1203 struct svm_cpudata *cpudata = vcpu->cpudata; 1204 1205 cpudata->drs[NVMM_X64_DR_DR0] = rdr0(); 1206 cpudata->drs[NVMM_X64_DR_DR1] = rdr1(); 1207 cpudata->drs[NVMM_X64_DR_DR2] = rdr2(); 1208 cpudata->drs[NVMM_X64_DR_DR3] = rdr3(); 1209 1210 x86_dbregs_restore(curlwp); 1211 } 1212 1213 static void 1214 svm_vcpu_guest_misc_enter(struct nvmm_cpu *vcpu) 1215 { 1216 struct svm_cpudata *cpudata = vcpu->cpudata; 1217 1218 cpudata->fsbase = rdmsr(MSR_FSBASE); 1219 cpudata->kernelgsbase = rdmsr(MSR_KERNELGSBASE); 1220 } 1221 1222 static void 1223 svm_vcpu_guest_misc_leave(struct nvmm_cpu *vcpu) 1224 { 1225 struct svm_cpudata *cpudata = vcpu->cpudata; 1226 1227 wrmsr(MSR_STAR, cpudata->star); 1228 wrmsr(MSR_LSTAR, cpudata->lstar); 1229 wrmsr(MSR_CSTAR, cpudata->cstar); 1230 wrmsr(MSR_SFMASK, cpudata->sfmask); 1231 wrmsr(MSR_FSBASE, cpudata->fsbase); 1232 wrmsr(MSR_KERNELGSBASE, cpudata->kernelgsbase); 1233 } 1234 1235 /* -------------------------------------------------------------------------- */ 1236 1237 static inline void 1238 svm_gtlb_catchup(struct nvmm_cpu *vcpu, int hcpu) 1239 { 1240 struct svm_cpudata *cpudata = vcpu->cpudata; 1241 1242 if (vcpu->hcpu_last != hcpu || cpudata->shared_asid) { 1243 cpudata->gtlb_want_flush = true; 1244 } 1245 } 1246 1247 static inline void 1248 svm_htlb_catchup(struct nvmm_cpu *vcpu, int hcpu) 1249 { 1250 /* 1251 * Nothing to do. If an hTLB flush was needed, either the VCPU was 1252 * executing on this hCPU and the hTLB already got flushed, or it 1253 * was executing on another hCPU in which case the catchup is done 1254 * in svm_gtlb_catchup(). 1255 */ 1256 } 1257 1258 static inline uint64_t 1259 svm_htlb_flush(struct svm_machdata *machdata, struct svm_cpudata *cpudata) 1260 { 1261 struct vmcb *vmcb = cpudata->vmcb; 1262 uint64_t machgen; 1263 1264 machgen = machdata->mach_htlb_gen; 1265 if (__predict_true(machgen == cpudata->vcpu_htlb_gen)) { 1266 return machgen; 1267 } 1268 1269 vmcb->ctrl.tlb_ctrl = svm_ctrl_tlb_flush; 1270 return machgen; 1271 } 1272 1273 static inline void 1274 svm_htlb_flush_ack(struct svm_cpudata *cpudata, uint64_t machgen) 1275 { 1276 struct vmcb *vmcb = cpudata->vmcb; 1277 1278 if (__predict_true(vmcb->ctrl.exitcode != VMCB_EXITCODE_INVALID)) { 1279 cpudata->vcpu_htlb_gen = machgen; 1280 } 1281 } 1282 1283 static inline void 1284 svm_exit_evt(struct svm_cpudata *cpudata, struct vmcb *vmcb) 1285 { 1286 cpudata->evt_pending = false; 1287 1288 if (__predict_false(vmcb->ctrl.exitintinfo & VMCB_CTRL_EXITINTINFO_V)) { 1289 vmcb->ctrl.eventinj = vmcb->ctrl.exitintinfo; 1290 cpudata->evt_pending = true; 1291 } 1292 } 1293 1294 static int 1295 svm_vcpu_run(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 1296 struct nvmm_exit *exit) 1297 { 1298 struct nvmm_comm_page *comm = vcpu->comm; 1299 struct svm_machdata *machdata = mach->machdata; 1300 struct svm_cpudata *cpudata = vcpu->cpudata; 1301 struct vmcb *vmcb = cpudata->vmcb; 1302 uint64_t machgen; 1303 int hcpu, s; 1304 1305 if (__predict_false(svm_vcpu_event_commit(vcpu) != 0)) { 1306 return EINVAL; 1307 } 1308 svm_vcpu_state_commit(vcpu); 1309 comm->state_cached = 0; 1310 1311 kpreempt_disable(); 1312 hcpu = cpu_number(); 1313 1314 svm_gtlb_catchup(vcpu, hcpu); 1315 svm_htlb_catchup(vcpu, hcpu); 1316 1317 if (vcpu->hcpu_last != hcpu) { 1318 svm_vmcb_cache_flush_all(vmcb); 1319 cpudata->gtsc_want_update = true; 1320 } 1321 1322 svm_vcpu_guest_dbregs_enter(vcpu); 1323 svm_vcpu_guest_misc_enter(vcpu); 1324 svm_vcpu_guest_fpu_enter(vcpu); 1325 1326 while (1) { 1327 if (cpudata->gtlb_want_flush) { 1328 vmcb->ctrl.tlb_ctrl = svm_ctrl_tlb_flush; 1329 } else { 1330 vmcb->ctrl.tlb_ctrl = 0; 1331 } 1332 1333 if (__predict_false(cpudata->gtsc_want_update)) { 1334 vmcb->ctrl.tsc_offset = cpudata->gtsc - rdtsc(); 1335 svm_vmcb_cache_flush(vmcb, VMCB_CTRL_VMCB_CLEAN_I); 1336 } 1337 1338 s = splhigh(); 1339 machgen = svm_htlb_flush(machdata, cpudata); 1340 svm_vmrun(cpudata->vmcb_pa, cpudata->gprs); 1341 svm_htlb_flush_ack(cpudata, machgen); 1342 splx(s); 1343 1344 svm_vmcb_cache_default(vmcb); 1345 1346 if (vmcb->ctrl.exitcode != VMCB_EXITCODE_INVALID) { 1347 cpudata->gtlb_want_flush = false; 1348 cpudata->gtsc_want_update = false; 1349 vcpu->hcpu_last = hcpu; 1350 } 1351 svm_exit_evt(cpudata, vmcb); 1352 1353 switch (vmcb->ctrl.exitcode) { 1354 case VMCB_EXITCODE_INTR: 1355 case VMCB_EXITCODE_NMI: 1356 exit->reason = NVMM_EXIT_NONE; 1357 break; 1358 case VMCB_EXITCODE_VINTR: 1359 svm_event_waitexit_disable(vcpu, false); 1360 exit->reason = NVMM_EXIT_INT_READY; 1361 break; 1362 case VMCB_EXITCODE_IRET: 1363 svm_event_waitexit_disable(vcpu, true); 1364 exit->reason = NVMM_EXIT_NMI_READY; 1365 break; 1366 case VMCB_EXITCODE_CPUID: 1367 svm_exit_cpuid(mach, vcpu, exit); 1368 break; 1369 case VMCB_EXITCODE_HLT: 1370 svm_exit_hlt(mach, vcpu, exit); 1371 break; 1372 case VMCB_EXITCODE_IOIO: 1373 svm_exit_io(mach, vcpu, exit); 1374 break; 1375 case VMCB_EXITCODE_MSR: 1376 svm_exit_msr(mach, vcpu, exit); 1377 break; 1378 case VMCB_EXITCODE_SHUTDOWN: 1379 exit->reason = NVMM_EXIT_SHUTDOWN; 1380 break; 1381 case VMCB_EXITCODE_RDPMC: 1382 case VMCB_EXITCODE_RSM: 1383 case VMCB_EXITCODE_INVLPGA: 1384 case VMCB_EXITCODE_VMRUN: 1385 case VMCB_EXITCODE_VMMCALL: 1386 case VMCB_EXITCODE_VMLOAD: 1387 case VMCB_EXITCODE_VMSAVE: 1388 case VMCB_EXITCODE_STGI: 1389 case VMCB_EXITCODE_CLGI: 1390 case VMCB_EXITCODE_SKINIT: 1391 case VMCB_EXITCODE_RDTSCP: 1392 svm_inject_ud(vcpu); 1393 exit->reason = NVMM_EXIT_NONE; 1394 break; 1395 case VMCB_EXITCODE_MONITOR: 1396 svm_exit_insn(vmcb, exit, NVMM_EXIT_MONITOR); 1397 break; 1398 case VMCB_EXITCODE_MWAIT: 1399 svm_exit_insn(vmcb, exit, NVMM_EXIT_MWAIT); 1400 break; 1401 case VMCB_EXITCODE_MWAIT_CONDITIONAL: 1402 svm_exit_insn(vmcb, exit, NVMM_EXIT_MWAIT_COND); 1403 break; 1404 case VMCB_EXITCODE_XSETBV: 1405 svm_exit_xsetbv(mach, vcpu, exit); 1406 break; 1407 case VMCB_EXITCODE_NPF: 1408 svm_exit_npf(mach, vcpu, exit); 1409 break; 1410 case VMCB_EXITCODE_FERR_FREEZE: /* ? */ 1411 default: 1412 svm_exit_invalid(exit, vmcb->ctrl.exitcode); 1413 break; 1414 } 1415 1416 /* If no reason to return to userland, keep rolling. */ 1417 if (curcpu()->ci_schedstate.spc_flags & SPCF_SHOULDYIELD) { 1418 break; 1419 } 1420 if (curcpu()->ci_data.cpu_softints != 0) { 1421 break; 1422 } 1423 if (curlwp->l_flag & LW_USERRET) { 1424 break; 1425 } 1426 if (exit->reason != NVMM_EXIT_NONE) { 1427 break; 1428 } 1429 } 1430 1431 cpudata->gtsc = rdtsc() + vmcb->ctrl.tsc_offset; 1432 1433 svm_vcpu_guest_fpu_leave(vcpu); 1434 svm_vcpu_guest_misc_leave(vcpu); 1435 svm_vcpu_guest_dbregs_leave(vcpu); 1436 1437 kpreempt_enable(); 1438 1439 exit->exitstate[NVMM_X64_EXITSTATE_CR8] = __SHIFTOUT(vmcb->ctrl.v, 1440 VMCB_CTRL_V_TPR); 1441 exit->exitstate[NVMM_X64_EXITSTATE_RFLAGS] = vmcb->state.rflags; 1442 1443 exit->exitstate[NVMM_X64_EXITSTATE_INT_SHADOW] = 1444 ((vmcb->ctrl.intr & VMCB_CTRL_INTR_SHADOW) != 0); 1445 exit->exitstate[NVMM_X64_EXITSTATE_INT_WINDOW_EXIT] = 1446 cpudata->int_window_exit; 1447 exit->exitstate[NVMM_X64_EXITSTATE_NMI_WINDOW_EXIT] = 1448 cpudata->nmi_window_exit; 1449 exit->exitstate[NVMM_X64_EXITSTATE_EVT_PENDING] = 1450 cpudata->evt_pending; 1451 1452 return 0; 1453 } 1454 1455 /* -------------------------------------------------------------------------- */ 1456 1457 static int 1458 svm_memalloc(paddr_t *pa, vaddr_t *va, size_t npages) 1459 { 1460 struct pglist pglist; 1461 paddr_t _pa; 1462 vaddr_t _va; 1463 size_t i; 1464 int ret; 1465 1466 ret = uvm_pglistalloc(npages * PAGE_SIZE, 0, ~0UL, PAGE_SIZE, 0, 1467 &pglist, 1, 0); 1468 if (ret != 0) 1469 return ENOMEM; 1470 _pa = TAILQ_FIRST(&pglist)->phys_addr; 1471 _va = uvm_km_alloc(kernel_map, npages * PAGE_SIZE, 0, 1472 UVM_KMF_VAONLY | UVM_KMF_NOWAIT); 1473 if (_va == 0) 1474 goto error; 1475 1476 for (i = 0; i < npages; i++) { 1477 pmap_kenter_pa(_va + i * PAGE_SIZE, _pa + i * PAGE_SIZE, 1478 VM_PROT_READ | VM_PROT_WRITE, PMAP_WRITE_BACK); 1479 } 1480 pmap_update(pmap_kernel()); 1481 1482 memset((void *)_va, 0, npages * PAGE_SIZE); 1483 1484 *pa = _pa; 1485 *va = _va; 1486 return 0; 1487 1488 error: 1489 for (i = 0; i < npages; i++) { 1490 uvm_pagefree(PHYS_TO_VM_PAGE(_pa + i * PAGE_SIZE)); 1491 } 1492 return ENOMEM; 1493 } 1494 1495 static void 1496 svm_memfree(paddr_t pa, vaddr_t va, size_t npages) 1497 { 1498 size_t i; 1499 1500 pmap_kremove(va, npages * PAGE_SIZE); 1501 pmap_update(pmap_kernel()); 1502 uvm_km_free(kernel_map, va, npages * PAGE_SIZE, UVM_KMF_VAONLY); 1503 for (i = 0; i < npages; i++) { 1504 uvm_pagefree(PHYS_TO_VM_PAGE(pa + i * PAGE_SIZE)); 1505 } 1506 } 1507 1508 /* -------------------------------------------------------------------------- */ 1509 1510 #define SVM_MSRBM_READ __BIT(0) 1511 #define SVM_MSRBM_WRITE __BIT(1) 1512 1513 static void 1514 svm_vcpu_msr_allow(uint8_t *bitmap, uint64_t msr, bool read, bool write) 1515 { 1516 uint64_t byte; 1517 uint8_t bitoff; 1518 1519 if (msr < 0x00002000) { 1520 /* Range 1 */ 1521 byte = ((msr - 0x00000000) >> 2UL) + 0x0000; 1522 } else if (msr >= 0xC0000000 && msr < 0xC0002000) { 1523 /* Range 2 */ 1524 byte = ((msr - 0xC0000000) >> 2UL) + 0x0800; 1525 } else if (msr >= 0xC0010000 && msr < 0xC0012000) { 1526 /* Range 3 */ 1527 byte = ((msr - 0xC0010000) >> 2UL) + 0x1000; 1528 } else { 1529 panic("%s: wrong range", __func__); 1530 } 1531 1532 bitoff = (msr & 0x3) << 1; 1533 1534 if (read) { 1535 bitmap[byte] &= ~(SVM_MSRBM_READ << bitoff); 1536 } 1537 if (write) { 1538 bitmap[byte] &= ~(SVM_MSRBM_WRITE << bitoff); 1539 } 1540 } 1541 1542 #define SVM_SEG_ATTRIB_TYPE __BITS(3,0) 1543 #define SVM_SEG_ATTRIB_S __BIT(4) 1544 #define SVM_SEG_ATTRIB_DPL __BITS(6,5) 1545 #define SVM_SEG_ATTRIB_P __BIT(7) 1546 #define SVM_SEG_ATTRIB_AVL __BIT(8) 1547 #define SVM_SEG_ATTRIB_L __BIT(9) 1548 #define SVM_SEG_ATTRIB_DEF __BIT(10) 1549 #define SVM_SEG_ATTRIB_G __BIT(11) 1550 1551 static void 1552 svm_vcpu_setstate_seg(const struct nvmm_x64_state_seg *seg, 1553 struct vmcb_segment *vseg) 1554 { 1555 vseg->selector = seg->selector; 1556 vseg->attrib = 1557 __SHIFTIN(seg->attrib.type, SVM_SEG_ATTRIB_TYPE) | 1558 __SHIFTIN(seg->attrib.s, SVM_SEG_ATTRIB_S) | 1559 __SHIFTIN(seg->attrib.dpl, SVM_SEG_ATTRIB_DPL) | 1560 __SHIFTIN(seg->attrib.p, SVM_SEG_ATTRIB_P) | 1561 __SHIFTIN(seg->attrib.avl, SVM_SEG_ATTRIB_AVL) | 1562 __SHIFTIN(seg->attrib.l, SVM_SEG_ATTRIB_L) | 1563 __SHIFTIN(seg->attrib.def, SVM_SEG_ATTRIB_DEF) | 1564 __SHIFTIN(seg->attrib.g, SVM_SEG_ATTRIB_G); 1565 vseg->limit = seg->limit; 1566 vseg->base = seg->base; 1567 } 1568 1569 static void 1570 svm_vcpu_getstate_seg(struct nvmm_x64_state_seg *seg, struct vmcb_segment *vseg) 1571 { 1572 seg->selector = vseg->selector; 1573 seg->attrib.type = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_TYPE); 1574 seg->attrib.s = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_S); 1575 seg->attrib.dpl = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_DPL); 1576 seg->attrib.p = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_P); 1577 seg->attrib.avl = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_AVL); 1578 seg->attrib.l = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_L); 1579 seg->attrib.def = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_DEF); 1580 seg->attrib.g = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_G); 1581 seg->limit = vseg->limit; 1582 seg->base = vseg->base; 1583 } 1584 1585 static inline bool 1586 svm_state_tlb_flush(const struct vmcb *vmcb, const struct nvmm_x64_state *state, 1587 uint64_t flags) 1588 { 1589 if (flags & NVMM_X64_STATE_CRS) { 1590 if ((vmcb->state.cr0 ^ 1591 state->crs[NVMM_X64_CR_CR0]) & CR0_TLB_FLUSH) { 1592 return true; 1593 } 1594 if (vmcb->state.cr3 != state->crs[NVMM_X64_CR_CR3]) { 1595 return true; 1596 } 1597 if ((vmcb->state.cr4 ^ 1598 state->crs[NVMM_X64_CR_CR4]) & CR4_TLB_FLUSH) { 1599 return true; 1600 } 1601 } 1602 1603 if (flags & NVMM_X64_STATE_MSRS) { 1604 if ((vmcb->state.efer ^ 1605 state->msrs[NVMM_X64_MSR_EFER]) & EFER_TLB_FLUSH) { 1606 return true; 1607 } 1608 } 1609 1610 return false; 1611 } 1612 1613 static void 1614 svm_vcpu_setstate(struct nvmm_cpu *vcpu) 1615 { 1616 struct nvmm_comm_page *comm = vcpu->comm; 1617 const struct nvmm_x64_state *state = &comm->state; 1618 struct svm_cpudata *cpudata = vcpu->cpudata; 1619 struct vmcb *vmcb = cpudata->vmcb; 1620 struct fxsave *fpustate; 1621 uint64_t flags; 1622 1623 flags = comm->state_wanted; 1624 1625 if (svm_state_tlb_flush(vmcb, state, flags)) { 1626 cpudata->gtlb_want_flush = true; 1627 } 1628 1629 if (flags & NVMM_X64_STATE_SEGS) { 1630 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_CS], 1631 &vmcb->state.cs); 1632 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_DS], 1633 &vmcb->state.ds); 1634 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_ES], 1635 &vmcb->state.es); 1636 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_FS], 1637 &vmcb->state.fs); 1638 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_GS], 1639 &vmcb->state.gs); 1640 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_SS], 1641 &vmcb->state.ss); 1642 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_GDT], 1643 &vmcb->state.gdt); 1644 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_IDT], 1645 &vmcb->state.idt); 1646 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_LDT], 1647 &vmcb->state.ldt); 1648 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_TR], 1649 &vmcb->state.tr); 1650 1651 vmcb->state.cpl = state->segs[NVMM_X64_SEG_SS].attrib.dpl; 1652 } 1653 1654 CTASSERT(sizeof(cpudata->gprs) == sizeof(state->gprs)); 1655 if (flags & NVMM_X64_STATE_GPRS) { 1656 memcpy(cpudata->gprs, state->gprs, sizeof(state->gprs)); 1657 1658 vmcb->state.rip = state->gprs[NVMM_X64_GPR_RIP]; 1659 vmcb->state.rsp = state->gprs[NVMM_X64_GPR_RSP]; 1660 vmcb->state.rax = state->gprs[NVMM_X64_GPR_RAX]; 1661 vmcb->state.rflags = state->gprs[NVMM_X64_GPR_RFLAGS]; 1662 } 1663 1664 if (flags & NVMM_X64_STATE_CRS) { 1665 vmcb->state.cr0 = state->crs[NVMM_X64_CR_CR0]; 1666 vmcb->state.cr2 = state->crs[NVMM_X64_CR_CR2]; 1667 vmcb->state.cr3 = state->crs[NVMM_X64_CR_CR3]; 1668 vmcb->state.cr4 = state->crs[NVMM_X64_CR_CR4]; 1669 1670 vmcb->ctrl.v &= ~VMCB_CTRL_V_TPR; 1671 vmcb->ctrl.v |= __SHIFTIN(state->crs[NVMM_X64_CR_CR8], 1672 VMCB_CTRL_V_TPR); 1673 1674 if (svm_xcr0_mask != 0) { 1675 /* Clear illegal XCR0 bits, set mandatory X87 bit. */ 1676 cpudata->gxcr0 = state->crs[NVMM_X64_CR_XCR0]; 1677 cpudata->gxcr0 &= svm_xcr0_mask; 1678 cpudata->gxcr0 |= XCR0_X87; 1679 } 1680 } 1681 1682 CTASSERT(sizeof(cpudata->drs) == sizeof(state->drs)); 1683 if (flags & NVMM_X64_STATE_DRS) { 1684 memcpy(cpudata->drs, state->drs, sizeof(state->drs)); 1685 1686 vmcb->state.dr6 = state->drs[NVMM_X64_DR_DR6]; 1687 vmcb->state.dr7 = state->drs[NVMM_X64_DR_DR7]; 1688 } 1689 1690 if (flags & NVMM_X64_STATE_MSRS) { 1691 /* 1692 * EFER_SVME is mandatory. 1693 */ 1694 vmcb->state.efer = state->msrs[NVMM_X64_MSR_EFER] | EFER_SVME; 1695 vmcb->state.star = state->msrs[NVMM_X64_MSR_STAR]; 1696 vmcb->state.lstar = state->msrs[NVMM_X64_MSR_LSTAR]; 1697 vmcb->state.cstar = state->msrs[NVMM_X64_MSR_CSTAR]; 1698 vmcb->state.sfmask = state->msrs[NVMM_X64_MSR_SFMASK]; 1699 vmcb->state.kernelgsbase = 1700 state->msrs[NVMM_X64_MSR_KERNELGSBASE]; 1701 vmcb->state.sysenter_cs = 1702 state->msrs[NVMM_X64_MSR_SYSENTER_CS]; 1703 vmcb->state.sysenter_esp = 1704 state->msrs[NVMM_X64_MSR_SYSENTER_ESP]; 1705 vmcb->state.sysenter_eip = 1706 state->msrs[NVMM_X64_MSR_SYSENTER_EIP]; 1707 vmcb->state.g_pat = state->msrs[NVMM_X64_MSR_PAT]; 1708 1709 cpudata->gtsc = state->msrs[NVMM_X64_MSR_TSC]; 1710 cpudata->gtsc_want_update = true; 1711 } 1712 1713 if (flags & NVMM_X64_STATE_INTR) { 1714 if (state->intr.int_shadow) { 1715 vmcb->ctrl.intr |= VMCB_CTRL_INTR_SHADOW; 1716 } else { 1717 vmcb->ctrl.intr &= ~VMCB_CTRL_INTR_SHADOW; 1718 } 1719 1720 if (state->intr.int_window_exiting) { 1721 svm_event_waitexit_enable(vcpu, false); 1722 } else { 1723 svm_event_waitexit_disable(vcpu, false); 1724 } 1725 1726 if (state->intr.nmi_window_exiting) { 1727 svm_event_waitexit_enable(vcpu, true); 1728 } else { 1729 svm_event_waitexit_disable(vcpu, true); 1730 } 1731 } 1732 1733 CTASSERT(sizeof(cpudata->gfpu.xsh_fxsave) == sizeof(state->fpu)); 1734 if (flags & NVMM_X64_STATE_FPU) { 1735 memcpy(cpudata->gfpu.xsh_fxsave, &state->fpu, 1736 sizeof(state->fpu)); 1737 1738 fpustate = (struct fxsave *)cpudata->gfpu.xsh_fxsave; 1739 fpustate->fx_mxcsr_mask &= x86_fpu_mxcsr_mask; 1740 fpustate->fx_mxcsr &= fpustate->fx_mxcsr_mask; 1741 1742 if (svm_xcr0_mask != 0) { 1743 /* Reset XSTATE_BV, to force a reload. */ 1744 cpudata->gfpu.xsh_xstate_bv = svm_xcr0_mask; 1745 } 1746 } 1747 1748 svm_vmcb_cache_update(vmcb, flags); 1749 1750 comm->state_wanted = 0; 1751 comm->state_cached |= flags; 1752 } 1753 1754 static void 1755 svm_vcpu_getstate(struct nvmm_cpu *vcpu) 1756 { 1757 struct nvmm_comm_page *comm = vcpu->comm; 1758 struct nvmm_x64_state *state = &comm->state; 1759 struct svm_cpudata *cpudata = vcpu->cpudata; 1760 struct vmcb *vmcb = cpudata->vmcb; 1761 uint64_t flags; 1762 1763 flags = comm->state_wanted; 1764 1765 if (flags & NVMM_X64_STATE_SEGS) { 1766 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_CS], 1767 &vmcb->state.cs); 1768 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_DS], 1769 &vmcb->state.ds); 1770 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_ES], 1771 &vmcb->state.es); 1772 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_FS], 1773 &vmcb->state.fs); 1774 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_GS], 1775 &vmcb->state.gs); 1776 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_SS], 1777 &vmcb->state.ss); 1778 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_GDT], 1779 &vmcb->state.gdt); 1780 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_IDT], 1781 &vmcb->state.idt); 1782 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_LDT], 1783 &vmcb->state.ldt); 1784 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_TR], 1785 &vmcb->state.tr); 1786 1787 state->segs[NVMM_X64_SEG_SS].attrib.dpl = vmcb->state.cpl; 1788 } 1789 1790 CTASSERT(sizeof(cpudata->gprs) == sizeof(state->gprs)); 1791 if (flags & NVMM_X64_STATE_GPRS) { 1792 memcpy(state->gprs, cpudata->gprs, sizeof(state->gprs)); 1793 1794 state->gprs[NVMM_X64_GPR_RIP] = vmcb->state.rip; 1795 state->gprs[NVMM_X64_GPR_RSP] = vmcb->state.rsp; 1796 state->gprs[NVMM_X64_GPR_RAX] = vmcb->state.rax; 1797 state->gprs[NVMM_X64_GPR_RFLAGS] = vmcb->state.rflags; 1798 } 1799 1800 if (flags & NVMM_X64_STATE_CRS) { 1801 state->crs[NVMM_X64_CR_CR0] = vmcb->state.cr0; 1802 state->crs[NVMM_X64_CR_CR2] = vmcb->state.cr2; 1803 state->crs[NVMM_X64_CR_CR3] = vmcb->state.cr3; 1804 state->crs[NVMM_X64_CR_CR4] = vmcb->state.cr4; 1805 state->crs[NVMM_X64_CR_CR8] = __SHIFTOUT(vmcb->ctrl.v, 1806 VMCB_CTRL_V_TPR); 1807 state->crs[NVMM_X64_CR_XCR0] = cpudata->gxcr0; 1808 } 1809 1810 CTASSERT(sizeof(cpudata->drs) == sizeof(state->drs)); 1811 if (flags & NVMM_X64_STATE_DRS) { 1812 memcpy(state->drs, cpudata->drs, sizeof(state->drs)); 1813 1814 state->drs[NVMM_X64_DR_DR6] = vmcb->state.dr6; 1815 state->drs[NVMM_X64_DR_DR7] = vmcb->state.dr7; 1816 } 1817 1818 if (flags & NVMM_X64_STATE_MSRS) { 1819 state->msrs[NVMM_X64_MSR_EFER] = vmcb->state.efer; 1820 state->msrs[NVMM_X64_MSR_STAR] = vmcb->state.star; 1821 state->msrs[NVMM_X64_MSR_LSTAR] = vmcb->state.lstar; 1822 state->msrs[NVMM_X64_MSR_CSTAR] = vmcb->state.cstar; 1823 state->msrs[NVMM_X64_MSR_SFMASK] = vmcb->state.sfmask; 1824 state->msrs[NVMM_X64_MSR_KERNELGSBASE] = 1825 vmcb->state.kernelgsbase; 1826 state->msrs[NVMM_X64_MSR_SYSENTER_CS] = 1827 vmcb->state.sysenter_cs; 1828 state->msrs[NVMM_X64_MSR_SYSENTER_ESP] = 1829 vmcb->state.sysenter_esp; 1830 state->msrs[NVMM_X64_MSR_SYSENTER_EIP] = 1831 vmcb->state.sysenter_eip; 1832 state->msrs[NVMM_X64_MSR_PAT] = vmcb->state.g_pat; 1833 state->msrs[NVMM_X64_MSR_TSC] = cpudata->gtsc; 1834 1835 /* Hide SVME. */ 1836 state->msrs[NVMM_X64_MSR_EFER] &= ~EFER_SVME; 1837 } 1838 1839 if (flags & NVMM_X64_STATE_INTR) { 1840 state->intr.int_shadow = 1841 (vmcb->ctrl.intr & VMCB_CTRL_INTR_SHADOW) != 0; 1842 state->intr.int_window_exiting = cpudata->int_window_exit; 1843 state->intr.nmi_window_exiting = cpudata->nmi_window_exit; 1844 state->intr.evt_pending = cpudata->evt_pending; 1845 } 1846 1847 CTASSERT(sizeof(cpudata->gfpu.xsh_fxsave) == sizeof(state->fpu)); 1848 if (flags & NVMM_X64_STATE_FPU) { 1849 memcpy(&state->fpu, cpudata->gfpu.xsh_fxsave, 1850 sizeof(state->fpu)); 1851 } 1852 1853 comm->state_wanted = 0; 1854 comm->state_cached |= flags; 1855 } 1856 1857 static void 1858 svm_vcpu_state_provide(struct nvmm_cpu *vcpu, uint64_t flags) 1859 { 1860 vcpu->comm->state_wanted = flags; 1861 svm_vcpu_getstate(vcpu); 1862 } 1863 1864 static void 1865 svm_vcpu_state_commit(struct nvmm_cpu *vcpu) 1866 { 1867 vcpu->comm->state_wanted = vcpu->comm->state_commit; 1868 vcpu->comm->state_commit = 0; 1869 svm_vcpu_setstate(vcpu); 1870 } 1871 1872 /* -------------------------------------------------------------------------- */ 1873 1874 static void 1875 svm_asid_alloc(struct nvmm_cpu *vcpu) 1876 { 1877 struct svm_cpudata *cpudata = vcpu->cpudata; 1878 struct vmcb *vmcb = cpudata->vmcb; 1879 size_t i, oct, bit; 1880 1881 mutex_enter(&svm_asidlock); 1882 1883 for (i = 0; i < svm_maxasid; i++) { 1884 oct = i / 8; 1885 bit = i % 8; 1886 1887 if (svm_asidmap[oct] & __BIT(bit)) { 1888 continue; 1889 } 1890 1891 svm_asidmap[oct] |= __BIT(bit); 1892 vmcb->ctrl.guest_asid = i; 1893 mutex_exit(&svm_asidlock); 1894 return; 1895 } 1896 1897 /* 1898 * No free ASID. Use the last one, which is shared and requires 1899 * special TLB handling. 1900 */ 1901 cpudata->shared_asid = true; 1902 vmcb->ctrl.guest_asid = svm_maxasid - 1; 1903 mutex_exit(&svm_asidlock); 1904 } 1905 1906 static void 1907 svm_asid_free(struct nvmm_cpu *vcpu) 1908 { 1909 struct svm_cpudata *cpudata = vcpu->cpudata; 1910 struct vmcb *vmcb = cpudata->vmcb; 1911 size_t oct, bit; 1912 1913 if (cpudata->shared_asid) { 1914 return; 1915 } 1916 1917 oct = vmcb->ctrl.guest_asid / 8; 1918 bit = vmcb->ctrl.guest_asid % 8; 1919 1920 mutex_enter(&svm_asidlock); 1921 svm_asidmap[oct] &= ~__BIT(bit); 1922 mutex_exit(&svm_asidlock); 1923 } 1924 1925 static void 1926 svm_vcpu_init(struct nvmm_machine *mach, struct nvmm_cpu *vcpu) 1927 { 1928 struct svm_cpudata *cpudata = vcpu->cpudata; 1929 struct vmcb *vmcb = cpudata->vmcb; 1930 1931 /* Allow reads/writes of Control Registers. */ 1932 vmcb->ctrl.intercept_cr = 0; 1933 1934 /* Allow reads/writes of Debug Registers. */ 1935 vmcb->ctrl.intercept_dr = 0; 1936 1937 /* Allow exceptions 0 to 31. */ 1938 vmcb->ctrl.intercept_vec = 0; 1939 1940 /* 1941 * Allow: 1942 * - SMI [smm interrupts] 1943 * - VINTR [virtual interrupts] 1944 * - CR0_SPEC [CR0 writes changing other fields than CR0.TS or CR0.MP] 1945 * - RIDTR [reads of IDTR] 1946 * - RGDTR [reads of GDTR] 1947 * - RLDTR [reads of LDTR] 1948 * - RTR [reads of TR] 1949 * - WIDTR [writes of IDTR] 1950 * - WGDTR [writes of GDTR] 1951 * - WLDTR [writes of LDTR] 1952 * - WTR [writes of TR] 1953 * - RDTSC [rdtsc instruction] 1954 * - PUSHF [pushf instruction] 1955 * - POPF [popf instruction] 1956 * - IRET [iret instruction] 1957 * - INTN [int $n instructions] 1958 * - INVD [invd instruction] 1959 * - PAUSE [pause instruction] 1960 * - INVLPG [invplg instruction] 1961 * - TASKSW [task switches] 1962 * 1963 * Intercept the rest below. 1964 */ 1965 vmcb->ctrl.intercept_misc1 = 1966 VMCB_CTRL_INTERCEPT_INTR | 1967 VMCB_CTRL_INTERCEPT_NMI | 1968 VMCB_CTRL_INTERCEPT_INIT | 1969 VMCB_CTRL_INTERCEPT_RDPMC | 1970 VMCB_CTRL_INTERCEPT_CPUID | 1971 VMCB_CTRL_INTERCEPT_RSM | 1972 VMCB_CTRL_INTERCEPT_HLT | 1973 VMCB_CTRL_INTERCEPT_INVLPGA | 1974 VMCB_CTRL_INTERCEPT_IOIO_PROT | 1975 VMCB_CTRL_INTERCEPT_MSR_PROT | 1976 VMCB_CTRL_INTERCEPT_FERR_FREEZE | 1977 VMCB_CTRL_INTERCEPT_SHUTDOWN; 1978 1979 /* 1980 * Allow: 1981 * - ICEBP [icebp instruction] 1982 * - WBINVD [wbinvd instruction] 1983 * - WCR_SPEC(0..15) [writes of CR0-15, received after instruction] 1984 * 1985 * Intercept the rest below. 1986 */ 1987 vmcb->ctrl.intercept_misc2 = 1988 VMCB_CTRL_INTERCEPT_VMRUN | 1989 VMCB_CTRL_INTERCEPT_VMMCALL | 1990 VMCB_CTRL_INTERCEPT_VMLOAD | 1991 VMCB_CTRL_INTERCEPT_VMSAVE | 1992 VMCB_CTRL_INTERCEPT_STGI | 1993 VMCB_CTRL_INTERCEPT_CLGI | 1994 VMCB_CTRL_INTERCEPT_SKINIT | 1995 VMCB_CTRL_INTERCEPT_RDTSCP | 1996 VMCB_CTRL_INTERCEPT_MONITOR | 1997 VMCB_CTRL_INTERCEPT_MWAIT | 1998 VMCB_CTRL_INTERCEPT_XSETBV; 1999 2000 /* Intercept all I/O accesses. */ 2001 memset(cpudata->iobm, 0xFF, IOBM_SIZE); 2002 vmcb->ctrl.iopm_base_pa = cpudata->iobm_pa; 2003 2004 /* Allow direct access to certain MSRs. */ 2005 memset(cpudata->msrbm, 0xFF, MSRBM_SIZE); 2006 svm_vcpu_msr_allow(cpudata->msrbm, MSR_EFER, true, false); 2007 svm_vcpu_msr_allow(cpudata->msrbm, MSR_STAR, true, true); 2008 svm_vcpu_msr_allow(cpudata->msrbm, MSR_LSTAR, true, true); 2009 svm_vcpu_msr_allow(cpudata->msrbm, MSR_CSTAR, true, true); 2010 svm_vcpu_msr_allow(cpudata->msrbm, MSR_SFMASK, true, true); 2011 svm_vcpu_msr_allow(cpudata->msrbm, MSR_KERNELGSBASE, true, true); 2012 svm_vcpu_msr_allow(cpudata->msrbm, MSR_SYSENTER_CS, true, true); 2013 svm_vcpu_msr_allow(cpudata->msrbm, MSR_SYSENTER_ESP, true, true); 2014 svm_vcpu_msr_allow(cpudata->msrbm, MSR_SYSENTER_EIP, true, true); 2015 svm_vcpu_msr_allow(cpudata->msrbm, MSR_FSBASE, true, true); 2016 svm_vcpu_msr_allow(cpudata->msrbm, MSR_GSBASE, true, true); 2017 svm_vcpu_msr_allow(cpudata->msrbm, MSR_CR_PAT, true, true); 2018 svm_vcpu_msr_allow(cpudata->msrbm, MSR_TSC, true, false); 2019 vmcb->ctrl.msrpm_base_pa = cpudata->msrbm_pa; 2020 2021 /* Generate ASID. */ 2022 svm_asid_alloc(vcpu); 2023 2024 /* Virtual TPR. */ 2025 vmcb->ctrl.v = VMCB_CTRL_V_INTR_MASKING; 2026 2027 /* Enable Nested Paging. */ 2028 vmcb->ctrl.enable1 = VMCB_CTRL_ENABLE_NP; 2029 vmcb->ctrl.n_cr3 = mach->vm->vm_map.pmap->pm_pdirpa[0]; 2030 2031 /* Init XSAVE header. */ 2032 cpudata->gfpu.xsh_xstate_bv = svm_xcr0_mask; 2033 cpudata->gfpu.xsh_xcomp_bv = 0; 2034 2035 /* These MSRs are static. */ 2036 cpudata->star = rdmsr(MSR_STAR); 2037 cpudata->lstar = rdmsr(MSR_LSTAR); 2038 cpudata->cstar = rdmsr(MSR_CSTAR); 2039 cpudata->sfmask = rdmsr(MSR_SFMASK); 2040 2041 /* Install the RESET state. */ 2042 memcpy(&vcpu->comm->state, &nvmm_x86_reset_state, 2043 sizeof(nvmm_x86_reset_state)); 2044 vcpu->comm->state_wanted = NVMM_X64_STATE_ALL; 2045 vcpu->comm->state_cached = 0; 2046 svm_vcpu_setstate(vcpu); 2047 } 2048 2049 static int 2050 svm_vcpu_create(struct nvmm_machine *mach, struct nvmm_cpu *vcpu) 2051 { 2052 struct svm_cpudata *cpudata; 2053 int error; 2054 2055 /* Allocate the SVM cpudata. */ 2056 cpudata = (struct svm_cpudata *)uvm_km_alloc(kernel_map, 2057 roundup(sizeof(*cpudata), PAGE_SIZE), 0, 2058 UVM_KMF_WIRED|UVM_KMF_ZERO); 2059 vcpu->cpudata = cpudata; 2060 2061 /* VMCB */ 2062 error = svm_memalloc(&cpudata->vmcb_pa, (vaddr_t *)&cpudata->vmcb, 2063 VMCB_NPAGES); 2064 if (error) 2065 goto error; 2066 2067 /* I/O Bitmap */ 2068 error = svm_memalloc(&cpudata->iobm_pa, (vaddr_t *)&cpudata->iobm, 2069 IOBM_NPAGES); 2070 if (error) 2071 goto error; 2072 2073 /* MSR Bitmap */ 2074 error = svm_memalloc(&cpudata->msrbm_pa, (vaddr_t *)&cpudata->msrbm, 2075 MSRBM_NPAGES); 2076 if (error) 2077 goto error; 2078 2079 /* Init the VCPU info. */ 2080 svm_vcpu_init(mach, vcpu); 2081 2082 return 0; 2083 2084 error: 2085 if (cpudata->vmcb_pa) { 2086 svm_memfree(cpudata->vmcb_pa, (vaddr_t)cpudata->vmcb, 2087 VMCB_NPAGES); 2088 } 2089 if (cpudata->iobm_pa) { 2090 svm_memfree(cpudata->iobm_pa, (vaddr_t)cpudata->iobm, 2091 IOBM_NPAGES); 2092 } 2093 if (cpudata->msrbm_pa) { 2094 svm_memfree(cpudata->msrbm_pa, (vaddr_t)cpudata->msrbm, 2095 MSRBM_NPAGES); 2096 } 2097 uvm_km_free(kernel_map, (vaddr_t)cpudata, 2098 roundup(sizeof(*cpudata), PAGE_SIZE), UVM_KMF_WIRED); 2099 return error; 2100 } 2101 2102 static void 2103 svm_vcpu_destroy(struct nvmm_machine *mach, struct nvmm_cpu *vcpu) 2104 { 2105 struct svm_cpudata *cpudata = vcpu->cpudata; 2106 2107 svm_asid_free(vcpu); 2108 2109 svm_memfree(cpudata->vmcb_pa, (vaddr_t)cpudata->vmcb, VMCB_NPAGES); 2110 svm_memfree(cpudata->iobm_pa, (vaddr_t)cpudata->iobm, IOBM_NPAGES); 2111 svm_memfree(cpudata->msrbm_pa, (vaddr_t)cpudata->msrbm, MSRBM_NPAGES); 2112 2113 uvm_km_free(kernel_map, (vaddr_t)cpudata, 2114 roundup(sizeof(*cpudata), PAGE_SIZE), UVM_KMF_WIRED); 2115 } 2116 2117 /* -------------------------------------------------------------------------- */ 2118 2119 static void 2120 svm_tlb_flush(struct pmap *pm) 2121 { 2122 struct nvmm_machine *mach = pm->pm_data; 2123 struct svm_machdata *machdata = mach->machdata; 2124 2125 atomic_inc_64(&machdata->mach_htlb_gen); 2126 2127 /* Generates IPIs, which cause #VMEXITs. */ 2128 pmap_tlb_shootdown(pmap_kernel(), -1, PTE_G, TLBSHOOT_UPDATE); 2129 } 2130 2131 static void 2132 svm_machine_create(struct nvmm_machine *mach) 2133 { 2134 struct svm_machdata *machdata; 2135 2136 /* Fill in pmap info. */ 2137 mach->vm->vm_map.pmap->pm_data = (void *)mach; 2138 mach->vm->vm_map.pmap->pm_tlb_flush = svm_tlb_flush; 2139 2140 machdata = kmem_zalloc(sizeof(struct svm_machdata), KM_SLEEP); 2141 mach->machdata = machdata; 2142 2143 /* Start with an hTLB flush everywhere. */ 2144 machdata->mach_htlb_gen = 1; 2145 } 2146 2147 static void 2148 svm_machine_destroy(struct nvmm_machine *mach) 2149 { 2150 kmem_free(mach->machdata, sizeof(struct svm_machdata)); 2151 } 2152 2153 static int 2154 svm_machine_configure(struct nvmm_machine *mach, uint64_t op, void *data) 2155 { 2156 struct nvmm_mach_conf_x86_cpuid *cpuid = data; 2157 struct svm_machdata *machdata = (struct svm_machdata *)mach->machdata; 2158 size_t i; 2159 2160 if (__predict_false(op != NVMM_MACH_CONF_MD(NVMM_MACH_CONF_X86_CPUID))) { 2161 return EINVAL; 2162 } 2163 2164 if (__predict_false((cpuid->set.eax & cpuid->del.eax) || 2165 (cpuid->set.ebx & cpuid->del.ebx) || 2166 (cpuid->set.ecx & cpuid->del.ecx) || 2167 (cpuid->set.edx & cpuid->del.edx))) { 2168 return EINVAL; 2169 } 2170 2171 /* If already here, replace. */ 2172 for (i = 0; i < SVM_NCPUIDS; i++) { 2173 if (!machdata->cpuidpresent[i]) { 2174 continue; 2175 } 2176 if (machdata->cpuid[i].leaf == cpuid->leaf) { 2177 memcpy(&machdata->cpuid[i], cpuid, 2178 sizeof(struct nvmm_mach_conf_x86_cpuid)); 2179 return 0; 2180 } 2181 } 2182 2183 /* Not here, insert. */ 2184 for (i = 0; i < SVM_NCPUIDS; i++) { 2185 if (!machdata->cpuidpresent[i]) { 2186 machdata->cpuidpresent[i] = true; 2187 memcpy(&machdata->cpuid[i], cpuid, 2188 sizeof(struct nvmm_mach_conf_x86_cpuid)); 2189 return 0; 2190 } 2191 } 2192 2193 return ENOBUFS; 2194 } 2195 2196 /* -------------------------------------------------------------------------- */ 2197 2198 static bool 2199 svm_ident(void) 2200 { 2201 u_int descs[4]; 2202 uint64_t msr; 2203 2204 if (cpu_vendor != CPUVENDOR_AMD) { 2205 return false; 2206 } 2207 if (!(cpu_feature[3] & CPUID_SVM)) { 2208 return false; 2209 } 2210 2211 if (curcpu()->ci_max_ext_cpuid < 0x8000000a) { 2212 return false; 2213 } 2214 x86_cpuid(0x8000000a, descs); 2215 2216 /* Want Nested Paging. */ 2217 if (!(descs[3] & CPUID_AMD_SVM_NP)) { 2218 return false; 2219 } 2220 2221 /* Want nRIP. */ 2222 if (!(descs[3] & CPUID_AMD_SVM_NRIPS)) { 2223 return false; 2224 } 2225 2226 svm_decode_assist = (descs[3] & CPUID_AMD_SVM_DecodeAssist) != 0; 2227 2228 msr = rdmsr(MSR_VMCR); 2229 if ((msr & VMCR_SVMED) && (msr & VMCR_LOCK)) { 2230 return false; 2231 } 2232 2233 return true; 2234 } 2235 2236 static void 2237 svm_init_asid(uint32_t maxasid) 2238 { 2239 size_t i, j, allocsz; 2240 2241 mutex_init(&svm_asidlock, MUTEX_DEFAULT, IPL_NONE); 2242 2243 /* Arbitrarily limit. */ 2244 maxasid = uimin(maxasid, 8192); 2245 2246 svm_maxasid = maxasid; 2247 allocsz = roundup(maxasid, 8) / 8; 2248 svm_asidmap = kmem_zalloc(allocsz, KM_SLEEP); 2249 2250 /* ASID 0 is reserved for the host. */ 2251 svm_asidmap[0] |= __BIT(0); 2252 2253 /* ASID n-1 is special, we share it. */ 2254 i = (maxasid - 1) / 8; 2255 j = (maxasid - 1) % 8; 2256 svm_asidmap[i] |= __BIT(j); 2257 } 2258 2259 static void 2260 svm_change_cpu(void *arg1, void *arg2) 2261 { 2262 bool enable = (bool)arg1; 2263 uint64_t msr; 2264 2265 msr = rdmsr(MSR_VMCR); 2266 if (msr & VMCR_SVMED) { 2267 wrmsr(MSR_VMCR, msr & ~VMCR_SVMED); 2268 } 2269 2270 if (!enable) { 2271 wrmsr(MSR_VM_HSAVE_PA, 0); 2272 } 2273 2274 msr = rdmsr(MSR_EFER); 2275 if (enable) { 2276 msr |= EFER_SVME; 2277 } else { 2278 msr &= ~EFER_SVME; 2279 } 2280 wrmsr(MSR_EFER, msr); 2281 2282 if (enable) { 2283 wrmsr(MSR_VM_HSAVE_PA, hsave[cpu_index(curcpu())].pa); 2284 } 2285 } 2286 2287 static void 2288 svm_init(void) 2289 { 2290 CPU_INFO_ITERATOR cii; 2291 struct cpu_info *ci; 2292 struct vm_page *pg; 2293 u_int descs[4]; 2294 uint64_t xc; 2295 2296 x86_cpuid(0x8000000a, descs); 2297 2298 /* The guest TLB flush command. */ 2299 if (descs[3] & CPUID_AMD_SVM_FlushByASID) { 2300 svm_ctrl_tlb_flush = VMCB_CTRL_TLB_CTRL_FLUSH_GUEST; 2301 } else { 2302 svm_ctrl_tlb_flush = VMCB_CTRL_TLB_CTRL_FLUSH_ALL; 2303 } 2304 2305 /* Init the ASID. */ 2306 svm_init_asid(descs[1]); 2307 2308 /* Init the XCR0 mask. */ 2309 svm_xcr0_mask = SVM_XCR0_MASK_DEFAULT & x86_xsave_features; 2310 2311 memset(hsave, 0, sizeof(hsave)); 2312 for (CPU_INFO_FOREACH(cii, ci)) { 2313 pg = uvm_pagealloc(NULL, 0, NULL, UVM_PGA_ZERO); 2314 hsave[cpu_index(ci)].pa = VM_PAGE_TO_PHYS(pg); 2315 } 2316 2317 xc = xc_broadcast(0, svm_change_cpu, (void *)true, NULL); 2318 xc_wait(xc); 2319 } 2320 2321 static void 2322 svm_fini_asid(void) 2323 { 2324 size_t allocsz; 2325 2326 allocsz = roundup(svm_maxasid, 8) / 8; 2327 kmem_free(svm_asidmap, allocsz); 2328 2329 mutex_destroy(&svm_asidlock); 2330 } 2331 2332 static void 2333 svm_fini(void) 2334 { 2335 uint64_t xc; 2336 size_t i; 2337 2338 xc = xc_broadcast(0, svm_change_cpu, (void *)false, NULL); 2339 xc_wait(xc); 2340 2341 for (i = 0; i < MAXCPUS; i++) { 2342 if (hsave[i].pa != 0) 2343 uvm_pagefree(PHYS_TO_VM_PAGE(hsave[i].pa)); 2344 } 2345 2346 svm_fini_asid(); 2347 } 2348 2349 static void 2350 svm_capability(struct nvmm_capability *cap) 2351 { 2352 cap->arch.xcr0_mask = svm_xcr0_mask; 2353 cap->arch.mxcsr_mask = x86_fpu_mxcsr_mask; 2354 cap->arch.conf_cpuid_maxops = SVM_NCPUIDS; 2355 } 2356 2357 const struct nvmm_impl nvmm_x86_svm = { 2358 .ident = svm_ident, 2359 .init = svm_init, 2360 .fini = svm_fini, 2361 .capability = svm_capability, 2362 .conf_max = NVMM_X86_NCONF, 2363 .conf_sizes = svm_conf_sizes, 2364 .state_size = sizeof(struct nvmm_x64_state), 2365 .machine_create = svm_machine_create, 2366 .machine_destroy = svm_machine_destroy, 2367 .machine_configure = svm_machine_configure, 2368 .vcpu_create = svm_vcpu_create, 2369 .vcpu_destroy = svm_vcpu_destroy, 2370 .vcpu_setstate = svm_vcpu_setstate, 2371 .vcpu_getstate = svm_vcpu_getstate, 2372 .vcpu_inject = svm_vcpu_inject, 2373 .vcpu_run = svm_vcpu_run 2374 }; 2375
Indexes created Thu Oct 02 01:09:59 GMT 2025