nvmm_x86_svm.c revision 1.63
1 /* $NetBSD: nvmm_x86_svm.c,v 1.63 2020/07/03 16:09:54 maxv Exp $ */ 2 3 /* 4 * Copyright (c) 2018-2020 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Maxime Villard. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: nvmm_x86_svm.c,v 1.63 2020/07/03 16:09:54 maxv Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/kmem.h> 39 #include <sys/cpu.h> 40 #include <sys/xcall.h> 41 #include <sys/mman.h> 42 43 #include <uvm/uvm.h> 44 #include <uvm/uvm_page.h> 45 46 #include <x86/cputypes.h> 47 #include <x86/specialreg.h> 48 #include <x86/pmap.h> 49 #include <x86/dbregs.h> 50 #include <x86/cpu_counter.h> 51 #include <machine/cpuvar.h> 52 53 #include <dev/nvmm/nvmm.h> 54 #include <dev/nvmm/nvmm_internal.h> 55 #include <dev/nvmm/x86/nvmm_x86.h> 56 57 int svm_vmrun(paddr_t, uint64_t *); 58 59 #define MSR_VM_HSAVE_PA 0xC0010117 60 61 /* -------------------------------------------------------------------------- */ 62 63 #define VMCB_EXITCODE_CR0_READ 0x0000 64 #define VMCB_EXITCODE_CR1_READ 0x0001 65 #define VMCB_EXITCODE_CR2_READ 0x0002 66 #define VMCB_EXITCODE_CR3_READ 0x0003 67 #define VMCB_EXITCODE_CR4_READ 0x0004 68 #define VMCB_EXITCODE_CR5_READ 0x0005 69 #define VMCB_EXITCODE_CR6_READ 0x0006 70 #define VMCB_EXITCODE_CR7_READ 0x0007 71 #define VMCB_EXITCODE_CR8_READ 0x0008 72 #define VMCB_EXITCODE_CR9_READ 0x0009 73 #define VMCB_EXITCODE_CR10_READ 0x000A 74 #define VMCB_EXITCODE_CR11_READ 0x000B 75 #define VMCB_EXITCODE_CR12_READ 0x000C 76 #define VMCB_EXITCODE_CR13_READ 0x000D 77 #define VMCB_EXITCODE_CR14_READ 0x000E 78 #define VMCB_EXITCODE_CR15_READ 0x000F 79 #define VMCB_EXITCODE_CR0_WRITE 0x0010 80 #define VMCB_EXITCODE_CR1_WRITE 0x0011 81 #define VMCB_EXITCODE_CR2_WRITE 0x0012 82 #define VMCB_EXITCODE_CR3_WRITE 0x0013 83 #define VMCB_EXITCODE_CR4_WRITE 0x0014 84 #define VMCB_EXITCODE_CR5_WRITE 0x0015 85 #define VMCB_EXITCODE_CR6_WRITE 0x0016 86 #define VMCB_EXITCODE_CR7_WRITE 0x0017 87 #define VMCB_EXITCODE_CR8_WRITE 0x0018 88 #define VMCB_EXITCODE_CR9_WRITE 0x0019 89 #define VMCB_EXITCODE_CR10_WRITE 0x001A 90 #define VMCB_EXITCODE_CR11_WRITE 0x001B 91 #define VMCB_EXITCODE_CR12_WRITE 0x001C 92 #define VMCB_EXITCODE_CR13_WRITE 0x001D 93 #define VMCB_EXITCODE_CR14_WRITE 0x001E 94 #define VMCB_EXITCODE_CR15_WRITE 0x001F 95 #define VMCB_EXITCODE_DR0_READ 0x0020 96 #define VMCB_EXITCODE_DR1_READ 0x0021 97 #define VMCB_EXITCODE_DR2_READ 0x0022 98 #define VMCB_EXITCODE_DR3_READ 0x0023 99 #define VMCB_EXITCODE_DR4_READ 0x0024 100 #define VMCB_EXITCODE_DR5_READ 0x0025 101 #define VMCB_EXITCODE_DR6_READ 0x0026 102 #define VMCB_EXITCODE_DR7_READ 0x0027 103 #define VMCB_EXITCODE_DR8_READ 0x0028 104 #define VMCB_EXITCODE_DR9_READ 0x0029 105 #define VMCB_EXITCODE_DR10_READ 0x002A 106 #define VMCB_EXITCODE_DR11_READ 0x002B 107 #define VMCB_EXITCODE_DR12_READ 0x002C 108 #define VMCB_EXITCODE_DR13_READ 0x002D 109 #define VMCB_EXITCODE_DR14_READ 0x002E 110 #define VMCB_EXITCODE_DR15_READ 0x002F 111 #define VMCB_EXITCODE_DR0_WRITE 0x0030 112 #define VMCB_EXITCODE_DR1_WRITE 0x0031 113 #define VMCB_EXITCODE_DR2_WRITE 0x0032 114 #define VMCB_EXITCODE_DR3_WRITE 0x0033 115 #define VMCB_EXITCODE_DR4_WRITE 0x0034 116 #define VMCB_EXITCODE_DR5_WRITE 0x0035 117 #define VMCB_EXITCODE_DR6_WRITE 0x0036 118 #define VMCB_EXITCODE_DR7_WRITE 0x0037 119 #define VMCB_EXITCODE_DR8_WRITE 0x0038 120 #define VMCB_EXITCODE_DR9_WRITE 0x0039 121 #define VMCB_EXITCODE_DR10_WRITE 0x003A 122 #define VMCB_EXITCODE_DR11_WRITE 0x003B 123 #define VMCB_EXITCODE_DR12_WRITE 0x003C 124 #define VMCB_EXITCODE_DR13_WRITE 0x003D 125 #define VMCB_EXITCODE_DR14_WRITE 0x003E 126 #define VMCB_EXITCODE_DR15_WRITE 0x003F 127 #define VMCB_EXITCODE_EXCP0 0x0040 128 #define VMCB_EXITCODE_EXCP1 0x0041 129 #define VMCB_EXITCODE_EXCP2 0x0042 130 #define VMCB_EXITCODE_EXCP3 0x0043 131 #define VMCB_EXITCODE_EXCP4 0x0044 132 #define VMCB_EXITCODE_EXCP5 0x0045 133 #define VMCB_EXITCODE_EXCP6 0x0046 134 #define VMCB_EXITCODE_EXCP7 0x0047 135 #define VMCB_EXITCODE_EXCP8 0x0048 136 #define VMCB_EXITCODE_EXCP9 0x0049 137 #define VMCB_EXITCODE_EXCP10 0x004A 138 #define VMCB_EXITCODE_EXCP11 0x004B 139 #define VMCB_EXITCODE_EXCP12 0x004C 140 #define VMCB_EXITCODE_EXCP13 0x004D 141 #define VMCB_EXITCODE_EXCP14 0x004E 142 #define VMCB_EXITCODE_EXCP15 0x004F 143 #define VMCB_EXITCODE_EXCP16 0x0050 144 #define VMCB_EXITCODE_EXCP17 0x0051 145 #define VMCB_EXITCODE_EXCP18 0x0052 146 #define VMCB_EXITCODE_EXCP19 0x0053 147 #define VMCB_EXITCODE_EXCP20 0x0054 148 #define VMCB_EXITCODE_EXCP21 0x0055 149 #define VMCB_EXITCODE_EXCP22 0x0056 150 #define VMCB_EXITCODE_EXCP23 0x0057 151 #define VMCB_EXITCODE_EXCP24 0x0058 152 #define VMCB_EXITCODE_EXCP25 0x0059 153 #define VMCB_EXITCODE_EXCP26 0x005A 154 #define VMCB_EXITCODE_EXCP27 0x005B 155 #define VMCB_EXITCODE_EXCP28 0x005C 156 #define VMCB_EXITCODE_EXCP29 0x005D 157 #define VMCB_EXITCODE_EXCP30 0x005E 158 #define VMCB_EXITCODE_EXCP31 0x005F 159 #define VMCB_EXITCODE_INTR 0x0060 160 #define VMCB_EXITCODE_NMI 0x0061 161 #define VMCB_EXITCODE_SMI 0x0062 162 #define VMCB_EXITCODE_INIT 0x0063 163 #define VMCB_EXITCODE_VINTR 0x0064 164 #define VMCB_EXITCODE_CR0_SEL_WRITE 0x0065 165 #define VMCB_EXITCODE_IDTR_READ 0x0066 166 #define VMCB_EXITCODE_GDTR_READ 0x0067 167 #define VMCB_EXITCODE_LDTR_READ 0x0068 168 #define VMCB_EXITCODE_TR_READ 0x0069 169 #define VMCB_EXITCODE_IDTR_WRITE 0x006A 170 #define VMCB_EXITCODE_GDTR_WRITE 0x006B 171 #define VMCB_EXITCODE_LDTR_WRITE 0x006C 172 #define VMCB_EXITCODE_TR_WRITE 0x006D 173 #define VMCB_EXITCODE_RDTSC 0x006E 174 #define VMCB_EXITCODE_RDPMC 0x006F 175 #define VMCB_EXITCODE_PUSHF 0x0070 176 #define VMCB_EXITCODE_POPF 0x0071 177 #define VMCB_EXITCODE_CPUID 0x0072 178 #define VMCB_EXITCODE_RSM 0x0073 179 #define VMCB_EXITCODE_IRET 0x0074 180 #define VMCB_EXITCODE_SWINT 0x0075 181 #define VMCB_EXITCODE_INVD 0x0076 182 #define VMCB_EXITCODE_PAUSE 0x0077 183 #define VMCB_EXITCODE_HLT 0x0078 184 #define VMCB_EXITCODE_INVLPG 0x0079 185 #define VMCB_EXITCODE_INVLPGA 0x007A 186 #define VMCB_EXITCODE_IOIO 0x007B 187 #define VMCB_EXITCODE_MSR 0x007C 188 #define VMCB_EXITCODE_TASK_SWITCH 0x007D 189 #define VMCB_EXITCODE_FERR_FREEZE 0x007E 190 #define VMCB_EXITCODE_SHUTDOWN 0x007F 191 #define VMCB_EXITCODE_VMRUN 0x0080 192 #define VMCB_EXITCODE_VMMCALL 0x0081 193 #define VMCB_EXITCODE_VMLOAD 0x0082 194 #define VMCB_EXITCODE_VMSAVE 0x0083 195 #define VMCB_EXITCODE_STGI 0x0084 196 #define VMCB_EXITCODE_CLGI 0x0085 197 #define VMCB_EXITCODE_SKINIT 0x0086 198 #define VMCB_EXITCODE_RDTSCP 0x0087 199 #define VMCB_EXITCODE_ICEBP 0x0088 200 #define VMCB_EXITCODE_WBINVD 0x0089 201 #define VMCB_EXITCODE_MONITOR 0x008A 202 #define VMCB_EXITCODE_MWAIT 0x008B 203 #define VMCB_EXITCODE_MWAIT_CONDITIONAL 0x008C 204 #define VMCB_EXITCODE_XSETBV 0x008D 205 #define VMCB_EXITCODE_RDPRU 0x008E 206 #define VMCB_EXITCODE_EFER_WRITE_TRAP 0x008F 207 #define VMCB_EXITCODE_CR0_WRITE_TRAP 0x0090 208 #define VMCB_EXITCODE_CR1_WRITE_TRAP 0x0091 209 #define VMCB_EXITCODE_CR2_WRITE_TRAP 0x0092 210 #define VMCB_EXITCODE_CR3_WRITE_TRAP 0x0093 211 #define VMCB_EXITCODE_CR4_WRITE_TRAP 0x0094 212 #define VMCB_EXITCODE_CR5_WRITE_TRAP 0x0095 213 #define VMCB_EXITCODE_CR6_WRITE_TRAP 0x0096 214 #define VMCB_EXITCODE_CR7_WRITE_TRAP 0x0097 215 #define VMCB_EXITCODE_CR8_WRITE_TRAP 0x0098 216 #define VMCB_EXITCODE_CR9_WRITE_TRAP 0x0099 217 #define VMCB_EXITCODE_CR10_WRITE_TRAP 0x009A 218 #define VMCB_EXITCODE_CR11_WRITE_TRAP 0x009B 219 #define VMCB_EXITCODE_CR12_WRITE_TRAP 0x009C 220 #define VMCB_EXITCODE_CR13_WRITE_TRAP 0x009D 221 #define VMCB_EXITCODE_CR14_WRITE_TRAP 0x009E 222 #define VMCB_EXITCODE_CR15_WRITE_TRAP 0x009F 223 #define VMCB_EXITCODE_MCOMMIT 0x00A3 224 #define VMCB_EXITCODE_NPF 0x0400 225 #define VMCB_EXITCODE_AVIC_INCOMP_IPI 0x0401 226 #define VMCB_EXITCODE_AVIC_NOACCEL 0x0402 227 #define VMCB_EXITCODE_VMGEXIT 0x0403 228 #define VMCB_EXITCODE_INVALID -1 229 230 /* -------------------------------------------------------------------------- */ 231 232 struct vmcb_ctrl { 233 uint32_t intercept_cr; 234 #define VMCB_CTRL_INTERCEPT_RCR(x) __BIT( 0 + x) 235 #define VMCB_CTRL_INTERCEPT_WCR(x) __BIT(16 + x) 236 237 uint32_t intercept_dr; 238 #define VMCB_CTRL_INTERCEPT_RDR(x) __BIT( 0 + x) 239 #define VMCB_CTRL_INTERCEPT_WDR(x) __BIT(16 + x) 240 241 uint32_t intercept_vec; 242 #define VMCB_CTRL_INTERCEPT_VEC(x) __BIT(x) 243 244 uint32_t intercept_misc1; 245 #define VMCB_CTRL_INTERCEPT_INTR __BIT(0) 246 #define VMCB_CTRL_INTERCEPT_NMI __BIT(1) 247 #define VMCB_CTRL_INTERCEPT_SMI __BIT(2) 248 #define VMCB_CTRL_INTERCEPT_INIT __BIT(3) 249 #define VMCB_CTRL_INTERCEPT_VINTR __BIT(4) 250 #define VMCB_CTRL_INTERCEPT_CR0_SPEC __BIT(5) 251 #define VMCB_CTRL_INTERCEPT_RIDTR __BIT(6) 252 #define VMCB_CTRL_INTERCEPT_RGDTR __BIT(7) 253 #define VMCB_CTRL_INTERCEPT_RLDTR __BIT(8) 254 #define VMCB_CTRL_INTERCEPT_RTR __BIT(9) 255 #define VMCB_CTRL_INTERCEPT_WIDTR __BIT(10) 256 #define VMCB_CTRL_INTERCEPT_WGDTR __BIT(11) 257 #define VMCB_CTRL_INTERCEPT_WLDTR __BIT(12) 258 #define VMCB_CTRL_INTERCEPT_WTR __BIT(13) 259 #define VMCB_CTRL_INTERCEPT_RDTSC __BIT(14) 260 #define VMCB_CTRL_INTERCEPT_RDPMC __BIT(15) 261 #define VMCB_CTRL_INTERCEPT_PUSHF __BIT(16) 262 #define VMCB_CTRL_INTERCEPT_POPF __BIT(17) 263 #define VMCB_CTRL_INTERCEPT_CPUID __BIT(18) 264 #define VMCB_CTRL_INTERCEPT_RSM __BIT(19) 265 #define VMCB_CTRL_INTERCEPT_IRET __BIT(20) 266 #define VMCB_CTRL_INTERCEPT_INTN __BIT(21) 267 #define VMCB_CTRL_INTERCEPT_INVD __BIT(22) 268 #define VMCB_CTRL_INTERCEPT_PAUSE __BIT(23) 269 #define VMCB_CTRL_INTERCEPT_HLT __BIT(24) 270 #define VMCB_CTRL_INTERCEPT_INVLPG __BIT(25) 271 #define VMCB_CTRL_INTERCEPT_INVLPGA __BIT(26) 272 #define VMCB_CTRL_INTERCEPT_IOIO_PROT __BIT(27) 273 #define VMCB_CTRL_INTERCEPT_MSR_PROT __BIT(28) 274 #define VMCB_CTRL_INTERCEPT_TASKSW __BIT(29) 275 #define VMCB_CTRL_INTERCEPT_FERR_FREEZE __BIT(30) 276 #define VMCB_CTRL_INTERCEPT_SHUTDOWN __BIT(31) 277 278 uint32_t intercept_misc2; 279 #define VMCB_CTRL_INTERCEPT_VMRUN __BIT(0) 280 #define VMCB_CTRL_INTERCEPT_VMMCALL __BIT(1) 281 #define VMCB_CTRL_INTERCEPT_VMLOAD __BIT(2) 282 #define VMCB_CTRL_INTERCEPT_VMSAVE __BIT(3) 283 #define VMCB_CTRL_INTERCEPT_STGI __BIT(4) 284 #define VMCB_CTRL_INTERCEPT_CLGI __BIT(5) 285 #define VMCB_CTRL_INTERCEPT_SKINIT __BIT(6) 286 #define VMCB_CTRL_INTERCEPT_RDTSCP __BIT(7) 287 #define VMCB_CTRL_INTERCEPT_ICEBP __BIT(8) 288 #define VMCB_CTRL_INTERCEPT_WBINVD __BIT(9) 289 #define VMCB_CTRL_INTERCEPT_MONITOR __BIT(10) 290 #define VMCB_CTRL_INTERCEPT_MWAIT __BIT(11) 291 #define VMCB_CTRL_INTERCEPT_MWAIT_ARMED __BIT(12) 292 #define VMCB_CTRL_INTERCEPT_XSETBV __BIT(13) 293 #define VMCB_CTRL_INTERCEPT_RDPRU __BIT(14) 294 #define VMCB_CTRL_INTERCEPT_EFER_SPEC __BIT(15) 295 #define VMCB_CTRL_INTERCEPT_WCR_SPEC(x) __BIT(16 + x) 296 297 uint32_t intercept_misc3; 298 #define VMCB_CTRL_INTERCEPT_MCOMMIT __BIT(3) 299 300 uint8_t rsvd1[36]; 301 uint16_t pause_filt_thresh; 302 uint16_t pause_filt_cnt; 303 uint64_t iopm_base_pa; 304 uint64_t msrpm_base_pa; 305 uint64_t tsc_offset; 306 uint32_t guest_asid; 307 308 uint32_t tlb_ctrl; 309 #define VMCB_CTRL_TLB_CTRL_FLUSH_ALL 0x01 310 #define VMCB_CTRL_TLB_CTRL_FLUSH_GUEST 0x03 311 #define VMCB_CTRL_TLB_CTRL_FLUSH_GUEST_NONGLOBAL 0x07 312 313 uint64_t v; 314 #define VMCB_CTRL_V_TPR __BITS(3,0) 315 #define VMCB_CTRL_V_IRQ __BIT(8) 316 #define VMCB_CTRL_V_VGIF __BIT(9) 317 #define VMCB_CTRL_V_INTR_PRIO __BITS(19,16) 318 #define VMCB_CTRL_V_IGN_TPR __BIT(20) 319 #define VMCB_CTRL_V_INTR_MASKING __BIT(24) 320 #define VMCB_CTRL_V_GUEST_VGIF __BIT(25) 321 #define VMCB_CTRL_V_AVIC_EN __BIT(31) 322 #define VMCB_CTRL_V_INTR_VECTOR __BITS(39,32) 323 324 uint64_t intr; 325 #define VMCB_CTRL_INTR_SHADOW __BIT(0) 326 327 uint64_t exitcode; 328 uint64_t exitinfo1; 329 uint64_t exitinfo2; 330 331 uint64_t exitintinfo; 332 #define VMCB_CTRL_EXITINTINFO_VECTOR __BITS(7,0) 333 #define VMCB_CTRL_EXITINTINFO_TYPE __BITS(10,8) 334 #define VMCB_CTRL_EXITINTINFO_EV __BIT(11) 335 #define VMCB_CTRL_EXITINTINFO_V __BIT(31) 336 #define VMCB_CTRL_EXITINTINFO_ERRORCODE __BITS(63,32) 337 338 uint64_t enable1; 339 #define VMCB_CTRL_ENABLE_NP __BIT(0) 340 #define VMCB_CTRL_ENABLE_SEV __BIT(1) 341 #define VMCB_CTRL_ENABLE_ES_SEV __BIT(2) 342 #define VMCB_CTRL_ENABLE_GMET __BIT(3) 343 #define VMCB_CTRL_ENABLE_VTE __BIT(5) 344 345 uint64_t avic; 346 #define VMCB_CTRL_AVIC_APIC_BAR __BITS(51,0) 347 348 uint64_t ghcb; 349 350 uint64_t eventinj; 351 #define VMCB_CTRL_EVENTINJ_VECTOR __BITS(7,0) 352 #define VMCB_CTRL_EVENTINJ_TYPE __BITS(10,8) 353 #define VMCB_CTRL_EVENTINJ_EV __BIT(11) 354 #define VMCB_CTRL_EVENTINJ_V __BIT(31) 355 #define VMCB_CTRL_EVENTINJ_ERRORCODE __BITS(63,32) 356 357 uint64_t n_cr3; 358 359 uint64_t enable2; 360 #define VMCB_CTRL_ENABLE_LBR __BIT(0) 361 #define VMCB_CTRL_ENABLE_VVMSAVE __BIT(1) 362 363 uint32_t vmcb_clean; 364 #define VMCB_CTRL_VMCB_CLEAN_I __BIT(0) 365 #define VMCB_CTRL_VMCB_CLEAN_IOPM __BIT(1) 366 #define VMCB_CTRL_VMCB_CLEAN_ASID __BIT(2) 367 #define VMCB_CTRL_VMCB_CLEAN_TPR __BIT(3) 368 #define VMCB_CTRL_VMCB_CLEAN_NP __BIT(4) 369 #define VMCB_CTRL_VMCB_CLEAN_CR __BIT(5) 370 #define VMCB_CTRL_VMCB_CLEAN_DR __BIT(6) 371 #define VMCB_CTRL_VMCB_CLEAN_DT __BIT(7) 372 #define VMCB_CTRL_VMCB_CLEAN_SEG __BIT(8) 373 #define VMCB_CTRL_VMCB_CLEAN_CR2 __BIT(9) 374 #define VMCB_CTRL_VMCB_CLEAN_LBR __BIT(10) 375 #define VMCB_CTRL_VMCB_CLEAN_AVIC __BIT(11) 376 377 uint32_t rsvd2; 378 uint64_t nrip; 379 uint8_t inst_len; 380 uint8_t inst_bytes[15]; 381 uint64_t avic_abpp; 382 uint64_t rsvd3; 383 uint64_t avic_ltp; 384 385 uint64_t avic_phys; 386 #define VMCB_CTRL_AVIC_PHYS_TABLE_PTR __BITS(51,12) 387 #define VMCB_CTRL_AVIC_PHYS_MAX_INDEX __BITS(7,0) 388 389 uint64_t rsvd4; 390 uint64_t vmcb_ptr; 391 392 uint8_t pad[752]; 393 } __packed; 394 395 CTASSERT(sizeof(struct vmcb_ctrl) == 1024); 396 397 struct vmcb_segment { 398 uint16_t selector; 399 uint16_t attrib; /* hidden */ 400 uint32_t limit; /* hidden */ 401 uint64_t base; /* hidden */ 402 } __packed; 403 404 CTASSERT(sizeof(struct vmcb_segment) == 16); 405 406 struct vmcb_state { 407 struct vmcb_segment es; 408 struct vmcb_segment cs; 409 struct vmcb_segment ss; 410 struct vmcb_segment ds; 411 struct vmcb_segment fs; 412 struct vmcb_segment gs; 413 struct vmcb_segment gdt; 414 struct vmcb_segment ldt; 415 struct vmcb_segment idt; 416 struct vmcb_segment tr; 417 uint8_t rsvd1[43]; 418 uint8_t cpl; 419 uint8_t rsvd2[4]; 420 uint64_t efer; 421 uint8_t rsvd3[112]; 422 uint64_t cr4; 423 uint64_t cr3; 424 uint64_t cr0; 425 uint64_t dr7; 426 uint64_t dr6; 427 uint64_t rflags; 428 uint64_t rip; 429 uint8_t rsvd4[88]; 430 uint64_t rsp; 431 uint8_t rsvd5[24]; 432 uint64_t rax; 433 uint64_t star; 434 uint64_t lstar; 435 uint64_t cstar; 436 uint64_t sfmask; 437 uint64_t kernelgsbase; 438 uint64_t sysenter_cs; 439 uint64_t sysenter_esp; 440 uint64_t sysenter_eip; 441 uint64_t cr2; 442 uint8_t rsvd6[32]; 443 uint64_t g_pat; 444 uint64_t dbgctl; 445 uint64_t br_from; 446 uint64_t br_to; 447 uint64_t int_from; 448 uint64_t int_to; 449 uint8_t pad[2408]; 450 } __packed; 451 452 CTASSERT(sizeof(struct vmcb_state) == 0xC00); 453 454 struct vmcb { 455 struct vmcb_ctrl ctrl; 456 struct vmcb_state state; 457 } __packed; 458 459 CTASSERT(sizeof(struct vmcb) == PAGE_SIZE); 460 CTASSERT(offsetof(struct vmcb, state) == 0x400); 461 462 /* -------------------------------------------------------------------------- */ 463 464 static void svm_vcpu_state_provide(struct nvmm_cpu *, uint64_t); 465 static void svm_vcpu_state_commit(struct nvmm_cpu *); 466 467 struct svm_hsave { 468 paddr_t pa; 469 }; 470 471 static struct svm_hsave hsave[MAXCPUS]; 472 473 static uint8_t *svm_asidmap __read_mostly; 474 static uint32_t svm_maxasid __read_mostly; 475 static kmutex_t svm_asidlock __cacheline_aligned; 476 477 static bool svm_decode_assist __read_mostly; 478 static uint32_t svm_ctrl_tlb_flush __read_mostly; 479 480 #define SVM_XCR0_MASK_DEFAULT (XCR0_X87|XCR0_SSE) 481 static uint64_t svm_xcr0_mask __read_mostly; 482 483 #define SVM_NCPUIDS 32 484 485 #define VMCB_NPAGES 1 486 487 #define MSRBM_NPAGES 2 488 #define MSRBM_SIZE (MSRBM_NPAGES * PAGE_SIZE) 489 490 #define IOBM_NPAGES 3 491 #define IOBM_SIZE (IOBM_NPAGES * PAGE_SIZE) 492 493 /* Does not include EFER_LMSLE. */ 494 #define EFER_VALID \ 495 (EFER_SCE|EFER_LME|EFER_LMA|EFER_NXE|EFER_SVME|EFER_FFXSR|EFER_TCE) 496 497 #define EFER_TLB_FLUSH \ 498 (EFER_NXE|EFER_LMA|EFER_LME) 499 #define CR0_TLB_FLUSH \ 500 (CR0_PG|CR0_WP|CR0_CD|CR0_NW) 501 #define CR4_TLB_FLUSH \ 502 (CR4_PGE|CR4_PAE|CR4_PSE) 503 504 /* -------------------------------------------------------------------------- */ 505 506 struct svm_machdata { 507 volatile uint64_t mach_htlb_gen; 508 }; 509 510 static const size_t svm_vcpu_conf_sizes[NVMM_X86_VCPU_NCONF] = { 511 [NVMM_VCPU_CONF_MD(NVMM_VCPU_CONF_CPUID)] = 512 sizeof(struct nvmm_vcpu_conf_cpuid), 513 [NVMM_VCPU_CONF_MD(NVMM_VCPU_CONF_TPR)] = 514 sizeof(struct nvmm_vcpu_conf_tpr) 515 }; 516 517 struct svm_cpudata { 518 /* General */ 519 bool shared_asid; 520 bool gtlb_want_flush; 521 bool gtsc_want_update; 522 uint64_t vcpu_htlb_gen; 523 524 /* VMCB */ 525 struct vmcb *vmcb; 526 paddr_t vmcb_pa; 527 528 /* I/O bitmap */ 529 uint8_t *iobm; 530 paddr_t iobm_pa; 531 532 /* MSR bitmap */ 533 uint8_t *msrbm; 534 paddr_t msrbm_pa; 535 536 /* Host state */ 537 uint64_t hxcr0; 538 uint64_t star; 539 uint64_t lstar; 540 uint64_t cstar; 541 uint64_t sfmask; 542 uint64_t fsbase; 543 uint64_t kernelgsbase; 544 545 /* Intr state */ 546 bool int_window_exit; 547 bool nmi_window_exit; 548 bool evt_pending; 549 550 /* Guest state */ 551 uint64_t gxcr0; 552 uint64_t gprs[NVMM_X64_NGPR]; 553 uint64_t drs[NVMM_X64_NDR]; 554 uint64_t gtsc; 555 struct xsave_header gfpu __aligned(64); 556 557 /* VCPU configuration. */ 558 bool cpuidpresent[SVM_NCPUIDS]; 559 struct nvmm_vcpu_conf_cpuid cpuid[SVM_NCPUIDS]; 560 }; 561 562 static void 563 svm_vmcb_cache_default(struct vmcb *vmcb) 564 { 565 vmcb->ctrl.vmcb_clean = 566 VMCB_CTRL_VMCB_CLEAN_I | 567 VMCB_CTRL_VMCB_CLEAN_IOPM | 568 VMCB_CTRL_VMCB_CLEAN_ASID | 569 VMCB_CTRL_VMCB_CLEAN_TPR | 570 VMCB_CTRL_VMCB_CLEAN_NP | 571 VMCB_CTRL_VMCB_CLEAN_CR | 572 VMCB_CTRL_VMCB_CLEAN_DR | 573 VMCB_CTRL_VMCB_CLEAN_DT | 574 VMCB_CTRL_VMCB_CLEAN_SEG | 575 VMCB_CTRL_VMCB_CLEAN_CR2 | 576 VMCB_CTRL_VMCB_CLEAN_LBR | 577 VMCB_CTRL_VMCB_CLEAN_AVIC; 578 } 579 580 static void 581 svm_vmcb_cache_update(struct vmcb *vmcb, uint64_t flags) 582 { 583 if (flags & NVMM_X64_STATE_SEGS) { 584 vmcb->ctrl.vmcb_clean &= 585 ~(VMCB_CTRL_VMCB_CLEAN_SEG | VMCB_CTRL_VMCB_CLEAN_DT); 586 } 587 if (flags & NVMM_X64_STATE_CRS) { 588 vmcb->ctrl.vmcb_clean &= 589 ~(VMCB_CTRL_VMCB_CLEAN_CR | VMCB_CTRL_VMCB_CLEAN_CR2 | 590 VMCB_CTRL_VMCB_CLEAN_TPR); 591 } 592 if (flags & NVMM_X64_STATE_DRS) { 593 vmcb->ctrl.vmcb_clean &= ~VMCB_CTRL_VMCB_CLEAN_DR; 594 } 595 if (flags & NVMM_X64_STATE_MSRS) { 596 /* CR for EFER, NP for PAT. */ 597 vmcb->ctrl.vmcb_clean &= 598 ~(VMCB_CTRL_VMCB_CLEAN_CR | VMCB_CTRL_VMCB_CLEAN_NP); 599 } 600 } 601 602 static inline void 603 svm_vmcb_cache_flush(struct vmcb *vmcb, uint64_t flags) 604 { 605 vmcb->ctrl.vmcb_clean &= ~flags; 606 } 607 608 static inline void 609 svm_vmcb_cache_flush_all(struct vmcb *vmcb) 610 { 611 vmcb->ctrl.vmcb_clean = 0; 612 } 613 614 #define SVM_EVENT_TYPE_HW_INT 0 615 #define SVM_EVENT_TYPE_NMI 2 616 #define SVM_EVENT_TYPE_EXC 3 617 #define SVM_EVENT_TYPE_SW_INT 4 618 619 static void 620 svm_event_waitexit_enable(struct nvmm_cpu *vcpu, bool nmi) 621 { 622 struct svm_cpudata *cpudata = vcpu->cpudata; 623 struct vmcb *vmcb = cpudata->vmcb; 624 625 if (nmi) { 626 vmcb->ctrl.intercept_misc1 |= VMCB_CTRL_INTERCEPT_IRET; 627 cpudata->nmi_window_exit = true; 628 } else { 629 vmcb->ctrl.intercept_misc1 |= VMCB_CTRL_INTERCEPT_VINTR; 630 vmcb->ctrl.v |= (VMCB_CTRL_V_IRQ | VMCB_CTRL_V_IGN_TPR); 631 svm_vmcb_cache_flush(vmcb, VMCB_CTRL_VMCB_CLEAN_TPR); 632 cpudata->int_window_exit = true; 633 } 634 635 svm_vmcb_cache_flush(vmcb, VMCB_CTRL_VMCB_CLEAN_I); 636 } 637 638 static void 639 svm_event_waitexit_disable(struct nvmm_cpu *vcpu, bool nmi) 640 { 641 struct svm_cpudata *cpudata = vcpu->cpudata; 642 struct vmcb *vmcb = cpudata->vmcb; 643 644 if (nmi) { 645 vmcb->ctrl.intercept_misc1 &= ~VMCB_CTRL_INTERCEPT_IRET; 646 cpudata->nmi_window_exit = false; 647 } else { 648 vmcb->ctrl.intercept_misc1 &= ~VMCB_CTRL_INTERCEPT_VINTR; 649 vmcb->ctrl.v &= ~(VMCB_CTRL_V_IRQ | VMCB_CTRL_V_IGN_TPR); 650 svm_vmcb_cache_flush(vmcb, VMCB_CTRL_VMCB_CLEAN_TPR); 651 cpudata->int_window_exit = false; 652 } 653 654 svm_vmcb_cache_flush(vmcb, VMCB_CTRL_VMCB_CLEAN_I); 655 } 656 657 static inline int 658 svm_event_has_error(uint8_t vector) 659 { 660 switch (vector) { 661 case 8: /* #DF */ 662 case 10: /* #TS */ 663 case 11: /* #NP */ 664 case 12: /* #SS */ 665 case 13: /* #GP */ 666 case 14: /* #PF */ 667 case 17: /* #AC */ 668 case 30: /* #SX */ 669 return 1; 670 default: 671 return 0; 672 } 673 } 674 675 static int 676 svm_vcpu_inject(struct nvmm_cpu *vcpu) 677 { 678 struct nvmm_comm_page *comm = vcpu->comm; 679 struct svm_cpudata *cpudata = vcpu->cpudata; 680 struct vmcb *vmcb = cpudata->vmcb; 681 u_int evtype; 682 uint8_t vector; 683 uint64_t error; 684 int type = 0, err = 0; 685 686 evtype = comm->event.type; 687 vector = comm->event.vector; 688 error = comm->event.u.excp.error; 689 __insn_barrier(); 690 691 switch (evtype) { 692 case NVMM_VCPU_EVENT_EXCP: 693 type = SVM_EVENT_TYPE_EXC; 694 if (vector == 2 || vector >= 32) 695 return EINVAL; 696 if (vector == 3 || vector == 0) 697 return EINVAL; 698 err = svm_event_has_error(vector); 699 break; 700 case NVMM_VCPU_EVENT_INTR: 701 type = SVM_EVENT_TYPE_HW_INT; 702 if (vector == 2) { 703 type = SVM_EVENT_TYPE_NMI; 704 svm_event_waitexit_enable(vcpu, true); 705 } 706 err = 0; 707 break; 708 default: 709 return EINVAL; 710 } 711 712 vmcb->ctrl.eventinj = 713 __SHIFTIN((uint64_t)vector, VMCB_CTRL_EVENTINJ_VECTOR) | 714 __SHIFTIN((uint64_t)type, VMCB_CTRL_EVENTINJ_TYPE) | 715 __SHIFTIN((uint64_t)err, VMCB_CTRL_EVENTINJ_EV) | 716 __SHIFTIN((uint64_t)1, VMCB_CTRL_EVENTINJ_V) | 717 __SHIFTIN((uint64_t)error, VMCB_CTRL_EVENTINJ_ERRORCODE); 718 719 cpudata->evt_pending = true; 720 721 return 0; 722 } 723 724 static void 725 svm_inject_ud(struct nvmm_cpu *vcpu) 726 { 727 struct nvmm_comm_page *comm = vcpu->comm; 728 int ret __diagused; 729 730 comm->event.type = NVMM_VCPU_EVENT_EXCP; 731 comm->event.vector = 6; 732 comm->event.u.excp.error = 0; 733 734 ret = svm_vcpu_inject(vcpu); 735 KASSERT(ret == 0); 736 } 737 738 static void 739 svm_inject_gp(struct nvmm_cpu *vcpu) 740 { 741 struct nvmm_comm_page *comm = vcpu->comm; 742 int ret __diagused; 743 744 comm->event.type = NVMM_VCPU_EVENT_EXCP; 745 comm->event.vector = 13; 746 comm->event.u.excp.error = 0; 747 748 ret = svm_vcpu_inject(vcpu); 749 KASSERT(ret == 0); 750 } 751 752 static inline int 753 svm_vcpu_event_commit(struct nvmm_cpu *vcpu) 754 { 755 if (__predict_true(!vcpu->comm->event_commit)) { 756 return 0; 757 } 758 vcpu->comm->event_commit = false; 759 return svm_vcpu_inject(vcpu); 760 } 761 762 static inline void 763 svm_inkernel_advance(struct vmcb *vmcb) 764 { 765 /* 766 * Maybe we should also apply single-stepping and debug exceptions. 767 * Matters for guest-ring3, because it can execute 'cpuid' under a 768 * debugger. 769 */ 770 vmcb->state.rip = vmcb->ctrl.nrip; 771 vmcb->ctrl.intr &= ~VMCB_CTRL_INTR_SHADOW; 772 } 773 774 #define SVM_CPUID_MAX_HYPERVISOR 0x40000000 775 776 static void 777 svm_inkernel_handle_cpuid(struct nvmm_cpu *vcpu, uint64_t eax, uint64_t ecx) 778 { 779 struct svm_cpudata *cpudata = vcpu->cpudata; 780 uint64_t cr4; 781 782 switch (eax) { 783 case 0x00000001: 784 cpudata->vmcb->state.rax &= nvmm_cpuid_00000001.eax; 785 786 cpudata->gprs[NVMM_X64_GPR_RBX] &= ~CPUID_LOCAL_APIC_ID; 787 cpudata->gprs[NVMM_X64_GPR_RBX] |= __SHIFTIN(vcpu->cpuid, 788 CPUID_LOCAL_APIC_ID); 789 790 cpudata->gprs[NVMM_X64_GPR_RCX] &= nvmm_cpuid_00000001.ecx; 791 cpudata->gprs[NVMM_X64_GPR_RCX] |= CPUID2_RAZ; 792 793 cpudata->gprs[NVMM_X64_GPR_RDX] &= nvmm_cpuid_00000001.edx; 794 795 /* CPUID2_OSXSAVE depends on CR4. */ 796 cr4 = cpudata->vmcb->state.cr4; 797 if (!(cr4 & CR4_OSXSAVE)) { 798 cpudata->gprs[NVMM_X64_GPR_RCX] &= ~CPUID2_OSXSAVE; 799 } 800 break; 801 case 0x00000002: /* Empty */ 802 case 0x00000003: /* Empty */ 803 case 0x00000004: /* Empty */ 804 case 0x00000005: /* Monitor/MWait */ 805 case 0x00000006: /* Power Management Related Features */ 806 cpudata->vmcb->state.rax = 0; 807 cpudata->gprs[NVMM_X64_GPR_RBX] = 0; 808 cpudata->gprs[NVMM_X64_GPR_RCX] = 0; 809 cpudata->gprs[NVMM_X64_GPR_RDX] = 0; 810 break; 811 case 0x00000007: /* Structured Extended Features */ 812 cpudata->vmcb->state.rax &= nvmm_cpuid_00000007.eax; 813 cpudata->gprs[NVMM_X64_GPR_RBX] &= nvmm_cpuid_00000007.ebx; 814 cpudata->gprs[NVMM_X64_GPR_RCX] &= nvmm_cpuid_00000007.ecx; 815 cpudata->gprs[NVMM_X64_GPR_RDX] &= nvmm_cpuid_00000007.edx; 816 break; 817 case 0x00000008: /* Empty */ 818 case 0x00000009: /* Empty */ 819 case 0x0000000A: /* Empty */ 820 case 0x0000000B: /* Empty */ 821 case 0x0000000C: /* Empty */ 822 cpudata->vmcb->state.rax = 0; 823 cpudata->gprs[NVMM_X64_GPR_RBX] = 0; 824 cpudata->gprs[NVMM_X64_GPR_RCX] = 0; 825 cpudata->gprs[NVMM_X64_GPR_RDX] = 0; 826 break; 827 case 0x0000000D: /* Processor Extended State Enumeration */ 828 if (svm_xcr0_mask == 0) { 829 break; 830 } 831 switch (ecx) { 832 case 0: 833 cpudata->vmcb->state.rax = svm_xcr0_mask & 0xFFFFFFFF; 834 if (cpudata->gxcr0 & XCR0_SSE) { 835 cpudata->gprs[NVMM_X64_GPR_RBX] = sizeof(struct fxsave); 836 } else { 837 cpudata->gprs[NVMM_X64_GPR_RBX] = sizeof(struct save87); 838 } 839 cpudata->gprs[NVMM_X64_GPR_RBX] += 64; /* XSAVE header */ 840 cpudata->gprs[NVMM_X64_GPR_RCX] = sizeof(struct fxsave) + 64; 841 cpudata->gprs[NVMM_X64_GPR_RDX] = svm_xcr0_mask >> 32; 842 break; 843 case 1: 844 cpudata->vmcb->state.rax &= 845 (CPUID_PES1_XSAVEOPT | CPUID_PES1_XSAVEC | 846 CPUID_PES1_XGETBV); 847 cpudata->gprs[NVMM_X64_GPR_RBX] = 0; 848 cpudata->gprs[NVMM_X64_GPR_RCX] = 0; 849 cpudata->gprs[NVMM_X64_GPR_RDX] = 0; 850 break; 851 default: 852 cpudata->vmcb->state.rax = 0; 853 cpudata->gprs[NVMM_X64_GPR_RBX] = 0; 854 cpudata->gprs[NVMM_X64_GPR_RCX] = 0; 855 cpudata->gprs[NVMM_X64_GPR_RDX] = 0; 856 break; 857 } 858 break; 859 860 case 0x40000000: /* Hypervisor Information */ 861 cpudata->vmcb->state.rax = SVM_CPUID_MAX_HYPERVISOR; 862 cpudata->gprs[NVMM_X64_GPR_RBX] = 0; 863 cpudata->gprs[NVMM_X64_GPR_RCX] = 0; 864 cpudata->gprs[NVMM_X64_GPR_RDX] = 0; 865 memcpy(&cpudata->gprs[NVMM_X64_GPR_RBX], "___ ", 4); 866 memcpy(&cpudata->gprs[NVMM_X64_GPR_RCX], "NVMM", 4); 867 memcpy(&cpudata->gprs[NVMM_X64_GPR_RDX], " ___", 4); 868 break; 869 870 case 0x80000001: 871 cpudata->vmcb->state.rax &= nvmm_cpuid_80000001.eax; 872 cpudata->gprs[NVMM_X64_GPR_RBX] &= nvmm_cpuid_80000001.ebx; 873 cpudata->gprs[NVMM_X64_GPR_RCX] &= nvmm_cpuid_80000001.ecx; 874 cpudata->gprs[NVMM_X64_GPR_RDX] &= nvmm_cpuid_80000001.edx; 875 break; 876 default: 877 break; 878 } 879 } 880 881 static void 882 svm_exit_insn(struct vmcb *vmcb, struct nvmm_vcpu_exit *exit, uint64_t reason) 883 { 884 exit->u.insn.npc = vmcb->ctrl.nrip; 885 exit->reason = reason; 886 } 887 888 static void 889 svm_exit_cpuid(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 890 struct nvmm_vcpu_exit *exit) 891 { 892 struct svm_cpudata *cpudata = vcpu->cpudata; 893 struct nvmm_vcpu_conf_cpuid *cpuid; 894 uint64_t eax, ecx; 895 u_int descs[4]; 896 size_t i; 897 898 eax = cpudata->vmcb->state.rax; 899 ecx = cpudata->gprs[NVMM_X64_GPR_RCX]; 900 x86_cpuid2(eax, ecx, descs); 901 902 cpudata->vmcb->state.rax = descs[0]; 903 cpudata->gprs[NVMM_X64_GPR_RBX] = descs[1]; 904 cpudata->gprs[NVMM_X64_GPR_RCX] = descs[2]; 905 cpudata->gprs[NVMM_X64_GPR_RDX] = descs[3]; 906 907 svm_inkernel_handle_cpuid(vcpu, eax, ecx); 908 909 for (i = 0; i < SVM_NCPUIDS; i++) { 910 if (!cpudata->cpuidpresent[i]) { 911 continue; 912 } 913 cpuid = &cpudata->cpuid[i]; 914 if (cpuid->leaf != eax) { 915 continue; 916 } 917 918 if (cpuid->exit) { 919 svm_exit_insn(cpudata->vmcb, exit, NVMM_VCPU_EXIT_CPUID); 920 return; 921 } 922 KASSERT(cpuid->mask); 923 924 /* del */ 925 cpudata->vmcb->state.rax &= ~cpuid->u.mask.del.eax; 926 cpudata->gprs[NVMM_X64_GPR_RBX] &= ~cpuid->u.mask.del.ebx; 927 cpudata->gprs[NVMM_X64_GPR_RCX] &= ~cpuid->u.mask.del.ecx; 928 cpudata->gprs[NVMM_X64_GPR_RDX] &= ~cpuid->u.mask.del.edx; 929 930 /* set */ 931 cpudata->vmcb->state.rax |= cpuid->u.mask.set.eax; 932 cpudata->gprs[NVMM_X64_GPR_RBX] |= cpuid->u.mask.set.ebx; 933 cpudata->gprs[NVMM_X64_GPR_RCX] |= cpuid->u.mask.set.ecx; 934 cpudata->gprs[NVMM_X64_GPR_RDX] |= cpuid->u.mask.set.edx; 935 936 break; 937 } 938 939 svm_inkernel_advance(cpudata->vmcb); 940 exit->reason = NVMM_VCPU_EXIT_NONE; 941 } 942 943 static void 944 svm_exit_hlt(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 945 struct nvmm_vcpu_exit *exit) 946 { 947 struct svm_cpudata *cpudata = vcpu->cpudata; 948 struct vmcb *vmcb = cpudata->vmcb; 949 950 if (cpudata->int_window_exit && (vmcb->state.rflags & PSL_I)) { 951 svm_event_waitexit_disable(vcpu, false); 952 } 953 954 svm_inkernel_advance(cpudata->vmcb); 955 exit->reason = NVMM_VCPU_EXIT_HALTED; 956 } 957 958 #define SVM_EXIT_IO_PORT __BITS(31,16) 959 #define SVM_EXIT_IO_SEG __BITS(12,10) 960 #define SVM_EXIT_IO_A64 __BIT(9) 961 #define SVM_EXIT_IO_A32 __BIT(8) 962 #define SVM_EXIT_IO_A16 __BIT(7) 963 #define SVM_EXIT_IO_SZ32 __BIT(6) 964 #define SVM_EXIT_IO_SZ16 __BIT(5) 965 #define SVM_EXIT_IO_SZ8 __BIT(4) 966 #define SVM_EXIT_IO_REP __BIT(3) 967 #define SVM_EXIT_IO_STR __BIT(2) 968 #define SVM_EXIT_IO_IN __BIT(0) 969 970 static void 971 svm_exit_io(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 972 struct nvmm_vcpu_exit *exit) 973 { 974 struct svm_cpudata *cpudata = vcpu->cpudata; 975 uint64_t info = cpudata->vmcb->ctrl.exitinfo1; 976 uint64_t nextpc = cpudata->vmcb->ctrl.exitinfo2; 977 978 exit->reason = NVMM_VCPU_EXIT_IO; 979 980 exit->u.io.in = (info & SVM_EXIT_IO_IN) != 0; 981 exit->u.io.port = __SHIFTOUT(info, SVM_EXIT_IO_PORT); 982 983 if (svm_decode_assist) { 984 KASSERT(__SHIFTOUT(info, SVM_EXIT_IO_SEG) < 6); 985 exit->u.io.seg = __SHIFTOUT(info, SVM_EXIT_IO_SEG); 986 } else { 987 exit->u.io.seg = -1; 988 } 989 990 if (info & SVM_EXIT_IO_A64) { 991 exit->u.io.address_size = 8; 992 } else if (info & SVM_EXIT_IO_A32) { 993 exit->u.io.address_size = 4; 994 } else if (info & SVM_EXIT_IO_A16) { 995 exit->u.io.address_size = 2; 996 } 997 998 if (info & SVM_EXIT_IO_SZ32) { 999 exit->u.io.operand_size = 4; 1000 } else if (info & SVM_EXIT_IO_SZ16) { 1001 exit->u.io.operand_size = 2; 1002 } else if (info & SVM_EXIT_IO_SZ8) { 1003 exit->u.io.operand_size = 1; 1004 } 1005 1006 exit->u.io.rep = (info & SVM_EXIT_IO_REP) != 0; 1007 exit->u.io.str = (info & SVM_EXIT_IO_STR) != 0; 1008 exit->u.io.npc = nextpc; 1009 1010 svm_vcpu_state_provide(vcpu, 1011 NVMM_X64_STATE_GPRS | NVMM_X64_STATE_SEGS | 1012 NVMM_X64_STATE_CRS | NVMM_X64_STATE_MSRS); 1013 } 1014 1015 static const uint64_t msr_ignore_list[] = { 1016 0xc0010055, /* MSR_CMPHALT */ 1017 MSR_DE_CFG, 1018 MSR_IC_CFG, 1019 MSR_UCODE_AMD_PATCHLEVEL 1020 }; 1021 1022 static bool 1023 svm_inkernel_handle_msr(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 1024 struct nvmm_vcpu_exit *exit) 1025 { 1026 struct svm_cpudata *cpudata = vcpu->cpudata; 1027 struct vmcb *vmcb = cpudata->vmcb; 1028 uint64_t val; 1029 size_t i; 1030 1031 if (exit->reason == NVMM_VCPU_EXIT_RDMSR) { 1032 if (exit->u.rdmsr.msr == MSR_NB_CFG) { 1033 val = NB_CFG_INITAPICCPUIDLO; 1034 vmcb->state.rax = (val & 0xFFFFFFFF); 1035 cpudata->gprs[NVMM_X64_GPR_RDX] = (val >> 32); 1036 goto handled; 1037 } 1038 for (i = 0; i < __arraycount(msr_ignore_list); i++) { 1039 if (msr_ignore_list[i] != exit->u.rdmsr.msr) 1040 continue; 1041 val = 0; 1042 vmcb->state.rax = (val & 0xFFFFFFFF); 1043 cpudata->gprs[NVMM_X64_GPR_RDX] = (val >> 32); 1044 goto handled; 1045 } 1046 } else { 1047 if (exit->u.wrmsr.msr == MSR_EFER) { 1048 if (__predict_false(exit->u.wrmsr.val & ~EFER_VALID)) { 1049 goto error; 1050 } 1051 if ((vmcb->state.efer ^ exit->u.wrmsr.val) & 1052 EFER_TLB_FLUSH) { 1053 cpudata->gtlb_want_flush = true; 1054 } 1055 vmcb->state.efer = exit->u.wrmsr.val | EFER_SVME; 1056 svm_vmcb_cache_flush(vmcb, VMCB_CTRL_VMCB_CLEAN_CR); 1057 goto handled; 1058 } 1059 if (exit->u.wrmsr.msr == MSR_TSC) { 1060 cpudata->gtsc = exit->u.wrmsr.val; 1061 cpudata->gtsc_want_update = true; 1062 goto handled; 1063 } 1064 for (i = 0; i < __arraycount(msr_ignore_list); i++) { 1065 if (msr_ignore_list[i] != exit->u.wrmsr.msr) 1066 continue; 1067 goto handled; 1068 } 1069 } 1070 1071 return false; 1072 1073 handled: 1074 svm_inkernel_advance(cpudata->vmcb); 1075 return true; 1076 1077 error: 1078 svm_inject_gp(vcpu); 1079 return true; 1080 } 1081 1082 static inline void 1083 svm_exit_rdmsr(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 1084 struct nvmm_vcpu_exit *exit) 1085 { 1086 struct svm_cpudata *cpudata = vcpu->cpudata; 1087 1088 exit->reason = NVMM_VCPU_EXIT_RDMSR; 1089 exit->u.rdmsr.msr = (cpudata->gprs[NVMM_X64_GPR_RCX] & 0xFFFFFFFF); 1090 exit->u.rdmsr.npc = cpudata->vmcb->ctrl.nrip; 1091 1092 if (svm_inkernel_handle_msr(mach, vcpu, exit)) { 1093 exit->reason = NVMM_VCPU_EXIT_NONE; 1094 return; 1095 } 1096 1097 svm_vcpu_state_provide(vcpu, NVMM_X64_STATE_GPRS); 1098 } 1099 1100 static inline void 1101 svm_exit_wrmsr(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 1102 struct nvmm_vcpu_exit *exit) 1103 { 1104 struct svm_cpudata *cpudata = vcpu->cpudata; 1105 uint64_t rdx, rax; 1106 1107 rdx = cpudata->gprs[NVMM_X64_GPR_RDX]; 1108 rax = cpudata->vmcb->state.rax; 1109 1110 exit->reason = NVMM_VCPU_EXIT_WRMSR; 1111 exit->u.wrmsr.msr = (cpudata->gprs[NVMM_X64_GPR_RCX] & 0xFFFFFFFF); 1112 exit->u.wrmsr.val = (rdx << 32) | (rax & 0xFFFFFFFF); 1113 exit->u.wrmsr.npc = cpudata->vmcb->ctrl.nrip; 1114 1115 if (svm_inkernel_handle_msr(mach, vcpu, exit)) { 1116 exit->reason = NVMM_VCPU_EXIT_NONE; 1117 return; 1118 } 1119 1120 svm_vcpu_state_provide(vcpu, NVMM_X64_STATE_GPRS); 1121 } 1122 1123 static void 1124 svm_exit_msr(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 1125 struct nvmm_vcpu_exit *exit) 1126 { 1127 struct svm_cpudata *cpudata = vcpu->cpudata; 1128 uint64_t info = cpudata->vmcb->ctrl.exitinfo1; 1129 1130 if (info == 0) { 1131 svm_exit_rdmsr(mach, vcpu, exit); 1132 } else { 1133 svm_exit_wrmsr(mach, vcpu, exit); 1134 } 1135 } 1136 1137 static void 1138 svm_exit_npf(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 1139 struct nvmm_vcpu_exit *exit) 1140 { 1141 struct svm_cpudata *cpudata = vcpu->cpudata; 1142 gpaddr_t gpa = cpudata->vmcb->ctrl.exitinfo2; 1143 1144 exit->reason = NVMM_VCPU_EXIT_MEMORY; 1145 if (cpudata->vmcb->ctrl.exitinfo1 & PGEX_W) 1146 exit->u.mem.prot = PROT_WRITE; 1147 else if (cpudata->vmcb->ctrl.exitinfo1 & PGEX_X) 1148 exit->u.mem.prot = PROT_EXEC; 1149 else 1150 exit->u.mem.prot = PROT_READ; 1151 exit->u.mem.gpa = gpa; 1152 exit->u.mem.inst_len = cpudata->vmcb->ctrl.inst_len; 1153 memcpy(exit->u.mem.inst_bytes, cpudata->vmcb->ctrl.inst_bytes, 1154 sizeof(exit->u.mem.inst_bytes)); 1155 1156 svm_vcpu_state_provide(vcpu, 1157 NVMM_X64_STATE_GPRS | NVMM_X64_STATE_SEGS | 1158 NVMM_X64_STATE_CRS | NVMM_X64_STATE_MSRS); 1159 } 1160 1161 static void 1162 svm_exit_xsetbv(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 1163 struct nvmm_vcpu_exit *exit) 1164 { 1165 struct svm_cpudata *cpudata = vcpu->cpudata; 1166 struct vmcb *vmcb = cpudata->vmcb; 1167 uint64_t val; 1168 1169 exit->reason = NVMM_VCPU_EXIT_NONE; 1170 1171 val = (cpudata->gprs[NVMM_X64_GPR_RDX] << 32) | 1172 (vmcb->state.rax & 0xFFFFFFFF); 1173 1174 if (__predict_false(cpudata->gprs[NVMM_X64_GPR_RCX] != 0)) { 1175 goto error; 1176 } else if (__predict_false(vmcb->state.cpl != 0)) { 1177 goto error; 1178 } else if (__predict_false((val & ~svm_xcr0_mask) != 0)) { 1179 goto error; 1180 } else if (__predict_false((val & XCR0_X87) == 0)) { 1181 goto error; 1182 } 1183 1184 cpudata->gxcr0 = val; 1185 if (svm_xcr0_mask != 0) { 1186 wrxcr(0, cpudata->gxcr0); 1187 } 1188 1189 svm_inkernel_advance(cpudata->vmcb); 1190 return; 1191 1192 error: 1193 svm_inject_gp(vcpu); 1194 } 1195 1196 static void 1197 svm_exit_invalid(struct nvmm_vcpu_exit *exit, uint64_t code) 1198 { 1199 exit->u.inv.hwcode = code; 1200 exit->reason = NVMM_VCPU_EXIT_INVALID; 1201 } 1202 1203 /* -------------------------------------------------------------------------- */ 1204 1205 static void 1206 svm_vcpu_guest_fpu_enter(struct nvmm_cpu *vcpu) 1207 { 1208 struct svm_cpudata *cpudata = vcpu->cpudata; 1209 1210 fpu_save(); 1211 fpu_area_restore(&cpudata->gfpu, svm_xcr0_mask); 1212 1213 if (svm_xcr0_mask != 0) { 1214 cpudata->hxcr0 = rdxcr(0); 1215 wrxcr(0, cpudata->gxcr0); 1216 } 1217 } 1218 1219 static void 1220 svm_vcpu_guest_fpu_leave(struct nvmm_cpu *vcpu) 1221 { 1222 struct svm_cpudata *cpudata = vcpu->cpudata; 1223 1224 if (svm_xcr0_mask != 0) { 1225 cpudata->gxcr0 = rdxcr(0); 1226 wrxcr(0, cpudata->hxcr0); 1227 } 1228 1229 fpu_area_save(&cpudata->gfpu, svm_xcr0_mask); 1230 } 1231 1232 static void 1233 svm_vcpu_guest_dbregs_enter(struct nvmm_cpu *vcpu) 1234 { 1235 struct svm_cpudata *cpudata = vcpu->cpudata; 1236 1237 x86_dbregs_save(curlwp); 1238 1239 ldr7(0); 1240 1241 ldr0(cpudata->drs[NVMM_X64_DR_DR0]); 1242 ldr1(cpudata->drs[NVMM_X64_DR_DR1]); 1243 ldr2(cpudata->drs[NVMM_X64_DR_DR2]); 1244 ldr3(cpudata->drs[NVMM_X64_DR_DR3]); 1245 } 1246 1247 static void 1248 svm_vcpu_guest_dbregs_leave(struct nvmm_cpu *vcpu) 1249 { 1250 struct svm_cpudata *cpudata = vcpu->cpudata; 1251 1252 cpudata->drs[NVMM_X64_DR_DR0] = rdr0(); 1253 cpudata->drs[NVMM_X64_DR_DR1] = rdr1(); 1254 cpudata->drs[NVMM_X64_DR_DR2] = rdr2(); 1255 cpudata->drs[NVMM_X64_DR_DR3] = rdr3(); 1256 1257 x86_dbregs_restore(curlwp); 1258 } 1259 1260 static void 1261 svm_vcpu_guest_misc_enter(struct nvmm_cpu *vcpu) 1262 { 1263 struct svm_cpudata *cpudata = vcpu->cpudata; 1264 1265 cpudata->fsbase = rdmsr(MSR_FSBASE); 1266 cpudata->kernelgsbase = rdmsr(MSR_KERNELGSBASE); 1267 } 1268 1269 static void 1270 svm_vcpu_guest_misc_leave(struct nvmm_cpu *vcpu) 1271 { 1272 struct svm_cpudata *cpudata = vcpu->cpudata; 1273 1274 wrmsr(MSR_STAR, cpudata->star); 1275 wrmsr(MSR_LSTAR, cpudata->lstar); 1276 wrmsr(MSR_CSTAR, cpudata->cstar); 1277 wrmsr(MSR_SFMASK, cpudata->sfmask); 1278 wrmsr(MSR_FSBASE, cpudata->fsbase); 1279 wrmsr(MSR_KERNELGSBASE, cpudata->kernelgsbase); 1280 } 1281 1282 /* -------------------------------------------------------------------------- */ 1283 1284 static inline void 1285 svm_gtlb_catchup(struct nvmm_cpu *vcpu, int hcpu) 1286 { 1287 struct svm_cpudata *cpudata = vcpu->cpudata; 1288 1289 if (vcpu->hcpu_last != hcpu || cpudata->shared_asid) { 1290 cpudata->gtlb_want_flush = true; 1291 } 1292 } 1293 1294 static inline void 1295 svm_htlb_catchup(struct nvmm_cpu *vcpu, int hcpu) 1296 { 1297 /* 1298 * Nothing to do. If an hTLB flush was needed, either the VCPU was 1299 * executing on this hCPU and the hTLB already got flushed, or it 1300 * was executing on another hCPU in which case the catchup is done 1301 * in svm_gtlb_catchup(). 1302 */ 1303 } 1304 1305 static inline uint64_t 1306 svm_htlb_flush(struct svm_machdata *machdata, struct svm_cpudata *cpudata) 1307 { 1308 struct vmcb *vmcb = cpudata->vmcb; 1309 uint64_t machgen; 1310 1311 machgen = machdata->mach_htlb_gen; 1312 if (__predict_true(machgen == cpudata->vcpu_htlb_gen)) { 1313 return machgen; 1314 } 1315 1316 vmcb->ctrl.tlb_ctrl = svm_ctrl_tlb_flush; 1317 return machgen; 1318 } 1319 1320 static inline void 1321 svm_htlb_flush_ack(struct svm_cpudata *cpudata, uint64_t machgen) 1322 { 1323 struct vmcb *vmcb = cpudata->vmcb; 1324 1325 if (__predict_true(vmcb->ctrl.exitcode != VMCB_EXITCODE_INVALID)) { 1326 cpudata->vcpu_htlb_gen = machgen; 1327 } 1328 } 1329 1330 static inline void 1331 svm_exit_evt(struct svm_cpudata *cpudata, struct vmcb *vmcb) 1332 { 1333 cpudata->evt_pending = false; 1334 1335 if (__predict_false(vmcb->ctrl.exitintinfo & VMCB_CTRL_EXITINTINFO_V)) { 1336 vmcb->ctrl.eventinj = vmcb->ctrl.exitintinfo; 1337 cpudata->evt_pending = true; 1338 } 1339 } 1340 1341 static int 1342 svm_vcpu_run(struct nvmm_machine *mach, struct nvmm_cpu *vcpu, 1343 struct nvmm_vcpu_exit *exit) 1344 { 1345 struct nvmm_comm_page *comm = vcpu->comm; 1346 struct svm_machdata *machdata = mach->machdata; 1347 struct svm_cpudata *cpudata = vcpu->cpudata; 1348 struct vmcb *vmcb = cpudata->vmcb; 1349 uint64_t machgen; 1350 int hcpu, s; 1351 1352 if (__predict_false(svm_vcpu_event_commit(vcpu) != 0)) { 1353 return EINVAL; 1354 } 1355 svm_vcpu_state_commit(vcpu); 1356 comm->state_cached = 0; 1357 1358 kpreempt_disable(); 1359 hcpu = cpu_number(); 1360 1361 svm_gtlb_catchup(vcpu, hcpu); 1362 svm_htlb_catchup(vcpu, hcpu); 1363 1364 if (vcpu->hcpu_last != hcpu) { 1365 svm_vmcb_cache_flush_all(vmcb); 1366 cpudata->gtsc_want_update = true; 1367 } 1368 1369 svm_vcpu_guest_dbregs_enter(vcpu); 1370 svm_vcpu_guest_misc_enter(vcpu); 1371 svm_vcpu_guest_fpu_enter(vcpu); 1372 1373 while (1) { 1374 if (cpudata->gtlb_want_flush) { 1375 vmcb->ctrl.tlb_ctrl = svm_ctrl_tlb_flush; 1376 } else { 1377 vmcb->ctrl.tlb_ctrl = 0; 1378 } 1379 1380 if (__predict_false(cpudata->gtsc_want_update)) { 1381 vmcb->ctrl.tsc_offset = cpudata->gtsc - rdtsc(); 1382 svm_vmcb_cache_flush(vmcb, VMCB_CTRL_VMCB_CLEAN_I); 1383 } 1384 1385 s = splhigh(); 1386 machgen = svm_htlb_flush(machdata, cpudata); 1387 svm_vmrun(cpudata->vmcb_pa, cpudata->gprs); 1388 svm_htlb_flush_ack(cpudata, machgen); 1389 splx(s); 1390 1391 svm_vmcb_cache_default(vmcb); 1392 1393 if (vmcb->ctrl.exitcode != VMCB_EXITCODE_INVALID) { 1394 cpudata->gtlb_want_flush = false; 1395 cpudata->gtsc_want_update = false; 1396 vcpu->hcpu_last = hcpu; 1397 } 1398 svm_exit_evt(cpudata, vmcb); 1399 1400 switch (vmcb->ctrl.exitcode) { 1401 case VMCB_EXITCODE_INTR: 1402 case VMCB_EXITCODE_NMI: 1403 exit->reason = NVMM_VCPU_EXIT_NONE; 1404 break; 1405 case VMCB_EXITCODE_VINTR: 1406 svm_event_waitexit_disable(vcpu, false); 1407 exit->reason = NVMM_VCPU_EXIT_INT_READY; 1408 break; 1409 case VMCB_EXITCODE_IRET: 1410 svm_event_waitexit_disable(vcpu, true); 1411 exit->reason = NVMM_VCPU_EXIT_NMI_READY; 1412 break; 1413 case VMCB_EXITCODE_CPUID: 1414 svm_exit_cpuid(mach, vcpu, exit); 1415 break; 1416 case VMCB_EXITCODE_HLT: 1417 svm_exit_hlt(mach, vcpu, exit); 1418 break; 1419 case VMCB_EXITCODE_IOIO: 1420 svm_exit_io(mach, vcpu, exit); 1421 break; 1422 case VMCB_EXITCODE_MSR: 1423 svm_exit_msr(mach, vcpu, exit); 1424 break; 1425 case VMCB_EXITCODE_SHUTDOWN: 1426 exit->reason = NVMM_VCPU_EXIT_SHUTDOWN; 1427 break; 1428 case VMCB_EXITCODE_RDPMC: 1429 case VMCB_EXITCODE_RSM: 1430 case VMCB_EXITCODE_INVLPGA: 1431 case VMCB_EXITCODE_VMRUN: 1432 case VMCB_EXITCODE_VMMCALL: 1433 case VMCB_EXITCODE_VMLOAD: 1434 case VMCB_EXITCODE_VMSAVE: 1435 case VMCB_EXITCODE_STGI: 1436 case VMCB_EXITCODE_CLGI: 1437 case VMCB_EXITCODE_SKINIT: 1438 case VMCB_EXITCODE_RDTSCP: 1439 svm_inject_ud(vcpu); 1440 exit->reason = NVMM_VCPU_EXIT_NONE; 1441 break; 1442 case VMCB_EXITCODE_MONITOR: 1443 svm_exit_insn(vmcb, exit, NVMM_VCPU_EXIT_MONITOR); 1444 break; 1445 case VMCB_EXITCODE_MWAIT: 1446 case VMCB_EXITCODE_MWAIT_CONDITIONAL: 1447 svm_exit_insn(vmcb, exit, NVMM_VCPU_EXIT_MWAIT); 1448 break; 1449 case VMCB_EXITCODE_XSETBV: 1450 svm_exit_xsetbv(mach, vcpu, exit); 1451 break; 1452 case VMCB_EXITCODE_NPF: 1453 svm_exit_npf(mach, vcpu, exit); 1454 break; 1455 case VMCB_EXITCODE_FERR_FREEZE: /* ? */ 1456 default: 1457 svm_exit_invalid(exit, vmcb->ctrl.exitcode); 1458 break; 1459 } 1460 1461 /* If no reason to return to userland, keep rolling. */ 1462 if (nvmm_return_needed()) { 1463 break; 1464 } 1465 if (exit->reason != NVMM_VCPU_EXIT_NONE) { 1466 break; 1467 } 1468 } 1469 1470 cpudata->gtsc = rdtsc() + vmcb->ctrl.tsc_offset; 1471 1472 svm_vcpu_guest_fpu_leave(vcpu); 1473 svm_vcpu_guest_misc_leave(vcpu); 1474 svm_vcpu_guest_dbregs_leave(vcpu); 1475 1476 kpreempt_enable(); 1477 1478 exit->exitstate.rflags = vmcb->state.rflags; 1479 exit->exitstate.cr8 = __SHIFTOUT(vmcb->ctrl.v, VMCB_CTRL_V_TPR); 1480 exit->exitstate.int_shadow = 1481 ((vmcb->ctrl.intr & VMCB_CTRL_INTR_SHADOW) != 0); 1482 exit->exitstate.int_window_exiting = cpudata->int_window_exit; 1483 exit->exitstate.nmi_window_exiting = cpudata->nmi_window_exit; 1484 exit->exitstate.evt_pending = cpudata->evt_pending; 1485 1486 return 0; 1487 } 1488 1489 /* -------------------------------------------------------------------------- */ 1490 1491 static int 1492 svm_memalloc(paddr_t *pa, vaddr_t *va, size_t npages) 1493 { 1494 struct pglist pglist; 1495 paddr_t _pa; 1496 vaddr_t _va; 1497 size_t i; 1498 int ret; 1499 1500 ret = uvm_pglistalloc(npages * PAGE_SIZE, 0, ~0UL, PAGE_SIZE, 0, 1501 &pglist, 1, 0); 1502 if (ret != 0) 1503 return ENOMEM; 1504 _pa = VM_PAGE_TO_PHYS(TAILQ_FIRST(&pglist)); 1505 _va = uvm_km_alloc(kernel_map, npages * PAGE_SIZE, 0, 1506 UVM_KMF_VAONLY | UVM_KMF_NOWAIT); 1507 if (_va == 0) 1508 goto error; 1509 1510 for (i = 0; i < npages; i++) { 1511 pmap_kenter_pa(_va + i * PAGE_SIZE, _pa + i * PAGE_SIZE, 1512 VM_PROT_READ | VM_PROT_WRITE, PMAP_WRITE_BACK); 1513 } 1514 pmap_update(pmap_kernel()); 1515 1516 memset((void *)_va, 0, npages * PAGE_SIZE); 1517 1518 *pa = _pa; 1519 *va = _va; 1520 return 0; 1521 1522 error: 1523 for (i = 0; i < npages; i++) { 1524 uvm_pagefree(PHYS_TO_VM_PAGE(_pa + i * PAGE_SIZE)); 1525 } 1526 return ENOMEM; 1527 } 1528 1529 static void 1530 svm_memfree(paddr_t pa, vaddr_t va, size_t npages) 1531 { 1532 size_t i; 1533 1534 pmap_kremove(va, npages * PAGE_SIZE); 1535 pmap_update(pmap_kernel()); 1536 uvm_km_free(kernel_map, va, npages * PAGE_SIZE, UVM_KMF_VAONLY); 1537 for (i = 0; i < npages; i++) { 1538 uvm_pagefree(PHYS_TO_VM_PAGE(pa + i * PAGE_SIZE)); 1539 } 1540 } 1541 1542 /* -------------------------------------------------------------------------- */ 1543 1544 #define SVM_MSRBM_READ __BIT(0) 1545 #define SVM_MSRBM_WRITE __BIT(1) 1546 1547 static void 1548 svm_vcpu_msr_allow(uint8_t *bitmap, uint64_t msr, bool read, bool write) 1549 { 1550 uint64_t byte; 1551 uint8_t bitoff; 1552 1553 if (msr < 0x00002000) { 1554 /* Range 1 */ 1555 byte = ((msr - 0x00000000) >> 2UL) + 0x0000; 1556 } else if (msr >= 0xC0000000 && msr < 0xC0002000) { 1557 /* Range 2 */ 1558 byte = ((msr - 0xC0000000) >> 2UL) + 0x0800; 1559 } else if (msr >= 0xC0010000 && msr < 0xC0012000) { 1560 /* Range 3 */ 1561 byte = ((msr - 0xC0010000) >> 2UL) + 0x1000; 1562 } else { 1563 panic("%s: wrong range", __func__); 1564 } 1565 1566 bitoff = (msr & 0x3) << 1; 1567 1568 if (read) { 1569 bitmap[byte] &= ~(SVM_MSRBM_READ << bitoff); 1570 } 1571 if (write) { 1572 bitmap[byte] &= ~(SVM_MSRBM_WRITE << bitoff); 1573 } 1574 } 1575 1576 #define SVM_SEG_ATTRIB_TYPE __BITS(3,0) 1577 #define SVM_SEG_ATTRIB_S __BIT(4) 1578 #define SVM_SEG_ATTRIB_DPL __BITS(6,5) 1579 #define SVM_SEG_ATTRIB_P __BIT(7) 1580 #define SVM_SEG_ATTRIB_AVL __BIT(8) 1581 #define SVM_SEG_ATTRIB_L __BIT(9) 1582 #define SVM_SEG_ATTRIB_DEF __BIT(10) 1583 #define SVM_SEG_ATTRIB_G __BIT(11) 1584 1585 static void 1586 svm_vcpu_setstate_seg(const struct nvmm_x64_state_seg *seg, 1587 struct vmcb_segment *vseg) 1588 { 1589 vseg->selector = seg->selector; 1590 vseg->attrib = 1591 __SHIFTIN(seg->attrib.type, SVM_SEG_ATTRIB_TYPE) | 1592 __SHIFTIN(seg->attrib.s, SVM_SEG_ATTRIB_S) | 1593 __SHIFTIN(seg->attrib.dpl, SVM_SEG_ATTRIB_DPL) | 1594 __SHIFTIN(seg->attrib.p, SVM_SEG_ATTRIB_P) | 1595 __SHIFTIN(seg->attrib.avl, SVM_SEG_ATTRIB_AVL) | 1596 __SHIFTIN(seg->attrib.l, SVM_SEG_ATTRIB_L) | 1597 __SHIFTIN(seg->attrib.def, SVM_SEG_ATTRIB_DEF) | 1598 __SHIFTIN(seg->attrib.g, SVM_SEG_ATTRIB_G); 1599 vseg->limit = seg->limit; 1600 vseg->base = seg->base; 1601 } 1602 1603 static void 1604 svm_vcpu_getstate_seg(struct nvmm_x64_state_seg *seg, struct vmcb_segment *vseg) 1605 { 1606 seg->selector = vseg->selector; 1607 seg->attrib.type = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_TYPE); 1608 seg->attrib.s = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_S); 1609 seg->attrib.dpl = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_DPL); 1610 seg->attrib.p = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_P); 1611 seg->attrib.avl = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_AVL); 1612 seg->attrib.l = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_L); 1613 seg->attrib.def = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_DEF); 1614 seg->attrib.g = __SHIFTOUT(vseg->attrib, SVM_SEG_ATTRIB_G); 1615 seg->limit = vseg->limit; 1616 seg->base = vseg->base; 1617 } 1618 1619 static inline bool 1620 svm_state_tlb_flush(const struct vmcb *vmcb, const struct nvmm_x64_state *state, 1621 uint64_t flags) 1622 { 1623 if (flags & NVMM_X64_STATE_CRS) { 1624 if ((vmcb->state.cr0 ^ 1625 state->crs[NVMM_X64_CR_CR0]) & CR0_TLB_FLUSH) { 1626 return true; 1627 } 1628 if (vmcb->state.cr3 != state->crs[NVMM_X64_CR_CR3]) { 1629 return true; 1630 } 1631 if ((vmcb->state.cr4 ^ 1632 state->crs[NVMM_X64_CR_CR4]) & CR4_TLB_FLUSH) { 1633 return true; 1634 } 1635 } 1636 1637 if (flags & NVMM_X64_STATE_MSRS) { 1638 if ((vmcb->state.efer ^ 1639 state->msrs[NVMM_X64_MSR_EFER]) & EFER_TLB_FLUSH) { 1640 return true; 1641 } 1642 } 1643 1644 return false; 1645 } 1646 1647 static void 1648 svm_vcpu_setstate(struct nvmm_cpu *vcpu) 1649 { 1650 struct nvmm_comm_page *comm = vcpu->comm; 1651 const struct nvmm_x64_state *state = &comm->state; 1652 struct svm_cpudata *cpudata = vcpu->cpudata; 1653 struct vmcb *vmcb = cpudata->vmcb; 1654 struct fxsave *fpustate; 1655 uint64_t flags; 1656 1657 flags = comm->state_wanted; 1658 1659 if (svm_state_tlb_flush(vmcb, state, flags)) { 1660 cpudata->gtlb_want_flush = true; 1661 } 1662 1663 if (flags & NVMM_X64_STATE_SEGS) { 1664 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_CS], 1665 &vmcb->state.cs); 1666 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_DS], 1667 &vmcb->state.ds); 1668 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_ES], 1669 &vmcb->state.es); 1670 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_FS], 1671 &vmcb->state.fs); 1672 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_GS], 1673 &vmcb->state.gs); 1674 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_SS], 1675 &vmcb->state.ss); 1676 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_GDT], 1677 &vmcb->state.gdt); 1678 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_IDT], 1679 &vmcb->state.idt); 1680 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_LDT], 1681 &vmcb->state.ldt); 1682 svm_vcpu_setstate_seg(&state->segs[NVMM_X64_SEG_TR], 1683 &vmcb->state.tr); 1684 1685 vmcb->state.cpl = state->segs[NVMM_X64_SEG_SS].attrib.dpl; 1686 } 1687 1688 CTASSERT(sizeof(cpudata->gprs) == sizeof(state->gprs)); 1689 if (flags & NVMM_X64_STATE_GPRS) { 1690 memcpy(cpudata->gprs, state->gprs, sizeof(state->gprs)); 1691 1692 vmcb->state.rip = state->gprs[NVMM_X64_GPR_RIP]; 1693 vmcb->state.rsp = state->gprs[NVMM_X64_GPR_RSP]; 1694 vmcb->state.rax = state->gprs[NVMM_X64_GPR_RAX]; 1695 vmcb->state.rflags = state->gprs[NVMM_X64_GPR_RFLAGS]; 1696 } 1697 1698 if (flags & NVMM_X64_STATE_CRS) { 1699 vmcb->state.cr0 = state->crs[NVMM_X64_CR_CR0]; 1700 vmcb->state.cr2 = state->crs[NVMM_X64_CR_CR2]; 1701 vmcb->state.cr3 = state->crs[NVMM_X64_CR_CR3]; 1702 vmcb->state.cr4 = state->crs[NVMM_X64_CR_CR4]; 1703 1704 vmcb->ctrl.v &= ~VMCB_CTRL_V_TPR; 1705 vmcb->ctrl.v |= __SHIFTIN(state->crs[NVMM_X64_CR_CR8], 1706 VMCB_CTRL_V_TPR); 1707 1708 if (svm_xcr0_mask != 0) { 1709 /* Clear illegal XCR0 bits, set mandatory X87 bit. */ 1710 cpudata->gxcr0 = state->crs[NVMM_X64_CR_XCR0]; 1711 cpudata->gxcr0 &= svm_xcr0_mask; 1712 cpudata->gxcr0 |= XCR0_X87; 1713 } 1714 } 1715 1716 CTASSERT(sizeof(cpudata->drs) == sizeof(state->drs)); 1717 if (flags & NVMM_X64_STATE_DRS) { 1718 memcpy(cpudata->drs, state->drs, sizeof(state->drs)); 1719 1720 vmcb->state.dr6 = state->drs[NVMM_X64_DR_DR6]; 1721 vmcb->state.dr7 = state->drs[NVMM_X64_DR_DR7]; 1722 } 1723 1724 if (flags & NVMM_X64_STATE_MSRS) { 1725 /* 1726 * EFER_SVME is mandatory. 1727 */ 1728 vmcb->state.efer = state->msrs[NVMM_X64_MSR_EFER] | EFER_SVME; 1729 vmcb->state.star = state->msrs[NVMM_X64_MSR_STAR]; 1730 vmcb->state.lstar = state->msrs[NVMM_X64_MSR_LSTAR]; 1731 vmcb->state.cstar = state->msrs[NVMM_X64_MSR_CSTAR]; 1732 vmcb->state.sfmask = state->msrs[NVMM_X64_MSR_SFMASK]; 1733 vmcb->state.kernelgsbase = 1734 state->msrs[NVMM_X64_MSR_KERNELGSBASE]; 1735 vmcb->state.sysenter_cs = 1736 state->msrs[NVMM_X64_MSR_SYSENTER_CS]; 1737 vmcb->state.sysenter_esp = 1738 state->msrs[NVMM_X64_MSR_SYSENTER_ESP]; 1739 vmcb->state.sysenter_eip = 1740 state->msrs[NVMM_X64_MSR_SYSENTER_EIP]; 1741 vmcb->state.g_pat = state->msrs[NVMM_X64_MSR_PAT]; 1742 1743 cpudata->gtsc = state->msrs[NVMM_X64_MSR_TSC]; 1744 cpudata->gtsc_want_update = true; 1745 } 1746 1747 if (flags & NVMM_X64_STATE_INTR) { 1748 if (state->intr.int_shadow) { 1749 vmcb->ctrl.intr |= VMCB_CTRL_INTR_SHADOW; 1750 } else { 1751 vmcb->ctrl.intr &= ~VMCB_CTRL_INTR_SHADOW; 1752 } 1753 1754 if (state->intr.int_window_exiting) { 1755 svm_event_waitexit_enable(vcpu, false); 1756 } else { 1757 svm_event_waitexit_disable(vcpu, false); 1758 } 1759 1760 if (state->intr.nmi_window_exiting) { 1761 svm_event_waitexit_enable(vcpu, true); 1762 } else { 1763 svm_event_waitexit_disable(vcpu, true); 1764 } 1765 } 1766 1767 CTASSERT(sizeof(cpudata->gfpu.xsh_fxsave) == sizeof(state->fpu)); 1768 if (flags & NVMM_X64_STATE_FPU) { 1769 memcpy(cpudata->gfpu.xsh_fxsave, &state->fpu, 1770 sizeof(state->fpu)); 1771 1772 fpustate = (struct fxsave *)cpudata->gfpu.xsh_fxsave; 1773 fpustate->fx_mxcsr_mask &= x86_fpu_mxcsr_mask; 1774 fpustate->fx_mxcsr &= fpustate->fx_mxcsr_mask; 1775 1776 if (svm_xcr0_mask != 0) { 1777 /* Reset XSTATE_BV, to force a reload. */ 1778 cpudata->gfpu.xsh_xstate_bv = svm_xcr0_mask; 1779 } 1780 } 1781 1782 svm_vmcb_cache_update(vmcb, flags); 1783 1784 comm->state_wanted = 0; 1785 comm->state_cached |= flags; 1786 } 1787 1788 static void 1789 svm_vcpu_getstate(struct nvmm_cpu *vcpu) 1790 { 1791 struct nvmm_comm_page *comm = vcpu->comm; 1792 struct nvmm_x64_state *state = &comm->state; 1793 struct svm_cpudata *cpudata = vcpu->cpudata; 1794 struct vmcb *vmcb = cpudata->vmcb; 1795 uint64_t flags; 1796 1797 flags = comm->state_wanted; 1798 1799 if (flags & NVMM_X64_STATE_SEGS) { 1800 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_CS], 1801 &vmcb->state.cs); 1802 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_DS], 1803 &vmcb->state.ds); 1804 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_ES], 1805 &vmcb->state.es); 1806 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_FS], 1807 &vmcb->state.fs); 1808 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_GS], 1809 &vmcb->state.gs); 1810 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_SS], 1811 &vmcb->state.ss); 1812 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_GDT], 1813 &vmcb->state.gdt); 1814 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_IDT], 1815 &vmcb->state.idt); 1816 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_LDT], 1817 &vmcb->state.ldt); 1818 svm_vcpu_getstate_seg(&state->segs[NVMM_X64_SEG_TR], 1819 &vmcb->state.tr); 1820 1821 state->segs[NVMM_X64_SEG_SS].attrib.dpl = vmcb->state.cpl; 1822 } 1823 1824 CTASSERT(sizeof(cpudata->gprs) == sizeof(state->gprs)); 1825 if (flags & NVMM_X64_STATE_GPRS) { 1826 memcpy(state->gprs, cpudata->gprs, sizeof(state->gprs)); 1827 1828 state->gprs[NVMM_X64_GPR_RIP] = vmcb->state.rip; 1829 state->gprs[NVMM_X64_GPR_RSP] = vmcb->state.rsp; 1830 state->gprs[NVMM_X64_GPR_RAX] = vmcb->state.rax; 1831 state->gprs[NVMM_X64_GPR_RFLAGS] = vmcb->state.rflags; 1832 } 1833 1834 if (flags & NVMM_X64_STATE_CRS) { 1835 state->crs[NVMM_X64_CR_CR0] = vmcb->state.cr0; 1836 state->crs[NVMM_X64_CR_CR2] = vmcb->state.cr2; 1837 state->crs[NVMM_X64_CR_CR3] = vmcb->state.cr3; 1838 state->crs[NVMM_X64_CR_CR4] = vmcb->state.cr4; 1839 state->crs[NVMM_X64_CR_CR8] = __SHIFTOUT(vmcb->ctrl.v, 1840 VMCB_CTRL_V_TPR); 1841 state->crs[NVMM_X64_CR_XCR0] = cpudata->gxcr0; 1842 } 1843 1844 CTASSERT(sizeof(cpudata->drs) == sizeof(state->drs)); 1845 if (flags & NVMM_X64_STATE_DRS) { 1846 memcpy(state->drs, cpudata->drs, sizeof(state->drs)); 1847 1848 state->drs[NVMM_X64_DR_DR6] = vmcb->state.dr6; 1849 state->drs[NVMM_X64_DR_DR7] = vmcb->state.dr7; 1850 } 1851 1852 if (flags & NVMM_X64_STATE_MSRS) { 1853 state->msrs[NVMM_X64_MSR_EFER] = vmcb->state.efer; 1854 state->msrs[NVMM_X64_MSR_STAR] = vmcb->state.star; 1855 state->msrs[NVMM_X64_MSR_LSTAR] = vmcb->state.lstar; 1856 state->msrs[NVMM_X64_MSR_CSTAR] = vmcb->state.cstar; 1857 state->msrs[NVMM_X64_MSR_SFMASK] = vmcb->state.sfmask; 1858 state->msrs[NVMM_X64_MSR_KERNELGSBASE] = 1859 vmcb->state.kernelgsbase; 1860 state->msrs[NVMM_X64_MSR_SYSENTER_CS] = 1861 vmcb->state.sysenter_cs; 1862 state->msrs[NVMM_X64_MSR_SYSENTER_ESP] = 1863 vmcb->state.sysenter_esp; 1864 state->msrs[NVMM_X64_MSR_SYSENTER_EIP] = 1865 vmcb->state.sysenter_eip; 1866 state->msrs[NVMM_X64_MSR_PAT] = vmcb->state.g_pat; 1867 state->msrs[NVMM_X64_MSR_TSC] = cpudata->gtsc; 1868 1869 /* Hide SVME. */ 1870 state->msrs[NVMM_X64_MSR_EFER] &= ~EFER_SVME; 1871 } 1872 1873 if (flags & NVMM_X64_STATE_INTR) { 1874 state->intr.int_shadow = 1875 (vmcb->ctrl.intr & VMCB_CTRL_INTR_SHADOW) != 0; 1876 state->intr.int_window_exiting = cpudata->int_window_exit; 1877 state->intr.nmi_window_exiting = cpudata->nmi_window_exit; 1878 state->intr.evt_pending = cpudata->evt_pending; 1879 } 1880 1881 CTASSERT(sizeof(cpudata->gfpu.xsh_fxsave) == sizeof(state->fpu)); 1882 if (flags & NVMM_X64_STATE_FPU) { 1883 memcpy(&state->fpu, cpudata->gfpu.xsh_fxsave, 1884 sizeof(state->fpu)); 1885 } 1886 1887 comm->state_wanted = 0; 1888 comm->state_cached |= flags; 1889 } 1890 1891 static void 1892 svm_vcpu_state_provide(struct nvmm_cpu *vcpu, uint64_t flags) 1893 { 1894 vcpu->comm->state_wanted = flags; 1895 svm_vcpu_getstate(vcpu); 1896 } 1897 1898 static void 1899 svm_vcpu_state_commit(struct nvmm_cpu *vcpu) 1900 { 1901 vcpu->comm->state_wanted = vcpu->comm->state_commit; 1902 vcpu->comm->state_commit = 0; 1903 svm_vcpu_setstate(vcpu); 1904 } 1905 1906 /* -------------------------------------------------------------------------- */ 1907 1908 static void 1909 svm_asid_alloc(struct nvmm_cpu *vcpu) 1910 { 1911 struct svm_cpudata *cpudata = vcpu->cpudata; 1912 struct vmcb *vmcb = cpudata->vmcb; 1913 size_t i, oct, bit; 1914 1915 mutex_enter(&svm_asidlock); 1916 1917 for (i = 0; i < svm_maxasid; i++) { 1918 oct = i / 8; 1919 bit = i % 8; 1920 1921 if (svm_asidmap[oct] & __BIT(bit)) { 1922 continue; 1923 } 1924 1925 svm_asidmap[oct] |= __BIT(bit); 1926 vmcb->ctrl.guest_asid = i; 1927 mutex_exit(&svm_asidlock); 1928 return; 1929 } 1930 1931 /* 1932 * No free ASID. Use the last one, which is shared and requires 1933 * special TLB handling. 1934 */ 1935 cpudata->shared_asid = true; 1936 vmcb->ctrl.guest_asid = svm_maxasid - 1; 1937 mutex_exit(&svm_asidlock); 1938 } 1939 1940 static void 1941 svm_asid_free(struct nvmm_cpu *vcpu) 1942 { 1943 struct svm_cpudata *cpudata = vcpu->cpudata; 1944 struct vmcb *vmcb = cpudata->vmcb; 1945 size_t oct, bit; 1946 1947 if (cpudata->shared_asid) { 1948 return; 1949 } 1950 1951 oct = vmcb->ctrl.guest_asid / 8; 1952 bit = vmcb->ctrl.guest_asid % 8; 1953 1954 mutex_enter(&svm_asidlock); 1955 svm_asidmap[oct] &= ~__BIT(bit); 1956 mutex_exit(&svm_asidlock); 1957 } 1958 1959 static void 1960 svm_vcpu_init(struct nvmm_machine *mach, struct nvmm_cpu *vcpu) 1961 { 1962 struct svm_cpudata *cpudata = vcpu->cpudata; 1963 struct vmcb *vmcb = cpudata->vmcb; 1964 1965 /* Allow reads/writes of Control Registers. */ 1966 vmcb->ctrl.intercept_cr = 0; 1967 1968 /* Allow reads/writes of Debug Registers. */ 1969 vmcb->ctrl.intercept_dr = 0; 1970 1971 /* Allow exceptions 0 to 31. */ 1972 vmcb->ctrl.intercept_vec = 0; 1973 1974 /* 1975 * Allow: 1976 * - SMI [smm interrupts] 1977 * - VINTR [virtual interrupts] 1978 * - CR0_SPEC [CR0 writes changing other fields than CR0.TS or CR0.MP] 1979 * - RIDTR [reads of IDTR] 1980 * - RGDTR [reads of GDTR] 1981 * - RLDTR [reads of LDTR] 1982 * - RTR [reads of TR] 1983 * - WIDTR [writes of IDTR] 1984 * - WGDTR [writes of GDTR] 1985 * - WLDTR [writes of LDTR] 1986 * - WTR [writes of TR] 1987 * - RDTSC [rdtsc instruction] 1988 * - PUSHF [pushf instruction] 1989 * - POPF [popf instruction] 1990 * - IRET [iret instruction] 1991 * - INTN [int $n instructions] 1992 * - INVD [invd instruction] 1993 * - PAUSE [pause instruction] 1994 * - INVLPG [invplg instruction] 1995 * - TASKSW [task switches] 1996 * 1997 * Intercept the rest below. 1998 */ 1999 vmcb->ctrl.intercept_misc1 = 2000 VMCB_CTRL_INTERCEPT_INTR | 2001 VMCB_CTRL_INTERCEPT_NMI | 2002 VMCB_CTRL_INTERCEPT_INIT | 2003 VMCB_CTRL_INTERCEPT_RDPMC | 2004 VMCB_CTRL_INTERCEPT_CPUID | 2005 VMCB_CTRL_INTERCEPT_RSM | 2006 VMCB_CTRL_INTERCEPT_HLT | 2007 VMCB_CTRL_INTERCEPT_INVLPGA | 2008 VMCB_CTRL_INTERCEPT_IOIO_PROT | 2009 VMCB_CTRL_INTERCEPT_MSR_PROT | 2010 VMCB_CTRL_INTERCEPT_FERR_FREEZE | 2011 VMCB_CTRL_INTERCEPT_SHUTDOWN; 2012 2013 /* 2014 * Allow: 2015 * - ICEBP [icebp instruction] 2016 * - WBINVD [wbinvd instruction] 2017 * - WCR_SPEC(0..15) [writes of CR0-15, received after instruction] 2018 * 2019 * Intercept the rest below. 2020 */ 2021 vmcb->ctrl.intercept_misc2 = 2022 VMCB_CTRL_INTERCEPT_VMRUN | 2023 VMCB_CTRL_INTERCEPT_VMMCALL | 2024 VMCB_CTRL_INTERCEPT_VMLOAD | 2025 VMCB_CTRL_INTERCEPT_VMSAVE | 2026 VMCB_CTRL_INTERCEPT_STGI | 2027 VMCB_CTRL_INTERCEPT_CLGI | 2028 VMCB_CTRL_INTERCEPT_SKINIT | 2029 VMCB_CTRL_INTERCEPT_RDTSCP | 2030 VMCB_CTRL_INTERCEPT_MONITOR | 2031 VMCB_CTRL_INTERCEPT_MWAIT | 2032 VMCB_CTRL_INTERCEPT_XSETBV; 2033 2034 /* Intercept all I/O accesses. */ 2035 memset(cpudata->iobm, 0xFF, IOBM_SIZE); 2036 vmcb->ctrl.iopm_base_pa = cpudata->iobm_pa; 2037 2038 /* Allow direct access to certain MSRs. */ 2039 memset(cpudata->msrbm, 0xFF, MSRBM_SIZE); 2040 svm_vcpu_msr_allow(cpudata->msrbm, MSR_EFER, true, false); 2041 svm_vcpu_msr_allow(cpudata->msrbm, MSR_STAR, true, true); 2042 svm_vcpu_msr_allow(cpudata->msrbm, MSR_LSTAR, true, true); 2043 svm_vcpu_msr_allow(cpudata->msrbm, MSR_CSTAR, true, true); 2044 svm_vcpu_msr_allow(cpudata->msrbm, MSR_SFMASK, true, true); 2045 svm_vcpu_msr_allow(cpudata->msrbm, MSR_KERNELGSBASE, true, true); 2046 svm_vcpu_msr_allow(cpudata->msrbm, MSR_SYSENTER_CS, true, true); 2047 svm_vcpu_msr_allow(cpudata->msrbm, MSR_SYSENTER_ESP, true, true); 2048 svm_vcpu_msr_allow(cpudata->msrbm, MSR_SYSENTER_EIP, true, true); 2049 svm_vcpu_msr_allow(cpudata->msrbm, MSR_FSBASE, true, true); 2050 svm_vcpu_msr_allow(cpudata->msrbm, MSR_GSBASE, true, true); 2051 svm_vcpu_msr_allow(cpudata->msrbm, MSR_CR_PAT, true, true); 2052 svm_vcpu_msr_allow(cpudata->msrbm, MSR_TSC, true, false); 2053 vmcb->ctrl.msrpm_base_pa = cpudata->msrbm_pa; 2054 2055 /* Generate ASID. */ 2056 svm_asid_alloc(vcpu); 2057 2058 /* Virtual TPR. */ 2059 vmcb->ctrl.v = VMCB_CTRL_V_INTR_MASKING; 2060 2061 /* Enable Nested Paging. */ 2062 vmcb->ctrl.enable1 = VMCB_CTRL_ENABLE_NP; 2063 vmcb->ctrl.n_cr3 = mach->vm->vm_map.pmap->pm_pdirpa[0]; 2064 2065 /* Init XSAVE header. */ 2066 cpudata->gfpu.xsh_xstate_bv = svm_xcr0_mask; 2067 cpudata->gfpu.xsh_xcomp_bv = 0; 2068 2069 /* These MSRs are static. */ 2070 cpudata->star = rdmsr(MSR_STAR); 2071 cpudata->lstar = rdmsr(MSR_LSTAR); 2072 cpudata->cstar = rdmsr(MSR_CSTAR); 2073 cpudata->sfmask = rdmsr(MSR_SFMASK); 2074 2075 /* Install the RESET state. */ 2076 memcpy(&vcpu->comm->state, &nvmm_x86_reset_state, 2077 sizeof(nvmm_x86_reset_state)); 2078 vcpu->comm->state_wanted = NVMM_X64_STATE_ALL; 2079 vcpu->comm->state_cached = 0; 2080 svm_vcpu_setstate(vcpu); 2081 } 2082 2083 static int 2084 svm_vcpu_create(struct nvmm_machine *mach, struct nvmm_cpu *vcpu) 2085 { 2086 struct svm_cpudata *cpudata; 2087 int error; 2088 2089 /* Allocate the SVM cpudata. */ 2090 cpudata = (struct svm_cpudata *)uvm_km_alloc(kernel_map, 2091 roundup(sizeof(*cpudata), PAGE_SIZE), 0, 2092 UVM_KMF_WIRED|UVM_KMF_ZERO); 2093 vcpu->cpudata = cpudata; 2094 2095 /* VMCB */ 2096 error = svm_memalloc(&cpudata->vmcb_pa, (vaddr_t *)&cpudata->vmcb, 2097 VMCB_NPAGES); 2098 if (error) 2099 goto error; 2100 2101 /* I/O Bitmap */ 2102 error = svm_memalloc(&cpudata->iobm_pa, (vaddr_t *)&cpudata->iobm, 2103 IOBM_NPAGES); 2104 if (error) 2105 goto error; 2106 2107 /* MSR Bitmap */ 2108 error = svm_memalloc(&cpudata->msrbm_pa, (vaddr_t *)&cpudata->msrbm, 2109 MSRBM_NPAGES); 2110 if (error) 2111 goto error; 2112 2113 /* Init the VCPU info. */ 2114 svm_vcpu_init(mach, vcpu); 2115 2116 return 0; 2117 2118 error: 2119 if (cpudata->vmcb_pa) { 2120 svm_memfree(cpudata->vmcb_pa, (vaddr_t)cpudata->vmcb, 2121 VMCB_NPAGES); 2122 } 2123 if (cpudata->iobm_pa) { 2124 svm_memfree(cpudata->iobm_pa, (vaddr_t)cpudata->iobm, 2125 IOBM_NPAGES); 2126 } 2127 if (cpudata->msrbm_pa) { 2128 svm_memfree(cpudata->msrbm_pa, (vaddr_t)cpudata->msrbm, 2129 MSRBM_NPAGES); 2130 } 2131 uvm_km_free(kernel_map, (vaddr_t)cpudata, 2132 roundup(sizeof(*cpudata), PAGE_SIZE), UVM_KMF_WIRED); 2133 return error; 2134 } 2135 2136 static void 2137 svm_vcpu_destroy(struct nvmm_machine *mach, struct nvmm_cpu *vcpu) 2138 { 2139 struct svm_cpudata *cpudata = vcpu->cpudata; 2140 2141 svm_asid_free(vcpu); 2142 2143 svm_memfree(cpudata->vmcb_pa, (vaddr_t)cpudata->vmcb, VMCB_NPAGES); 2144 svm_memfree(cpudata->iobm_pa, (vaddr_t)cpudata->iobm, IOBM_NPAGES); 2145 svm_memfree(cpudata->msrbm_pa, (vaddr_t)cpudata->msrbm, MSRBM_NPAGES); 2146 2147 uvm_km_free(kernel_map, (vaddr_t)cpudata, 2148 roundup(sizeof(*cpudata), PAGE_SIZE), UVM_KMF_WIRED); 2149 } 2150 2151 /* -------------------------------------------------------------------------- */ 2152 2153 static int 2154 svm_vcpu_configure_cpuid(struct svm_cpudata *cpudata, void *data) 2155 { 2156 struct nvmm_vcpu_conf_cpuid *cpuid = data; 2157 size_t i; 2158 2159 if (__predict_false(cpuid->mask && cpuid->exit)) { 2160 return EINVAL; 2161 } 2162 if (__predict_false(cpuid->mask && 2163 ((cpuid->u.mask.set.eax & cpuid->u.mask.del.eax) || 2164 (cpuid->u.mask.set.ebx & cpuid->u.mask.del.ebx) || 2165 (cpuid->u.mask.set.ecx & cpuid->u.mask.del.ecx) || 2166 (cpuid->u.mask.set.edx & cpuid->u.mask.del.edx)))) { 2167 return EINVAL; 2168 } 2169 2170 /* If unset, delete, to restore the default behavior. */ 2171 if (!cpuid->mask && !cpuid->exit) { 2172 for (i = 0; i < SVM_NCPUIDS; i++) { 2173 if (!cpudata->cpuidpresent[i]) { 2174 continue; 2175 } 2176 if (cpudata->cpuid[i].leaf == cpuid->leaf) { 2177 cpudata->cpuidpresent[i] = false; 2178 } 2179 } 2180 return 0; 2181 } 2182 2183 /* If already here, replace. */ 2184 for (i = 0; i < SVM_NCPUIDS; i++) { 2185 if (!cpudata->cpuidpresent[i]) { 2186 continue; 2187 } 2188 if (cpudata->cpuid[i].leaf == cpuid->leaf) { 2189 memcpy(&cpudata->cpuid[i], cpuid, 2190 sizeof(struct nvmm_vcpu_conf_cpuid)); 2191 return 0; 2192 } 2193 } 2194 2195 /* Not here, insert. */ 2196 for (i = 0; i < SVM_NCPUIDS; i++) { 2197 if (!cpudata->cpuidpresent[i]) { 2198 cpudata->cpuidpresent[i] = true; 2199 memcpy(&cpudata->cpuid[i], cpuid, 2200 sizeof(struct nvmm_vcpu_conf_cpuid)); 2201 return 0; 2202 } 2203 } 2204 2205 return ENOBUFS; 2206 } 2207 2208 static int 2209 svm_vcpu_configure(struct nvmm_cpu *vcpu, uint64_t op, void *data) 2210 { 2211 struct svm_cpudata *cpudata = vcpu->cpudata; 2212 2213 switch (op) { 2214 case NVMM_VCPU_CONF_MD(NVMM_VCPU_CONF_CPUID): 2215 return svm_vcpu_configure_cpuid(cpudata, data); 2216 default: 2217 return EINVAL; 2218 } 2219 } 2220 2221 /* -------------------------------------------------------------------------- */ 2222 2223 static void 2224 svm_tlb_flush(struct pmap *pm) 2225 { 2226 struct nvmm_machine *mach = pm->pm_data; 2227 struct svm_machdata *machdata = mach->machdata; 2228 2229 atomic_inc_64(&machdata->mach_htlb_gen); 2230 2231 /* Generates IPIs, which cause #VMEXITs. */ 2232 pmap_tlb_shootdown(pmap_kernel(), -1, PTE_G, TLBSHOOT_NVMM); 2233 } 2234 2235 static void 2236 svm_machine_create(struct nvmm_machine *mach) 2237 { 2238 struct svm_machdata *machdata; 2239 2240 /* Fill in pmap info. */ 2241 mach->vm->vm_map.pmap->pm_data = (void *)mach; 2242 mach->vm->vm_map.pmap->pm_tlb_flush = svm_tlb_flush; 2243 2244 machdata = kmem_zalloc(sizeof(struct svm_machdata), KM_SLEEP); 2245 mach->machdata = machdata; 2246 2247 /* Start with an hTLB flush everywhere. */ 2248 machdata->mach_htlb_gen = 1; 2249 } 2250 2251 static void 2252 svm_machine_destroy(struct nvmm_machine *mach) 2253 { 2254 kmem_free(mach->machdata, sizeof(struct svm_machdata)); 2255 } 2256 2257 static int 2258 svm_machine_configure(struct nvmm_machine *mach, uint64_t op, void *data) 2259 { 2260 panic("%s: impossible", __func__); 2261 } 2262 2263 /* -------------------------------------------------------------------------- */ 2264 2265 static bool 2266 svm_ident(void) 2267 { 2268 u_int descs[4]; 2269 uint64_t msr; 2270 2271 if (cpu_vendor != CPUVENDOR_AMD) { 2272 return false; 2273 } 2274 if (!(cpu_feature[3] & CPUID_SVM)) { 2275 printf("NVMM: SVM not supported\n"); 2276 return false; 2277 } 2278 2279 if (curcpu()->ci_max_ext_cpuid < 0x8000000a) { 2280 printf("NVMM: CPUID leaf not available\n"); 2281 return false; 2282 } 2283 x86_cpuid(0x8000000a, descs); 2284 2285 /* Want Nested Paging. */ 2286 if (!(descs[3] & CPUID_AMD_SVM_NP)) { 2287 printf("NVMM: SVM-NP not supported\n"); 2288 return false; 2289 } 2290 2291 /* Want nRIP. */ 2292 if (!(descs[3] & CPUID_AMD_SVM_NRIPS)) { 2293 printf("NVMM: SVM-NRIPS not supported\n"); 2294 return false; 2295 } 2296 2297 svm_decode_assist = (descs[3] & CPUID_AMD_SVM_DecodeAssist) != 0; 2298 2299 msr = rdmsr(MSR_VMCR); 2300 if ((msr & VMCR_SVMED) && (msr & VMCR_LOCK)) { 2301 printf("NVMM: SVM disabled in BIOS\n"); 2302 return false; 2303 } 2304 2305 return true; 2306 } 2307 2308 static void 2309 svm_init_asid(uint32_t maxasid) 2310 { 2311 size_t i, j, allocsz; 2312 2313 mutex_init(&svm_asidlock, MUTEX_DEFAULT, IPL_NONE); 2314 2315 /* Arbitrarily limit. */ 2316 maxasid = uimin(maxasid, 8192); 2317 2318 svm_maxasid = maxasid; 2319 allocsz = roundup(maxasid, 8) / 8; 2320 svm_asidmap = kmem_zalloc(allocsz, KM_SLEEP); 2321 2322 /* ASID 0 is reserved for the host. */ 2323 svm_asidmap[0] |= __BIT(0); 2324 2325 /* ASID n-1 is special, we share it. */ 2326 i = (maxasid - 1) / 8; 2327 j = (maxasid - 1) % 8; 2328 svm_asidmap[i] |= __BIT(j); 2329 } 2330 2331 static void 2332 svm_change_cpu(void *arg1, void *arg2) 2333 { 2334 bool enable = arg1 != NULL; 2335 uint64_t msr; 2336 2337 msr = rdmsr(MSR_VMCR); 2338 if (msr & VMCR_SVMED) { 2339 wrmsr(MSR_VMCR, msr & ~VMCR_SVMED); 2340 } 2341 2342 if (!enable) { 2343 wrmsr(MSR_VM_HSAVE_PA, 0); 2344 } 2345 2346 msr = rdmsr(MSR_EFER); 2347 if (enable) { 2348 msr |= EFER_SVME; 2349 } else { 2350 msr &= ~EFER_SVME; 2351 } 2352 wrmsr(MSR_EFER, msr); 2353 2354 if (enable) { 2355 wrmsr(MSR_VM_HSAVE_PA, hsave[cpu_index(curcpu())].pa); 2356 } 2357 } 2358 2359 static void 2360 svm_init(void) 2361 { 2362 CPU_INFO_ITERATOR cii; 2363 struct cpu_info *ci; 2364 struct vm_page *pg; 2365 u_int descs[4]; 2366 uint64_t xc; 2367 2368 x86_cpuid(0x8000000a, descs); 2369 2370 /* The guest TLB flush command. */ 2371 if (descs[3] & CPUID_AMD_SVM_FlushByASID) { 2372 svm_ctrl_tlb_flush = VMCB_CTRL_TLB_CTRL_FLUSH_GUEST; 2373 } else { 2374 svm_ctrl_tlb_flush = VMCB_CTRL_TLB_CTRL_FLUSH_ALL; 2375 } 2376 2377 /* Init the ASID. */ 2378 svm_init_asid(descs[1]); 2379 2380 /* Init the XCR0 mask. */ 2381 svm_xcr0_mask = SVM_XCR0_MASK_DEFAULT & x86_xsave_features; 2382 2383 memset(hsave, 0, sizeof(hsave)); 2384 for (CPU_INFO_FOREACH(cii, ci)) { 2385 pg = uvm_pagealloc(NULL, 0, NULL, UVM_PGA_ZERO); 2386 hsave[cpu_index(ci)].pa = VM_PAGE_TO_PHYS(pg); 2387 } 2388 2389 xc = xc_broadcast(0, svm_change_cpu, (void *)true, NULL); 2390 xc_wait(xc); 2391 } 2392 2393 static void 2394 svm_fini_asid(void) 2395 { 2396 size_t allocsz; 2397 2398 allocsz = roundup(svm_maxasid, 8) / 8; 2399 kmem_free(svm_asidmap, allocsz); 2400 2401 mutex_destroy(&svm_asidlock); 2402 } 2403 2404 static void 2405 svm_fini(void) 2406 { 2407 uint64_t xc; 2408 size_t i; 2409 2410 xc = xc_broadcast(0, svm_change_cpu, (void *)false, NULL); 2411 xc_wait(xc); 2412 2413 for (i = 0; i < MAXCPUS; i++) { 2414 if (hsave[i].pa != 0) 2415 uvm_pagefree(PHYS_TO_VM_PAGE(hsave[i].pa)); 2416 } 2417 2418 svm_fini_asid(); 2419 } 2420 2421 static void 2422 svm_capability(struct nvmm_capability *cap) 2423 { 2424 cap->arch.mach_conf_support = 0; 2425 cap->arch.vcpu_conf_support = 2426 NVMM_CAP_ARCH_VCPU_CONF_CPUID; 2427 cap->arch.xcr0_mask = svm_xcr0_mask; 2428 cap->arch.mxcsr_mask = x86_fpu_mxcsr_mask; 2429 cap->arch.conf_cpuid_maxops = SVM_NCPUIDS; 2430 } 2431 2432 const struct nvmm_impl nvmm_x86_svm = { 2433 .name = "x86-svm", 2434 .ident = svm_ident, 2435 .init = svm_init, 2436 .fini = svm_fini, 2437 .capability = svm_capability, 2438 .mach_conf_max = NVMM_X86_MACH_NCONF, 2439 .mach_conf_sizes = NULL, 2440 .vcpu_conf_max = NVMM_X86_VCPU_NCONF, 2441 .vcpu_conf_sizes = svm_vcpu_conf_sizes, 2442 .state_size = sizeof(struct nvmm_x64_state), 2443 .machine_create = svm_machine_create, 2444 .machine_destroy = svm_machine_destroy, 2445 .machine_configure = svm_machine_configure, 2446 .vcpu_create = svm_vcpu_create, 2447 .vcpu_destroy = svm_vcpu_destroy, 2448 .vcpu_configure = svm_vcpu_configure, 2449 .vcpu_setstate = svm_vcpu_setstate, 2450 .vcpu_getstate = svm_vcpu_getstate, 2451 .vcpu_inject = svm_vcpu_inject, 2452 .vcpu_run = svm_vcpu_run 2453 }; 2454
Indexes created Thu Oct 02 01:09:59 GMT 2025